Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16862

1

T4

6

T9

10

T11

10

auto[1]

11443

1

T14

32

T15

208

T17

194

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3623	1			T17	162		T20	98		T65	22
values[1]	3439	1			T15	126		T17	94		T24	22
values[2]	3818	1			T15	40		T17	117		T21	12
values[3]	3697	1			T15	133		T17	46		T148	10
values[4]	3429	1			T4	6		T19	24		T18	30
values[5]	2632	1			T9	10		T11	10		T14	32
values[6]	4054	1			T15	95		T307	2		T22	14
values[7]	3613	1			T15	20		T16	12		T17	24

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3258	1			T15	40		T17	20		T23	2
values[1]	3508	1			T9	10		T15	40		T17	123
values[2]	3597	1			T18	30		T15	81		T17	112
values[3]	3810	1			T11	10		T19	24		T15	127
values[4]	3754	1			T15	103		T16	12		T17	32
values[5]	3110	1			T14	32		T148	10		T308	20
values[6]	3656	1			T4	6		T15	20		T17	45
values[7]	3612	1			T15	67		T17	64		T59	4

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	375	1			T20	42		T210	10		T309	20
auto[0]	values[0]	values[1]	330	1			T17	80		T20	40		T26	7
auto[0]	values[0]	values[2]	325	1			T17	6		T28	24		T310	10
auto[0]	values[0]	values[3]	250	1			T17	15		T65	22		T247	5
auto[0]	values[0]	values[4]	338	1			T28	5		T289	20		T123	27
auto[0]	values[0]	values[5]	233	1			T27	11		T311	36		T245	71
auto[0]	values[0]	values[6]	182	1			T30	50		T231	8		T252	8
auto[0]	values[0]	values[7]	206	1			T27	17		T312	2		T30	11
auto[0]	values[1]	values[0]	143	1			T231	10		T313	24		T245	11
auto[0]	values[1]	values[1]	400	1			T17	14		T24	22		T20	11
auto[0]	values[1]	values[2]	236	1			T15	32		T61	6		T212	28
auto[0]	values[1]	values[3]	209	1			T212	26		T245	14		T314	19
auto[0]	values[1]	values[4]	224	1			T15	13		T315	4		T262	12
auto[0]	values[1]	values[5]	278	1			T316	18		T255	17		T212	12
auto[0]	values[1]	values[6]	224	1			T251	53		T213	8		T212	8
auto[0]	values[1]	values[7]	298	1			T15	13		T17	10		T20	16
auto[0]	values[2]	values[0]	219	1			T15	12		T17	5		T317	4
auto[0]	values[2]	values[1]	132	1			T294	28		T26	8		T318	12
auto[0]	values[2]	values[2]	265	1			T17	12		T239	8		T30	15
auto[0]	values[2]	values[3]	386	1			T15	12		T29	23		T121	15
auto[0]	values[2]	values[4]	221	1			T17	22		T21	12		T227	13
auto[0]	values[2]	values[5]	165	1			T210	10		T247	13		T123	16
auto[0]	values[2]	values[6]	494	1			T17	38		T20	19		T210	12
auto[0]	values[2]	values[7]	265	1			T29	4		T319	14		T30	20
auto[0]	values[3]	values[0]	190	1			T231	15		T241	6		T244	10
auto[0]	values[3]	values[1]	245	1			T15	10		T26	8		T27	33
auto[0]	values[3]	values[2]	172	1			T15	10		T17	35		T81	16
auto[0]	values[3]	values[3]	402	1			T15	25		T210	7		T231	12
auto[0]	values[3]	values[4]	322	1			T15	15		T28	13		T231	15
auto[0]	values[3]	values[5]	428	1			T148	10		T231	14		T227	28
auto[0]	values[3]	values[6]	209	1			T287	18		T210	19		T320	10
auto[0]	values[3]	values[7]	280	1			T253	14		T231	11		T81	11
auto[0]	values[4]	values[0]	226	1			T15	12		T28	13		T30	12
auto[0]	values[4]	values[1]	187	1			T26	11		T209	56		T321	14
auto[0]	values[4]	values[2]	478	1			T18	30		T15	12		T26	13
auto[0]	values[4]	values[3]	208	1			T19	24		T20	20		T271	14
auto[0]	values[4]	values[4]	205	1			T15	16		T247	6		T271	6
auto[0]	values[4]	values[5]	221	1			T26	29		T30	12		T322	8
auto[0]	values[4]	values[6]	338	1			T4	6		T27	9		T323	10
auto[0]	values[4]	values[7]	165	1			T210	18		T81	10		T262	6
auto[0]	values[5]	values[0]	150	1			T23	2		T210	37		T226	16
auto[0]	values[5]	values[1]	285	1			T9	10		T212	24		T250	10
auto[0]	values[5]	values[2]	256	1			T324	2		T131	14		T325	10
auto[0]	values[5]	values[3]	187	1			T11	10		T20	12		T28	19
auto[0]	values[5]	values[4]	172	1			T81	7		T227	10		T262	13
auto[0]	values[5]	values[5]	157	1			T308	20		T30	15		T231	14
auto[0]	values[5]	values[6]	210	1			T111	10		T27	20		T123	9
auto[0]	values[5]	values[7]	170	1			T248	2		T212	6		T231	16
auto[0]	values[6]	values[0]	274	1			T326	16		T247	11		T277	14
auto[0]	values[6]	values[1]	280	1			T26	17		T212	14		T81	15
auto[0]	values[6]	values[2]	231	1			T307	2		T20	12		T327	24
auto[0]	values[6]	values[3]	549	1			T15	67		T28	15		T276	10
auto[0]	values[6]	values[4]	248	1			T28	17		T328	4		T329	14
auto[0]	values[6]	values[5]	199	1			T22	14		T26	15		T29	23
auto[0]	values[6]	values[6]	355	1			T15	7		T30	11		T330	4
auto[0]	values[6]	values[7]	256	1			T20	15		T232	28		T30	6
auto[0]	values[7]	values[0]	271	1			T27	11		T280	10		T29	18
auto[0]	values[7]	values[1]	299	1			T15	14		T272	18		T249	20
auto[0]	values[7]	values[2]	265	1			T17	12		T64	12		T27	8
auto[0]	values[7]	values[3]	148	1			T29	11		T210	13		T212	14
auto[0]	values[7]	values[4]	367	1			T16	12		T331	12		T29	45
auto[0]	values[7]	values[5]	191	1			T332	75		T231	19		T256	18
auto[0]	values[7]	values[6]	432	1			T110	40		T231	16		T333	6
auto[0]	values[7]	values[7]	236	1			T59	4		T20	11		T210	37
auto[1]	values[0]	values[0]	211	1			T210	10		T329	45		T245	25
auto[1]	values[0]	values[1]	350	1			T17	13		T20	16		T26	17
auto[1]	values[0]	values[2]	229	1			T17	16		T28	5		T30	19
auto[1]	values[0]	values[3]	149	1			T17	32		T334	26		T247	20
auto[1]	values[0]	values[4]	120	1			T28	15		T123	7		T262	8
auto[1]	values[0]	values[5]	112	1			T27	9		T245	8		T335	7
auto[1]	values[0]	values[6]	56	1			T30	6		T231	12		T252	12
auto[1]	values[0]	values[7]	157	1			T27	8		T30	38		T212	5
auto[1]	values[1]	values[0]	169	1			T231	23		T245	9		T336	4
auto[1]	values[1]	values[1]	215	1			T17	16		T20	9		T30	5
auto[1]	values[1]	values[2]	141	1			T15	7		T212	10		T231	6
auto[1]	values[1]	values[3]	157	1			T212	3		T245	6		T314	7
auto[1]	values[1]	values[4]	159	1			T15	7		T262	32		T245	10
auto[1]	values[1]	values[5]	180	1			T255	5		T212	8		T247	8
auto[1]	values[1]	values[6]	108	1			T337	16		T212	17		T81	8
auto[1]	values[1]	values[7]	298	1			T15	54		T17	54		T20	4
auto[1]	values[2]	values[0]	255	1			T15	8		T17	15		T270	22
auto[1]	values[2]	values[1]	68	1			T26	18		T246	3		T238	14
auto[1]	values[2]	values[2]	211	1			T17	8		T30	5		T231	15
auto[1]	values[2]	values[3]	168	1			T15	8		T29	7		T121	5
auto[1]	values[2]	values[4]	395	1			T17	10		T227	12		T338	2
auto[1]	values[2]	values[5]	124	1			T210	25		T247	18		T123	4
auto[1]	values[2]	values[6]	228	1			T17	7		T20	8		T210	8
auto[1]	values[2]	values[7]	222	1			T29	16		T30	6		T244	16
auto[1]	values[3]	values[0]	132	1			T231	10		T244	12		T336	4
auto[1]	values[3]	values[1]	179	1			T15	10		T26	22		T27	26
auto[1]	values[3]	values[2]	97	1			T15	10		T17	11		T81	8
auto[1]	values[3]	values[3]	267	1			T15	7		T210	39		T234	18
auto[1]	values[3]	values[4]	260	1			T15	46		T28	7		T231	5
auto[1]	values[3]	values[5]	181	1			T231	11		T227	10		T246	7
auto[1]	values[3]	values[6]	149	1			T210	33		T212	7		T274	28
auto[1]	values[3]	values[7]	184	1			T231	9		T81	17		T227	12
auto[1]	values[4]	values[0]	118	1			T15	8		T28	12		T30	8
auto[1]	values[4]	values[1]	90	1			T26	23		T335	8		T269	15
auto[1]	values[4]	values[2]	139	1			T15	10		T26	7		T210	19
auto[1]	values[4]	values[3]	105	1			T20	6		T288	12		T271	6
auto[1]	values[4]	values[4]	200	1			T15	6		T339	34		T247	20
auto[1]	values[4]	values[5]	328	1			T133	34		T26	7		T30	20
auto[1]	values[4]	values[6]	183	1			T27	11		T210	12		T212	12
auto[1]	values[4]	values[7]	238	1			T210	2		T81	10		T262	37
auto[1]	values[5]	values[0]	86	1			T210	8		T123	9		T244	14
auto[1]	values[5]	values[1]	134	1			T212	6		T252	70		T269	27
auto[1]	values[5]	values[2]	182	1			T212	88		T277	7		T227	10
auto[1]	values[5]	values[3]	150	1			T20	8		T28	10		T210	4
auto[1]	values[5]	values[4]	166	1			T235	4		T81	13		T227	10
auto[1]	values[5]	values[5]	150	1			T14	32		T132	30		T30	8
auto[1]	values[5]	values[6]	79	1			T27	5		T123	11		T244	9
auto[1]	values[5]	values[7]	98	1			T212	14		T231	6		T340	14
auto[1]	values[6]	values[0]	217	1			T341	20		T247	15		T277	6
auto[1]	values[6]	values[1]	174	1			T26	7		T212	45		T81	7
auto[1]	values[6]	values[2]	166	1			T20	16		T231	7		T81	46
auto[1]	values[6]	values[3]	342	1			T15	8		T28	16		T210	12
auto[1]	values[6]	values[4]	138	1			T28	9		T329	6		T252	20
auto[1]	values[6]	values[5]	109	1			T26	5		T29	7		T229	17
auto[1]	values[6]	values[6]	218	1			T15	13		T342	4		T30	9
auto[1]	values[6]	values[7]	298	1			T20	5		T30	23		T210	7
auto[1]	values[7]	values[0]	222	1			T27	9		T29	28		T123	12
auto[1]	values[7]	values[1]	140	1			T15	6		T247	3		T271	13
auto[1]	values[7]	values[2]	204	1			T17	12		T27	12		T28	9
auto[1]	values[7]	values[3]	133	1			T29	9		T210	50		T212	6
auto[1]	values[7]	values[4]	219	1			T29	9		T210	20		T246	6
auto[1]	values[7]	values[5]	54	1			T231	4		T343	6		T344	6
auto[1]	values[7]	values[6]	191	1			T231	8		T123	9		T244	11
auto[1]	values[7]	values[7]	241	1			T20	9		T210	19		T211	22