Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	12	0	12	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6078887	1			T1	2		T4	1		T2	2
all_pins[1]	6078887	1			T1	2		T4	1		T2	2
all_pins[2]	6078887	1			T1	2		T4	1		T2	2
all_pins[3]	6078887	1			T1	2		T4	1		T2	2
all_pins[4]	6078887	1			T1	2		T4	1		T2	2
all_pins[5]	6078887	1			T1	2		T4	1		T2	2
all_pins[6]	6078887	1			T1	2		T4	1		T2	2
all_pins[7]	6078887	1			T1	2		T4	1		T2	2
all_pins[8]	6078887	1			T1	2		T4	1		T2	2
all_pins[9]	6078887	1			T1	2		T4	1		T2	2
all_pins[10]	6078887	1			T1	2		T4	1		T2	2
all_pins[11]	6078887	1			T1	2		T4	1		T2	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	72893338	1			T1	24		T4	12		T2	24
values[0x1]	53306	1			T3	1		T7	1		T76	1
transitions[0x0=>0x1]	52180	1			T3	1		T7	1		T76	1
transitions[0x1=>0x0]	52197	1			T3	1		T7	1		T76	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	6078384	1			T1	2		T4	1		T2	2
all_pins[0]	values[0x1]	503	1			T7	1		T77	2		T79	1
all_pins[0]	transitions[0x0=>0x1]	323	1			T7	1		T77	2		T79	1
all_pins[0]	transitions[0x1=>0x0]	44816	1			T98	2		T173	3		T207	1
all_pins[1]	values[0x0]	6033891	1			T1	2		T4	1		T2	2
all_pins[1]	values[0x1]	44996	1			T98	5		T173	3		T207	1
all_pins[1]	transitions[0x0=>0x1]	44877	1			T98	5		T173	3		T207	1
all_pins[1]	transitions[0x1=>0x0]	440	1			T3	1		T77	2		T78	4
all_pins[2]	values[0x0]	6078328	1			T1	2		T4	1		T2	2
all_pins[2]	values[0x1]	559	1			T3	1		T77	2		T78	4
all_pins[2]	transitions[0x0=>0x1]	536	1			T3	1		T77	2		T78	2
all_pins[2]	transitions[0x1=>0x0]	109	1			T79	1		T97	2		T98	1
all_pins[3]	values[0x0]	6078755	1			T1	2		T4	1		T2	2
all_pins[3]	values[0x1]	132	1			T78	2		T79	1		T97	3
all_pins[3]	transitions[0x0=>0x1]	105	1			T97	3		T98	1		T99	1
all_pins[3]	transitions[0x1=>0x0]	406	1			T79	2		T98	1		T99	4
all_pins[4]	values[0x0]	6078454	1			T1	2		T4	1		T2	2
all_pins[4]	values[0x1]	433	1			T78	2		T79	3		T98	1
all_pins[4]	transitions[0x0=>0x1]	238	1			T79	1		T98	1		T99	4
all_pins[4]	transitions[0x1=>0x0]	1772	1			T79	1		T97	1		T99	1
all_pins[5]	values[0x0]	6076920	1			T1	2		T4	1		T2	2
all_pins[5]	values[0x1]	1967	1			T78	2		T79	3		T97	1
all_pins[5]	transitions[0x0=>0x1]	1942	1			T78	2		T79	3		T99	2
all_pins[5]	transitions[0x1=>0x0]	635	1			T99	2		T172	1		T206	2
all_pins[6]	values[0x0]	6078227	1			T1	2		T4	1		T2	2
all_pins[6]	values[0x1]	660	1			T97	1		T99	2		T172	3
all_pins[6]	transitions[0x0=>0x1]	376	1			T97	1		T99	2		T172	3
all_pins[6]	transitions[0x1=>0x0]	84	1			T79	1		T98	1		T99	1
all_pins[7]	values[0x0]	6078519	1			T1	2		T4	1		T2	2
all_pins[7]	values[0x1]	368	1			T79	1		T98	1		T99	1
all_pins[7]	transitions[0x0=>0x1]	185	1			T79	1		T98	1		T173	3
all_pins[7]	transitions[0x1=>0x0]	111	1			T77	3		T78	2		T207	2
all_pins[8]	values[0x0]	6078593	1			T1	2		T4	1		T2	2
all_pins[8]	values[0x1]	294	1			T77	3		T78	2		T99	1
all_pins[8]	transitions[0x0=>0x1]	273	1			T77	3		T78	2		T99	1
all_pins[8]	transitions[0x1=>0x0]	79	1			T77	1		T79	4		T97	1
all_pins[9]	values[0x0]	6078787	1			T1	2		T4	1		T2	2
all_pins[9]	values[0x1]	100	1			T77	1		T79	4		T97	1
all_pins[9]	transitions[0x0=>0x1]	79	1			T77	1		T79	4		T97	1
all_pins[9]	transitions[0x1=>0x0]	60	1			T97	2		T98	2		T207	3
all_pins[10]	values[0x0]	6078806	1			T1	2		T4	1		T2	2
all_pins[10]	values[0x1]	81	1			T97	2		T98	2		T207	5
all_pins[10]	transitions[0x0=>0x1]	67	1			T97	1		T98	2		T207	5
all_pins[10]	transitions[0x1=>0x0]	3199	1			T76	1		T77	1		T78	1
all_pins[11]	values[0x0]	6075674	1			T1	2		T4	1		T2	2
all_pins[11]	values[0x1]	3213	1			T76	1		T77	1		T78	1
all_pins[11]	transitions[0x0=>0x1]	3179	1			T76	1		T78	1		T97	1
all_pins[11]	transitions[0x1=>0x0]	486	1			T7	1		T77	2		T79	1