Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	366	1			T15	2		T17	1		T272	2
auto[ReadAddrCrossIntoMailbox]	288	1			T9	2		T15	1		T17	2
auto[ReadAddrCrossOutOfMailbox]	318	1			T9	2		T15	6		T17	4
auto[ReadAddrCrossAllMailbox]	215	1			T9	4		T17	3		T24	4
auto[ReadAddrOutsideMailbox]	3392	1			T9	2		T11	8		T14	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2242

1

T9

5

T11

4

T14

1

auto[1]

2337

1

T9

5

T11

4

T14

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	730	1			T11	2		T14	2		T18	2
read_ops[0x0b]	777	1			T18	2		T15	8		T17	16
read_ops[0x3b]	772	1			T18	8		T15	12		T17	11
read_ops[0x6b]	766	1			T18	2		T15	13		T17	7
read_ops[0xbb]	769	1			T9	6		T18	4		T15	19
read_ops[0xeb]	765	1			T9	4		T11	6		T18	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T20	1		T231	1		T345	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T26	2		T231	2		T345	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T254	1		T212	1		T231	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T30	1		T254	1		T271	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T254	1		T231	4		T277	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T254	1		T246	2		T343	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T227	1		T329	1		T252	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T26	1		T30	1		T231	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	269	1			T11	1		T14	1		T18	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	275	1			T11	1		T14	1		T18	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T26	1		T247	1		T231	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T15	2		T262	1		T245	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T24	1		T28	1		T30	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T24	1		T247	1		T333	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T24	1		T28	1		T30	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T15	1		T17	2		T24	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T24	1		T27	1		T212	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T17	1		T24	1		T28	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	271	1			T18	1		T15	2		T17	6
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	321	1			T18	1		T15	3		T17	7
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T17	1		T272	1		T20	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T272	1		T20	2		T287	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T17	1		T24	1		T29	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T24	1		T27	2		T30	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T24	4		T231	1		T329	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T24	4		T27	1		T29	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T17	1		T272	1		T28	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T272	1		T313	1		T252	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	274	1			T18	4		T15	5		T17	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	314	1			T18	4		T15	7		T17	6
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T287	2		T26	1		T29	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T287	2		T210	1		T260	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T272	1		T26	2		T29	3
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T15	1		T272	1		T26	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T15	1		T261	2		T210	3
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T15	1		T20	1		T26	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T261	1		T30	1		T210	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	32	1			T20	1		T261	1		T30	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	283	1			T18	1		T15	5		T17	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	254	1			T18	1		T15	5		T17	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T287	2		T30	1		T212	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T287	2		T30	1		T210	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T20	1		T261	1		T285	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T26	1		T28	1		T261	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T17	1		T26	1		T261	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T15	2		T28	1		T261	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T9	2		T17	1		T254	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T9	2		T254	1		T212	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	261	1			T9	1		T18	2		T15	5
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	305	1			T9	1		T18	2		T15	12
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T287	3		T29	1		T81	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T287	3		T27	3		T29	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T9	1		T20	1		T30	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T9	1		T17	1		T27	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T9	1		T15	1		T17	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T9	1		T27	1		T260	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T24	1		T272	1		T26	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T24	1		T272	1		T29	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	283	1			T11	3		T18	1		T15	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	282	1			T11	3		T18	1		T15	3