Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3442	1			T15	102		T17	67		T20	40
values[1]	3608	1			T18	30		T15	20		T17	40
values[2]	3661	1			T9	10		T17	20		T307	2
values[3]	3545	1			T15	128		T17	30		T23	2
values[4]	3248	1			T16	12		T17	143		T324	2
values[5]	2903	1			T19	24		T15	71		T17	50
values[6]	4077	1			T4	6		T15	117		T131	14
values[7]	3821	1			T11	10		T14	32		T15	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3625	1			T15	75		T17	20		T331	12
values[1]	3344	1			T15	20		T17	47		T24	22
values[2]	3302	1			T15	83		T17	46		T110	40
values[3]	4310	1			T11	10		T14	32		T15	131
values[4]	3689	1			T15	42		T148	10		T287	18
values[5]	3194	1			T9	10		T16	12		T21	12
values[6]	3084	1			T4	6		T19	24		T15	87
values[7]	3757	1			T18	30		T15	40		T17	163

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27835

1

T4

6

T9

10

T11

10

auto[1]

470

1

T14

10

T15

3

T17

11

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	457	1			T28	20		T325	10		T315	4
auto[0]	values[0]	values[1]	315	1			T20	20		T289	20		T319	14
auto[0]	values[0]	values[2]	322	1			T15	22		T26	58		T30	19
auto[0]	values[0]	values[3]	459	1			T15	60		T20	18		T26	20
auto[0]	values[0]	values[4]	584	1			T28	20		T212	20		T123	46
auto[0]	values[0]	values[5]	327	1			T26	26		T29	30		T322	8
auto[0]	values[0]	values[6]	507	1			T17	20		T30	28		T321	14
auto[0]	values[0]	values[7]	413	1			T15	20		T17	42		T295	22
auto[0]	values[1]	values[0]	451	1			T17	20		T331	12		T210	31
auto[0]	values[1]	values[1]	328	1			T133	34		T27	19		T341	20
auto[0]	values[1]	values[2]	510	1			T17	20		T280	10		T310	10
auto[0]	values[1]	values[3]	780	1			T27	40		T251	53		T231	25
auto[0]	values[1]	values[4]	403	1			T287	18		T332	75		T261	22
auto[0]	values[1]	values[5]	378	1			T21	12		T132	30		T26	20
auto[0]	values[1]	values[6]	275	1			T15	20		T111	10		T20	20
auto[0]	values[1]	values[7]	422	1			T18	30		T20	20		T81	24
auto[0]	values[2]	values[0]	453	1			T253	14		T255	21		T231	72
auto[0]	values[2]	values[1]	385	1			T212	79		T81	20		T123	40
auto[0]	values[2]	values[2]	495	1			T231	20		T123	72		T246	40
auto[0]	values[2]	values[3]	538	1			T17	20		T20	34		T339	34
auto[0]	values[2]	values[4]	403	1			T28	56		T247	18		T231	19
auto[0]	values[2]	values[5]	634	1			T9	10		T307	2		T25	14
auto[0]	values[2]	values[6]	224	1			T210	16		T231	20		T227	24
auto[0]	values[2]	values[7]	459	1			T209	56		T323	10		T346	10
auto[0]	values[3]	values[0]	434	1			T250	10		T338	95		T314	26
auto[0]	values[3]	values[1]	555	1			T20	25		T248	2		T81	28
auto[0]	values[3]	values[2]	453	1			T15	61		T29	20		T342	4
auto[0]	values[3]	values[3]	358	1			T29	20		T347	2		T210	28
auto[0]	values[3]	values[4]	437	1			T148	10		T30	44		T271	20
auto[0]	values[3]	values[5]	289	1			T29	30		T312	2		T330	4
auto[0]	values[3]	values[6]	480	1			T15	67		T26	32		T29	28
auto[0]	values[3]	values[7]	482	1			T17	30		T23	2		T22	14
auto[0]	values[4]	values[0]	288	1			T272	18		T294	28		T210	36
auto[0]	values[4]	values[1]	330	1			T17	45		T28	24		T348	10
auto[0]	values[4]	values[2]	398	1			T28	29		T29	25		T212	23
auto[0]	values[4]	values[3]	739	1			T17	30		T61	6		T20	51
auto[0]	values[4]	values[4]	477	1			T327	24		T349	28		T210	20
auto[0]	values[4]	values[5]	229	1			T16	12		T324	2		T65	22
auto[0]	values[4]	values[6]	373	1			T30	25		T244	17		T229	20
auto[0]	values[4]	values[7]	361	1			T17	64		T350	10		T244	20
auto[0]	values[5]	values[0]	515	1			T340	12		T351	12		T244	28
auto[0]	values[5]	values[1]	346	1			T59	4		T30	29		T210	20
auto[0]	values[5]	values[2]	270	1			T17	26		T352	28		T247	26
auto[0]	values[5]	values[3]	374	1			T15	69		T210	20		T211	14
auto[0]	values[5]	values[4]	251	1			T123	34		T252	20		T262	42
auto[0]	values[5]	values[5]	348	1			T328	4		T237	8		T232	28
auto[0]	values[5]	values[6]	347	1			T19	24		T231	25		T353	2
auto[0]	values[5]	values[7]	407	1			T17	24		T308	20		T30	56
auto[0]	values[6]	values[0]	695	1			T15	74		T30	23		T212	30
auto[0]	values[6]	values[1]	520	1			T123	20		T329	31		T338	20
auto[0]	values[6]	values[2]	451	1			T110	40		T249	20		T354	6
auto[0]	values[6]	values[3]	529	1			T28	29		T30	31		T326	16
auto[0]	values[6]	values[4]	621	1			T15	42		T30	20		T210	57
auto[0]	values[6]	values[5]	445	1			T210	90		T260	22		T212	49
auto[0]	values[6]	values[6]	331	1			T4	6		T131	14		T27	57
auto[0]	values[6]	values[7]	433	1			T64	12		T276	10		T247	20
auto[0]	values[7]	values[0]	276	1			T262	20		T355	14		T335	20
auto[0]	values[7]	values[1]	514	1			T15	20		T24	22		T20	20
auto[0]	values[7]	values[2]	341	1			T239	8		T356	12		T210	20
auto[0]	values[7]	values[3]	460	1			T11	10		T14	22		T20	42
auto[0]	values[7]	values[4]	465	1			T241	6		T357	2		T358	4
auto[0]	values[7]	values[5]	493	1			T236	12		T359	30		T244	36
auto[0]	values[7]	values[6]	498	1			T17	91		T27	20		T28	25
auto[0]	values[7]	values[7]	700	1			T15	20		T20	19		T26	50
auto[1]	values[0]	values[0]	7	1			T212	1		T338	3		T360	1
auto[1]	values[0]	values[1]	5	1			T262	1		T360	3		T361	1
auto[1]	values[0]	values[2]	9	1			T26	2		T30	1		T210	1
auto[1]	values[0]	values[3]	6	1			T20	2		T230	4		-	-
auto[1]	values[0]	values[4]	4	1			T252	1		T335	1		T362	1
auto[1]	values[0]	values[5]	7	1			T314	1		T335	2		T363	1
auto[1]	values[0]	values[6]	12	1			T17	2		T336	2		T364	3
auto[1]	values[0]	values[7]	8	1			T17	3		T245	1		T365	1
auto[1]	values[1]	values[0]	11	1			T210	1		T229	2		T336	2
auto[1]	values[1]	values[1]	4	1			T27	1		T252	1		T269	2
auto[1]	values[1]	values[2]	10	1			T366	3		T269	3		T367	2
auto[1]	values[1]	values[3]	7	1			T229	2		T230	4		T368	1
auto[1]	values[1]	values[4]	2	1			T362	2		-	-		-	-
auto[1]	values[1]	values[5]	5	1			T246	1		T338	2		T369	2
auto[1]	values[1]	values[6]	3	1			T262	2		T361	1		-	-
auto[1]	values[1]	values[7]	19	1			T370	10		T229	4		T335	1
auto[1]	values[2]	values[0]	8	1			T255	1		T231	3		T246	1
auto[1]	values[2]	values[1]	13	1			T212	6		T329	2		T335	1
auto[1]	values[2]	values[2]	5	1			T123	1		T371	2		T372	2
auto[1]	values[2]	values[3]	7	1			T20	2		T247	2		T369	2
auto[1]	values[2]	values[4]	6	1			T28	1		T247	2		T231	1
auto[1]	values[2]	values[5]	14	1			T25	2		T238	2		T229	1
auto[1]	values[2]	values[6]	5	1			T210	4		T373	1		-	-
auto[1]	values[2]	values[7]	12	1			T374	2		T365	1		T375	1
auto[1]	values[3]	values[0]	6	1			T374	1		T376	2		T377	2
auto[1]	values[3]	values[1]	4	1			T20	2		T227	2		-	-
auto[1]	values[3]	values[2]	5	1			T231	1		T338	1		T343	1
auto[1]	values[3]	values[3]	7	1			T262	1		T245	1		T378	1
auto[1]	values[3]	values[4]	12	1			T30	5		T262	1		T371	1
auto[1]	values[3]	values[5]	6	1			T210	1		T269	1		T379	1
auto[1]	values[3]	values[6]	6	1			T26	2		T288	2		T123	1
auto[1]	values[3]	values[7]	11	1			T262	2		T364	5		T230	2
auto[1]	values[4]	values[0]	3	1			T231	2		T329	1		-	-
auto[1]	values[4]	values[1]	8	1			T17	2		T28	1		T338	4
auto[1]	values[4]	values[2]	12	1			T29	1		T212	2		T227	2
auto[1]	values[4]	values[3]	13	1			T17	2		T20	3		T212	2
auto[1]	values[4]	values[4]	7	1			T212	5		T245	2		-	-
auto[1]	values[4]	values[5]	1	1			T81	1		-	-		-	-
auto[1]	values[4]	values[6]	5	1			T30	1		T244	3		T371	1
auto[1]	values[4]	values[7]	4	1			T380	1		T360	3		-	-
auto[1]	values[5]	values[0]	8	1			T340	2		T351	4		T252	2
auto[1]	values[5]	values[1]	1	1			T373	1		-	-		-	-
auto[1]	values[5]	values[2]	3	1			T246	1		T245	2		-	-
auto[1]	values[5]	values[3]	17	1			T15	2		T211	8		T247	1
auto[1]	values[5]	values[4]	4	1			T262	1		T269	1		T279	1
auto[1]	values[5]	values[5]	3	1			T210	1		T314	2		-	-
auto[1]	values[5]	values[6]	4	1			T231	1		T362	1		T374	2
auto[1]	values[5]	values[7]	5	1			T246	3		T279	1		T372	1
auto[1]	values[6]	values[0]	9	1			T15	1		T364	2		T381	2
auto[1]	values[6]	values[1]	10	1			T329	1		T245	2		T269	1
auto[1]	values[6]	values[2]	6	1			T81	2		T252	1		T269	1
auto[1]	values[6]	values[3]	4	1			T30	1		T262	2		T382	1
auto[1]	values[6]	values[4]	9	1			T247	1		T329	2		T374	2
auto[1]	values[6]	values[5]	7	1			T210	1		T383	6		-	-
auto[1]	values[6]	values[6]	2	1			T27	2		-	-		-	-
auto[1]	values[6]	values[7]	5	1			T384	1		T269	3		T385	1
auto[1]	values[7]	values[0]	4	1			T386	1		T372	3		-	-
auto[1]	values[7]	values[1]	6	1			T210	3		T244	1		T336	2
auto[1]	values[7]	values[2]	12	1			T227	4		T252	1		T371	3
auto[1]	values[7]	values[3]	12	1			T14	10		T387	1		T379	1
auto[1]	values[7]	values[4]	4	1			T379	1		T369	1		T373	2
auto[1]	values[7]	values[5]	8	1			T230	6		T388	1		T377	1
auto[1]	values[7]	values[6]	12	1			T17	2		T247	2		T363	1
auto[1]	values[7]	values[7]	16	1			T20	1		T26	4		T277	1