Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2548

1

T3

14

T13

6

T31

8

auto[1]

2441

1

T3

13

T13

2

T31

10

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2374

1

T3

27

T13

7

T5

24

auto[1]

2615

1

T13

1

T31

18

T35

40

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4100

1

T3

18

T13

7

T31

18

auto[1]

889

1

T3

9

T13

1

T5

10

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	989	1			T3	4		T13	1		T31	5
valid[1]	1012	1			T3	8		T13	2		T31	1
valid[2]	1039	1			T3	5		T13	3		T35	6
valid[3]	928	1			T3	6		T13	1		T31	4
valid[4]	1021	1			T3	4		T13	1		T31	8

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	161	1			T3	1		T13	1		T5	1
auto[0]	auto[0]	valid[0]	auto[1]	260	1			T31	3		T35	3		T46	1
auto[0]	auto[0]	valid[1]	auto[0]	138	1			T3	4		T13	2		T15	1
auto[0]	auto[0]	valid[1]	auto[1]	275	1			T35	5		T46	3		T114	3
auto[0]	auto[0]	valid[2]	auto[0]	160	1			T3	2		T13	1		T5	2
auto[0]	auto[0]	valid[2]	auto[1]	273	1			T35	4		T46	5		T125	6
auto[0]	auto[0]	valid[3]	auto[0]	123	1			T3	2		T13	1		T5	2
auto[0]	auto[0]	valid[3]	auto[1]	262	1			T31	4		T35	7		T46	1
auto[0]	auto[0]	valid[4]	auto[0]	172	1			T15	1		T17	1		T113	1
auto[0]	auto[0]	valid[4]	auto[1]	271	1			T31	1		T35	4		T46	3
auto[0]	auto[1]	valid[0]	auto[0]	138	1			T3	1		T5	1		T113	2
auto[0]	auto[1]	valid[0]	auto[1]	253	1			T31	2		T35	3		T46	7
auto[0]	auto[1]	valid[1]	auto[0]	156	1			T3	3		T5	1		T116	4
auto[0]	auto[1]	valid[1]	auto[1]	270	1			T31	1		T35	5		T46	4
auto[0]	auto[1]	valid[2]	auto[0]	147	1			T3	2		T5	4		T15	2
auto[0]	auto[1]	valid[2]	auto[1]	266	1			T13	1		T35	2		T46	2
auto[0]	auto[1]	valid[3]	auto[0]	121	1			T3	1		T5	1		T15	1
auto[0]	auto[1]	valid[3]	auto[1]	249	1			T35	5		T46	4		T114	1
auto[0]	auto[1]	valid[4]	auto[0]	169	1			T3	2		T13	1		T5	2
auto[0]	auto[1]	valid[4]	auto[1]	236	1			T31	7		T35	2		T46	5
auto[1]	auto[0]	valid[0]	auto[0]	85	1			T3	1		T17	1		T113	1
auto[1]	auto[0]	valid[1]	auto[0]	98	1			T3	1		T113	1		T116	2
auto[1]	auto[0]	valid[2]	auto[0]	93	1			T3	1		T13	1		T5	1
auto[1]	auto[0]	valid[3]	auto[0]	83	1			T3	2		T113	1		T116	1
auto[1]	auto[0]	valid[4]	auto[0]	94	1			T5	1		T17	2		T116	1
auto[1]	auto[1]	valid[0]	auto[0]	92	1			T3	1		T5	1		T17	1
auto[1]	auto[1]	valid[1]	auto[0]	75	1			T5	2		T113	1		T116	1
auto[1]	auto[1]	valid[2]	auto[0]	100	1			T113	1		T108	2		T26	2
auto[1]	auto[1]	valid[3]	auto[0]	90	1			T3	1		T5	3		T17	1
auto[1]	auto[1]	valid[4]	auto[0]	79	1			T3	2		T5	2		T15	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal