Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	72	2	70	97.22

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	72	2	70	97.22	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	423	1			T76	4		T77	4		T78	4
all_values[1]	423	1			T76	4		T77	4		T78	4
all_values[2]	423	1			T76	4		T77	4		T78	4
all_values[3]	423	1			T76	4		T77	4		T78	4
all_values[4]	423	1			T76	4		T77	4		T78	4
all_values[5]	423	1			T76	4		T77	4		T78	4
all_values[6]	423	1			T76	4		T77	4		T78	4
all_values[7]	423	1			T76	4		T77	4		T78	4
all_values[8]	423	1			T76	4		T77	4		T78	4
all_values[9]	423	1			T76	4		T77	4		T78	4
all_values[10]	423	1			T76	4		T77	4		T78	4
all_values[11]	423	1			T76	4		T77	4		T78	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2837

1

T76

30

T77

33

T78

31

auto[1]

2239

1

T76

18

T77

15

T78

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1977

1

T76

31

T77

16

T78

23

auto[1]

3099

1

T76

17

T77

32

T78

25

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2888

1

T76

35

T77

26

T78

31

auto[1]

2188

1

T76

13

T77

22

T78

17

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	2	70	97.22	2
Automatically Generated Cross Bins	72	2	70	97.22	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[11]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	81	1			T77	1		T78	1		T79	2
all_values[0]	auto[0]	auto[0]	auto[1]	46	1			T76	2		T173	1		T206	1
all_values[0]	auto[0]	auto[1]	auto[0]	57	1			T78	2		T79	1		T98	1
all_values[0]	auto[0]	auto[1]	auto[1]	47	1			T77	1		T97	4		T98	2
all_values[0]	auto[1]	auto[0]	auto[1]	110	1			T76	2		T77	1		T78	1
all_values[0]	auto[1]	auto[1]	auto[1]	82	1			T77	1		T79	1		T98	3
all_values[1]	auto[0]	auto[0]	auto[0]	91	1			T77	1		T78	1		T79	3
all_values[1]	auto[0]	auto[0]	auto[1]	48	1			T76	2		T97	2		T98	1
all_values[1]	auto[0]	auto[1]	auto[0]	80	1			T78	3		T97	1		T99	1
all_values[1]	auto[0]	auto[1]	auto[1]	25	1			T98	3		T173	2		T206	1
all_values[1]	auto[1]	auto[0]	auto[1]	109	1			T76	2		T77	3		T79	1
all_values[1]	auto[1]	auto[1]	auto[1]	70	1			T97	2		T98	2		T172	1
all_values[2]	auto[0]	auto[0]	auto[0]	82	1			T76	3		T98	2		T99	2
all_values[2]	auto[0]	auto[0]	auto[1]	35	1			T77	1		T98	1		T99	1
all_values[2]	auto[0]	auto[1]	auto[0]	71	1			T99	1		T173	1		T197	1
all_values[2]	auto[0]	auto[1]	auto[1]	50	1			T77	1		T78	2		T79	3
all_values[2]	auto[1]	auto[0]	auto[1]	109	1			T77	2		T78	1		T97	3
all_values[2]	auto[1]	auto[1]	auto[1]	76	1			T76	1		T78	1		T79	1
all_values[3]	auto[0]	auto[0]	auto[0]	80	1			T78	1		T79	2		T97	3
all_values[3]	auto[0]	auto[0]	auto[1]	45	1			T77	3		T98	1		T99	1
all_values[3]	auto[0]	auto[1]	auto[0]	62	1			T76	3		T78	1		T97	1
all_values[3]	auto[0]	auto[1]	auto[1]	54	1			T78	1		T97	2		T98	1
all_values[3]	auto[1]	auto[0]	auto[1]	97	1			T77	1		T79	2		T97	1
all_values[3]	auto[1]	auto[1]	auto[1]	85	1			T76	1		T78	1		T98	1
all_values[4]	auto[0]	auto[0]	auto[0]	84	1			T76	2		T77	1		T97	4
all_values[4]	auto[0]	auto[0]	auto[1]	43	1			T207	2		T206	1		T208	1
all_values[4]	auto[0]	auto[1]	auto[0]	72	1			T76	1		T79	1		T97	2
all_values[4]	auto[0]	auto[1]	auto[1]	40	1			T78	1		T79	1		T99	3
all_values[4]	auto[1]	auto[0]	auto[1]	110	1			T76	1		T77	2		T78	3
all_values[4]	auto[1]	auto[1]	auto[1]	74	1			T77	1		T79	2		T97	1
all_values[5]	auto[0]	auto[0]	auto[0]	89	1			T76	2		T77	1		T78	1
all_values[5]	auto[0]	auto[0]	auto[1]	48	1			T77	1		T78	1		T97	2
all_values[5]	auto[0]	auto[1]	auto[0]	56	1			T76	1		T98	3		T99	2
all_values[5]	auto[0]	auto[1]	auto[1]	42	1			T78	1		T79	2		T99	1
all_values[5]	auto[1]	auto[0]	auto[1]	98	1			T76	1		T77	2		T78	1
all_values[5]	auto[1]	auto[1]	auto[1]	90	1			T79	2		T97	2		T99	3
all_values[6]	auto[0]	auto[0]	auto[0]	98	1			T76	2		T77	3		T78	3
all_values[6]	auto[0]	auto[0]	auto[1]	46	1			T173	1		T207	3		T206	1
all_values[6]	auto[0]	auto[1]	auto[0]	66	1			T76	1		T77	1		T78	1
all_values[6]	auto[0]	auto[1]	auto[1]	42	1			T97	1		T99	2		T172	1
all_values[6]	auto[1]	auto[0]	auto[1]	109	1			T79	3		T97	2		T98	3
all_values[6]	auto[1]	auto[1]	auto[1]	62	1			T76	1		T98	1		T99	1
all_values[7]	auto[0]	auto[0]	auto[0]	86	1			T77	1		T78	1		T79	2
all_values[7]	auto[0]	auto[0]	auto[1]	30	1			T78	1		T98	1		T197	1
all_values[7]	auto[0]	auto[1]	auto[0]	79	1			T76	4		T77	2		T79	1
all_values[7]	auto[0]	auto[1]	auto[1]	39	1			T173	1		T197	1		T207	1
all_values[7]	auto[1]	auto[0]	auto[1]	98	1			T77	1		T78	2		T97	1
all_values[7]	auto[1]	auto[1]	auto[1]	91	1			T79	1		T98	1		T99	1
all_values[8]	auto[0]	auto[0]	auto[0]	104	1			T76	2		T77	1		T78	1
all_values[8]	auto[0]	auto[0]	auto[1]	44	1			T97	1		T99	2		T172	1
all_values[8]	auto[0]	auto[1]	auto[0]	67	1			T76	1		T97	2		T98	2
all_values[8]	auto[0]	auto[1]	auto[1]	36	1			T77	1		T78	1		T206	2
all_values[8]	auto[1]	auto[0]	auto[1]	98	1			T76	1		T77	1		T78	2
all_values[8]	auto[1]	auto[1]	auto[1]	74	1			T77	1		T99	1		T197	1
all_values[9]	auto[0]	auto[0]	auto[0]	92	1			T76	2		T78	2		T97	2
all_values[9]	auto[0]	auto[0]	auto[1]	36	1			T98	1		T99	2		T173	1
all_values[9]	auto[0]	auto[1]	auto[0]	60	1			T77	1		T78	1		T97	1
all_values[9]	auto[0]	auto[1]	auto[1]	41	1			T77	1		T79	1		T99	1
all_values[9]	auto[1]	auto[0]	auto[1]	106	1			T76	2		T77	1		T78	1
all_values[9]	auto[1]	auto[1]	auto[1]	88	1			T77	1		T79	3		T97	1
all_values[10]	auto[0]	auto[0]	auto[0]	104	1			T76	1		T77	1		T78	2
all_values[10]	auto[0]	auto[0]	auto[1]	42	1			T77	1		T79	1		T98	1
all_values[10]	auto[0]	auto[1]	auto[0]	76	1			T76	3		T97	2		T99	1
all_values[10]	auto[0]	auto[1]	auto[1]	32	1			T97	1		T173	1		T207	2
all_values[10]	auto[1]	auto[0]	auto[1]	102	1			T77	1		T78	2		T79	2
all_values[10]	auto[1]	auto[1]	auto[1]	67	1			T77	1		T97	2		T98	2
all_values[11]	auto[0]	auto[0]	auto[0]	132	1			T76	2		T77	2		T78	1
all_values[11]	auto[0]	auto[1]	auto[0]	108	1			T76	1		T78	1		T97	3
all_values[11]	auto[1]	auto[0]	auto[1]	105	1			T76	1		T78	2		T79	1
all_values[11]	auto[1]	auto[1]	auto[1]	78	1			T77	2		T97	1		T98	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal