Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60279

1

T3

673

T13

188

T5

574

auto[1]

27855

1

T3

4

T13

29

T31

18

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65903

1

T3

429

T13

142

T31

18

auto[1]

22231

1

T3

248

T13

75

T5

209

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	45514	1			T3	325		T13	111		T31	18
others[1]	7341	1			T3	65		T13	21		T35	49
others[2]	7493	1			T3	66		T13	19		T35	57
others[3]	8309	1			T3	60		T13	24		T35	42
interest[1]	4873	1			T3	38		T13	12		T35	39
interest[4]	29781	1			T3	214		T13	80		T31	18
interest[64]	14604	1			T3	123		T13	30		T35	89

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	19485	1			T3	201		T13	57		T5	178
auto[0]	auto[0]	others[1]	3205	1			T3	42		T13	8		T5	35
auto[0]	auto[0]	others[2]	3316	1			T3	42		T13	10		T5	42
auto[0]	auto[0]	others[3]	3587	1			T3	39		T13	14		T5	34
auto[0]	auto[0]	interest[1]	2150	1			T3	26		T13	7		T5	20
auto[0]	auto[0]	interest[4]	12678	1			T3	129		T13	38		T5	117
auto[0]	auto[0]	interest[64]	6305	1			T3	75		T13	17		T5	56
auto[0]	auto[1]	others[0]	14559	1			T3	2		T13	16		T31	18
auto[0]	auto[1]	others[1]	2319	1			T3	2		T13	3		T35	49
auto[0]	auto[1]	others[2]	2260	1			T13	3		T35	57		T46	40
auto[0]	auto[1]	others[3]	2606	1			T13	1		T35	42		T46	35
auto[0]	auto[1]	interest[1]	1502	1			T13	1		T35	39		T46	20
auto[0]	auto[1]	interest[4]	9615	1			T3	1		T13	9		T31	18
auto[0]	auto[1]	interest[64]	4609	1			T13	5		T35	89		T46	67
auto[1]	auto[0]	others[0]	11470	1			T3	122		T13	38		T5	116
auto[1]	auto[0]	others[1]	1817	1			T3	21		T13	10		T5	15
auto[1]	auto[0]	others[2]	1917	1			T3	24		T13	6		T5	18
auto[1]	auto[0]	others[3]	2116	1			T3	21		T13	9		T5	20
auto[1]	auto[0]	interest[1]	1221	1			T3	12		T13	4		T5	8
auto[1]	auto[0]	interest[4]	7488	1			T3	84		T13	33		T5	79
auto[1]	auto[0]	interest[64]	3690	1			T3	48		T13	8		T5	32

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal