Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.11 99.02 96.33 98.63 92.06 98.07 95.86 99.76


Total test records in report: 1782
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T1753 /workspace/coverage/default/1.spi_device_mem_parity.2298275216 Jan 03 01:51:05 PM PST 24 Jan 03 01:51:12 PM PST 24 37794444 ps
T1754 /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2605175300 Jan 03 02:02:52 PM PST 24 Jan 03 02:07:12 PM PST 24 277103091615 ps
T1755 /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2042035184 Jan 03 01:50:08 PM PST 24 Jan 03 01:50:50 PM PST 24 11985366172 ps
T385 /workspace/coverage/default/13.spi_device_stress_all.3711396759 Jan 03 01:56:19 PM PST 24 Jan 03 02:09:30 PM PST 24 62838561063 ps
T1756 /workspace/coverage/default/2.spi_device_abort.1507184311 Jan 03 01:50:48 PM PST 24 Jan 03 01:50:58 PM PST 24 16032740 ps
T1757 /workspace/coverage/default/20.spi_device_dummy_item_extra_dly.1120824969 Jan 03 01:57:28 PM PST 24 Jan 03 02:50:58 PM PST 24 131033338944 ps
T1758 /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1108247216 Jan 03 01:57:20 PM PST 24 Jan 03 01:57:30 PM PST 24 1250211767 ps
T1759 /workspace/coverage/default/11.spi_device_stress_all.1449400266 Jan 03 01:56:15 PM PST 24 Jan 03 02:18:47 PM PST 24 549002321540 ps
T1760 /workspace/coverage/default/40.spi_device_extreme_fifo_size.2557775609 Jan 03 02:01:38 PM PST 24 Jan 03 02:31:30 PM PST 24 186363627312 ps
T1761 /workspace/coverage/default/11.spi_device_rx_timeout.1278096071 Jan 03 01:54:41 PM PST 24 Jan 03 01:54:57 PM PST 24 862373154 ps
T1762 /workspace/coverage/default/49.spi_device_dummy_item_extra_dly.3219171690 Jan 03 02:03:35 PM PST 24 Jan 03 02:12:08 PM PST 24 240339740884 ps
T1763 /workspace/coverage/default/39.spi_device_tx_async_fifo_reset.1301542338 Jan 03 02:00:53 PM PST 24 Jan 03 02:01:07 PM PST 24 54866594 ps
T1764 /workspace/coverage/default/32.spi_device_rx_async_fifo_reset.2719168126 Jan 03 01:59:39 PM PST 24 Jan 03 01:59:48 PM PST 24 72866054 ps
T1765 /workspace/coverage/default/45.spi_device_csb_read.2564822759 Jan 03 02:03:13 PM PST 24 Jan 03 02:03:23 PM PST 24 46712748 ps
T1766 /workspace/coverage/default/30.spi_device_rx_async_fifo_reset.306282749 Jan 03 01:59:33 PM PST 24 Jan 03 01:59:41 PM PST 24 45831381 ps
T1767 /workspace/coverage/default/14.spi_device_csb_read.1243647700 Jan 03 01:56:19 PM PST 24 Jan 03 01:56:31 PM PST 24 74272128 ps
T1768 /workspace/coverage/default/18.spi_device_txrx.453163055 Jan 03 01:57:03 PM PST 24 Jan 03 02:02:20 PM PST 24 136794008873 ps
T1769 /workspace/coverage/default/30.spi_device_tpm_rw.540066614 Jan 03 01:59:34 PM PST 24 Jan 03 01:59:48 PM PST 24 668785033 ps
T1770 /workspace/coverage/default/43.spi_device_csb_read.317636588 Jan 03 02:01:35 PM PST 24 Jan 03 02:01:53 PM PST 24 19761228 ps
T1771 /workspace/coverage/default/0.spi_device_mailbox.2863163296 Jan 03 01:50:33 PM PST 24 Jan 03 01:50:45 PM PST 24 405319176 ps
T1772 /workspace/coverage/default/6.spi_device_mailbox.1884876408 Jan 03 01:51:26 PM PST 24 Jan 03 01:51:50 PM PST 24 7786729790 ps
T1773 /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3260113068 Jan 03 01:57:26 PM PST 24 Jan 03 01:57:40 PM PST 24 2900986241 ps
T1774 /workspace/coverage/default/24.spi_device_txrx.3350903361 Jan 03 01:58:40 PM PST 24 Jan 03 02:03:23 PM PST 24 145841877725 ps
T372 /workspace/coverage/default/16.spi_device_flash_and_tpm.3781763602 Jan 03 01:57:23 PM PST 24 Jan 03 02:04:53 PM PST 24 56660178032 ps
T1775 /workspace/coverage/default/9.spi_device_abort.3971156964 Jan 03 01:54:37 PM PST 24 Jan 03 01:54:42 PM PST 24 16537462 ps
T1776 /workspace/coverage/default/22.spi_device_tpm_sts_read.3293107061 Jan 03 01:58:40 PM PST 24 Jan 03 01:58:53 PM PST 24 16182009 ps
T1777 /workspace/coverage/default/19.spi_device_alert_test.4269961095 Jan 03 01:57:25 PM PST 24 Jan 03 01:57:35 PM PST 24 39230911 ps
T1778 /workspace/coverage/default/12.spi_device_byte_transfer.1909944645 Jan 03 01:56:16 PM PST 24 Jan 03 01:56:28 PM PST 24 61165481 ps
T1779 /workspace/coverage/default/5.spi_device_dummy_item_extra_dly.272448018 Jan 03 01:51:28 PM PST 24 Jan 03 02:13:08 PM PST 24 54684200543 ps
T1780 /workspace/coverage/default/43.spi_device_tpm_all.1087450967 Jan 03 02:01:32 PM PST 24 Jan 03 02:02:09 PM PST 24 10848355594 ps
T1781 /workspace/coverage/default/40.spi_device_fifo_full.1118409662 Jan 03 02:01:32 PM PST 24 Jan 03 02:17:14 PM PST 24 15816854088 ps
T1782 /workspace/coverage/default/11.spi_device_byte_transfer.4060754713 Jan 03 01:54:43 PM PST 24 Jan 03 01:54:56 PM PST 24 476479604 ps

Test location /workspace/coverage/default/34.spi_device_stress_all.150578607
Short name T3
Test name
Test status
Simulation time 400043776989 ps
CPU time 427.85 seconds
Started Jan 03 02:01:20 PM PST 24
Finished Jan 03 02:08:43 PM PST 24
Peak memory 289168 kb
Host smart-123a47ce-b99c-4943-bbd7-8e72cbf533ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150578607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.150578607
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1372958921
Short name T15
Test name
Test status
Simulation time 145417530596 ps
CPU time 344.75 seconds
Started Jan 03 01:54:41 PM PST 24
Finished Jan 03 02:00:35 PM PST 24
Peak memory 274420 kb
Host smart-4b2ead0e-87d0-4dd3-9fa9-a7e87d300bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372958921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1372958921
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1711600861
Short name T71
Test name
Test status
Simulation time 2796460756 ps
CPU time 16.22 seconds
Started Jan 03 01:29:52 PM PST 24
Finished Jan 03 01:30:41 PM PST 24
Peak memory 215964 kb
Host smart-7395cdd4-1215-4a03-8f33-1ca5cfd11c33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711600861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1711600861
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.40842210
Short name T28
Test name
Test status
Simulation time 20417123499 ps
CPU time 438.68 seconds
Started Jan 03 02:01:34 PM PST 24
Finished Jan 03 02:09:10 PM PST 24
Peak memory 331588 kb
Host smart-a611cdd2-21f2-4493-834f-2b295344e699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40842210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress
_all.40842210
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3987493322
Short name T99
Test name
Test status
Simulation time 22332201 ps
CPU time 0.75 seconds
Started Jan 03 01:28:05 PM PST 24
Finished Jan 03 01:28:16 PM PST 24
Peak memory 204920 kb
Host smart-b27bd517-8d3c-4f42-8e22-583d9b94252c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987493322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
987493322
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2622302250
Short name T231
Test name
Test status
Simulation time 113915043350 ps
CPU time 676.65 seconds
Started Jan 03 02:00:48 PM PST 24
Finished Jan 03 02:12:16 PM PST 24
Peak memory 267420 kb
Host smart-22711980-e384-4812-892d-3e370f7ee38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622302250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2622302250
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1754425673
Short name T26
Test name
Test status
Simulation time 83761549614 ps
CPU time 120.2 seconds
Started Jan 03 01:59:30 PM PST 24
Finished Jan 03 02:01:35 PM PST 24
Peak memory 257860 kb
Host smart-10fb332d-8f78-4207-8b3c-b5f84e25a053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754425673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1754425673
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.1264761463
Short name T577
Test name
Test status
Simulation time 17347145 ps
CPU time 0.75 seconds
Started Jan 03 01:54:37 PM PST 24
Finished Jan 03 01:54:43 PM PST 24
Peak memory 216736 kb
Host smart-3f7a01aa-567e-432d-95e3-0ae8b45a2971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264761463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.1264761463
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3017297675
Short name T169
Test name
Test status
Simulation time 312019782 ps
CPU time 2.71 seconds
Started Jan 03 01:28:09 PM PST 24
Finished Jan 03 01:28:21 PM PST 24
Peak memory 215912 kb
Host smart-6610f9fc-a870-473d-8536-b405bfe1eb8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017297675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
017297675
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2062204787
Short name T135
Test name
Test status
Simulation time 4293194113 ps
CPU time 5.94 seconds
Started Jan 03 01:28:08 PM PST 24
Finished Jan 03 01:28:24 PM PST 24
Peak memory 216112 kb
Host smart-fb4ad78b-558a-42ac-b05e-3d88e324121e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062204787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
062204787
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3160030739
Short name T27
Test name
Test status
Simulation time 19746757921 ps
CPU time 136.5 seconds
Started Jan 03 01:58:34 PM PST 24
Finished Jan 03 02:00:55 PM PST 24
Peak memory 268280 kb
Host smart-98969c77-9b79-437a-be26-6a27ac363452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160030739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3160030739
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3915024729
Short name T20
Test name
Test status
Simulation time 11982489372 ps
CPU time 163.41 seconds
Started Jan 03 01:54:39 PM PST 24
Finished Jan 03 01:57:31 PM PST 24
Peak memory 264988 kb
Host smart-3a1ce83a-f917-42ad-b927-5db4d86dbf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915024729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3915024729
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_rx_timeout.3021848047
Short name T631
Test name
Test status
Simulation time 11429237026 ps
CPU time 6.09 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 01:56:35 PM PST 24
Peak memory 216900 kb
Host smart-b10ebb47-d022-4374-bab6-afc7b76cf3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021848047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_rx_timeout.3021848047
Directory /workspace/14.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2594499701
Short name T210
Test name
Test status
Simulation time 96485999342 ps
CPU time 467.58 seconds
Started Jan 03 02:03:08 PM PST 24
Finished Jan 03 02:11:05 PM PST 24
Peak memory 282428 kb
Host smart-192b5c5a-dd2e-4f47-90fa-f9d40d048f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594499701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2594499701
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4236370257
Short name T10
Test name
Test status
Simulation time 26763141411 ps
CPU time 18.11 seconds
Started Jan 03 01:58:34 PM PST 24
Finished Jan 03 01:58:56 PM PST 24
Peak memory 249760 kb
Host smart-277cb5ec-431d-4f9f-82ad-f3d0604e54da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236370257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4236370257
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2550378332
Short name T206
Test name
Test status
Simulation time 31090286 ps
CPU time 0.75 seconds
Started Jan 03 01:30:00 PM PST 24
Finished Jan 03 01:30:51 PM PST 24
Peak memory 204912 kb
Host smart-5ca0027d-42f0-4d1d-83d2-dbc750b86cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550378332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2550378332
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.85655132
Short name T262
Test name
Test status
Simulation time 163096583839 ps
CPU time 377.36 seconds
Started Jan 03 01:50:35 PM PST 24
Finished Jan 03 01:56:59 PM PST 24
Peak memory 281720 kb
Host smart-e2305e73-bc95-4cae-9326-a286cbdd2dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85655132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.85655132
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2188882303
Short name T44
Test name
Test status
Simulation time 138686772682 ps
CPU time 2544.76 seconds
Started Jan 03 01:57:23 PM PST 24
Finished Jan 03 02:39:55 PM PST 24
Peak memory 466192 kb
Host smart-080564b0-85b0-45e8-a2f6-8aede0a64233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188882303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2188882303
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2557752468
Short name T247
Test name
Test status
Simulation time 239277167805 ps
CPU time 2464.76 seconds
Started Jan 03 01:51:29 PM PST 24
Finished Jan 03 02:32:56 PM PST 24
Peak memory 333896 kb
Host smart-4d821e3f-eb71-45b6-b89a-8a5b89eb4741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557752468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2557752468
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.4104133552
Short name T212
Test name
Test status
Simulation time 40309093409 ps
CPU time 247.47 seconds
Started Jan 03 01:52:29 PM PST 24
Finished Jan 03 01:56:44 PM PST 24
Peak memory 266128 kb
Host smart-6e22ec24-8324-435e-a0ea-3d7e82db669f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104133552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.4104133552
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_extreme_fifo_size.365311632
Short name T8
Test name
Test status
Simulation time 62297843424 ps
CPU time 848.7 seconds
Started Jan 03 02:03:27 PM PST 24
Finished Jan 03 02:18:04 PM PST 24
Peak memory 218196 kb
Host smart-112407db-e4e7-4de8-95d1-558c7e742a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365311632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_extreme_fifo_size.365311632
Directory /workspace/48.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1307706521
Short name T104
Test name
Test status
Simulation time 314255286 ps
CPU time 1.2 seconds
Started Jan 03 01:50:47 PM PST 24
Finished Jan 03 01:50:57 PM PST 24
Peak memory 236996 kb
Host smart-e55e124c-5f93-4be3-9912-d33f750569c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307706521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1307706521
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3141207618
Short name T230
Test name
Test status
Simulation time 8005146095 ps
CPU time 129.82 seconds
Started Jan 03 01:59:33 PM PST 24
Finished Jan 03 02:01:48 PM PST 24
Peak memory 282552 kb
Host smart-c234e592-a8f8-4ca7-b35b-84ec5387eaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141207618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3141207618
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1972280604
Short name T150
Test name
Test status
Simulation time 110146792572 ps
CPU time 684.03 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 02:07:54 PM PST 24
Peak memory 360248 kb
Host smart-a1a7f460-026a-4378-abac-6b22c7f9e4c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972280604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1972280604
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1211279756
Short name T252
Test name
Test status
Simulation time 57670796040 ps
CPU time 300.8 seconds
Started Jan 03 02:01:22 PM PST 24
Finished Jan 03 02:06:38 PM PST 24
Peak memory 268396 kb
Host smart-70509167-43d4-4943-9114-3d8aecac3895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211279756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1211279756
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3424995837
Short name T30
Test name
Test status
Simulation time 96533420599 ps
CPU time 748.12 seconds
Started Jan 03 01:51:53 PM PST 24
Finished Jan 03 02:04:35 PM PST 24
Peak memory 302292 kb
Host smart-a7153a40-88fb-447e-924a-f875f8fb4ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424995837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3424995837
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_bit_transfer.723651678
Short name T519
Test name
Test status
Simulation time 465453274 ps
CPU time 2.88 seconds
Started Jan 03 01:54:41 PM PST 24
Finished Jan 03 01:54:53 PM PST 24
Peak memory 216888 kb
Host smart-276a3785-4068-43d4-89ad-ab1f3901e6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723651678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_bit_transfer.723651678
Directory /workspace/11.spi_device_bit_transfer/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3514657789
Short name T97
Test name
Test status
Simulation time 18772921 ps
CPU time 0.74 seconds
Started Jan 03 01:28:56 PM PST 24
Finished Jan 03 01:29:01 PM PST 24
Peak memory 204884 kb
Host smart-e4e6ecb0-8d94-4dc3-9420-3c7b78ae39ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514657789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3514657789
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.111753461
Short name T374
Test name
Test status
Simulation time 31015740592 ps
CPU time 232.23 seconds
Started Jan 03 01:57:27 PM PST 24
Finished Jan 03 02:01:28 PM PST 24
Peak memory 274436 kb
Host smart-717b01bf-5859-44af-8e51-7164403f5dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111753461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.111753461
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.305007949
Short name T35
Test name
Test status
Simulation time 8465506052 ps
CPU time 23.92 seconds
Started Jan 03 02:03:17 PM PST 24
Finished Jan 03 02:03:57 PM PST 24
Peak memory 216872 kb
Host smart-84d0ca71-a4ab-483c-adc0-ad989a7ada9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305007949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.305007949
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.115356106
Short name T81
Test name
Test status
Simulation time 53182752210 ps
CPU time 562.45 seconds
Started Jan 03 01:54:42 PM PST 24
Finished Jan 03 02:04:15 PM PST 24
Peak memory 352932 kb
Host smart-4473936b-189d-487a-b6c0-67863c58ff6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115356106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.115356106
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3060852902
Short name T246
Test name
Test status
Simulation time 16740065054 ps
CPU time 149.13 seconds
Started Jan 03 02:01:40 PM PST 24
Finished Jan 03 02:04:27 PM PST 24
Peak memory 269820 kb
Host smart-953901ad-7c77-4be2-bef1-c30e7368bc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060852902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3060852902
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2434623504
Short name T1071
Test name
Test status
Simulation time 44580758 ps
CPU time 1.04 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 01:56:29 PM PST 24
Peak memory 218848 kb
Host smart-ff2aa683-cded-4cac-8c47-e9ca64faf0da
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434623504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2434623504
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.81078064
Short name T6
Test name
Test status
Simulation time 3319130799 ps
CPU time 49.48 seconds
Started Jan 03 01:58:06 PM PST 24
Finished Jan 03 01:59:03 PM PST 24
Peak memory 254580 kb
Host smart-7306c91f-13ce-460d-8903-a4bf1878a23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81078064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.81078064
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2759548167
Short name T163
Test name
Test status
Simulation time 12090138823 ps
CPU time 23.3 seconds
Started Jan 03 01:28:11 PM PST 24
Finished Jan 03 01:28:44 PM PST 24
Peak memory 216040 kb
Host smart-a8999c6d-2463-448c-9891-ba6c7d8c28c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759548167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2759548167
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2147918089
Short name T269
Test name
Test status
Simulation time 32825723466 ps
CPU time 164.26 seconds
Started Jan 03 01:58:45 PM PST 24
Finished Jan 03 02:01:43 PM PST 24
Peak memory 268896 kb
Host smart-219dcaa6-d312-4bec-bcd6-1c568c521662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147918089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2147918089
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3999870688
Short name T335
Test name
Test status
Simulation time 447512305352 ps
CPU time 546.63 seconds
Started Jan 03 02:03:36 PM PST 24
Finished Jan 03 02:13:49 PM PST 24
Peak memory 264540 kb
Host smart-82454107-25b6-4787-945b-981c0a7b464c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999870688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3999870688
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3651852925
Short name T95
Test name
Test status
Simulation time 61338997 ps
CPU time 1.18 seconds
Started Jan 03 01:28:11 PM PST 24
Finished Jan 03 01:28:22 PM PST 24
Peak memory 207552 kb
Host smart-0fe58ea5-4612-4d21-aaf6-c3092c746a25
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651852925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3651852925
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2654244582
Short name T454
Test name
Test status
Simulation time 370712972 ps
CPU time 4.73 seconds
Started Jan 03 01:28:11 PM PST 24
Finished Jan 03 01:28:26 PM PST 24
Peak memory 216060 kb
Host smart-00c8e76c-613a-4478-b748-df9d3ad3eaa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654244582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
654244582
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/42.spi_device_bit_transfer.902096832
Short name T184
Test name
Test status
Simulation time 316431908 ps
CPU time 2.23 seconds
Started Jan 03 02:01:29 PM PST 24
Finished Jan 03 02:01:46 PM PST 24
Peak memory 216724 kb
Host smart-7c1b17a7-6960-4c41-b605-7e7e147fe7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902096832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_bit_transfer.902096832
Directory /workspace/42.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3266308850
Short name T264
Test name
Test status
Simulation time 22701064882 ps
CPU time 42.5 seconds
Started Jan 03 01:50:58 PM PST 24
Finished Jan 03 01:51:46 PM PST 24
Peak memory 247440 kb
Host smart-f81fd319-0fac-461d-b893-2057030e3f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266308850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3266308850
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_extreme_fifo_size.4079768477
Short name T300
Test name
Test status
Simulation time 203351004034 ps
CPU time 1728.82 seconds
Started Jan 03 01:51:06 PM PST 24
Finished Jan 03 02:20:01 PM PST 24
Peak memory 225252 kb
Host smart-718e944e-b78d-4aae-858f-6164a13bb8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079768477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_extreme_fifo_size.4079768477
Directory /workspace/1.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.697905260
Short name T116
Test name
Test status
Simulation time 3666451387 ps
CPU time 57.8 seconds
Started Jan 03 01:54:41 PM PST 24
Finished Jan 03 01:55:49 PM PST 24
Peak memory 222052 kb
Host smart-650ec1d5-fad5-4224-9e5b-cdd6497494b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697905260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.697905260
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3781763602
Short name T372
Test name
Test status
Simulation time 56660178032 ps
CPU time 443.85 seconds
Started Jan 03 01:57:23 PM PST 24
Finished Jan 03 02:04:53 PM PST 24
Peak memory 274376 kb
Host smart-9f5f2147-0ffc-47a5-86af-9968ba3864f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781763602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3781763602
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3551463391
Short name T14
Test name
Test status
Simulation time 6423018031 ps
CPU time 7.06 seconds
Started Jan 03 01:58:28 PM PST 24
Finished Jan 03 01:58:39 PM PST 24
Peak memory 230232 kb
Host smart-12f8bcad-fd41-4ad1-9019-622532297662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551463391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3551463391
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3860221040
Short name T373
Test name
Test status
Simulation time 171336941991 ps
CPU time 197.32 seconds
Started Jan 03 01:59:37 PM PST 24
Finished Jan 03 02:03:02 PM PST 24
Peak memory 266132 kb
Host smart-a30e27e6-7636-4686-9fac-4757d6804d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860221040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3860221040
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.612981345
Short name T17
Test name
Test status
Simulation time 14238410115 ps
CPU time 123.16 seconds
Started Jan 03 01:52:29 PM PST 24
Finished Jan 03 01:54:41 PM PST 24
Peak memory 273904 kb
Host smart-0dd40093-7eaf-4916-a5e4-5bca85f194f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612981345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
612981345
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_extreme_fifo_size.2409572479
Short name T47
Test name
Test status
Simulation time 119857540777 ps
CPU time 825.83 seconds
Started Jan 03 01:54:36 PM PST 24
Finished Jan 03 02:08:27 PM PST 24
Peak memory 219100 kb
Host smart-3265769f-a50a-499b-8fb0-a0ff9b0aeffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409572479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_extreme_fifo_size.2409572479
Directory /workspace/10.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3356311374
Short name T441
Test name
Test status
Simulation time 32415492 ps
CPU time 2.83 seconds
Started Jan 03 01:28:07 PM PST 24
Finished Jan 03 01:28:20 PM PST 24
Peak memory 219368 kb
Host smart-4739fd33-d538-425b-8dc3-41577bdfcf03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356311374 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3356311374
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.99704270
Short name T197
Test name
Test status
Simulation time 15139177 ps
CPU time 0.72 seconds
Started Jan 03 01:29:24 PM PST 24
Finished Jan 03 01:29:37 PM PST 24
Peak memory 204956 kb
Host smart-205e03c7-9251-41cb-a176-4f66bb77d88a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99704270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.99704270
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/default/11.spi_device_fifo_underflow_overflow.1823326302
Short name T1749
Test name
Test status
Simulation time 180368124227 ps
CPU time 2131.82 seconds
Started Jan 03 01:54:43 PM PST 24
Finished Jan 03 02:30:25 PM PST 24
Peak memory 813648 kb
Host smart-fc123401-9f4f-43cb-b0bf-5df84cdd1997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823326302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_fifo_underflow_overf
low.1823326302
Directory /workspace/11.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3903081124
Short name T360
Test name
Test status
Simulation time 3097537733 ps
CPU time 59.08 seconds
Started Jan 03 01:54:40 PM PST 24
Finished Jan 03 01:55:49 PM PST 24
Peak memory 262204 kb
Host smart-7e2bd442-2273-401f-9b20-9894e360fd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903081124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3903081124
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_txrx.4046648089
Short name T1681
Test name
Test status
Simulation time 43764594774 ps
CPU time 295.65 seconds
Started Jan 03 01:54:38 PM PST 24
Finished Jan 03 01:59:41 PM PST 24
Peak memory 274348 kb
Host smart-3f661ea0-4137-4edb-add0-b8b90187c7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046648089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_txrx.4046648089
Directory /workspace/11.spi_device_txrx/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3481358450
Short name T362
Test name
Test status
Simulation time 57632035493 ps
CPU time 144.21 seconds
Started Jan 03 02:01:38 PM PST 24
Finished Jan 03 02:04:19 PM PST 24
Peak memory 273988 kb
Host smart-ef516bdd-cbef-45ba-9103-832f27890c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481358450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3481358450
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_abort.1562964389
Short name T42
Test name
Test status
Simulation time 26763678 ps
CPU time 0.77 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 01:57:34 PM PST 24
Peak memory 206556 kb
Host smart-93da3c35-6320-4225-8665-21c1be167985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562964389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_abort.1562964389
Directory /workspace/19.spi_device_abort/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1803701827
Short name T123
Test name
Test status
Simulation time 172181059148 ps
CPU time 238.57 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 02:00:27 PM PST 24
Peak memory 258832 kb
Host smart-700efbbf-23ac-4bd8-b22f-34a30cf2259e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803701827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1803701827
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3333348361
Short name T239
Test name
Test status
Simulation time 2006896034 ps
CPU time 14.63 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 01:57:48 PM PST 24
Peak memory 255304 kb
Host smart-a3afba91-9c1d-4502-b82c-e21b3de334af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333348361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3333348361
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.4103700729
Short name T571
Test name
Test status
Simulation time 21209771 ps
CPU time 0.72 seconds
Started Jan 03 01:56:16 PM PST 24
Finished Jan 03 01:56:26 PM PST 24
Peak memory 206456 kb
Host smart-477c8525-96fd-4446-9ebe-c61bc7c1946a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103700729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
4103700729
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1785976635
Short name T517
Test name
Test status
Simulation time 16534118 ps
CPU time 0.78 seconds
Started Jan 03 01:54:38 PM PST 24
Finished Jan 03 01:54:44 PM PST 24
Peak memory 206512 kb
Host smart-bf794d4e-6917-4698-b2cd-f995cecfd273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785976635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1785976635
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_rx_async_fifo_reset.3274844669
Short name T88
Test name
Test status
Simulation time 82785958 ps
CPU time 0.87 seconds
Started Jan 03 01:54:40 PM PST 24
Finished Jan 03 01:54:50 PM PST 24
Peak memory 208484 kb
Host smart-2f8150c1-b7f5-4dce-8180-fbd808a992c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274844669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_rx_async_fifo_reset.3274844669
Directory /workspace/11.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/11.spi_device_tx_async_fifo_reset.2084384653
Short name T610
Test name
Test status
Simulation time 57177231 ps
CPU time 0.78 seconds
Started Jan 03 01:54:41 PM PST 24
Finished Jan 03 01:54:52 PM PST 24
Peak memory 208448 kb
Host smart-87ef79e0-acd9-49fb-8c23-37f4f8c4cffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084384653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tx_async_fifo_reset.2084384653
Directory /workspace/11.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2449689403
Short name T198
Test name
Test status
Simulation time 23590976061 ps
CPU time 66.72 seconds
Started Jan 03 01:51:27 PM PST 24
Finished Jan 03 01:52:55 PM PST 24
Peak memory 264788 kb
Host smart-a23a6498-0f49-4112-ab1e-3e7e15614094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449689403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2449689403
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2680799240
Short name T437
Test name
Test status
Simulation time 425312652 ps
CPU time 9.45 seconds
Started Jan 03 01:28:13 PM PST 24
Finished Jan 03 01:28:35 PM PST 24
Peak memory 217012 kb
Host smart-f14905d0-e576-4efd-bf66-532489177e47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680799240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2680799240
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1261227362
Short name T414
Test name
Test status
Simulation time 11896702239 ps
CPU time 41.07 seconds
Started Jan 03 01:28:10 PM PST 24
Finished Jan 03 01:29:02 PM PST 24
Peak memory 215836 kb
Host smart-88d420de-7fae-42a7-b735-26d64448fa71
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261227362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1261227362
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2664894378
Short name T418
Test name
Test status
Simulation time 87278997 ps
CPU time 1.49 seconds
Started Jan 03 01:28:10 PM PST 24
Finished Jan 03 01:28:22 PM PST 24
Peak memory 217096 kb
Host smart-b5aa6a23-ef85-41ad-9bb2-9bca0d6a0faf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664894378 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2664894378
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1168719082
Short name T160
Test name
Test status
Simulation time 20416988 ps
CPU time 1.21 seconds
Started Jan 03 01:28:11 PM PST 24
Finished Jan 03 01:28:22 PM PST 24
Peak memory 215812 kb
Host smart-cb503243-84f5-48b2-b4db-06352b5bf5d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168719082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
168719082
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3504351941
Short name T495
Test name
Test status
Simulation time 44960262 ps
CPU time 0.69 seconds
Started Jan 03 01:28:10 PM PST 24
Finished Jan 03 01:28:21 PM PST 24
Peak memory 204896 kb
Host smart-251e23ff-d851-46a6-b83a-0378d478c538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504351941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
504351941
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3780644203
Short name T175
Test name
Test status
Simulation time 204977250 ps
CPU time 4.11 seconds
Started Jan 03 01:28:09 PM PST 24
Finished Jan 03 01:28:23 PM PST 24
Peak memory 215852 kb
Host smart-2bbb9995-86e6-4b26-aef7-b65d58e568c5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780644203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3780644203
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2141866366
Short name T424
Test name
Test status
Simulation time 2738648394 ps
CPU time 11.05 seconds
Started Jan 03 01:28:08 PM PST 24
Finished Jan 03 01:28:29 PM PST 24
Peak memory 215832 kb
Host smart-e3c72131-f01e-4627-b060-688d88efc305
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141866366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2141866366
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2016139952
Short name T482
Test name
Test status
Simulation time 904384844 ps
CPU time 3.94 seconds
Started Jan 03 01:28:11 PM PST 24
Finished Jan 03 01:28:26 PM PST 24
Peak memory 215796 kb
Host smart-99e89c47-2390-4997-8473-440afd8279c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016139952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2016139952
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.768830119
Short name T142
Test name
Test status
Simulation time 311777205 ps
CPU time 2.22 seconds
Started Jan 03 01:28:11 PM PST 24
Finished Jan 03 01:28:23 PM PST 24
Peak memory 216072 kb
Host smart-49886895-b094-4de2-a49d-4bf2c4c561e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768830119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.768830119
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2033375436
Short name T130
Test name
Test status
Simulation time 1253505423 ps
CPU time 18.11 seconds
Started Jan 03 01:28:09 PM PST 24
Finished Jan 03 01:28:37 PM PST 24
Peak memory 215868 kb
Host smart-f7be36fe-f737-4860-b23f-372c852e8256
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033375436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2033375436
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3337668685
Short name T412
Test name
Test status
Simulation time 525301025 ps
CPU time 8.97 seconds
Started Jan 03 01:28:08 PM PST 24
Finished Jan 03 01:28:27 PM PST 24
Peak memory 207592 kb
Host smart-9ad6a628-8c30-47eb-a89c-40bc7237e30a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337668685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3337668685
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2681978724
Short name T170
Test name
Test status
Simulation time 7820674336 ps
CPU time 27.42 seconds
Started Jan 03 01:28:13 PM PST 24
Finished Jan 03 01:28:52 PM PST 24
Peak memory 215956 kb
Host smart-569b88c1-df36-4759-8f3b-4596aeee0873
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681978724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2681978724
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.494776205
Short name T472
Test name
Test status
Simulation time 244661405 ps
CPU time 1.48 seconds
Started Jan 03 01:28:13 PM PST 24
Finished Jan 03 01:28:26 PM PST 24
Peak memory 207504 kb
Host smart-ea352aad-5d7c-4fa3-8f82-1e1ef00a2f18
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494776205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.494776205
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2286639356
Short name T473
Test name
Test status
Simulation time 1240092232 ps
CPU time 2.07 seconds
Started Jan 03 01:28:13 PM PST 24
Finished Jan 03 01:28:27 PM PST 24
Peak memory 215624 kb
Host smart-5137594b-3568-4d21-91db-b0fdea8459b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286639356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
286639356
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2725251413
Short name T494
Test name
Test status
Simulation time 11953694 ps
CPU time 0.74 seconds
Started Jan 03 01:28:11 PM PST 24
Finished Jan 03 01:28:21 PM PST 24
Peak memory 204944 kb
Host smart-e6749f7e-f0d3-4e0e-b3a4-4698859e7493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725251413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
725251413
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3744347049
Short name T181
Test name
Test status
Simulation time 1078892087 ps
CPU time 6.94 seconds
Started Jan 03 01:28:14 PM PST 24
Finished Jan 03 01:28:32 PM PST 24
Peak memory 215788 kb
Host smart-f46adb08-c75e-4d4d-bbd6-d9cacee71de9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744347049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3744347049
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.212220734
Short name T165
Test name
Test status
Simulation time 1393313528 ps
CPU time 15.76 seconds
Started Jan 03 01:28:12 PM PST 24
Finished Jan 03 01:28:40 PM PST 24
Peak memory 215684 kb
Host smart-f94a8cd5-9cda-448f-9a29-9f9314e9b158
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212220734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.212220734
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3547938572
Short name T195
Test name
Test status
Simulation time 621319314 ps
CPU time 3.51 seconds
Started Jan 03 01:28:08 PM PST 24
Finished Jan 03 01:28:22 PM PST 24
Peak memory 215796 kb
Host smart-338fea2c-624e-436e-9591-f5cc29e565d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547938572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3547938572
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.939624395
Short name T136
Test name
Test status
Simulation time 128233171 ps
CPU time 3.26 seconds
Started Jan 03 01:28:10 PM PST 24
Finished Jan 03 01:28:23 PM PST 24
Peak memory 215872 kb
Host smart-bd5bc9b5-d001-4844-afb8-c4267f5c5c5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939624395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.939624395
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.4189821131
Short name T434
Test name
Test status
Simulation time 1272368912 ps
CPU time 7.11 seconds
Started Jan 03 01:28:09 PM PST 24
Finished Jan 03 01:28:26 PM PST 24
Peak memory 216284 kb
Host smart-5c25cb8f-6664-405a-8ef2-0d089fedb22f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189821131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.4189821131
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.99099451
Short name T72
Test name
Test status
Simulation time 36364447 ps
CPU time 2.21 seconds
Started Jan 03 01:29:24 PM PST 24
Finished Jan 03 01:29:38 PM PST 24
Peak memory 219876 kb
Host smart-fb6a0851-2634-4dfa-af82-d6f991082399
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99099451 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.99099451
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2147047082
Short name T490
Test name
Test status
Simulation time 65562715 ps
CPU time 1.93 seconds
Started Jan 03 01:29:24 PM PST 24
Finished Jan 03 01:29:38 PM PST 24
Peak memory 207604 kb
Host smart-41c27f56-4ab6-4770-a8bb-52b562120cff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147047082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2147047082
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3865909672
Short name T420
Test name
Test status
Simulation time 18551907 ps
CPU time 0.73 seconds
Started Jan 03 01:29:48 PM PST 24
Finished Jan 03 01:30:04 PM PST 24
Peak memory 204892 kb
Host smart-9765edb0-a2ba-40e0-b081-c438978edeb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865909672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3865909672
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.128836293
Short name T480
Test name
Test status
Simulation time 239546298 ps
CPU time 2.04 seconds
Started Jan 03 01:29:22 PM PST 24
Finished Jan 03 01:29:36 PM PST 24
Peak memory 215844 kb
Host smart-510ff7d5-5629-4908-af1c-a5ae79802eb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128836293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.128836293
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3181426305
Short name T70
Test name
Test status
Simulation time 115590795 ps
CPU time 2.78 seconds
Started Jan 03 01:29:22 PM PST 24
Finished Jan 03 01:29:37 PM PST 24
Peak memory 216176 kb
Host smart-b2b3631f-0937-489c-9498-c582a545407d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181426305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3181426305
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.646496266
Short name T162
Test name
Test status
Simulation time 996742089 ps
CPU time 20.93 seconds
Started Jan 03 01:29:46 PM PST 24
Finished Jan 03 01:30:22 PM PST 24
Peak memory 215816 kb
Host smart-5c9ac4cc-612a-4f43-a76e-bb22bccc89c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646496266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.646496266
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3699237917
Short name T425
Test name
Test status
Simulation time 33736208 ps
CPU time 1.83 seconds
Started Jan 03 01:29:20 PM PST 24
Finished Jan 03 01:29:33 PM PST 24
Peak memory 218268 kb
Host smart-8c5741a3-1c9c-4ad9-bb4d-88125960a56a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699237917 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3699237917
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.427780185
Short name T451
Test name
Test status
Simulation time 38013357 ps
CPU time 1.31 seconds
Started Jan 03 01:29:23 PM PST 24
Finished Jan 03 01:29:36 PM PST 24
Peak memory 215888 kb
Host smart-69ca8e7c-c37c-41c5-8007-ca7c32b64fde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427780185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.427780185
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2279956851
Short name T411
Test name
Test status
Simulation time 87776821 ps
CPU time 2.01 seconds
Started Jan 03 01:29:24 PM PST 24
Finished Jan 03 01:29:38 PM PST 24
Peak memory 215700 kb
Host smart-9e1dd9ef-89c1-4d23-b427-6e45c1e9227c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279956851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2279956851
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1319319024
Short name T487
Test name
Test status
Simulation time 178460267 ps
CPU time 3.65 seconds
Started Jan 03 01:29:12 PM PST 24
Finished Jan 03 01:29:20 PM PST 24
Peak memory 215976 kb
Host smart-20a0bb86-afaa-42af-b377-503358a8f136
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319319024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1319319024
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3874889172
Short name T415
Test name
Test status
Simulation time 6438022337 ps
CPU time 15.42 seconds
Started Jan 03 01:29:24 PM PST 24
Finished Jan 03 01:29:52 PM PST 24
Peak memory 215924 kb
Host smart-c482ebd6-681a-4e00-8a5f-13b88b569318
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874889172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3874889172
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3530587574
Short name T486
Test name
Test status
Simulation time 26506764 ps
CPU time 1.32 seconds
Started Jan 03 01:29:25 PM PST 24
Finished Jan 03 01:29:39 PM PST 24
Peak memory 217160 kb
Host smart-a2ec3baa-0d68-493a-9b87-fee65c75be20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530587574 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3530587574
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1290409496
Short name T439
Test name
Test status
Simulation time 73829259 ps
CPU time 1.27 seconds
Started Jan 03 01:29:54 PM PST 24
Finished Jan 03 01:30:33 PM PST 24
Peak memory 207624 kb
Host smart-fc651fe4-b161-479f-9db0-14eb4ee5c0fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290409496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1290409496
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2586913665
Short name T450
Test name
Test status
Simulation time 11600313 ps
CPU time 0.75 seconds
Started Jan 03 01:29:55 PM PST 24
Finished Jan 03 01:30:40 PM PST 24
Peak memory 204920 kb
Host smart-026015b3-b875-4c9f-bb03-f6b528a1d96f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586913665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2586913665
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2738063554
Short name T196
Test name
Test status
Simulation time 160354631 ps
CPU time 2.01 seconds
Started Jan 03 01:29:25 PM PST 24
Finished Jan 03 01:29:40 PM PST 24
Peak memory 207576 kb
Host smart-fe2beb17-f49e-47d9-8221-371dad101dbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738063554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2738063554
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1302717235
Short name T138
Test name
Test status
Simulation time 367853555 ps
CPU time 3.68 seconds
Started Jan 03 01:29:52 PM PST 24
Finished Jan 03 01:30:27 PM PST 24
Peak memory 216040 kb
Host smart-04701ee6-8aaa-4d45-9572-d84d371eac5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302717235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1302717235
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.294027330
Short name T463
Test name
Test status
Simulation time 30644842 ps
CPU time 1.31 seconds
Started Jan 03 01:29:59 PM PST 24
Finished Jan 03 01:30:52 PM PST 24
Peak memory 217048 kb
Host smart-b3b73cb9-efe1-4b63-9bad-f31eb711e95f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294027330 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.294027330
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1795439779
Short name T178
Test name
Test status
Simulation time 31005688 ps
CPU time 1.87 seconds
Started Jan 03 01:29:34 PM PST 24
Finished Jan 03 01:29:54 PM PST 24
Peak memory 215880 kb
Host smart-94cc4744-0859-43c3-acb3-f5cae5bbb60f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795439779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1795439779
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2063342090
Short name T413
Test name
Test status
Simulation time 14413758 ps
CPU time 0.7 seconds
Started Jan 03 01:29:33 PM PST 24
Finished Jan 03 01:29:52 PM PST 24
Peak memory 204908 kb
Host smart-63e72086-ab16-4231-a6cb-f52207eca3af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063342090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2063342090
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4031751588
Short name T171
Test name
Test status
Simulation time 397827272 ps
CPU time 1.85 seconds
Started Jan 03 01:29:54 PM PST 24
Finished Jan 03 01:30:34 PM PST 24
Peak memory 215760 kb
Host smart-e8e1ab1a-cc2e-4bd6-a1ea-ef38ca3a40d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031751588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.4031751588
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2940393789
Short name T433
Test name
Test status
Simulation time 151457299 ps
CPU time 5.41 seconds
Started Jan 03 01:29:52 PM PST 24
Finished Jan 03 01:30:32 PM PST 24
Peak memory 216028 kb
Host smart-21f5ec75-08cf-433c-b32d-7f64d1d50687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940393789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2940393789
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.429333003
Short name T134
Test name
Test status
Simulation time 2947850215 ps
CPU time 14.32 seconds
Started Jan 03 01:29:52 PM PST 24
Finished Jan 03 01:30:37 PM PST 24
Peak memory 216388 kb
Host smart-7539e79e-cf92-4f1a-b0a2-17de72fc39d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429333003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.429333003
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4119960257
Short name T193
Test name
Test status
Simulation time 152388581 ps
CPU time 2.3 seconds
Started Jan 03 01:30:00 PM PST 24
Finished Jan 03 01:30:53 PM PST 24
Peak memory 219704 kb
Host smart-7ae1ba98-374b-4535-b408-2a35a6f14ba4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119960257 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4119960257
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.446731048
Short name T477
Test name
Test status
Simulation time 206940916 ps
CPU time 1.56 seconds
Started Jan 03 01:29:53 PM PST 24
Finished Jan 03 01:30:30 PM PST 24
Peak memory 207592 kb
Host smart-3cc8e51d-bc77-42b3-b613-4b62770e1c1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446731048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.446731048
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.907142514
Short name T403
Test name
Test status
Simulation time 12238842 ps
CPU time 0.69 seconds
Started Jan 03 01:29:55 PM PST 24
Finished Jan 03 01:30:40 PM PST 24
Peak memory 204840 kb
Host smart-4922ff81-95c5-436c-9f17-26183f8654bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907142514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.907142514
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.824937074
Short name T69
Test name
Test status
Simulation time 1100082352 ps
CPU time 4.34 seconds
Started Jan 03 01:29:57 PM PST 24
Finished Jan 03 01:30:55 PM PST 24
Peak memory 215844 kb
Host smart-a6ec1097-f654-48d3-b272-6c8ca67f469a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824937074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.824937074
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2672922860
Short name T143
Test name
Test status
Simulation time 199364960 ps
CPU time 3.9 seconds
Started Jan 03 01:29:55 PM PST 24
Finished Jan 03 01:30:43 PM PST 24
Peak memory 215980 kb
Host smart-27b1072d-691c-4fed-bfd5-d31367fb1152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672922860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2672922860
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1481334067
Short name T466
Test name
Test status
Simulation time 412038475 ps
CPU time 13.66 seconds
Started Jan 03 01:29:54 PM PST 24
Finished Jan 03 01:30:50 PM PST 24
Peak memory 215804 kb
Host smart-28db7a97-9c05-4a0e-88b3-6a515c67cd40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481334067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1481334067
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2795766565
Short name T499
Test name
Test status
Simulation time 35910745 ps
CPU time 1.43 seconds
Started Jan 03 01:29:57 PM PST 24
Finished Jan 03 01:30:52 PM PST 24
Peak memory 217420 kb
Host smart-74670a49-87db-4aa1-81ec-fd02deefb86e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795766565 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2795766565
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.967658944
Short name T176
Test name
Test status
Simulation time 188258356 ps
CPU time 2.37 seconds
Started Jan 03 01:28:43 PM PST 24
Finished Jan 03 01:28:53 PM PST 24
Peak memory 215800 kb
Host smart-5ef6449a-987a-41af-9ff2-42228a74dac5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967658944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.967658944
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2862927368
Short name T458
Test name
Test status
Simulation time 89592274 ps
CPU time 0.76 seconds
Started Jan 03 01:29:54 PM PST 24
Finished Jan 03 01:30:34 PM PST 24
Peak memory 204944 kb
Host smart-4be7fc52-cfd4-43e8-93c6-a52ec241eb3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862927368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2862927368
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2283981911
Short name T401
Test name
Test status
Simulation time 65940597 ps
CPU time 3.99 seconds
Started Jan 03 01:29:56 PM PST 24
Finished Jan 03 01:30:47 PM PST 24
Peak memory 215780 kb
Host smart-bae4308f-aef1-4b0c-84d5-9b023ccf71eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283981911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2283981911
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1501367580
Short name T481
Test name
Test status
Simulation time 112934654 ps
CPU time 3.16 seconds
Started Jan 03 01:29:55 PM PST 24
Finished Jan 03 01:30:40 PM PST 24
Peak memory 215980 kb
Host smart-eb725a1b-de04-434b-aa29-1b284c514da4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501367580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1501367580
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2730353285
Short name T217
Test name
Test status
Simulation time 1293546842 ps
CPU time 18.93 seconds
Started Jan 03 01:29:55 PM PST 24
Finished Jan 03 01:30:59 PM PST 24
Peak memory 215784 kb
Host smart-f601e0cb-ab5a-4339-9217-88e692038dd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730353285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2730353285
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2742029601
Short name T455
Test name
Test status
Simulation time 68793746 ps
CPU time 2.29 seconds
Started Jan 03 01:29:17 PM PST 24
Finished Jan 03 01:29:31 PM PST 24
Peak memory 217788 kb
Host smart-d1a1f94c-7e56-4a91-b190-9ca483fd29b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742029601 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2742029601
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2265514309
Short name T423
Test name
Test status
Simulation time 592065715 ps
CPU time 1.4 seconds
Started Jan 03 01:28:55 PM PST 24
Finished Jan 03 01:29:01 PM PST 24
Peak memory 207616 kb
Host smart-e3aa664a-5036-45e1-998f-54094dea7c3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265514309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2265514309
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3529981634
Short name T396
Test name
Test status
Simulation time 11612186 ps
CPU time 0.75 seconds
Started Jan 03 01:29:03 PM PST 24
Finished Jan 03 01:29:09 PM PST 24
Peak memory 204908 kb
Host smart-645375c5-0c00-47f3-831f-6962e5679ecb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529981634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3529981634
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.935789834
Short name T485
Test name
Test status
Simulation time 768383099 ps
CPU time 4.36 seconds
Started Jan 03 01:28:59 PM PST 24
Finished Jan 03 01:29:09 PM PST 24
Peak memory 215788 kb
Host smart-7b7f82e1-0f52-453a-8f9f-1804f3032a16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935789834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.935789834
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4089573479
Short name T476
Test name
Test status
Simulation time 242020605 ps
CPU time 1.97 seconds
Started Jan 03 01:28:58 PM PST 24
Finished Jan 03 01:29:05 PM PST 24
Peak memory 216052 kb
Host smart-59de3644-600a-40be-8ef5-74d75194d5af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089573479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
4089573479
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2144207073
Short name T421
Test name
Test status
Simulation time 1508389321 ps
CPU time 8.68 seconds
Started Jan 03 01:28:43 PM PST 24
Finished Jan 03 01:29:00 PM PST 24
Peak memory 215776 kb
Host smart-ac194367-dfcf-42e7-ace4-0bad0c46c01f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144207073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2144207073
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2929024463
Short name T394
Test name
Test status
Simulation time 23859768 ps
CPU time 2.09 seconds
Started Jan 03 01:29:21 PM PST 24
Finished Jan 03 01:29:35 PM PST 24
Peak memory 218756 kb
Host smart-5758eeee-10de-494c-abd1-b7f3e0d04573
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929024463 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2929024463
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.276939487
Short name T180
Test name
Test status
Simulation time 126163630 ps
CPU time 2.84 seconds
Started Jan 03 01:29:13 PM PST 24
Finished Jan 03 01:29:23 PM PST 24
Peak memory 215936 kb
Host smart-55c1aa15-193e-4f83-a737-35f067d92841
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276939487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.276939487
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3464602811
Short name T428
Test name
Test status
Simulation time 24508403 ps
CPU time 0.79 seconds
Started Jan 03 01:29:27 PM PST 24
Finished Jan 03 01:29:43 PM PST 24
Peak memory 204840 kb
Host smart-e40e18a2-fa8d-44d0-86ed-8e6be35177b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464602811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3464602811
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.332706651
Short name T498
Test name
Test status
Simulation time 115082654 ps
CPU time 1.92 seconds
Started Jan 03 01:28:58 PM PST 24
Finished Jan 03 01:29:05 PM PST 24
Peak memory 215832 kb
Host smart-84983ae8-5e7e-4b44-9776-9dd32ed44d0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332706651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.332706651
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3899836265
Short name T443
Test name
Test status
Simulation time 151850770 ps
CPU time 3.74 seconds
Started Jan 03 01:28:43 PM PST 24
Finished Jan 03 01:28:55 PM PST 24
Peak memory 216992 kb
Host smart-fafe153b-600a-438f-934a-f7119e6b8395
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899836265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3899836265
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1054087524
Short name T166
Test name
Test status
Simulation time 110856609 ps
CPU time 6.4 seconds
Started Jan 03 01:28:44 PM PST 24
Finished Jan 03 01:28:58 PM PST 24
Peak memory 215816 kb
Host smart-4b1c639f-7f2a-4019-98bb-5da9f4e00626
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054087524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1054087524
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3932867973
Short name T161
Test name
Test status
Simulation time 43441518 ps
CPU time 2.49 seconds
Started Jan 03 01:29:56 PM PST 24
Finished Jan 03 01:30:44 PM PST 24
Peak memory 218880 kb
Host smart-11e494da-50a0-4fe0-930d-7a24dd35f1d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932867973 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3932867973
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3107819569
Short name T496
Test name
Test status
Simulation time 681193880 ps
CPU time 2.14 seconds
Started Jan 03 01:29:24 PM PST 24
Finished Jan 03 01:29:38 PM PST 24
Peak memory 215780 kb
Host smart-da716b1f-2417-48f3-92f4-35197103cd34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107819569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3107819569
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3987402819
Short name T402
Test name
Test status
Simulation time 52378179 ps
CPU time 0.75 seconds
Started Jan 03 01:28:59 PM PST 24
Finished Jan 03 01:29:05 PM PST 24
Peak memory 204880 kb
Host smart-bff4a8a0-0628-4b67-b712-6967f8b4a552
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987402819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3987402819
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4012305404
Short name T460
Test name
Test status
Simulation time 149348434 ps
CPU time 3.27 seconds
Started Jan 03 01:29:47 PM PST 24
Finished Jan 03 01:30:05 PM PST 24
Peak memory 215708 kb
Host smart-3222a123-0e6a-4b0f-81f4-c0c9e920574c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012305404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4012305404
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.195922463
Short name T462
Test name
Test status
Simulation time 118299795 ps
CPU time 1.96 seconds
Started Jan 03 01:29:14 PM PST 24
Finished Jan 03 01:29:24 PM PST 24
Peak memory 215952 kb
Host smart-55d7a858-a6e8-4c36-bcfa-ec42d41df7aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195922463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.195922463
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3544826775
Short name T459
Test name
Test status
Simulation time 376002045 ps
CPU time 6.97 seconds
Started Jan 03 01:29:28 PM PST 24
Finished Jan 03 01:29:51 PM PST 24
Peak memory 216052 kb
Host smart-f4e97c38-4758-4203-9005-72f0d6d4a3fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544826775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3544826775
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2149660639
Short name T465
Test name
Test status
Simulation time 19574023 ps
CPU time 1.33 seconds
Started Jan 03 01:29:23 PM PST 24
Finished Jan 03 01:29:36 PM PST 24
Peak memory 217116 kb
Host smart-a35449b3-24c2-4ea6-b316-d936ad33a643
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149660639 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2149660639
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4200801152
Short name T406
Test name
Test status
Simulation time 36539637 ps
CPU time 1.33 seconds
Started Jan 03 01:29:43 PM PST 24
Finished Jan 03 01:29:57 PM PST 24
Peak memory 207656 kb
Host smart-96a6fd6c-5410-4457-985d-c4c4462ff5dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200801152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4200801152
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3954367918
Short name T483
Test name
Test status
Simulation time 42021962 ps
CPU time 0.73 seconds
Started Jan 03 01:29:24 PM PST 24
Finished Jan 03 01:29:37 PM PST 24
Peak memory 204908 kb
Host smart-63b0ce49-9830-446a-8120-9e20234823da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954367918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3954367918
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2715483005
Short name T422
Test name
Test status
Simulation time 101172638 ps
CPU time 1.8 seconds
Started Jan 03 01:29:46 PM PST 24
Finished Jan 03 01:30:03 PM PST 24
Peak memory 215824 kb
Host smart-6619bcb2-48ee-44b5-a74f-cff43799afd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715483005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2715483005
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1978721098
Short name T479
Test name
Test status
Simulation time 126232934 ps
CPU time 2.83 seconds
Started Jan 03 01:29:47 PM PST 24
Finished Jan 03 01:30:06 PM PST 24
Peak memory 215992 kb
Host smart-2d7b05f3-b199-421c-823e-89d2230c4f24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978721098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1978721098
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.214912655
Short name T474
Test name
Test status
Simulation time 565527780 ps
CPU time 7.31 seconds
Started Jan 03 01:29:50 PM PST 24
Finished Jan 03 01:30:23 PM PST 24
Peak memory 215700 kb
Host smart-cec68bb7-be89-4d24-8cab-27f2e45f2c21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214912655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.214912655
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.660199456
Short name T430
Test name
Test status
Simulation time 1128289176 ps
CPU time 25.33 seconds
Started Jan 03 01:28:08 PM PST 24
Finished Jan 03 01:28:43 PM PST 24
Peak memory 207588 kb
Host smart-a34031fe-e361-402a-8cf5-96c68fef94ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660199456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.660199456
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.516609649
Short name T174
Test name
Test status
Simulation time 5544127850 ps
CPU time 25.99 seconds
Started Jan 03 01:28:06 PM PST 24
Finished Jan 03 01:28:43 PM PST 24
Peak memory 215884 kb
Host smart-dd484be8-c35a-4b41-89f4-4353d79643e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516609649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.516609649
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.849485423
Short name T452
Test name
Test status
Simulation time 65465288 ps
CPU time 1.2 seconds
Started Jan 03 01:28:07 PM PST 24
Finished Jan 03 01:28:19 PM PST 24
Peak memory 207572 kb
Host smart-d5eab1de-d7c7-425c-abbd-e2057341bed7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849485423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.849485423
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2979922449
Short name T447
Test name
Test status
Simulation time 59893846 ps
CPU time 2.59 seconds
Started Jan 03 01:28:08 PM PST 24
Finished Jan 03 01:28:21 PM PST 24
Peak memory 219540 kb
Host smart-facdc861-ea2f-4bc1-8a3b-72b29d0094b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979922449 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2979922449
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2331271593
Short name T405
Test name
Test status
Simulation time 140982974 ps
CPU time 1.41 seconds
Started Jan 03 01:28:07 PM PST 24
Finished Jan 03 01:28:18 PM PST 24
Peak memory 215824 kb
Host smart-913d5abc-f80c-4a7b-b0be-42a7b7e9b64f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331271593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
331271593
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1510490177
Short name T491
Test name
Test status
Simulation time 24596590 ps
CPU time 0.77 seconds
Started Jan 03 01:28:08 PM PST 24
Finished Jan 03 01:28:18 PM PST 24
Peak memory 204864 kb
Host smart-96453eba-cd0d-4a24-bc9b-9fe13a8cea6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510490177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
510490177
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2430601171
Short name T446
Test name
Test status
Simulation time 936404224 ps
CPU time 7.11 seconds
Started Jan 03 01:28:06 PM PST 24
Finished Jan 03 01:28:24 PM PST 24
Peak memory 215832 kb
Host smart-77561737-9fb1-4d02-8b56-a22081f96dda
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430601171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2430601171
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2348402144
Short name T410
Test name
Test status
Simulation time 5503207587 ps
CPU time 10.6 seconds
Started Jan 03 01:28:08 PM PST 24
Finished Jan 03 01:28:29 PM PST 24
Peak memory 215900 kb
Host smart-cd7edd5c-105b-42ec-9568-9f8ca5c44a74
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348402144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2348402144
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3876484190
Short name T442
Test name
Test status
Simulation time 67331578 ps
CPU time 2 seconds
Started Jan 03 01:28:08 PM PST 24
Finished Jan 03 01:28:20 PM PST 24
Peak memory 215828 kb
Host smart-1a2c1d7d-e27f-4c5e-8fe2-ef13b186d20e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876484190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3876484190
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2408066775
Short name T461
Test name
Test status
Simulation time 270144786 ps
CPU time 3.67 seconds
Started Jan 03 01:28:06 PM PST 24
Finished Jan 03 01:28:20 PM PST 24
Peak memory 215976 kb
Host smart-0d3ffaf0-1dda-4cd2-8e3f-41b2514ef806
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408066775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
408066775
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1954663071
Short name T192
Test name
Test status
Simulation time 947842951 ps
CPU time 7.87 seconds
Started Jan 03 01:28:07 PM PST 24
Finished Jan 03 01:28:25 PM PST 24
Peak memory 215784 kb
Host smart-1c7c79bb-9839-45ca-8221-8df3c941c922
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954663071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1954663071
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.414833888
Short name T426
Test name
Test status
Simulation time 17228803 ps
CPU time 0.76 seconds
Started Jan 03 01:29:54 PM PST 24
Finished Jan 03 01:30:33 PM PST 24
Peak memory 204904 kb
Host smart-fe5074d7-127e-47ad-9b56-e493aee86ebb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414833888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.414833888
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2668237901
Short name T453
Test name
Test status
Simulation time 13271935 ps
CPU time 0.71 seconds
Started Jan 03 01:29:53 PM PST 24
Finished Jan 03 01:30:32 PM PST 24
Peak memory 204932 kb
Host smart-1862edd1-888b-4a08-b029-5fa06ef11ba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668237901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2668237901
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4136987153
Short name T500
Test name
Test status
Simulation time 114091740 ps
CPU time 0.71 seconds
Started Jan 03 01:29:52 PM PST 24
Finished Jan 03 01:30:26 PM PST 24
Peak memory 204932 kb
Host smart-7f06e015-ed77-463c-9139-5aa5e3d21f10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136987153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
4136987153
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.808873870
Short name T493
Test name
Test status
Simulation time 18873431 ps
CPU time 0.76 seconds
Started Jan 03 01:29:52 PM PST 24
Finished Jan 03 01:30:26 PM PST 24
Peak memory 204912 kb
Host smart-488605f1-7db3-4706-9e65-48ba232b4de3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808873870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.808873870
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.354794918
Short name T208
Test name
Test status
Simulation time 23296485 ps
CPU time 0.72 seconds
Started Jan 03 01:29:53 PM PST 24
Finished Jan 03 01:30:32 PM PST 24
Peak memory 204848 kb
Host smart-4916f8f0-f799-4f3e-8434-2c3224b94460
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354794918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.354794918
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1276404342
Short name T467
Test name
Test status
Simulation time 33662183 ps
CPU time 0.77 seconds
Started Jan 03 01:29:55 PM PST 24
Finished Jan 03 01:30:39 PM PST 24
Peak memory 204836 kb
Host smart-ea21a103-99e3-48a4-a4a0-33ef20478f94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276404342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1276404342
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3728524201
Short name T76
Test name
Test status
Simulation time 25908042 ps
CPU time 0.7 seconds
Started Jan 03 01:29:55 PM PST 24
Finished Jan 03 01:30:39 PM PST 24
Peak memory 204912 kb
Host smart-1e66bdfb-9b79-4107-ab07-027d138d46b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728524201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3728524201
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.990994957
Short name T440
Test name
Test status
Simulation time 12864610 ps
CPU time 0.78 seconds
Started Jan 03 01:30:00 PM PST 24
Finished Jan 03 01:30:51 PM PST 24
Peak memory 204900 kb
Host smart-e8fcb6b4-f81e-4c68-a42d-d5ea291842d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990994957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.990994957
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3132207960
Short name T432
Test name
Test status
Simulation time 14466767 ps
CPU time 0.7 seconds
Started Jan 03 01:29:53 PM PST 24
Finished Jan 03 01:30:29 PM PST 24
Peak memory 204888 kb
Host smart-5044949f-ea41-4d33-8daf-2779958ad5ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132207960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3132207960
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3677699552
Short name T501
Test name
Test status
Simulation time 33726409 ps
CPU time 0.77 seconds
Started Jan 03 01:29:57 PM PST 24
Finished Jan 03 01:30:51 PM PST 24
Peak memory 204984 kb
Host smart-1f9c134b-3424-4dab-a260-aa12a8021e1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677699552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3677699552
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.855641729
Short name T469
Test name
Test status
Simulation time 5531281802 ps
CPU time 28.04 seconds
Started Jan 03 01:28:09 PM PST 24
Finished Jan 03 01:28:47 PM PST 24
Peak memory 207732 kb
Host smart-1b1f465d-4288-407f-baab-352a3eb3585a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855641729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.855641729
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2617876782
Short name T395
Test name
Test status
Simulation time 820153236 ps
CPU time 12.62 seconds
Started Jan 03 01:28:09 PM PST 24
Finished Jan 03 01:28:31 PM PST 24
Peak memory 215788 kb
Host smart-bc06d1ee-2c25-4743-88e3-113f6544ff41
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617876782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2617876782
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.815833485
Short name T448
Test name
Test status
Simulation time 21594998 ps
CPU time 0.97 seconds
Started Jan 03 01:28:08 PM PST 24
Finished Jan 03 01:28:19 PM PST 24
Peak memory 207448 kb
Host smart-296644d1-8104-4a33-80fc-d2cfcd0526ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815833485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.815833485
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1024660175
Short name T505
Test name
Test status
Simulation time 40439922 ps
CPU time 1.25 seconds
Started Jan 03 01:28:09 PM PST 24
Finished Jan 03 01:28:21 PM PST 24
Peak memory 217280 kb
Host smart-fc712219-dcc9-4d2c-ba97-7a8de25ccfad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024660175 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1024660175
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1609021844
Short name T504
Test name
Test status
Simulation time 38828640 ps
CPU time 2.28 seconds
Started Jan 03 01:28:10 PM PST 24
Finished Jan 03 01:28:22 PM PST 24
Peak memory 215916 kb
Host smart-7b4cc912-0afc-4c71-9bb3-5dc422911a4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609021844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
609021844
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2371416654
Short name T429
Test name
Test status
Simulation time 43896182 ps
CPU time 0.67 seconds
Started Jan 03 01:28:05 PM PST 24
Finished Jan 03 01:28:17 PM PST 24
Peak memory 204964 kb
Host smart-b50ef1f7-be29-449b-9e4f-edd1b353ebac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371416654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
371416654
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.25213357
Short name T475
Test name
Test status
Simulation time 200584112 ps
CPU time 4.76 seconds
Started Jan 03 01:28:09 PM PST 24
Finished Jan 03 01:28:23 PM PST 24
Peak memory 215848 kb
Host smart-d923970c-1235-4ddc-8b10-143f24f6831f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25213357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_d
evice_mem_partial_access.25213357
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3482956635
Short name T416
Test name
Test status
Simulation time 135206055 ps
CPU time 9.4 seconds
Started Jan 03 01:28:10 PM PST 24
Finished Jan 03 01:28:30 PM PST 24
Peak memory 215788 kb
Host smart-a4d64574-4b06-46de-9ee4-2ca589fee122
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482956635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3482956635
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2866398330
Short name T194
Test name
Test status
Simulation time 171941042 ps
CPU time 2.19 seconds
Started Jan 03 01:28:11 PM PST 24
Finished Jan 03 01:28:24 PM PST 24
Peak memory 215756 kb
Host smart-5a38fba6-5dd2-43fa-a638-58984095de1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866398330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2866398330
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4101610613
Short name T489
Test name
Test status
Simulation time 320283395 ps
CPU time 6.79 seconds
Started Jan 03 01:28:10 PM PST 24
Finished Jan 03 01:28:27 PM PST 24
Peak memory 215784 kb
Host smart-19c1b114-012f-43a8-abfd-275e3dfa073e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101610613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.4101610613
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2768578865
Short name T506
Test name
Test status
Simulation time 15454043 ps
CPU time 0.76 seconds
Started Jan 03 01:30:02 PM PST 24
Finished Jan 03 01:30:53 PM PST 24
Peak memory 204864 kb
Host smart-a43faf82-fe42-4abb-8592-1745ba1c384a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768578865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2768578865
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.854310060
Short name T431
Test name
Test status
Simulation time 13755894 ps
CPU time 0.73 seconds
Started Jan 03 01:29:57 PM PST 24
Finished Jan 03 01:30:51 PM PST 24
Peak memory 204892 kb
Host smart-5ebc885a-2e6c-4fdb-8543-36db266bcc5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854310060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.854310060
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1083559047
Short name T449
Test name
Test status
Simulation time 15538064 ps
CPU time 0.71 seconds
Started Jan 03 01:29:55 PM PST 24
Finished Jan 03 01:30:39 PM PST 24
Peak memory 204928 kb
Host smart-56c1911c-8d28-4a94-b364-3359a28fba27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083559047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1083559047
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.208766377
Short name T470
Test name
Test status
Simulation time 15160516 ps
CPU time 0.69 seconds
Started Jan 03 01:29:55 PM PST 24
Finished Jan 03 01:30:38 PM PST 24
Peak memory 204960 kb
Host smart-84510983-21e2-445c-be58-4d5a6ba86f6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208766377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.208766377
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.904922672
Short name T468
Test name
Test status
Simulation time 30554840 ps
CPU time 0.76 seconds
Started Jan 03 01:29:57 PM PST 24
Finished Jan 03 01:30:50 PM PST 24
Peak memory 204928 kb
Host smart-901e941c-fb66-4251-b5dd-c16180a9d476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904922672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.904922672
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1253654661
Short name T77
Test name
Test status
Simulation time 41331270 ps
CPU time 0.72 seconds
Started Jan 03 01:30:01 PM PST 24
Finished Jan 03 01:30:53 PM PST 24
Peak memory 204692 kb
Host smart-7266d96d-539b-4d11-9bd8-cc844de12236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253654661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1253654661
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1295488528
Short name T172
Test name
Test status
Simulation time 29879759 ps
CPU time 0.68 seconds
Started Jan 03 01:30:02 PM PST 24
Finished Jan 03 01:30:53 PM PST 24
Peak memory 204868 kb
Host smart-796288c0-7c56-489c-8fdc-dfd2fc345f96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295488528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1295488528
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.345329335
Short name T398
Test name
Test status
Simulation time 51266635 ps
CPU time 0.75 seconds
Started Jan 03 01:28:44 PM PST 24
Finished Jan 03 01:28:52 PM PST 24
Peak memory 204956 kb
Host smart-6b567bdb-8228-4da0-bcae-bed04f4aabe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345329335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.345329335
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1339871233
Short name T417
Test name
Test status
Simulation time 43447010 ps
CPU time 0.73 seconds
Started Jan 03 01:30:05 PM PST 24
Finished Jan 03 01:30:59 PM PST 24
Peak memory 204928 kb
Host smart-4b323420-cbec-46e8-978f-c48fc49377f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339871233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1339871233
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.753053444
Short name T445
Test name
Test status
Simulation time 1047765616 ps
CPU time 15.98 seconds
Started Jan 03 01:28:13 PM PST 24
Finished Jan 03 01:28:41 PM PST 24
Peak memory 217048 kb
Host smart-08a0f55c-0df4-44c6-b2ae-ebf3ec3a0915
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753053444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.753053444
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3962443393
Short name T407
Test name
Test status
Simulation time 389270543 ps
CPU time 22.4 seconds
Started Jan 03 01:28:12 PM PST 24
Finished Jan 03 01:28:46 PM PST 24
Peak memory 215732 kb
Host smart-e0e40a0a-1220-4885-8a72-e7d853488f3f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962443393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3962443393
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1206919266
Short name T177
Test name
Test status
Simulation time 20155570 ps
CPU time 1.19 seconds
Started Jan 03 01:28:08 PM PST 24
Finished Jan 03 01:28:20 PM PST 24
Peak memory 207544 kb
Host smart-ac504ac6-1ab7-44e6-9f30-a8966b41363a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206919266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1206919266
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1371977896
Short name T158
Test name
Test status
Simulation time 16152134 ps
CPU time 1.43 seconds
Started Jan 03 01:28:10 PM PST 24
Finished Jan 03 01:28:21 PM PST 24
Peak memory 217200 kb
Host smart-a7a9031c-7931-4e73-b90a-2c55c732c889
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371977896 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1371977896
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2612619770
Short name T478
Test name
Test status
Simulation time 12614185 ps
CPU time 0.7 seconds
Started Jan 03 01:28:12 PM PST 24
Finished Jan 03 01:28:24 PM PST 24
Peak memory 204932 kb
Host smart-41c7521d-975f-4703-914f-146bcc931746
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612619770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
612619770
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3554536885
Short name T74
Test name
Test status
Simulation time 860128433 ps
CPU time 6.74 seconds
Started Jan 03 01:28:10 PM PST 24
Finished Jan 03 01:28:27 PM PST 24
Peak memory 215904 kb
Host smart-25590595-87cf-4851-aaf7-63957c67469a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554536885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3554536885
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4160247601
Short name T438
Test name
Test status
Simulation time 396890724 ps
CPU time 14.25 seconds
Started Jan 03 01:28:13 PM PST 24
Finished Jan 03 01:28:39 PM PST 24
Peak memory 215796 kb
Host smart-d6daf5d4-008f-4358-8a76-f3b7736d142f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160247601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4160247601
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.862285823
Short name T408
Test name
Test status
Simulation time 81123512 ps
CPU time 2.1 seconds
Started Jan 03 01:28:09 PM PST 24
Finished Jan 03 01:28:21 PM PST 24
Peak memory 215696 kb
Host smart-33d9bef6-2e53-43d6-a3fb-3a037b8ad74f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862285823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.862285823
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1326478778
Short name T436
Test name
Test status
Simulation time 39110449 ps
CPU time 0.7 seconds
Started Jan 03 01:30:06 PM PST 24
Finished Jan 03 01:31:01 PM PST 24
Peak memory 204924 kb
Host smart-27785a2c-4acf-4865-8dc0-639b213d2f04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326478778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1326478778
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2257430650
Short name T98
Test name
Test status
Simulation time 16015213 ps
CPU time 0.74 seconds
Started Jan 03 01:30:06 PM PST 24
Finished Jan 03 01:31:00 PM PST 24
Peak memory 204948 kb
Host smart-6fb05abe-a24b-4e76-b881-118ead5603ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257430650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2257430650
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3337001521
Short name T79
Test name
Test status
Simulation time 13973207 ps
CPU time 0.7 seconds
Started Jan 03 01:30:05 PM PST 24
Finished Jan 03 01:30:58 PM PST 24
Peak memory 204932 kb
Host smart-d87b171a-1ed8-4c0c-8287-df3124ceb03f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337001521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3337001521
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1539908661
Short name T503
Test name
Test status
Simulation time 12908887 ps
CPU time 0.7 seconds
Started Jan 03 01:30:05 PM PST 24
Finished Jan 03 01:30:57 PM PST 24
Peak memory 204928 kb
Host smart-5d69ed3d-04e0-4749-982c-c308b242fa0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539908661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1539908661
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1157386988
Short name T173
Test name
Test status
Simulation time 51373955 ps
CPU time 0.7 seconds
Started Jan 03 01:30:00 PM PST 24
Finished Jan 03 01:30:52 PM PST 24
Peak memory 204944 kb
Host smart-e77a4fcd-71fb-4d08-96df-752843fd3b13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157386988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1157386988
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.837956888
Short name T488
Test name
Test status
Simulation time 174528582 ps
CPU time 0.72 seconds
Started Jan 03 01:30:05 PM PST 24
Finished Jan 03 01:31:00 PM PST 24
Peak memory 204936 kb
Host smart-3759b525-da51-4332-9143-2e026de3320f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837956888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.837956888
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2429716149
Short name T404
Test name
Test status
Simulation time 36193882 ps
CPU time 0.7 seconds
Started Jan 03 01:29:13 PM PST 24
Finished Jan 03 01:29:21 PM PST 24
Peak memory 204964 kb
Host smart-68df75a3-bffc-4468-ac46-2fea9b643131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429716149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2429716149
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.4080486759
Short name T456
Test name
Test status
Simulation time 52930130 ps
CPU time 0.72 seconds
Started Jan 03 01:28:46 PM PST 24
Finished Jan 03 01:28:54 PM PST 24
Peak memory 204904 kb
Host smart-dc22a7f9-3cb1-4e86-b591-182ccaf0cb23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080486759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
4080486759
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2317922176
Short name T78
Test name
Test status
Simulation time 14929739 ps
CPU time 0.7 seconds
Started Jan 03 01:28:43 PM PST 24
Finished Jan 03 01:28:52 PM PST 24
Peak memory 204936 kb
Host smart-00203b4e-8383-4fb0-baaf-899b9e0f84c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317922176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2317922176
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2337025657
Short name T159
Test name
Test status
Simulation time 22668622 ps
CPU time 1.78 seconds
Started Jan 03 01:28:13 PM PST 24
Finished Jan 03 01:28:26 PM PST 24
Peak memory 218380 kb
Host smart-8cd6e757-fb1e-4f1f-bcb3-42d01cfd2490
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337025657 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2337025657
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1328841792
Short name T179
Test name
Test status
Simulation time 38171165 ps
CPU time 2.51 seconds
Started Jan 03 01:28:11 PM PST 24
Finished Jan 03 01:28:23 PM PST 24
Peak memory 215800 kb
Host smart-e4f26a38-d549-464c-804a-f3975a3a8041
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328841792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
328841792
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3918757191
Short name T397
Test name
Test status
Simulation time 52739636 ps
CPU time 0.82 seconds
Started Jan 03 01:28:10 PM PST 24
Finished Jan 03 01:28:21 PM PST 24
Peak memory 204916 kb
Host smart-f5a8d636-50f8-493e-b6b0-132b024d3e08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918757191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
918757191
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2001105419
Short name T168
Test name
Test status
Simulation time 877410380 ps
CPU time 4.16 seconds
Started Jan 03 01:28:13 PM PST 24
Finished Jan 03 01:28:29 PM PST 24
Peak memory 215768 kb
Host smart-4b8eaebc-d78b-4dc2-9a41-2dcfde1e28ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001105419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2001105419
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2863292236
Short name T140
Test name
Test status
Simulation time 54451581 ps
CPU time 4.06 seconds
Started Jan 03 01:28:11 PM PST 24
Finished Jan 03 01:28:25 PM PST 24
Peak memory 215976 kb
Host smart-5c78d81f-8c44-45d4-82bc-dcf03e7ed785
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863292236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
863292236
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2398587501
Short name T464
Test name
Test status
Simulation time 526411710 ps
CPU time 6.04 seconds
Started Jan 03 01:28:10 PM PST 24
Finished Jan 03 01:28:26 PM PST 24
Peak memory 215784 kb
Host smart-acae5b13-c4e1-4164-bcf8-c21e5f12b556
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398587501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2398587501
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.192715253
Short name T435
Test name
Test status
Simulation time 148465632 ps
CPU time 3.39 seconds
Started Jan 03 01:28:11 PM PST 24
Finished Jan 03 01:28:25 PM PST 24
Peak memory 218576 kb
Host smart-7f6c6607-4132-428e-8f32-cb6b6c7d57a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192715253 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.192715253
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.49243871
Short name T96
Test name
Test status
Simulation time 176518731 ps
CPU time 2.63 seconds
Started Jan 03 01:28:14 PM PST 24
Finished Jan 03 01:28:28 PM PST 24
Peak memory 215828 kb
Host smart-2b47095b-ff96-4e97-ba9b-4128a5d2a546
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49243871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.49243871
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2126712683
Short name T400
Test name
Test status
Simulation time 100391498 ps
CPU time 0.76 seconds
Started Jan 03 01:28:13 PM PST 24
Finished Jan 03 01:28:25 PM PST 24
Peak memory 204920 kb
Host smart-170d7902-0e13-4bc5-a6a2-ca061255299a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126712683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
126712683
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.385282342
Short name T409
Test name
Test status
Simulation time 73828132 ps
CPU time 1.97 seconds
Started Jan 03 01:28:12 PM PST 24
Finished Jan 03 01:28:25 PM PST 24
Peak memory 215728 kb
Host smart-0ea023c2-2915-43c2-97dc-9f980187756c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385282342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.385282342
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.630767978
Short name T137
Test name
Test status
Simulation time 685293510 ps
CPU time 3.86 seconds
Started Jan 03 01:28:13 PM PST 24
Finished Jan 03 01:28:28 PM PST 24
Peak memory 215916 kb
Host smart-5733e11a-631d-4b94-85e1-cf7acf5f2e9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630767978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.630767978
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4168021126
Short name T164
Test name
Test status
Simulation time 299272394 ps
CPU time 7.55 seconds
Started Jan 03 01:28:14 PM PST 24
Finished Jan 03 01:28:33 PM PST 24
Peak memory 215792 kb
Host smart-706b563e-a9b4-471e-a147-aa29c3729409
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168021126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.4168021126
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3988242602
Short name T502
Test name
Test status
Simulation time 53896358 ps
CPU time 1.53 seconds
Started Jan 03 01:28:58 PM PST 24
Finished Jan 03 01:29:04 PM PST 24
Peak memory 217160 kb
Host smart-9343eed3-eb76-486a-9530-1b990403df43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988242602 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3988242602
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1162035107
Short name T427
Test name
Test status
Simulation time 536664680 ps
CPU time 2.77 seconds
Started Jan 03 01:28:59 PM PST 24
Finished Jan 03 01:29:07 PM PST 24
Peak memory 215800 kb
Host smart-942e5fe1-eaf8-4efa-b01a-b8de65d75206
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162035107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
162035107
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.359581066
Short name T497
Test name
Test status
Simulation time 1055935840 ps
CPU time 4.76 seconds
Started Jan 03 01:28:55 PM PST 24
Finished Jan 03 01:29:05 PM PST 24
Peak memory 215852 kb
Host smart-52ec243a-76d8-40c6-8aa2-7a8285658c6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359581066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.359581066
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.737750458
Short name T139
Test name
Test status
Simulation time 414931775 ps
CPU time 5.27 seconds
Started Jan 03 01:28:13 PM PST 24
Finished Jan 03 01:28:31 PM PST 24
Peak memory 215888 kb
Host smart-af03ee7a-44e9-4e4d-abc5-6f7a9c0d8551
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737750458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.737750458
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2012759961
Short name T167
Test name
Test status
Simulation time 435427959 ps
CPU time 13.6 seconds
Started Jan 03 01:28:11 PM PST 24
Finished Jan 03 01:28:35 PM PST 24
Peak memory 215748 kb
Host smart-0f3fff2d-73e4-423f-8d1b-62db81b18660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012759961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2012759961
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3633772191
Short name T444
Test name
Test status
Simulation time 54122838 ps
CPU time 1.95 seconds
Started Jan 03 01:29:12 PM PST 24
Finished Jan 03 01:29:17 PM PST 24
Peak memory 218036 kb
Host smart-dbd21161-71cf-4a76-bfc8-5fb6fcf9b8e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633772191 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3633772191
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.919139379
Short name T492
Test name
Test status
Simulation time 77066050 ps
CPU time 1.25 seconds
Started Jan 03 01:29:13 PM PST 24
Finished Jan 03 01:29:20 PM PST 24
Peak memory 207688 kb
Host smart-e348cdeb-df99-4eb7-a687-a4fce63ecf02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919139379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.919139379
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3891200818
Short name T207
Test name
Test status
Simulation time 40258659 ps
CPU time 0.75 seconds
Started Jan 03 01:29:00 PM PST 24
Finished Jan 03 01:29:07 PM PST 24
Peak memory 204880 kb
Host smart-3a2d2bf1-55f1-4cf1-8a70-703efc1f4ecd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891200818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
891200818
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1118489600
Short name T419
Test name
Test status
Simulation time 462741008 ps
CPU time 1.94 seconds
Started Jan 03 01:28:59 PM PST 24
Finished Jan 03 01:29:06 PM PST 24
Peak memory 207584 kb
Host smart-156b7dc2-ea64-496c-8c08-4c7476278295
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118489600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1118489600
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2686726606
Short name T141
Test name
Test status
Simulation time 22420875 ps
CPU time 1.61 seconds
Started Jan 03 01:28:42 PM PST 24
Finished Jan 03 01:28:52 PM PST 24
Peak memory 216048 kb
Host smart-d776b047-c0dd-426d-8bff-5a88d4dc59d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686726606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
686726606
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3511956439
Short name T507
Test name
Test status
Simulation time 276474266 ps
CPU time 7.6 seconds
Started Jan 03 01:28:44 PM PST 24
Finished Jan 03 01:28:59 PM PST 24
Peak memory 223956 kb
Host smart-c7695d30-215f-4b63-ad02-2c7a6e8f1f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511956439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3511956439
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1662456606
Short name T399
Test name
Test status
Simulation time 185821258 ps
CPU time 1.98 seconds
Started Jan 03 01:28:57 PM PST 24
Finished Jan 03 01:29:03 PM PST 24
Peak memory 218636 kb
Host smart-9356010c-48c7-4847-be51-796147e850c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662456606 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1662456606
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3641630508
Short name T484
Test name
Test status
Simulation time 1217274246 ps
CPU time 2.42 seconds
Started Jan 03 01:29:22 PM PST 24
Finished Jan 03 01:29:36 PM PST 24
Peak memory 215844 kb
Host smart-4b11895c-c6b5-4ca7-9416-330aaeed552e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641630508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
641630508
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3842657980
Short name T457
Test name
Test status
Simulation time 134716812 ps
CPU time 0.76 seconds
Started Jan 03 01:29:14 PM PST 24
Finished Jan 03 01:29:22 PM PST 24
Peak memory 204880 kb
Host smart-5848b043-74e7-4335-b75f-4072bb0308c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842657980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
842657980
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3653669705
Short name T471
Test name
Test status
Simulation time 164859697 ps
CPU time 2.15 seconds
Started Jan 03 01:29:00 PM PST 24
Finished Jan 03 01:29:08 PM PST 24
Peak memory 215832 kb
Host smart-46d6ba4f-b5a0-4cf5-bd6a-833b9fafbda1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653669705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3653669705
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4271862632
Short name T73
Test name
Test status
Simulation time 699062107 ps
CPU time 4.78 seconds
Started Jan 03 01:28:45 PM PST 24
Finished Jan 03 01:28:58 PM PST 24
Peak memory 215928 kb
Host smart-cf1c501f-09c5-4c63-8274-c5ac4f33db1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271862632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
271862632
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.62701057
Short name T218
Test name
Test status
Simulation time 1155039141 ps
CPU time 8.51 seconds
Started Jan 03 01:29:00 PM PST 24
Finished Jan 03 01:29:15 PM PST 24
Peak memory 215804 kb
Host smart-bf76d0b9-9aec-4ee0-85eb-9b284dbd49f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62701057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_t
l_intg_err.62701057
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_abort.1356304605
Short name T954
Test name
Test status
Simulation time 57630116 ps
CPU time 0.76 seconds
Started Jan 03 01:50:12 PM PST 24
Finished Jan 03 01:50:33 PM PST 24
Peak memory 206596 kb
Host smart-b94df3c0-6bd8-44e6-9e02-6259b0ecfa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356304605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_abort.1356304605
Directory /workspace/0.spi_device_abort/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.4048362626
Short name T907
Test name
Test status
Simulation time 14837498 ps
CPU time 0.68 seconds
Started Jan 03 01:51:00 PM PST 24
Finished Jan 03 01:51:05 PM PST 24
Peak memory 206496 kb
Host smart-32da910a-cec5-4699-aedb-2de822d364f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048362626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4
048362626
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_bit_transfer.3469681752
Short name T782
Test name
Test status
Simulation time 819722689 ps
CPU time 2.79 seconds
Started Jan 03 01:50:29 PM PST 24
Finished Jan 03 01:50:42 PM PST 24
Peak memory 216816 kb
Host smart-6d54a548-de25-4d22-8f18-8d5b39d66b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469681752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_bit_transfer.3469681752
Directory /workspace/0.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/0.spi_device_byte_transfer.2101143146
Short name T2
Test name
Test status
Simulation time 436449874 ps
CPU time 2.44 seconds
Started Jan 03 01:50:11 PM PST 24
Finished Jan 03 01:50:35 PM PST 24
Peak memory 216832 kb
Host smart-2366c891-1871-4c23-b069-90764fbb8a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101143146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_byte_transfer.2101143146
Directory /workspace/0.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1261997357
Short name T1061
Test name
Test status
Simulation time 335985058 ps
CPU time 3.03 seconds
Started Jan 03 01:50:26 PM PST 24
Finished Jan 03 01:50:41 PM PST 24
Peak memory 218296 kb
Host smart-41175372-cf3d-4bb6-ab3a-7d7aea5972e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261997357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1261997357
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.443426415
Short name T963
Test name
Test status
Simulation time 64589211 ps
CPU time 0.74 seconds
Started Jan 03 01:50:08 PM PST 24
Finished Jan 03 01:50:31 PM PST 24
Peak memory 206616 kb
Host smart-e34235dd-4f5e-4032-9e4f-b207460bab49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443426415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.443426415
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_dummy_item_extra_dly.3562504169
Short name T1353
Test name
Test status
Simulation time 192448357275 ps
CPU time 138.66 seconds
Started Jan 03 01:50:12 PM PST 24
Finished Jan 03 01:52:51 PM PST 24
Peak memory 265472 kb
Host smart-2de8d03c-a542-4d22-a5c2-83b18b6937a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562504169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_dummy_item_extra_dly.3562504169
Directory /workspace/0.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/0.spi_device_extreme_fifo_size.3365440551
Short name T1701
Test name
Test status
Simulation time 4598250555 ps
CPU time 38.09 seconds
Started Jan 03 01:50:07 PM PST 24
Finished Jan 03 01:51:08 PM PST 24
Peak memory 233688 kb
Host smart-cc944c96-0820-482a-b1df-c8f2c5d2ab0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365440551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_extreme_fifo_size.3365440551
Directory /workspace/0.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/0.spi_device_fifo_full.1454904811
Short name T1373
Test name
Test status
Simulation time 34247197148 ps
CPU time 549.11 seconds
Started Jan 03 01:50:08 PM PST 24
Finished Jan 03 01:59:39 PM PST 24
Peak memory 282608 kb
Host smart-f3731826-01bd-4b60-ab8e-c2f49790fea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454904811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_fifo_full.1454904811
Directory /workspace/0.spi_device_fifo_full/latest

Test location /workspace/coverage/default/0.spi_device_fifo_underflow_overflow.3653973732
Short name T1647
Test name
Test status
Simulation time 9986633261 ps
CPU time 65.26 seconds
Started Jan 03 01:50:07 PM PST 24
Finished Jan 03 01:51:35 PM PST 24
Peak memory 264440 kb
Host smart-492c6c5a-36a0-4908-a040-639cd9bcec46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653973732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_fifo_underflow_overfl
ow.3653973732
Directory /workspace/0.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1253421852
Short name T387
Test name
Test status
Simulation time 18771161940 ps
CPU time 124.14 seconds
Started Jan 03 01:50:33 PM PST 24
Finished Jan 03 01:52:45 PM PST 24
Peak memory 249728 kb
Host smart-851c2922-e227-4d7a-aaec-8b626fdd32b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253421852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1253421852
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2014920708
Short name T1520
Test name
Test status
Simulation time 40605224544 ps
CPU time 331.34 seconds
Started Jan 03 01:51:02 PM PST 24
Finished Jan 03 01:56:38 PM PST 24
Peak memory 256292 kb
Host smart-dd039387-2dd4-487c-8774-63efb58bbdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014920708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2014920708
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1464699528
Short name T1349
Test name
Test status
Simulation time 1379864306 ps
CPU time 8.35 seconds
Started Jan 03 01:50:26 PM PST 24
Finished Jan 03 01:50:47 PM PST 24
Peak memory 238552 kb
Host smart-93942898-976e-4a8f-a0d4-ef68f2faed48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464699528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1464699528
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_intr.630752741
Short name T1721
Test name
Test status
Simulation time 57591466294 ps
CPU time 82.89 seconds
Started Jan 03 01:50:08 PM PST 24
Finished Jan 03 01:51:53 PM PST 24
Peak memory 241580 kb
Host smart-81d60677-206f-489f-be0f-74af719a7f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630752741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intr.630752741
Directory /workspace/0.spi_device_intr/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2863163296
Short name T1771
Test name
Test status
Simulation time 405319176 ps
CPU time 4.14 seconds
Started Jan 03 01:50:33 PM PST 24
Finished Jan 03 01:50:45 PM PST 24
Peak memory 220628 kb
Host smart-c7b7b2e8-2ec6-47d2-ae48-f5b8140e8a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863163296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2863163296
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3810929142
Short name T1318
Test name
Test status
Simulation time 60407868 ps
CPU time 1.07 seconds
Started Jan 03 01:50:09 PM PST 24
Finished Jan 03 01:50:33 PM PST 24
Peak memory 218820 kb
Host smart-7a3952d3-6597-4381-bf7c-397fdcc109da
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810929142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3810929142
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3163978158
Short name T1479
Test name
Test status
Simulation time 17095770556 ps
CPU time 13.15 seconds
Started Jan 03 01:50:35 PM PST 24
Finished Jan 03 01:50:55 PM PST 24
Peak memory 225052 kb
Host smart-8659309a-2e73-4abd-b2fe-fcbfc7d477c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163978158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3163978158
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3190949836
Short name T1140
Test name
Test status
Simulation time 18008865738 ps
CPU time 25.48 seconds
Started Jan 03 01:50:26 PM PST 24
Finished Jan 03 01:51:04 PM PST 24
Peak memory 241468 kb
Host smart-4d3ba3eb-01f1-4960-8492-b7cce75ebbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190949836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3190949836
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_perf.1105708020
Short name T796
Test name
Test status
Simulation time 264630855810 ps
CPU time 546.92 seconds
Started Jan 03 01:50:07 PM PST 24
Finished Jan 03 01:59:37 PM PST 24
Peak memory 266080 kb
Host smart-060c2472-0f19-4419-acc5-75ff170f8dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105708020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_perf.1105708020
Directory /workspace/0.spi_device_perf/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1754919121
Short name T1485
Test name
Test status
Simulation time 41311293 ps
CPU time 0.72 seconds
Started Jan 03 01:50:07 PM PST 24
Finished Jan 03 01:50:31 PM PST 24
Peak memory 216696 kb
Host smart-8ec5a008-0a1d-46fc-a337-0853dcbd2682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754919121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1754919121
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3711479310
Short name T191
Test name
Test status
Simulation time 10399211913 ps
CPU time 6.29 seconds
Started Jan 03 01:50:33 PM PST 24
Finished Jan 03 01:50:47 PM PST 24
Peak memory 218900 kb
Host smart-c682cf63-47c5-4d6e-a8ae-3db8154e6ee8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3711479310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3711479310
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_rx_async_fifo_reset.4092061337
Short name T1370
Test name
Test status
Simulation time 34272699 ps
CPU time 0.87 seconds
Started Jan 03 01:50:29 PM PST 24
Finished Jan 03 01:50:40 PM PST 24
Peak memory 208540 kb
Host smart-8d23969b-a1c7-48e8-9d38-6aa93157b35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092061337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_rx_async_fifo_reset.4092061337
Directory /workspace/0.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/0.spi_device_rx_timeout.371383302
Short name T914
Test name
Test status
Simulation time 658624771 ps
CPU time 6.04 seconds
Started Jan 03 01:50:12 PM PST 24
Finished Jan 03 01:50:38 PM PST 24
Peak memory 216804 kb
Host smart-0acaee90-4e3b-4506-ad0f-eef598c1d801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371383302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_rx_timeout.371383302
Directory /workspace/0.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/0.spi_device_smoke.3532265395
Short name T1152
Test name
Test status
Simulation time 207472130 ps
CPU time 1.07 seconds
Started Jan 03 01:50:06 PM PST 24
Finished Jan 03 01:50:30 PM PST 24
Peak memory 208124 kb
Host smart-2af0a81a-64b9-44b1-a4f2-7b4945c72385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532265395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_smoke.3532265395
Directory /workspace/0.spi_device_smoke/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.78797177
Short name T1253
Test name
Test status
Simulation time 210884688081 ps
CPU time 893.75 seconds
Started Jan 03 01:50:49 PM PST 24
Finished Jan 03 02:05:52 PM PST 24
Peak memory 451480 kb
Host smart-d5e0f065-8ad6-4f1b-8897-3ca96c11cc47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78797177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_
all.78797177
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3714418403
Short name T1200
Test name
Test status
Simulation time 861552074 ps
CPU time 14.69 seconds
Started Jan 03 01:50:12 PM PST 24
Finished Jan 03 01:50:47 PM PST 24
Peak memory 216808 kb
Host smart-0b6dcb4b-db48-431c-9903-81d89420be86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714418403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3714418403
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.594639362
Short name T897
Test name
Test status
Simulation time 21635503298 ps
CPU time 32.1 seconds
Started Jan 03 01:50:10 PM PST 24
Finished Jan 03 01:51:04 PM PST 24
Peak memory 216836 kb
Host smart-c86054d2-4dd0-4e92-9993-547b866e6812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594639362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.594639362
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1975714417
Short name T659
Test name
Test status
Simulation time 64498172 ps
CPU time 1.08 seconds
Started Jan 03 01:50:11 PM PST 24
Finished Jan 03 01:50:33 PM PST 24
Peak memory 207992 kb
Host smart-0d216dc2-ed09-4820-a20c-3706f15f4d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975714417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1975714417
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.523080431
Short name T1099
Test name
Test status
Simulation time 253385131 ps
CPU time 0.95 seconds
Started Jan 03 01:50:13 PM PST 24
Finished Jan 03 01:50:34 PM PST 24
Peak memory 207992 kb
Host smart-e479e13b-4ed5-4262-a070-cafc3be98e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523080431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.523080431
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_tx_async_fifo_reset.2447233894
Short name T1237
Test name
Test status
Simulation time 21971937 ps
CPU time 0.83 seconds
Started Jan 03 01:50:27 PM PST 24
Finished Jan 03 01:50:40 PM PST 24
Peak memory 208428 kb
Host smart-13b7c2f2-ba9c-4a90-997a-61e1d43520d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447233894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tx_async_fifo_reset.2447233894
Directory /workspace/0.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/0.spi_device_txrx.1486861849
Short name T676
Test name
Test status
Simulation time 10000139564 ps
CPU time 127.64 seconds
Started Jan 03 01:50:07 PM PST 24
Finished Jan 03 01:52:38 PM PST 24
Peak memory 272552 kb
Host smart-a4a2adfa-f863-40f8-9b52-f790b4cd727e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486861849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_txrx.1486861849
Directory /workspace/0.spi_device_txrx/latest

Test location /workspace/coverage/default/0.spi_device_upload.799991664
Short name T1031
Test name
Test status
Simulation time 5519083252 ps
CPU time 21.64 seconds
Started Jan 03 01:50:26 PM PST 24
Finished Jan 03 01:51:00 PM PST 24
Peak memory 219100 kb
Host smart-8c5a981c-250f-4bc2-940d-81639dba16b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799991664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.799991664
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_abort.3157523659
Short name T581
Test name
Test status
Simulation time 121120172 ps
CPU time 0.77 seconds
Started Jan 03 01:50:07 PM PST 24
Finished Jan 03 01:50:30 PM PST 24
Peak memory 206652 kb
Host smart-84340ed1-6ce9-4101-b611-489ecf8d7fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157523659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_abort.3157523659
Directory /workspace/1.spi_device_abort/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2211059318
Short name T733
Test name
Test status
Simulation time 14881388 ps
CPU time 0.76 seconds
Started Jan 03 01:50:32 PM PST 24
Finished Jan 03 01:50:41 PM PST 24
Peak memory 206524 kb
Host smart-86460d5d-991f-4e0e-b2c4-3ffae9461b68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211059318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
211059318
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_bit_transfer.848872078
Short name T778
Test name
Test status
Simulation time 227768146 ps
CPU time 2.38 seconds
Started Jan 03 01:50:10 PM PST 24
Finished Jan 03 01:50:34 PM PST 24
Peak memory 216744 kb
Host smart-b94824f8-a431-4049-b673-33968afb5ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848872078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_bit_transfer.848872078
Directory /workspace/1.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/1.spi_device_byte_transfer.858083969
Short name T1388
Test name
Test status
Simulation time 402416473 ps
CPU time 2.47 seconds
Started Jan 03 01:51:04 PM PST 24
Finished Jan 03 01:51:11 PM PST 24
Peak memory 216784 kb
Host smart-2806e3cc-f2c9-4ca1-90bc-d6bf30f67078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858083969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_byte_transfer.858083969
Directory /workspace/1.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2415814496
Short name T630
Test name
Test status
Simulation time 1686991823 ps
CPU time 7.28 seconds
Started Jan 03 01:50:10 PM PST 24
Finished Jan 03 01:50:39 PM PST 24
Peak memory 224956 kb
Host smart-64f0c562-73d3-4c52-8f28-5bd791ea5bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415814496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2415814496
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3709203466
Short name T1614
Test name
Test status
Simulation time 39292100 ps
CPU time 0.77 seconds
Started Jan 03 01:51:06 PM PST 24
Finished Jan 03 01:51:14 PM PST 24
Peak memory 207480 kb
Host smart-2bb2bfd3-24cd-4cc3-bfd6-6965c0c0992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709203466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3709203466
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_dummy_item_extra_dly.2479741353
Short name T633
Test name
Test status
Simulation time 102124156337 ps
CPU time 855.18 seconds
Started Jan 03 01:51:01 PM PST 24
Finished Jan 03 02:05:21 PM PST 24
Peak memory 271484 kb
Host smart-541b2457-a18d-45c1-ad92-9c2bc0cfb34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479741353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_dummy_item_extra_dly.2479741353
Directory /workspace/1.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/1.spi_device_fifo_full.3934187319
Short name T1738
Test name
Test status
Simulation time 26704355114 ps
CPU time 451.24 seconds
Started Jan 03 01:50:45 PM PST 24
Finished Jan 03 01:58:26 PM PST 24
Peak memory 300064 kb
Host smart-a336db39-f651-45ae-a5ff-8b01565a1a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934187319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_fifo_full.3934187319
Directory /workspace/1.spi_device_fifo_full/latest

Test location /workspace/coverage/default/1.spi_device_fifo_underflow_overflow.3487575613
Short name T699
Test name
Test status
Simulation time 34085885508 ps
CPU time 113.31 seconds
Started Jan 03 01:51:08 PM PST 24
Finished Jan 03 01:53:10 PM PST 24
Peak memory 316468 kb
Host smart-70190714-c4ee-4985-bde4-91fd330531f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487575613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_fifo_underflow_overfl
ow.3487575613
Directory /workspace/1.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.246125402
Short name T753
Test name
Test status
Simulation time 1129868419 ps
CPU time 4.49 seconds
Started Jan 03 01:50:33 PM PST 24
Finished Jan 03 01:50:46 PM PST 24
Peak memory 220952 kb
Host smart-2904781c-e077-4ea2-b6f5-6aed2d0c279e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246125402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.246125402
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1222997389
Short name T1542
Test name
Test status
Simulation time 2754847472 ps
CPU time 58.46 seconds
Started Jan 03 01:50:37 PM PST 24
Finished Jan 03 01:51:41 PM PST 24
Peak memory 249780 kb
Host smart-11170212-64f4-4dc3-a06b-c96eacff1e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222997389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1222997389
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2651916364
Short name T776
Test name
Test status
Simulation time 59285658628 ps
CPU time 123.56 seconds
Started Jan 03 01:50:46 PM PST 24
Finished Jan 03 01:52:59 PM PST 24
Peak memory 255468 kb
Host smart-b6ff61cb-6d57-4973-b065-c3a77defd527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651916364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2651916364
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1963909916
Short name T1678
Test name
Test status
Simulation time 5091028350 ps
CPU time 25.58 seconds
Started Jan 03 01:50:09 PM PST 24
Finished Jan 03 01:50:57 PM PST 24
Peak memory 246448 kb
Host smart-8111e534-a8c2-4e5d-9b13-9f99b8d6d6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963909916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1963909916
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2166021953
Short name T18
Test name
Test status
Simulation time 700537412 ps
CPU time 5.63 seconds
Started Jan 03 01:50:11 PM PST 24
Finished Jan 03 01:50:38 PM PST 24
Peak memory 238436 kb
Host smart-692131e8-b58a-4ce7-a61a-b6268d8de506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166021953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2166021953
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_intr.2288036942
Short name T917
Test name
Test status
Simulation time 6244130380 ps
CPU time 37.21 seconds
Started Jan 03 01:51:04 PM PST 24
Finished Jan 03 01:51:45 PM PST 24
Peak memory 232964 kb
Host smart-7356d79f-71a4-4a17-893a-2cfbb8c6ab04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288036942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intr.2288036942
Directory /workspace/1.spi_device_intr/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3943495388
Short name T1074
Test name
Test status
Simulation time 3553213163 ps
CPU time 13.19 seconds
Started Jan 03 01:50:07 PM PST 24
Finished Jan 03 01:50:43 PM PST 24
Peak memory 232320 kb
Host smart-6b3df174-ae9f-4b4c-9730-0398606f630e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943495388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3943495388
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2298275216
Short name T1753
Test name
Test status
Simulation time 37794444 ps
CPU time 1.04 seconds
Started Jan 03 01:51:05 PM PST 24
Finished Jan 03 01:51:12 PM PST 24
Peak memory 218820 kb
Host smart-c0fb2c06-348d-4b4e-9216-8b6f610d1307
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298275216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2298275216
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2042035184
Short name T1755
Test name
Test status
Simulation time 11985366172 ps
CPU time 19.27 seconds
Started Jan 03 01:50:08 PM PST 24
Finished Jan 03 01:50:50 PM PST 24
Peak memory 249624 kb
Host smart-8eaf234c-d26c-436c-b469-ec076c63b6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042035184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2042035184
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1084327348
Short name T318
Test name
Test status
Simulation time 6286722444 ps
CPU time 13.68 seconds
Started Jan 03 01:50:08 PM PST 24
Finished Jan 03 01:50:44 PM PST 24
Peak memory 225140 kb
Host smart-a1eb89b9-12b4-4b00-842e-0d40408f95ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084327348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1084327348
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_perf.587258435
Short name T1571
Test name
Test status
Simulation time 6047160579 ps
CPU time 166.54 seconds
Started Jan 03 01:51:04 PM PST 24
Finished Jan 03 01:53:56 PM PST 24
Peak memory 257116 kb
Host smart-55a7dbeb-58b3-4800-8b04-d31084be13e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587258435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_perf.587258435
Directory /workspace/1.spi_device_perf/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.4293866058
Short name T1291
Test name
Test status
Simulation time 21075493 ps
CPU time 0.77 seconds
Started Jan 03 01:51:28 PM PST 24
Finished Jan 03 01:51:50 PM PST 24
Peak memory 216704 kb
Host smart-cbc5d624-b583-4f5b-9847-146077fa0220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293866058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.4293866058
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2809274603
Short name T1043
Test name
Test status
Simulation time 2781284177 ps
CPU time 4.94 seconds
Started Jan 03 01:50:46 PM PST 24
Finished Jan 03 01:51:01 PM PST 24
Peak memory 221204 kb
Host smart-28111eae-b8bd-475d-b577-fc28cb1c84f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2809274603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2809274603
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_rx_async_fifo_reset.1523791155
Short name T1409
Test name
Test status
Simulation time 100859391 ps
CPU time 0.89 seconds
Started Jan 03 01:51:25 PM PST 24
Finished Jan 03 01:51:43 PM PST 24
Peak memory 208496 kb
Host smart-d960fa02-303d-478d-91dc-02db2788d465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523791155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_rx_async_fifo_reset.1523791155
Directory /workspace/1.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/1.spi_device_rx_timeout.3119006447
Short name T860
Test name
Test status
Simulation time 2980470939 ps
CPU time 5.89 seconds
Started Jan 03 01:51:23 PM PST 24
Finished Jan 03 01:51:43 PM PST 24
Peak memory 216820 kb
Host smart-18336457-93ae-4aa2-9e8f-4f4f1bedf4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119006447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_rx_timeout.3119006447
Directory /workspace/1.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3712831941
Short name T103
Test name
Test status
Simulation time 84486196 ps
CPU time 1 seconds
Started Jan 03 01:50:28 PM PST 24
Finished Jan 03 01:50:40 PM PST 24
Peak memory 237052 kb
Host smart-01bde539-a41c-4157-8ad3-998d93c10c2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712831941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3712831941
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_smoke.1034110373
Short name T970
Test name
Test status
Simulation time 35126809 ps
CPU time 0.95 seconds
Started Jan 03 01:51:02 PM PST 24
Finished Jan 03 01:51:07 PM PST 24
Peak memory 207948 kb
Host smart-13bd2c3d-c08e-453b-bc66-52215a6e1965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034110373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_smoke.1034110373
Directory /workspace/1.spi_device_smoke/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3840056936
Short name T1121
Test name
Test status
Simulation time 7101603198 ps
CPU time 42.94 seconds
Started Jan 03 01:50:09 PM PST 24
Finished Jan 03 01:51:14 PM PST 24
Peak memory 220676 kb
Host smart-12977016-2286-4d52-ad48-8c726da3d779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840056936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3840056936
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.385684811
Short name T1509
Test name
Test status
Simulation time 70727115544 ps
CPU time 30.88 seconds
Started Jan 03 01:50:08 PM PST 24
Finished Jan 03 01:51:01 PM PST 24
Peak memory 216884 kb
Host smart-c29784f9-f867-4fd2-a5cb-c144a61000bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385684811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.385684811
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.4069569515
Short name T1077
Test name
Test status
Simulation time 308898962 ps
CPU time 2.81 seconds
Started Jan 03 01:50:09 PM PST 24
Finished Jan 03 01:50:34 PM PST 24
Peak memory 216804 kb
Host smart-ef0df3ed-8631-4560-a780-f819b234432b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069569515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.4069569515
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.687686
Short name T1158
Test name
Test status
Simulation time 47374051 ps
CPU time 0.94 seconds
Started Jan 03 01:50:11 PM PST 24
Finished Jan 03 01:50:33 PM PST 24
Peak memory 207936 kb
Host smart-30beb77d-d00e-4f23-86df-b04fda993b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.687686
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_tx_async_fifo_reset.3426428265
Short name T1707
Test name
Test status
Simulation time 15537062 ps
CPU time 0.76 seconds
Started Jan 03 01:50:09 PM PST 24
Finished Jan 03 01:50:31 PM PST 24
Peak memory 208516 kb
Host smart-04b66f60-bbaa-41d4-a6b5-d781475dfe9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426428265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tx_async_fifo_reset.3426428265
Directory /workspace/1.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/1.spi_device_txrx.3150676573
Short name T1743
Test name
Test status
Simulation time 25303701403 ps
CPU time 197.61 seconds
Started Jan 03 01:50:30 PM PST 24
Finished Jan 03 01:53:57 PM PST 24
Peak memory 252220 kb
Host smart-f7f0e5bb-03c8-44d7-9821-9a2e73724a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150676573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_txrx.3150676573
Directory /workspace/1.spi_device_txrx/latest

Test location /workspace/coverage/default/1.spi_device_upload.204675645
Short name T323
Test name
Test status
Simulation time 1738357540 ps
CPU time 4.73 seconds
Started Jan 03 01:50:10 PM PST 24
Finished Jan 03 01:50:36 PM PST 24
Peak memory 240512 kb
Host smart-6b3f68ef-ba69-45df-a124-d7f6e6b9a045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204675645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.204675645
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_abort.1117697898
Short name T540
Test name
Test status
Simulation time 19626134 ps
CPU time 0.76 seconds
Started Jan 03 01:54:38 PM PST 24
Finished Jan 03 01:54:47 PM PST 24
Peak memory 206640 kb
Host smart-57a4a4a9-9995-4ec4-8b44-719c3d906008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117697898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_abort.1117697898
Directory /workspace/10.spi_device_abort/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2697041120
Short name T755
Test name
Test status
Simulation time 91813456 ps
CPU time 0.7 seconds
Started Jan 03 01:54:40 PM PST 24
Finished Jan 03 01:54:49 PM PST 24
Peak memory 206484 kb
Host smart-97119b6a-312e-4e3f-a937-52debe81f669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697041120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2697041120
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_bit_transfer.1696131979
Short name T1612
Test name
Test status
Simulation time 376511743 ps
CPU time 2.57 seconds
Started Jan 03 01:54:37 PM PST 24
Finished Jan 03 01:54:45 PM PST 24
Peak memory 216812 kb
Host smart-8462deaa-b2d2-4269-99f1-f68ef3ff8a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696131979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_bit_transfer.1696131979
Directory /workspace/10.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/10.spi_device_byte_transfer.1899797078
Short name T1457
Test name
Test status
Simulation time 228633098 ps
CPU time 3.26 seconds
Started Jan 03 01:54:36 PM PST 24
Finished Jan 03 01:54:45 PM PST 24
Peak memory 216800 kb
Host smart-ac2149b0-437d-47c5-be27-5d88bc2a41eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899797078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_byte_transfer.1899797078
Directory /workspace/10.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2116878127
Short name T1419
Test name
Test status
Simulation time 41348902 ps
CPU time 2.64 seconds
Started Jan 03 01:54:41 PM PST 24
Finished Jan 03 01:54:53 PM PST 24
Peak memory 225076 kb
Host smart-e7b3e972-162d-4865-8d97-ebfeec3ad4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116878127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2116878127
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_dummy_item_extra_dly.1617596895
Short name T220
Test name
Test status
Simulation time 103353663008 ps
CPU time 496.02 seconds
Started Jan 03 01:54:36 PM PST 24
Finished Jan 03 02:02:58 PM PST 24
Peak memory 282344 kb
Host smart-e0eb5933-0e9e-4ccc-9478-131c534b9f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617596895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_dummy_item_extra_dly.1617596895
Directory /workspace/10.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/10.spi_device_fifo_full.3804277031
Short name T583
Test name
Test status
Simulation time 15558200648 ps
CPU time 184.88 seconds
Started Jan 03 01:54:37 PM PST 24
Finished Jan 03 01:57:47 PM PST 24
Peak memory 269088 kb
Host smart-6f3f9896-e6b0-46e3-8cbc-7b409e033eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804277031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_fifo_full.3804277031
Directory /workspace/10.spi_device_fifo_full/latest

Test location /workspace/coverage/default/10.spi_device_fifo_underflow_overflow.1094095134
Short name T1288
Test name
Test status
Simulation time 124672118872 ps
CPU time 343.58 seconds
Started Jan 03 01:54:38 PM PST 24
Finished Jan 03 02:00:27 PM PST 24
Peak memory 335916 kb
Host smart-b05c3390-602d-40d6-a334-7b63abff4e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094095134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_fifo_underflow_overf
low.1094095134
Directory /workspace/10.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2179252045
Short name T281
Test name
Test status
Simulation time 29749018988 ps
CPU time 173.01 seconds
Started Jan 03 01:54:41 PM PST 24
Finished Jan 03 01:57:43 PM PST 24
Peak memory 266116 kb
Host smart-289173e9-d7ac-4dea-ba02-0f6aba9963e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179252045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2179252045
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3313971158
Short name T1434
Test name
Test status
Simulation time 13052203047 ps
CPU time 121.68 seconds
Started Jan 03 01:54:40 PM PST 24
Finished Jan 03 01:56:51 PM PST 24
Peak memory 239448 kb
Host smart-75927a7e-10aa-44f0-bf01-30ca82a59ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313971158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3313971158
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2412662551
Short name T1594
Test name
Test status
Simulation time 19267752171 ps
CPU time 47.29 seconds
Started Jan 03 01:54:40 PM PST 24
Finished Jan 03 01:55:36 PM PST 24
Peak memory 253348 kb
Host smart-4a34ed38-4df7-4904-a938-9fb92a956606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412662551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2412662551
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1093156423
Short name T1067
Test name
Test status
Simulation time 3043204832 ps
CPU time 5.52 seconds
Started Jan 03 01:54:39 PM PST 24
Finished Jan 03 01:54:53 PM PST 24
Peak memory 219564 kb
Host smart-2f280683-5737-4ede-a40e-96326a4a92aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093156423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1093156423
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_intr.2081861207
Short name T1734
Test name
Test status
Simulation time 148616755561 ps
CPU time 137.7 seconds
Started Jan 03 01:54:35 PM PST 24
Finished Jan 03 01:56:58 PM PST 24
Peak memory 249376 kb
Host smart-54d255a4-fd64-439b-8571-9b8299915a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081861207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intr.2081861207
Directory /workspace/10.spi_device_intr/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1495570908
Short name T1240
Test name
Test status
Simulation time 1603313338 ps
CPU time 8.28 seconds
Started Jan 03 01:54:40 PM PST 24
Finished Jan 03 01:54:57 PM PST 24
Peak memory 220204 kb
Host smart-1fa2219b-9f68-4814-a367-4c105f0d0488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495570908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1495570908
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1538095688
Short name T1284
Test name
Test status
Simulation time 14850685 ps
CPU time 1 seconds
Started Jan 03 01:54:38 PM PST 24
Finished Jan 03 01:54:45 PM PST 24
Peak memory 217820 kb
Host smart-9b6c6e59-401d-45d9-87c1-956a65cda871
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538095688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1538095688
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3215324566
Short name T340
Test name
Test status
Simulation time 2372619062 ps
CPU time 15.78 seconds
Started Jan 03 01:54:37 PM PST 24
Finished Jan 03 01:54:59 PM PST 24
Peak memory 255720 kb
Host smart-3a7b6d9e-520c-41a9-b394-296123c51d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215324566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3215324566
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2617071561
Short name T295
Test name
Test status
Simulation time 38985714238 ps
CPU time 21.46 seconds
Started Jan 03 01:54:36 PM PST 24
Finished Jan 03 01:55:03 PM PST 24
Peak memory 238980 kb
Host smart-cc78f93f-52f3-41b0-a306-ee80ce200c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617071561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2617071561
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_perf.3179805123
Short name T1292
Test name
Test status
Simulation time 66398346512 ps
CPU time 252.67 seconds
Started Jan 03 01:54:36 PM PST 24
Finished Jan 03 01:58:54 PM PST 24
Peak memory 282008 kb
Host smart-8a3e3ad3-89c4-498c-ac9d-4f34aa21e0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179805123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_perf.3179805123
Directory /workspace/10.spi_device_perf/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3144232039
Short name T1241
Test name
Test status
Simulation time 6380631974 ps
CPU time 8.71 seconds
Started Jan 03 01:54:40 PM PST 24
Finished Jan 03 01:54:58 PM PST 24
Peak memory 234836 kb
Host smart-e8cb1a10-45ba-49e5-b223-a873d56c2d74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3144232039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3144232039
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_rx_async_fifo_reset.3737959684
Short name T817
Test name
Test status
Simulation time 60408176 ps
CPU time 0.85 seconds
Started Jan 03 01:54:38 PM PST 24
Finished Jan 03 01:54:45 PM PST 24
Peak memory 208476 kb
Host smart-0c2730e4-13e3-4c52-8c95-a0618454a00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737959684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_rx_async_fifo_reset.3737959684
Directory /workspace/10.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/10.spi_device_rx_timeout.922754843
Short name T972
Test name
Test status
Simulation time 1911888653 ps
CPU time 7.01 seconds
Started Jan 03 01:54:36 PM PST 24
Finished Jan 03 01:54:48 PM PST 24
Peak memory 216788 kb
Host smart-006b7098-fdaf-4e8c-b51b-3744b78dd48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922754843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_rx_timeout.922754843
Directory /workspace/10.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/10.spi_device_smoke.71274956
Short name T629
Test name
Test status
Simulation time 114099206 ps
CPU time 1.08 seconds
Started Jan 03 01:54:36 PM PST 24
Finished Jan 03 01:54:43 PM PST 24
Peak memory 216588 kb
Host smart-1763a9cf-1728-4904-9f11-097d2aef3dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71274956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_smoke.71274956
Directory /workspace/10.spi_device_smoke/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1404353099
Short name T392
Test name
Test status
Simulation time 33640316970 ps
CPU time 245.79 seconds
Started Jan 03 01:54:36 PM PST 24
Finished Jan 03 01:58:47 PM PST 24
Peak memory 216972 kb
Host smart-cd7b44e1-2252-439f-8fab-bf925167ba05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404353099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1404353099
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2858451616
Short name T125
Test name
Test status
Simulation time 17888422124 ps
CPU time 20.06 seconds
Started Jan 03 01:54:38 PM PST 24
Finished Jan 03 01:55:04 PM PST 24
Peak memory 216904 kb
Host smart-f4ab8168-9068-40d7-81bf-bd9001dbda27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858451616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2858451616
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2539062376
Short name T757
Test name
Test status
Simulation time 683973649 ps
CPU time 2.27 seconds
Started Jan 03 01:54:39 PM PST 24
Finished Jan 03 01:54:49 PM PST 24
Peak memory 216772 kb
Host smart-8bda5d49-573a-46f4-835b-976c9d4e9216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539062376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2539062376
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1356645337
Short name T545
Test name
Test status
Simulation time 64824495 ps
CPU time 0.69 seconds
Started Jan 03 01:54:40 PM PST 24
Finished Jan 03 01:54:50 PM PST 24
Peak memory 206928 kb
Host smart-24c05c01-2c52-4fc4-a639-8ef4426ef733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356645337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1356645337
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_tx_async_fifo_reset.905906464
Short name T842
Test name
Test status
Simulation time 52855946 ps
CPU time 0.74 seconds
Started Jan 03 01:54:37 PM PST 24
Finished Jan 03 01:54:43 PM PST 24
Peak memory 208512 kb
Host smart-5fe71625-adbe-4930-9032-565857b55e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905906464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tx_async_fifo_reset.905906464
Directory /workspace/10.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/10.spi_device_txrx.4227333188
Short name T183
Test name
Test status
Simulation time 19728730162 ps
CPU time 208.98 seconds
Started Jan 03 01:54:35 PM PST 24
Finished Jan 03 01:58:09 PM PST 24
Peak memory 273360 kb
Host smart-7b8cb9ea-b4c5-4e80-9388-8b36ba3bf547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227333188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_txrx.4227333188
Directory /workspace/10.spi_device_txrx/latest

Test location /workspace/coverage/default/10.spi_device_upload.3738580267
Short name T1403
Test name
Test status
Simulation time 3002236953 ps
CPU time 7.25 seconds
Started Jan 03 01:54:39 PM PST 24
Finished Jan 03 01:54:55 PM PST 24
Peak memory 238708 kb
Host smart-e629a11a-7818-489a-9ae0-2c3ebceda9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738580267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3738580267
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_abort.2753713957
Short name T933
Test name
Test status
Simulation time 58257681 ps
CPU time 0.75 seconds
Started Jan 03 01:54:41 PM PST 24
Finished Jan 03 01:54:51 PM PST 24
Peak memory 206644 kb
Host smart-ea5cea47-6e81-4a3d-93eb-4f370d6324b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753713957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_abort.2753713957
Directory /workspace/11.spi_device_abort/latest

Test location /workspace/coverage/default/11.spi_device_byte_transfer.4060754713
Short name T1782
Test name
Test status
Simulation time 476479604 ps
CPU time 2.95 seconds
Started Jan 03 01:54:43 PM PST 24
Finished Jan 03 01:54:56 PM PST 24
Peak memory 216884 kb
Host smart-1431d314-e49e-4949-9360-059344e28d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060754713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_byte_transfer.4060754713
Directory /workspace/11.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1361528304
Short name T1045
Test name
Test status
Simulation time 1697586288 ps
CPU time 3.42 seconds
Started Jan 03 01:54:37 PM PST 24
Finished Jan 03 01:54:46 PM PST 24
Peak memory 218332 kb
Host smart-7e29d7cd-7326-438b-81c7-da4a049c1a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361528304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1361528304
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2071199022
Short name T671
Test name
Test status
Simulation time 46147398 ps
CPU time 0.77 seconds
Started Jan 03 01:54:40 PM PST 24
Finished Jan 03 01:54:50 PM PST 24
Peak memory 207632 kb
Host smart-efa69d6d-e7f2-4254-bd37-5e89e2cd94af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071199022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2071199022
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_dummy_item_extra_dly.1396870859
Short name T1211
Test name
Test status
Simulation time 57298641217 ps
CPU time 358.28 seconds
Started Jan 03 01:54:43 PM PST 24
Finished Jan 03 02:00:52 PM PST 24
Peak memory 295948 kb
Host smart-29ae2aed-b26b-4e14-94f5-84864f30ee8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396870859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_dummy_item_extra_dly.1396870859
Directory /workspace/11.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/11.spi_device_extreme_fifo_size.2457659647
Short name T1462
Test name
Test status
Simulation time 2050153510 ps
CPU time 18.75 seconds
Started Jan 03 01:54:38 PM PST 24
Finished Jan 03 01:55:04 PM PST 24
Peak memory 225096 kb
Host smart-d1b00c67-373a-497a-9267-1d1ebc6c1e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457659647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_extreme_fifo_size.2457659647
Directory /workspace/11.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/11.spi_device_fifo_full.641425034
Short name T672
Test name
Test status
Simulation time 55118630987 ps
CPU time 835.81 seconds
Started Jan 03 01:54:41 PM PST 24
Finished Jan 03 02:08:47 PM PST 24
Peak memory 257916 kb
Host smart-ebb6863f-37b4-4eab-b965-5b71251ed0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641425034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_fifo_full.641425034
Directory /workspace/11.spi_device_fifo_full/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2234777535
Short name T965
Test name
Test status
Simulation time 240595701158 ps
CPU time 92.98 seconds
Started Jan 03 01:54:38 PM PST 24
Finished Jan 03 01:56:19 PM PST 24
Peak memory 250828 kb
Host smart-a9180353-0600-4ebe-b16e-98c1fdfcd619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234777535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2234777535
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.928300184
Short name T847
Test name
Test status
Simulation time 62759159258 ps
CPU time 145.7 seconds
Started Jan 03 01:54:38 PM PST 24
Finished Jan 03 01:57:10 PM PST 24
Peak memory 257456 kb
Host smart-2f7ba20d-e271-435d-885d-7a4fa5a55b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928300184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.928300184
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1894886245
Short name T1065
Test name
Test status
Simulation time 8572324782 ps
CPU time 41.45 seconds
Started Jan 03 01:54:39 PM PST 24
Finished Jan 03 01:55:28 PM PST 24
Peak memory 240104 kb
Host smart-15bd90a0-ee23-44c4-9a6d-d8a386f78c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894886245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1894886245
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2992636233
Short name T1465
Test name
Test status
Simulation time 2234793381 ps
CPU time 6.19 seconds
Started Jan 03 01:54:38 PM PST 24
Finished Jan 03 01:54:51 PM PST 24
Peak memory 239916 kb
Host smart-2fabb9de-b4fe-4070-8d78-7a78d220d31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992636233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2992636233
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_intr.2745580571
Short name T1169
Test name
Test status
Simulation time 9048888057 ps
CPU time 31.96 seconds
Started Jan 03 01:54:43 PM PST 24
Finished Jan 03 01:55:25 PM PST 24
Peak memory 240120 kb
Host smart-cb1af195-481d-49ac-ae12-eb51f2061c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745580571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intr.2745580571
Directory /workspace/11.spi_device_intr/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.4221727365
Short name T1299
Test name
Test status
Simulation time 3125745318 ps
CPU time 9.96 seconds
Started Jan 03 01:54:39 PM PST 24
Finished Jan 03 01:54:58 PM PST 24
Peak memory 224684 kb
Host smart-bb09c755-5c9d-461c-b041-3240972799a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221727365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.4221727365
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2087161507
Short name T1644
Test name
Test status
Simulation time 83824262 ps
CPU time 1.05 seconds
Started Jan 03 01:54:42 PM PST 24
Finished Jan 03 01:54:53 PM PST 24
Peak memory 218984 kb
Host smart-71f017e7-30db-49b2-9d82-36b503164b16
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087161507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2087161507
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1786952517
Short name T771
Test name
Test status
Simulation time 305163358 ps
CPU time 2.67 seconds
Started Jan 03 01:54:38 PM PST 24
Finished Jan 03 01:54:48 PM PST 24
Peak memory 237948 kb
Host smart-a8abfd58-c295-40ab-a851-c676c53c3ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786952517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1786952517
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.813248262
Short name T881
Test name
Test status
Simulation time 115723423 ps
CPU time 3.04 seconds
Started Jan 03 01:54:37 PM PST 24
Finished Jan 03 01:54:46 PM PST 24
Peak memory 234244 kb
Host smart-1b169b09-1dce-4814-b7b9-7e5374bf6c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813248262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.813248262
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_perf.18642587
Short name T1341
Test name
Test status
Simulation time 42693626595 ps
CPU time 269.62 seconds
Started Jan 03 01:54:43 PM PST 24
Finished Jan 03 01:59:23 PM PST 24
Peak memory 249492 kb
Host smart-03e0ddaf-873b-4829-a3d1-d5df5366d668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18642587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_perf.18642587
Directory /workspace/11.spi_device_perf/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.2430596615
Short name T702
Test name
Test status
Simulation time 19346730 ps
CPU time 0.75 seconds
Started Jan 03 01:54:41 PM PST 24
Finished Jan 03 01:54:52 PM PST 24
Peak memory 216736 kb
Host smart-621c8bfb-a923-41ce-b8cd-a3aba8090514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430596615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.2430596615
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1394148796
Short name T988
Test name
Test status
Simulation time 11011168159 ps
CPU time 7.03 seconds
Started Jan 03 01:54:39 PM PST 24
Finished Jan 03 01:54:54 PM PST 24
Peak memory 234948 kb
Host smart-18766c54-1704-4b98-84f4-fa79e09c2933
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1394148796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1394148796
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_rx_timeout.1278096071
Short name T1761
Test name
Test status
Simulation time 862373154 ps
CPU time 6.14 seconds
Started Jan 03 01:54:41 PM PST 24
Finished Jan 03 01:54:57 PM PST 24
Peak memory 216832 kb
Host smart-328da743-ba7f-45ba-9634-5549cda49de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278096071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_rx_timeout.1278096071
Directory /workspace/11.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/11.spi_device_smoke.3061927062
Short name T1399
Test name
Test status
Simulation time 198460357 ps
CPU time 1.24 seconds
Started Jan 03 01:54:41 PM PST 24
Finished Jan 03 01:54:52 PM PST 24
Peak memory 216760 kb
Host smart-69570546-8cec-4b8e-bdd5-1b250b5982f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061927062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_smoke.3061927062
Directory /workspace/11.spi_device_smoke/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1449400266
Short name T1759
Test name
Test status
Simulation time 549002321540 ps
CPU time 1342.9 seconds
Started Jan 03 01:56:15 PM PST 24
Finished Jan 03 02:18:47 PM PST 24
Peak memory 282488 kb
Host smart-2474ebd1-2d1d-40ac-8e81-9baa9d4b2bc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449400266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1449400266
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.819848489
Short name T979
Test name
Test status
Simulation time 2156062703 ps
CPU time 12.88 seconds
Started Jan 03 01:54:42 PM PST 24
Finished Jan 03 01:55:05 PM PST 24
Peak memory 216868 kb
Host smart-59a75623-f10a-44a4-a08a-88ab5bd06863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819848489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.819848489
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3295887899
Short name T617
Test name
Test status
Simulation time 23896052 ps
CPU time 0.95 seconds
Started Jan 03 01:54:42 PM PST 24
Finished Jan 03 01:54:53 PM PST 24
Peak memory 207532 kb
Host smart-927c2ad9-2bf5-4d25-96e9-f523fbce5e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295887899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3295887899
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.840056234
Short name T1188
Test name
Test status
Simulation time 95323764 ps
CPU time 0.89 seconds
Started Jan 03 01:54:41 PM PST 24
Finished Jan 03 01:54:52 PM PST 24
Peak memory 206900 kb
Host smart-c61f7905-b93f-4afd-bf41-fa341d115be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840056234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.840056234
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3343837812
Short name T911
Test name
Test status
Simulation time 6089840222 ps
CPU time 23.9 seconds
Started Jan 03 01:54:37 PM PST 24
Finished Jan 03 01:55:06 PM PST 24
Peak memory 229400 kb
Host smart-45c20837-13d6-4fcc-b409-cd3c1afb9759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343837812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3343837812
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_abort.1706079049
Short name T1344
Test name
Test status
Simulation time 43955105 ps
CPU time 0.74 seconds
Started Jan 03 01:56:14 PM PST 24
Finished Jan 03 01:56:24 PM PST 24
Peak memory 206644 kb
Host smart-7caf1563-d36b-4dfd-b9e8-cad8e70ec2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706079049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_abort.1706079049
Directory /workspace/12.spi_device_abort/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3156989212
Short name T546
Test name
Test status
Simulation time 45339687 ps
CPU time 0.73 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 01:56:29 PM PST 24
Peak memory 206516 kb
Host smart-b0ee0431-df75-45a1-83ea-7c3453949f3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156989212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3156989212
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_bit_transfer.1342710088
Short name T1147
Test name
Test status
Simulation time 864032276 ps
CPU time 2.52 seconds
Started Jan 03 01:56:22 PM PST 24
Finished Jan 03 01:56:39 PM PST 24
Peak memory 216860 kb
Host smart-a30cdf7f-ba12-442f-b7be-4e3e2c089b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342710088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_bit_transfer.1342710088
Directory /workspace/12.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/12.spi_device_byte_transfer.1909944645
Short name T1778
Test name
Test status
Simulation time 61165481 ps
CPU time 2.49 seconds
Started Jan 03 01:56:16 PM PST 24
Finished Jan 03 01:56:28 PM PST 24
Peak memory 216884 kb
Host smart-74f8fe54-1d03-4327-9382-74617a95aebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909944645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_byte_transfer.1909944645
Directory /workspace/12.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.423027107
Short name T1607
Test name
Test status
Simulation time 1016431188 ps
CPU time 4.44 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 01:56:33 PM PST 24
Peak memory 222656 kb
Host smart-01f33fa0-986b-403b-91f4-6505e8cee64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423027107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.423027107
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.597242923
Short name T777
Test name
Test status
Simulation time 54436564 ps
CPU time 0.81 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 01:56:30 PM PST 24
Peak memory 207608 kb
Host smart-2a20ca9b-145b-4832-b5ba-359bc861be86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597242923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.597242923
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_dummy_item_extra_dly.130647216
Short name T656
Test name
Test status
Simulation time 102755144517 ps
CPU time 251.32 seconds
Started Jan 03 01:56:14 PM PST 24
Finished Jan 03 02:00:35 PM PST 24
Peak memory 266372 kb
Host smart-ea2f2f56-c658-4291-89ed-1214e227a860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130647216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_dummy_item_extra_dly.130647216
Directory /workspace/12.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/12.spi_device_extreme_fifo_size.2702692344
Short name T1581
Test name
Test status
Simulation time 47280643627 ps
CPU time 621.65 seconds
Started Jan 03 01:56:14 PM PST 24
Finished Jan 03 02:06:45 PM PST 24
Peak memory 218872 kb
Host smart-6900c5ff-be53-4f96-96b6-c40733154ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702692344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_extreme_fifo_size.2702692344
Directory /workspace/12.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/12.spi_device_fifo_full.2233975778
Short name T1578
Test name
Test status
Simulation time 222300985146 ps
CPU time 789.96 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 02:09:39 PM PST 24
Peak memory 276220 kb
Host smart-4c3873cc-ae1f-40aa-9493-326c847fee31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233975778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_fifo_full.2233975778
Directory /workspace/12.spi_device_fifo_full/latest

Test location /workspace/coverage/default/12.spi_device_fifo_underflow_overflow.1440301015
Short name T205
Test name
Test status
Simulation time 299506171510 ps
CPU time 454.86 seconds
Started Jan 03 01:56:13 PM PST 24
Finished Jan 03 02:03:56 PM PST 24
Peak memory 343384 kb
Host smart-b1f6a684-5e1b-4a8c-a8f1-b9bbca3ed5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440301015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_fifo_underflow_overf
low.1440301015
Directory /workspace/12.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2875965872
Short name T284
Test name
Test status
Simulation time 6489227457 ps
CPU time 54.02 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 01:57:23 PM PST 24
Peak memory 255104 kb
Host smart-687a2f33-d138-4511-8c62-66f0040110d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875965872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2875965872
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2997328084
Short name T45
Test name
Test status
Simulation time 4816507641 ps
CPU time 95.64 seconds
Started Jan 03 01:56:16 PM PST 24
Finished Jan 03 01:58:00 PM PST 24
Peak memory 251224 kb
Host smart-3eaae67b-be28-4f9d-9cc8-0c659cd05197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997328084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2997328084
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2768212977
Short name T1272
Test name
Test status
Simulation time 11595488632 ps
CPU time 43.12 seconds
Started Jan 03 01:56:21 PM PST 24
Finished Jan 03 01:57:19 PM PST 24
Peak memory 223840 kb
Host smart-a6e95ce6-163b-4205-949d-349afebdf814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768212977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2768212977
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2734758337
Short name T1001
Test name
Test status
Simulation time 292407444 ps
CPU time 7.25 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 01:56:36 PM PST 24
Peak memory 251684 kb
Host smart-9adbef06-9bab-402c-ab6a-3fc1912ac7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734758337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2734758337
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.24821069
Short name T1131
Test name
Test status
Simulation time 228444858 ps
CPU time 3.79 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:35 PM PST 24
Peak memory 234392 kb
Host smart-8cebdf8a-bbd1-4eb1-bbcb-dc72bee4e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24821069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.24821069
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_intr.904139147
Short name T960
Test name
Test status
Simulation time 5136101017 ps
CPU time 22.5 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 01:56:51 PM PST 24
Peak memory 221432 kb
Host smart-5622757f-bcc2-4c21-8139-c70ab0e3c7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904139147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intr.904139147
Directory /workspace/12.spi_device_intr/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.4065391061
Short name T742
Test name
Test status
Simulation time 380339502 ps
CPU time 2.64 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 01:56:29 PM PST 24
Peak memory 224980 kb
Host smart-0651ffff-3648-480d-b66f-f63673803f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065391061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4065391061
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3346217821
Short name T1154
Test name
Test status
Simulation time 52971291 ps
CPU time 1.02 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 01:56:27 PM PST 24
Peak memory 218912 kb
Host smart-18bb7046-3aed-4599-a9b6-d3d1243784c8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346217821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3346217821
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1814069158
Short name T286
Test name
Test status
Simulation time 2011169808 ps
CPU time 5.69 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 01:56:34 PM PST 24
Peak memory 238644 kb
Host smart-e5710475-6366-4da1-ae96-69156acde172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814069158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1814069158
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1719717884
Short name T1297
Test name
Test status
Simulation time 3895721195 ps
CPU time 9.64 seconds
Started Jan 03 01:56:15 PM PST 24
Finished Jan 03 01:56:33 PM PST 24
Peak memory 256380 kb
Host smart-d5087ea3-8165-40dc-91cc-11f2f5973236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719717884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1719717884
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_perf.2115748414
Short name T706
Test name
Test status
Simulation time 122492321263 ps
CPU time 657.18 seconds
Started Jan 03 01:56:16 PM PST 24
Finished Jan 03 02:07:22 PM PST 24
Peak memory 274032 kb
Host smart-1456d190-b0f7-4570-ab3d-fdb6c76890e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115748414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_perf.2115748414
Directory /workspace/12.spi_device_perf/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.3422651554
Short name T1641
Test name
Test status
Simulation time 39225304 ps
CPU time 0.77 seconds
Started Jan 03 01:56:14 PM PST 24
Finished Jan 03 01:56:24 PM PST 24
Peak memory 216588 kb
Host smart-b5ba321a-4088-43b4-a27d-b2dc373593ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422651554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.3422651554
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.379293363
Short name T190
Test name
Test status
Simulation time 1947805286 ps
CPU time 3.86 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 01:56:33 PM PST 24
Peak memory 234140 kb
Host smart-37ff4e45-f43c-4666-94c0-d371337944e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=379293363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.379293363
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_rx_async_fifo_reset.1000216472
Short name T558
Test name
Test status
Simulation time 47269931 ps
CPU time 0.99 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 01:56:28 PM PST 24
Peak memory 208444 kb
Host smart-6afbef43-87e3-46e9-b30b-58be70f36110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000216472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_rx_async_fifo_reset.1000216472
Directory /workspace/12.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/12.spi_device_rx_timeout.299573485
Short name T646
Test name
Test status
Simulation time 7294781273 ps
CPU time 6.05 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:37 PM PST 24
Peak memory 216816 kb
Host smart-e05d4bbd-37cb-4bd3-b213-11cb521630ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299573485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_rx_timeout.299573485
Directory /workspace/12.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/12.spi_device_smoke.798648103
Short name T537
Test name
Test status
Simulation time 17154900 ps
CPU time 1.01 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 01:56:29 PM PST 24
Peak memory 208084 kb
Host smart-0ca5ea19-02e5-4737-9b81-83ccff15f25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798648103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_smoke.798648103
Directory /workspace/12.spi_device_smoke/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.607463627
Short name T1404
Test name
Test status
Simulation time 810717257363 ps
CPU time 1520.16 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 02:21:48 PM PST 24
Peak memory 374168 kb
Host smart-76bf206d-ab83-4570-b757-4cd3821d0073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607463627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.607463627
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2763034721
Short name T1694
Test name
Test status
Simulation time 4023091300 ps
CPU time 40.15 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 01:57:05 PM PST 24
Peak memory 216876 kb
Host smart-e587c17f-5f3c-4027-81d8-2efc8555d16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763034721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2763034721
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3413836528
Short name T601
Test name
Test status
Simulation time 1532839671 ps
CPU time 6.46 seconds
Started Jan 03 01:56:15 PM PST 24
Finished Jan 03 01:56:31 PM PST 24
Peak memory 217968 kb
Host smart-a6118fd1-01c3-44b8-8de3-c46a0058ff0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413836528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3413836528
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2726532497
Short name T1548
Test name
Test status
Simulation time 106070518 ps
CPU time 1.38 seconds
Started Jan 03 01:56:16 PM PST 24
Finished Jan 03 01:56:26 PM PST 24
Peak memory 216736 kb
Host smart-d423d008-df88-4953-a3e5-07b2d48b1493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726532497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2726532497
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.537118323
Short name T831
Test name
Test status
Simulation time 192787859 ps
CPU time 0.72 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 01:56:27 PM PST 24
Peak memory 206936 kb
Host smart-b9619c93-ac7a-4028-88ba-b22cb1bc0e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537118323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.537118323
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_tx_async_fifo_reset.182085607
Short name T614
Test name
Test status
Simulation time 85705597 ps
CPU time 0.78 seconds
Started Jan 03 01:56:15 PM PST 24
Finished Jan 03 01:56:24 PM PST 24
Peak memory 208508 kb
Host smart-f36afe1c-5395-4254-88b6-f5fddeb26857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182085607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tx_async_fifo_reset.182085607
Directory /workspace/12.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/12.spi_device_txrx.3263522873
Short name T1541
Test name
Test status
Simulation time 208595832453 ps
CPU time 1160.92 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 02:15:49 PM PST 24
Peak memory 254004 kb
Host smart-d52e61ee-a25c-4a80-bbd7-d8f501e26874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263522873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_txrx.3263522873
Directory /workspace/12.spi_device_txrx/latest

Test location /workspace/coverage/default/12.spi_device_upload.3070228335
Short name T1056
Test name
Test status
Simulation time 37227894861 ps
CPU time 22.23 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 01:56:48 PM PST 24
Peak memory 249748 kb
Host smart-d61deb03-3600-4700-a18e-3ac55bf26393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070228335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3070228335
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_abort.20111336
Short name T599
Test name
Test status
Simulation time 23963815 ps
CPU time 0.74 seconds
Started Jan 03 01:56:16 PM PST 24
Finished Jan 03 01:56:26 PM PST 24
Peak memory 206688 kb
Host smart-af90592d-f63e-4aa6-9da2-e8aceda43697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20111336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_abort.20111336
Directory /workspace/13.spi_device_abort/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.815331247
Short name T751
Test name
Test status
Simulation time 18692978 ps
CPU time 0.69 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 01:56:29 PM PST 24
Peak memory 206488 kb
Host smart-101b20d7-a3a8-4d35-b1fe-1b6d00d9b1ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815331247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.815331247
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_bit_transfer.1676065805
Short name T1316
Test name
Test status
Simulation time 117211156 ps
CPU time 2.26 seconds
Started Jan 03 01:56:16 PM PST 24
Finished Jan 03 01:56:27 PM PST 24
Peak memory 216796 kb
Host smart-a6dcbfe8-d447-47a2-b753-ece436139427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676065805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_bit_transfer.1676065805
Directory /workspace/13.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/13.spi_device_byte_transfer.727741028
Short name T1004
Test name
Test status
Simulation time 331347617 ps
CPU time 3.12 seconds
Started Jan 03 01:56:15 PM PST 24
Finished Jan 03 01:56:27 PM PST 24
Peak memory 216916 kb
Host smart-fe9688a1-9ea8-42b7-8ed7-0f98da8bb1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727741028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_byte_transfer.727741028
Directory /workspace/13.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2313646581
Short name T1559
Test name
Test status
Simulation time 54754318 ps
CPU time 3.12 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:33 PM PST 24
Peak memory 237576 kb
Host smart-d24abe6a-6e59-4c0d-af07-32ce59edd617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313646581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2313646581
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.987392754
Short name T708
Test name
Test status
Simulation time 32414115 ps
CPU time 0.8 seconds
Started Jan 03 01:56:20 PM PST 24
Finished Jan 03 01:56:33 PM PST 24
Peak memory 207556 kb
Host smart-dd59b06e-17b5-48cf-9e5b-4894eb09d1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987392754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.987392754
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_dummy_item_extra_dly.4023697703
Short name T900
Test name
Test status
Simulation time 49157145019 ps
CPU time 475.31 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 02:04:24 PM PST 24
Peak memory 267456 kb
Host smart-3a0a24a3-e37e-48ed-89b5-9317441c9f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023697703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_dummy_item_extra_dly.4023697703
Directory /workspace/13.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/13.spi_device_extreme_fifo_size.836412979
Short name T1122
Test name
Test status
Simulation time 134961337731 ps
CPU time 537.07 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 02:05:25 PM PST 24
Peak memory 225012 kb
Host smart-bf76856f-3bee-4fde-ba9f-d203d8c7cfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836412979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_extreme_fifo_size.836412979
Directory /workspace/13.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/13.spi_device_fifo_full.2689462133
Short name T693
Test name
Test status
Simulation time 53936403830 ps
CPU time 1608.59 seconds
Started Jan 03 01:56:15 PM PST 24
Finished Jan 03 02:23:12 PM PST 24
Peak memory 282284 kb
Host smart-5389a9a2-29f8-4102-bdcf-8fb69190443d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689462133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_fifo_full.2689462133
Directory /workspace/13.spi_device_fifo_full/latest

Test location /workspace/coverage/default/13.spi_device_fifo_underflow_overflow.3526938669
Short name T201
Test name
Test status
Simulation time 240639315563 ps
CPU time 389.82 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 02:02:56 PM PST 24
Peak memory 388652 kb
Host smart-af180420-c78a-47c7-a708-a6107922de58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526938669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_fifo_underflow_overf
low.3526938669
Directory /workspace/13.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2083571146
Short name T1495
Test name
Test status
Simulation time 1998717195 ps
CPU time 13.79 seconds
Started Jan 03 01:56:20 PM PST 24
Finished Jan 03 01:56:47 PM PST 24
Peak memory 249416 kb
Host smart-48189ea9-e688-4987-8167-cb8e4b9bcf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083571146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2083571146
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.78079740
Short name T1543
Test name
Test status
Simulation time 35038170231 ps
CPU time 158.14 seconds
Started Jan 03 01:56:20 PM PST 24
Finished Jan 03 01:59:10 PM PST 24
Peak memory 241680 kb
Host smart-e0fa551b-4ba1-4dda-8cf7-b0ddfc4192d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78079740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.78079740
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.890596148
Short name T1160
Test name
Test status
Simulation time 6642872706 ps
CPU time 35.95 seconds
Started Jan 03 01:56:20 PM PST 24
Finished Jan 03 01:57:09 PM PST 24
Peak memory 249468 kb
Host smart-c382286a-ab79-4cff-8b25-9f14c60a9eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890596148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.890596148
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2325058058
Short name T263
Test name
Test status
Simulation time 9524242841 ps
CPU time 7.25 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:38 PM PST 24
Peak memory 241644 kb
Host smart-60b21fd4-9674-4b46-9394-79e8ac6b378b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325058058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2325058058
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_intr.2832601267
Short name T1675
Test name
Test status
Simulation time 40570262375 ps
CPU time 40.05 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:57:10 PM PST 24
Peak memory 225128 kb
Host smart-9ee6ae68-97ef-42c5-b68a-7a32b036f83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832601267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intr.2832601267
Directory /workspace/13.spi_device_intr/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2182213159
Short name T315
Test name
Test status
Simulation time 23896106246 ps
CPU time 41.4 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:57:12 PM PST 24
Peak memory 241428 kb
Host smart-461606c6-b749-4e31-9576-df3785d59119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182213159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2182213159
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1893688485
Short name T1314
Test name
Test status
Simulation time 69429878 ps
CPU time 1 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:32 PM PST 24
Peak memory 218944 kb
Host smart-b83e9c3a-85de-4462-8bed-c0821dd8ced6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893688485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1893688485
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2588078509
Short name T341
Test name
Test status
Simulation time 3393959098 ps
CPU time 11.46 seconds
Started Jan 03 01:56:21 PM PST 24
Finished Jan 03 01:56:46 PM PST 24
Peak memory 220644 kb
Host smart-a46fd728-d21b-46e4-af52-f23bb5e715e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588078509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2588078509
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2218098971
Short name T226
Test name
Test status
Simulation time 3397649354 ps
CPU time 11.48 seconds
Started Jan 03 01:56:22 PM PST 24
Finished Jan 03 01:56:48 PM PST 24
Peak memory 218700 kb
Host smart-c14c5db0-996a-4e78-b4bc-f9fb50496814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218098971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2218098971
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_perf.1832222200
Short name T802
Test name
Test status
Simulation time 15944088106 ps
CPU time 1069.71 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 02:14:16 PM PST 24
Peak memory 257704 kb
Host smart-71680c3e-e74c-44d8-a651-3da0375deb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832222200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_perf.1832222200
Directory /workspace/13.spi_device_perf/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.3393051735
Short name T1477
Test name
Test status
Simulation time 146163960 ps
CPU time 0.72 seconds
Started Jan 03 01:56:20 PM PST 24
Finished Jan 03 01:56:34 PM PST 24
Peak memory 216716 kb
Host smart-4962b1f0-2e9b-43c4-ba6f-4735eec80e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393051735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.3393051735
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2789165175
Short name T1192
Test name
Test status
Simulation time 401905931 ps
CPU time 4.73 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:35 PM PST 24
Peak memory 218908 kb
Host smart-b12ebc67-ad9c-454f-a6b6-e7b273a208d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2789165175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2789165175
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_rx_async_fifo_reset.4197812005
Short name T89
Test name
Test status
Simulation time 95414269 ps
CPU time 0.98 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 01:56:31 PM PST 24
Peak memory 208440 kb
Host smart-34859e62-9b01-465d-a05b-5c05fa58a2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197812005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_rx_async_fifo_reset.4197812005
Directory /workspace/13.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/13.spi_device_rx_timeout.1168793955
Short name T1617
Test name
Test status
Simulation time 1394353994 ps
CPU time 4.3 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 01:56:31 PM PST 24
Peak memory 216788 kb
Host smart-6ddb8f41-b94c-4e7d-8daf-4f201cf65c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168793955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_rx_timeout.1168793955
Directory /workspace/13.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/13.spi_device_smoke.4117270915
Short name T1334
Test name
Test status
Simulation time 56707345 ps
CPU time 1.14 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:31 PM PST 24
Peak memory 208016 kb
Host smart-879af77d-4473-484d-82de-c0ac6c4068e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117270915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_smoke.4117270915
Directory /workspace/13.spi_device_smoke/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3711396759
Short name T385
Test name
Test status
Simulation time 62838561063 ps
CPU time 779.85 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 02:09:30 PM PST 24
Peak memory 340240 kb
Host smart-b3fbaf5c-73cf-4e8d-ae56-f0b88fea604a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711396759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3711396759
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2143964594
Short name T122
Test name
Test status
Simulation time 45491558979 ps
CPU time 27.92 seconds
Started Jan 03 01:56:16 PM PST 24
Finished Jan 03 01:56:53 PM PST 24
Peak memory 217104 kb
Host smart-0a09389a-5859-45e9-aa5d-efe92431470d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143964594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2143964594
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.278379288
Short name T575
Test name
Test status
Simulation time 1670600172 ps
CPU time 5.19 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 01:56:35 PM PST 24
Peak memory 216772 kb
Host smart-86b7e160-fbb2-44d1-808d-1625077842dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278379288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.278379288
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.267532016
Short name T1593
Test name
Test status
Simulation time 592163831 ps
CPU time 2.38 seconds
Started Jan 03 01:56:15 PM PST 24
Finished Jan 03 01:56:26 PM PST 24
Peak memory 216836 kb
Host smart-7f8627a3-aef2-4e1d-b3b9-01c54e65055b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267532016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.267532016
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3564756339
Short name T1562
Test name
Test status
Simulation time 24988084 ps
CPU time 0.73 seconds
Started Jan 03 01:56:16 PM PST 24
Finished Jan 03 01:56:25 PM PST 24
Peak memory 206916 kb
Host smart-41d1fe40-bd8d-4f34-a6ae-daf577a4c4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564756339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3564756339
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_tx_async_fifo_reset.1167730723
Short name T1296
Test name
Test status
Simulation time 93665309 ps
CPU time 0.81 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 01:56:28 PM PST 24
Peak memory 208488 kb
Host smart-0d39b8a6-428c-4241-b236-94d831ed1069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167730723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tx_async_fifo_reset.1167730723
Directory /workspace/13.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/13.spi_device_txrx.701056825
Short name T157
Test name
Test status
Simulation time 78616284916 ps
CPU time 672.72 seconds
Started Jan 03 01:56:16 PM PST 24
Finished Jan 03 02:07:37 PM PST 24
Peak memory 266200 kb
Host smart-2047d54e-9615-4b19-a8d0-0c91fed869b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701056825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_txrx.701056825
Directory /workspace/13.spi_device_txrx/latest

Test location /workspace/coverage/default/13.spi_device_upload.1281391008
Short name T1215
Test name
Test status
Simulation time 77740165824 ps
CPU time 22.73 seconds
Started Jan 03 01:56:20 PM PST 24
Finished Jan 03 01:56:57 PM PST 24
Peak memory 235440 kb
Host smart-24675c12-e8a7-4bb6-9151-713bd5aa71d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281391008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1281391008
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_abort.1549904343
Short name T591
Test name
Test status
Simulation time 59241188 ps
CPU time 0.73 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:32 PM PST 24
Peak memory 206624 kb
Host smart-eeff95ec-4ed8-40b3-83ba-fcc854e1f433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549904343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_abort.1549904343
Directory /workspace/14.spi_device_abort/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.984288041
Short name T677
Test name
Test status
Simulation time 13474594 ps
CPU time 0.73 seconds
Started Jan 03 01:56:20 PM PST 24
Finished Jan 03 01:56:35 PM PST 24
Peak memory 206460 kb
Host smart-1d89ccd0-4dda-409b-979c-701970de1bb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984288041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.984288041
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_bit_transfer.1715340424
Short name T749
Test name
Test status
Simulation time 577098367 ps
CPU time 2.73 seconds
Started Jan 03 01:56:16 PM PST 24
Finished Jan 03 01:56:27 PM PST 24
Peak memory 216880 kb
Host smart-db72ef7e-9e1c-4bd1-b773-cbbc36a4305a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715340424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_bit_transfer.1715340424
Directory /workspace/14.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/14.spi_device_byte_transfer.1179791015
Short name T756
Test name
Test status
Simulation time 1273198650 ps
CPU time 3.53 seconds
Started Jan 03 01:56:16 PM PST 24
Finished Jan 03 01:56:28 PM PST 24
Peak memory 216900 kb
Host smart-554c49f1-c7aa-4319-b2bd-35bd25a2228d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179791015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_byte_transfer.1179791015
Directory /workspace/14.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1222951602
Short name T1592
Test name
Test status
Simulation time 855943686 ps
CPU time 3.73 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:34 PM PST 24
Peak memory 218920 kb
Host smart-9ecc1d1e-2519-4f76-980e-26e6416f3580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222951602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1222951602
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1243647700
Short name T1767
Test name
Test status
Simulation time 74272128 ps
CPU time 0.81 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:31 PM PST 24
Peak memory 207644 kb
Host smart-94ba6bc1-dd47-48f0-948f-e0c75f11d8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243647700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1243647700
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_dummy_item_extra_dly.2802914541
Short name T1219
Test name
Test status
Simulation time 86626570582 ps
CPU time 1668.24 seconds
Started Jan 03 01:56:21 PM PST 24
Finished Jan 03 02:24:25 PM PST 24
Peak memory 299084 kb
Host smart-923a3075-eb87-4a12-b09e-db2485d5b233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802914541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_dummy_item_extra_dly.2802914541
Directory /workspace/14.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/14.spi_device_extreme_fifo_size.4264213585
Short name T816
Test name
Test status
Simulation time 285226125990 ps
CPU time 595.2 seconds
Started Jan 03 01:56:21 PM PST 24
Finished Jan 03 02:06:31 PM PST 24
Peak memory 219156 kb
Host smart-00287655-5666-4958-b173-d1ad69ed8150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264213585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_extreme_fifo_size.4264213585
Directory /workspace/14.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/14.spi_device_fifo_full.1931716482
Short name T1053
Test name
Test status
Simulation time 149693616291 ps
CPU time 609.03 seconds
Started Jan 03 01:56:21 PM PST 24
Finished Jan 03 02:06:43 PM PST 24
Peak memory 291144 kb
Host smart-025917fc-733a-4c14-a2f4-f3f823a229bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931716482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_fifo_full.1931716482
Directory /workspace/14.spi_device_fifo_full/latest

Test location /workspace/coverage/default/14.spi_device_fifo_underflow_overflow.2280950848
Short name T1273
Test name
Test status
Simulation time 13223979309 ps
CPU time 145.62 seconds
Started Jan 03 01:56:37 PM PST 24
Finished Jan 03 01:59:08 PM PST 24
Peak memory 318088 kb
Host smart-81bc222e-7d9d-48ac-ba27-bb6af608b20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280950848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_fifo_underflow_overf
low.2280950848
Directory /workspace/14.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1152650395
Short name T257
Test name
Test status
Simulation time 9538821379 ps
CPU time 53.43 seconds
Started Jan 03 01:56:20 PM PST 24
Finished Jan 03 01:57:26 PM PST 24
Peak memory 241436 kb
Host smart-30b6da88-fb05-4573-b8d6-7f63e1de0859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152650395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1152650395
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.921291306
Short name T807
Test name
Test status
Simulation time 82305477026 ps
CPU time 181.36 seconds
Started Jan 03 01:56:21 PM PST 24
Finished Jan 03 01:59:36 PM PST 24
Peak memory 272744 kb
Host smart-cbba3945-2b62-4b40-9c39-8080d47f848e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921291306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.921291306
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.522583852
Short name T968
Test name
Test status
Simulation time 15193582523 ps
CPU time 45.01 seconds
Started Jan 03 01:56:20 PM PST 24
Finished Jan 03 01:57:19 PM PST 24
Peak memory 250208 kb
Host smart-b83735f2-70ba-4b8f-b139-ced9e854db09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522583852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.522583852
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1365704111
Short name T1278
Test name
Test status
Simulation time 3548865474 ps
CPU time 12.47 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:44 PM PST 24
Peak memory 241540 kb
Host smart-aebb2c13-fe82-43ce-b46b-8979593f19bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365704111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1365704111
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_intr.4028328896
Short name T635
Test name
Test status
Simulation time 38585223685 ps
CPU time 26.48 seconds
Started Jan 03 01:56:37 PM PST 24
Finished Jan 03 01:57:08 PM PST 24
Peak memory 221096 kb
Host smart-f19e5ae9-a71a-4f95-bfcb-adf3d36cb85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028328896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intr.4028328896
Directory /workspace/14.spi_device_intr/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.378248471
Short name T1575
Test name
Test status
Simulation time 1920357685 ps
CPU time 8.55 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 01:56:37 PM PST 24
Peak memory 247664 kb
Host smart-652f98ab-28b5-4f52-a650-8396a64017c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378248471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.378248471
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2598281812
Short name T1008
Test name
Test status
Simulation time 259150201 ps
CPU time 3.65 seconds
Started Jan 03 01:56:33 PM PST 24
Finished Jan 03 01:56:45 PM PST 24
Peak memory 234384 kb
Host smart-a121ecaa-6f1c-49ed-883c-b46f9fca9f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598281812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2598281812
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1115485278
Short name T319
Test name
Test status
Simulation time 5559481978 ps
CPU time 19.6 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 01:56:49 PM PST 24
Peak memory 249712 kb
Host smart-17d6baa3-9d37-4596-be2c-8f61b732f669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115485278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1115485278
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_perf.244939327
Short name T840
Test name
Test status
Simulation time 60846073066 ps
CPU time 445.63 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 02:03:55 PM PST 24
Peak memory 249640 kb
Host smart-394cd79b-ef81-4d93-82bf-30470cc1cc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244939327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_perf.244939327
Directory /workspace/14.spi_device_perf/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.2540222112
Short name T1390
Test name
Test status
Simulation time 16957267 ps
CPU time 0.73 seconds
Started Jan 03 01:56:14 PM PST 24
Finished Jan 03 01:56:24 PM PST 24
Peak memory 216716 kb
Host smart-19c9e7be-b220-4444-bc18-2f4b5d3970ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540222112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.2540222112
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3197632725
Short name T714
Test name
Test status
Simulation time 592825151 ps
CPU time 4.52 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:36 PM PST 24
Peak memory 234124 kb
Host smart-f62aa208-29ba-4b11-8d69-f47c1be45b8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3197632725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3197632725
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_rx_async_fifo_reset.2916520961
Short name T1113
Test name
Test status
Simulation time 50870341 ps
CPU time 0.96 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 01:56:30 PM PST 24
Peak memory 208500 kb
Host smart-263884d3-ab13-4442-a55a-262dffc748d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916520961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_rx_async_fifo_reset.2916520961
Directory /workspace/14.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/14.spi_device_smoke.4216862192
Short name T1153
Test name
Test status
Simulation time 163578813 ps
CPU time 1.1 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:33 PM PST 24
Peak memory 208344 kb
Host smart-43338f98-c270-4360-9fc5-3d78c04fd349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216862192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_smoke.4216862192
Directory /workspace/14.spi_device_smoke/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4282074242
Short name T391
Test name
Test status
Simulation time 603787242 ps
CPU time 7.56 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 01:56:34 PM PST 24
Peak memory 220504 kb
Host smart-ba653b90-7440-4db2-982b-e572bbfd220a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282074242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4282074242
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3833012518
Short name T1692
Test name
Test status
Simulation time 1744906428 ps
CPU time 11.45 seconds
Started Jan 03 01:56:16 PM PST 24
Finished Jan 03 01:56:36 PM PST 24
Peak memory 216892 kb
Host smart-67689cbc-36ad-48fd-b63c-7c42b1e66952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833012518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3833012518
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3999647958
Short name T639
Test name
Test status
Simulation time 101069756 ps
CPU time 1.87 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 01:56:29 PM PST 24
Peak memory 208672 kb
Host smart-daed1945-316f-45ea-ad27-917421a54c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999647958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3999647958
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3171747030
Short name T1277
Test name
Test status
Simulation time 409868809 ps
CPU time 1.14 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 01:56:31 PM PST 24
Peak memory 207976 kb
Host smart-1b2d1e40-5d09-428e-a736-222d1291b230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171747030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3171747030
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_tx_async_fifo_reset.2023621244
Short name T84
Test name
Test status
Simulation time 31224171 ps
CPU time 0.78 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:31 PM PST 24
Peak memory 208524 kb
Host smart-68c04626-5c40-4c90-b4dd-8fab42b8eb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023621244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tx_async_fifo_reset.2023621244
Directory /workspace/14.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/14.spi_device_txrx.2606468555
Short name T579
Test name
Test status
Simulation time 54632188752 ps
CPU time 397.52 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 02:03:07 PM PST 24
Peak memory 295932 kb
Host smart-8ca9ee01-7e14-441b-ad4a-004bd2b8d408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606468555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_txrx.2606468555
Directory /workspace/14.spi_device_txrx/latest

Test location /workspace/coverage/default/14.spi_device_upload.3922647533
Short name T1138
Test name
Test status
Simulation time 2987140878 ps
CPU time 8.97 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:40 PM PST 24
Peak memory 231904 kb
Host smart-83fcfccc-5fa5-45ff-97e0-53d2b135f357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922647533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3922647533
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_abort.2437526475
Short name T877
Test name
Test status
Simulation time 13911570 ps
CPU time 0.77 seconds
Started Jan 03 01:57:23 PM PST 24
Finished Jan 03 01:57:30 PM PST 24
Peak memory 206628 kb
Host smart-be0db168-69e2-4426-a600-d4ac8eac7d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437526475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_abort.2437526475
Directory /workspace/15.spi_device_abort/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3674707795
Short name T748
Test name
Test status
Simulation time 64593124 ps
CPU time 0.71 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:31 PM PST 24
Peak memory 206456 kb
Host smart-f8a3e9f6-c613-4cdd-9ddb-452881990e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674707795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3674707795
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_bit_transfer.4222718522
Short name T1381
Test name
Test status
Simulation time 977977488 ps
CPU time 2.65 seconds
Started Jan 03 01:56:51 PM PST 24
Finished Jan 03 01:56:56 PM PST 24
Peak memory 216800 kb
Host smart-da7d39a8-a22b-4fe9-a7c2-f41e72eb49ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222718522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_bit_transfer.4222718522
Directory /workspace/15.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/15.spi_device_byte_transfer.3841949980
Short name T915
Test name
Test status
Simulation time 2458968793 ps
CPU time 3.06 seconds
Started Jan 03 01:56:22 PM PST 24
Finished Jan 03 01:56:40 PM PST 24
Peak memory 216828 kb
Host smart-856f04fb-2b24-4b9b-9004-c822e015f8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841949980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_byte_transfer.3841949980
Directory /workspace/15.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4150174072
Short name T1156
Test name
Test status
Simulation time 513468575 ps
CPU time 2.94 seconds
Started Jan 03 01:56:16 PM PST 24
Finished Jan 03 01:56:28 PM PST 24
Peak memory 238832 kb
Host smart-7f9340f6-0880-45ec-88da-7563e9ef1f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150174072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4150174072
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2886162555
Short name T827
Test name
Test status
Simulation time 16851500 ps
CPU time 0.79 seconds
Started Jan 03 01:56:23 PM PST 24
Finished Jan 03 01:56:38 PM PST 24
Peak memory 207564 kb
Host smart-0c6acae8-3e77-4aab-b898-1e2ba5e9dc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886162555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2886162555
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_dummy_item_extra_dly.2875846333
Short name T1696
Test name
Test status
Simulation time 56800443680 ps
CPU time 246.81 seconds
Started Jan 03 01:56:23 PM PST 24
Finished Jan 03 02:00:44 PM PST 24
Peak memory 315944 kb
Host smart-92727f6f-5441-4c6a-bb87-fff7628c7e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875846333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_dummy_item_extra_dly.2875846333
Directory /workspace/15.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/15.spi_device_extreme_fifo_size.1791385464
Short name T32
Test name
Test status
Simulation time 179490712931 ps
CPU time 1942.64 seconds
Started Jan 03 01:56:38 PM PST 24
Finished Jan 03 02:29:05 PM PST 24
Peak memory 218112 kb
Host smart-ad341486-c082-456e-bcf4-349fc8f54f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791385464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_extreme_fifo_size.1791385464
Directory /workspace/15.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/15.spi_device_fifo_full.3338392164
Short name T531
Test name
Test status
Simulation time 17405554962 ps
CPU time 399.14 seconds
Started Jan 03 01:56:38 PM PST 24
Finished Jan 03 02:03:22 PM PST 24
Peak memory 269192 kb
Host smart-cdf2050c-a3ee-4065-a1f2-23ff9e5db89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338392164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_fifo_full.3338392164
Directory /workspace/15.spi_device_fifo_full/latest

Test location /workspace/coverage/default/15.spi_device_fifo_underflow_overflow.1110499517
Short name T844
Test name
Test status
Simulation time 60973119611 ps
CPU time 387.17 seconds
Started Jan 03 01:56:35 PM PST 24
Finished Jan 03 02:03:09 PM PST 24
Peak memory 316760 kb
Host smart-e1dc57a3-5d56-4c3b-9573-f35410852d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110499517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_fifo_underflow_overf
low.1110499517
Directory /workspace/15.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3852488475
Short name T1378
Test name
Test status
Simulation time 12502026995 ps
CPU time 52.1 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 01:57:17 PM PST 24
Peak memory 250792 kb
Host smart-1dd1e790-9465-4ab2-906a-4944b9d5bba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852488475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3852488475
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.4093811266
Short name T336
Test name
Test status
Simulation time 40547052529 ps
CPU time 375.67 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 02:02:43 PM PST 24
Peak memory 281848 kb
Host smart-a456cabb-7894-4c20-b7c5-1e11927582c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093811266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.4093811266
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2278731130
Short name T1640
Test name
Test status
Simulation time 5492141195 ps
CPU time 23.36 seconds
Started Jan 03 01:56:16 PM PST 24
Finished Jan 03 01:56:48 PM PST 24
Peak memory 240856 kb
Host smart-543bf3ab-7026-4b76-90a4-fa4c02add817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278731130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2278731130
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3344201749
Short name T621
Test name
Test status
Simulation time 1845847631 ps
CPU time 3.65 seconds
Started Jan 03 01:57:03 PM PST 24
Finished Jan 03 01:57:10 PM PST 24
Peak memory 218124 kb
Host smart-1d1bb8e3-3eb0-48cc-b376-4cc197750ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344201749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3344201749
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_intr.1267738108
Short name T716
Test name
Test status
Simulation time 27123307655 ps
CPU time 14.79 seconds
Started Jan 03 01:56:23 PM PST 24
Finished Jan 03 01:56:52 PM PST 24
Peak memory 216896 kb
Host smart-40816449-815c-4833-8ac1-3c4ef1d7e62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267738108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intr.1267738108
Directory /workspace/15.spi_device_intr/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1281461709
Short name T1290
Test name
Test status
Simulation time 13296855536 ps
CPU time 16.97 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 01:56:44 PM PST 24
Peak memory 256780 kb
Host smart-d5ca837a-b84b-4f52-b803-84d8a2a1748d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281461709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1281461709
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3397227058
Short name T1579
Test name
Test status
Simulation time 86274547 ps
CPU time 1.09 seconds
Started Jan 03 01:56:50 PM PST 24
Finished Jan 03 01:56:53 PM PST 24
Peak memory 218904 kb
Host smart-5c147188-18d4-41cd-8b52-9a933bed8f5a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397227058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3397227058
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1637856129
Short name T344
Test name
Test status
Simulation time 94599436 ps
CPU time 4.53 seconds
Started Jan 03 01:57:19 PM PST 24
Finished Jan 03 01:57:26 PM PST 24
Peak memory 237848 kb
Host smart-d1f3d659-da10-4760-8bb5-88703bad504c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637856129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1637856129
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3857013209
Short name T1608
Test name
Test status
Simulation time 2134106952 ps
CPU time 14.22 seconds
Started Jan 03 01:57:01 PM PST 24
Finished Jan 03 01:57:20 PM PST 24
Peak memory 249668 kb
Host smart-78b278bb-d7d0-4991-bfd0-9ec55eb9ec7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857013209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3857013209
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_perf.540357743
Short name T1112
Test name
Test status
Simulation time 57517510189 ps
CPU time 1389.63 seconds
Started Jan 03 01:56:37 PM PST 24
Finished Jan 03 02:19:51 PM PST 24
Peak memory 282656 kb
Host smart-d84e687b-2988-4f84-adf0-2e2bc7dfd5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540357743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_perf.540357743
Directory /workspace/15.spi_device_perf/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.3055242022
Short name T958
Test name
Test status
Simulation time 16657647 ps
CPU time 0.73 seconds
Started Jan 03 01:56:39 PM PST 24
Finished Jan 03 01:56:44 PM PST 24
Peak memory 216716 kb
Host smart-7a422268-75de-4b75-91e5-2af28bd0cb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055242022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.3055242022
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.4203881712
Short name T604
Test name
Test status
Simulation time 736072684 ps
CPU time 4.43 seconds
Started Jan 03 01:56:16 PM PST 24
Finished Jan 03 01:56:29 PM PST 24
Peak memory 234228 kb
Host smart-52c3e4c6-ecf9-469c-bac4-8459e1a31c8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4203881712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.4203881712
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_rx_async_fifo_reset.4218824316
Short name T899
Test name
Test status
Simulation time 182345106 ps
CPU time 0.92 seconds
Started Jan 03 01:56:47 PM PST 24
Finished Jan 03 01:56:51 PM PST 24
Peak memory 208472 kb
Host smart-00ec85bb-ea9f-4ca6-b257-12bbf25fbe06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218824316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_rx_async_fifo_reset.4218824316
Directory /workspace/15.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/15.spi_device_rx_timeout.2534146895
Short name T557
Test name
Test status
Simulation time 417915285 ps
CPU time 4.53 seconds
Started Jan 03 01:56:50 PM PST 24
Finished Jan 03 01:56:57 PM PST 24
Peak memory 216836 kb
Host smart-16a14e38-e715-4f17-9a74-682187a5f8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534146895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_rx_timeout.2534146895
Directory /workspace/15.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/15.spi_device_smoke.3451996178
Short name T1511
Test name
Test status
Simulation time 352248012 ps
CPU time 1.4 seconds
Started Jan 03 01:56:21 PM PST 24
Finished Jan 03 01:56:37 PM PST 24
Peak memory 216856 kb
Host smart-88985090-2ea6-47d3-85e3-454d7b2c8280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451996178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_smoke.3451996178
Directory /workspace/15.spi_device_smoke/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.727756428
Short name T1626
Test name
Test status
Simulation time 36043530202 ps
CPU time 69.54 seconds
Started Jan 03 01:56:21 PM PST 24
Finished Jan 03 01:57:44 PM PST 24
Peak memory 223100 kb
Host smart-658849f1-ab45-4348-b7ca-d73612dd57fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727756428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.727756428
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2337833172
Short name T46
Test name
Test status
Simulation time 11687993328 ps
CPU time 17.07 seconds
Started Jan 03 01:57:00 PM PST 24
Finished Jan 03 01:57:22 PM PST 24
Peak memory 216952 kb
Host smart-de32814d-60ca-4f49-8925-cb3bfd726c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337833172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2337833172
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3160067119
Short name T967
Test name
Test status
Simulation time 222218475 ps
CPU time 2.51 seconds
Started Jan 03 01:56:14 PM PST 24
Finished Jan 03 01:56:26 PM PST 24
Peak memory 216900 kb
Host smart-f72198d8-d6f7-448c-9c8d-123a1966af0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160067119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3160067119
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3877036173
Short name T903
Test name
Test status
Simulation time 166869059 ps
CPU time 1.17 seconds
Started Jan 03 01:57:04 PM PST 24
Finished Jan 03 01:57:08 PM PST 24
Peak memory 206844 kb
Host smart-26cde2e0-2398-4a82-ab2c-04735edfba11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877036173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3877036173
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_tx_async_fifo_reset.2570234177
Short name T729
Test name
Test status
Simulation time 15166152 ps
CPU time 0.8 seconds
Started Jan 03 01:56:58 PM PST 24
Finished Jan 03 01:57:00 PM PST 24
Peak memory 208480 kb
Host smart-59df0ce0-eb85-4094-bfc4-f35674637193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570234177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tx_async_fifo_reset.2570234177
Directory /workspace/15.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/15.spi_device_txrx.1710115519
Short name T547
Test name
Test status
Simulation time 40821028361 ps
CPU time 148.18 seconds
Started Jan 03 01:56:37 PM PST 24
Finished Jan 03 01:59:10 PM PST 24
Peak memory 281936 kb
Host smart-add48358-b755-4460-973a-951dbbb77fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710115519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_txrx.1710115519
Directory /workspace/15.spi_device_txrx/latest

Test location /workspace/coverage/default/15.spi_device_upload.3098300622
Short name T251
Test name
Test status
Simulation time 15236421724 ps
CPU time 14.14 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 01:56:43 PM PST 24
Peak memory 229820 kb
Host smart-ba95e766-825c-40e4-8bf9-9ea40768930c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098300622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3098300622
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_abort.1064269258
Short name T806
Test name
Test status
Simulation time 17028346 ps
CPU time 0.8 seconds
Started Jan 03 01:57:03 PM PST 24
Finished Jan 03 01:57:07 PM PST 24
Peak memory 206648 kb
Host smart-77ff58de-85c7-428a-93b6-2eebc7640c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064269258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_abort.1064269258
Directory /workspace/16.spi_device_abort/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2510050261
Short name T1402
Test name
Test status
Simulation time 26459595 ps
CPU time 0.73 seconds
Started Jan 03 01:57:27 PM PST 24
Finished Jan 03 01:57:37 PM PST 24
Peak memory 206444 kb
Host smart-46540572-de78-4bb3-aa71-3efe366a05ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510050261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2510050261
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_bit_transfer.2414905511
Short name T598
Test name
Test status
Simulation time 146892348 ps
CPU time 2.52 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:33 PM PST 24
Peak memory 216820 kb
Host smart-961e5ed2-11a9-4334-a9cd-975d8e522a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414905511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_bit_transfer.2414905511
Directory /workspace/16.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/16.spi_device_byte_transfer.523791164
Short name T1101
Test name
Test status
Simulation time 2426499370 ps
CPU time 3.16 seconds
Started Jan 03 01:56:20 PM PST 24
Finished Jan 03 01:56:37 PM PST 24
Peak memory 216748 kb
Host smart-a06e8c71-cb55-44a3-a6d8-b7dd365c24a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523791164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_byte_transfer.523791164
Directory /workspace/16.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2526304757
Short name T1391
Test name
Test status
Simulation time 341039033 ps
CPU time 3.77 seconds
Started Jan 03 01:57:22 PM PST 24
Finished Jan 03 01:57:31 PM PST 24
Peak memory 241388 kb
Host smart-c5cd2e01-b152-4112-95fc-ecead56ed783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526304757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2526304757
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2092952953
Short name T580
Test name
Test status
Simulation time 13923947 ps
CPU time 0.74 seconds
Started Jan 03 01:56:18 PM PST 24
Finished Jan 03 01:56:30 PM PST 24
Peak memory 206596 kb
Host smart-194c53f9-d659-498b-ab92-84b61e81c982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092952953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2092952953
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_dummy_item_extra_dly.2805898125
Short name T1347
Test name
Test status
Simulation time 36416692877 ps
CPU time 310.47 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 02:01:42 PM PST 24
Peak memory 270084 kb
Host smart-0e2914fa-0a47-4fa2-a9e6-ac70c0442e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805898125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_dummy_item_extra_dly.2805898125
Directory /workspace/16.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/16.spi_device_extreme_fifo_size.2896497500
Short name T1051
Test name
Test status
Simulation time 7543879753 ps
CPU time 111.46 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:58:23 PM PST 24
Peak memory 241336 kb
Host smart-313de915-41fc-4ab0-8e09-0e08699ed79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896497500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_extreme_fifo_size.2896497500
Directory /workspace/16.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/16.spi_device_fifo_full.3741879781
Short name T514
Test name
Test status
Simulation time 68055839168 ps
CPU time 1110.25 seconds
Started Jan 03 01:56:17 PM PST 24
Finished Jan 03 02:14:56 PM PST 24
Peak memory 257592 kb
Host smart-335c4e03-fd95-4924-b7d7-4aed0ff297de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741879781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_fifo_full.3741879781
Directory /workspace/16.spi_device_fifo_full/latest

Test location /workspace/coverage/default/16.spi_device_fifo_underflow_overflow.3160770376
Short name T53
Test name
Test status
Simulation time 546508548703 ps
CPU time 1469.32 seconds
Started Jan 03 01:56:20 PM PST 24
Finished Jan 03 02:21:02 PM PST 24
Peak memory 644372 kb
Host smart-95685ede-d253-441d-abfd-3c7b28f87e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160770376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_fifo_underflow_overf
low.3160770376
Directory /workspace/16.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.4176317948
Short name T845
Test name
Test status
Simulation time 41327591040 ps
CPU time 223.34 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 02:01:17 PM PST 24
Peak memory 257896 kb
Host smart-88f0da9b-2f4e-46e8-8fbf-dd9896efcd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176317948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.4176317948
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3710943057
Short name T1458
Test name
Test status
Simulation time 31742906232 ps
CPU time 41.24 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 01:58:14 PM PST 24
Peak memory 249872 kb
Host smart-f4442c38-9554-4925-a1a7-9c57031d99c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710943057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3710943057
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3376653236
Short name T723
Test name
Test status
Simulation time 36912521937 ps
CPU time 49.95 seconds
Started Jan 03 01:57:17 PM PST 24
Finished Jan 03 01:58:09 PM PST 24
Peak memory 252940 kb
Host smart-03308063-1fba-4049-acb0-3e0d1bd906d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376653236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3376653236
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2607634911
Short name T242
Test name
Test status
Simulation time 337086154 ps
CPU time 4.5 seconds
Started Jan 03 01:57:23 PM PST 24
Finished Jan 03 01:57:34 PM PST 24
Peak memory 218084 kb
Host smart-806d9f86-6e9a-43bf-9fc6-f0bf612e8cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607634911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2607634911
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_intr.2748783530
Short name T1274
Test name
Test status
Simulation time 44610846410 ps
CPU time 31.84 seconds
Started Jan 03 01:56:20 PM PST 24
Finished Jan 03 01:57:04 PM PST 24
Peak memory 224684 kb
Host smart-62fe9868-46f3-430a-a5cd-d587ae298325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748783530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intr.2748783530
Directory /workspace/16.spi_device_intr/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.194132821
Short name T944
Test name
Test status
Simulation time 3675888084 ps
CPU time 4.01 seconds
Started Jan 03 01:57:22 PM PST 24
Finished Jan 03 01:57:32 PM PST 24
Peak memory 233424 kb
Host smart-21a2affe-92a0-41d0-915a-cb6b56bd5f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194132821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.194132821
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.4007116137
Short name T888
Test name
Test status
Simulation time 53617494 ps
CPU time 1 seconds
Started Jan 03 01:56:39 PM PST 24
Finished Jan 03 01:56:44 PM PST 24
Peak memory 218868 kb
Host smart-20d84075-2d05-4c73-8aee-6ecced14cc71
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007116137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.4007116137
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2295462978
Short name T288
Test name
Test status
Simulation time 6826399443 ps
CPU time 10.07 seconds
Started Jan 03 01:57:19 PM PST 24
Finished Jan 03 01:57:31 PM PST 24
Peak memory 247940 kb
Host smart-2ab332f3-5a20-4bd3-85b4-69ac94145f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295462978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2295462978
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3014155626
Short name T356
Test name
Test status
Simulation time 14782430950 ps
CPU time 8.4 seconds
Started Jan 03 01:57:05 PM PST 24
Finished Jan 03 01:57:16 PM PST 24
Peak memory 218308 kb
Host smart-e14a7708-07f5-4c02-83dd-1d9725d5eca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014155626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3014155626
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_perf.2012530188
Short name T543
Test name
Test status
Simulation time 235416957645 ps
CPU time 975.17 seconds
Started Jan 03 01:56:21 PM PST 24
Finished Jan 03 02:12:50 PM PST 24
Peak memory 249292 kb
Host smart-df6ef778-4eb6-40e3-be4e-e024e5c62913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012530188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_perf.2012530188
Directory /workspace/16.spi_device_perf/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.3977748765
Short name T938
Test name
Test status
Simulation time 33024379 ps
CPU time 0.73 seconds
Started Jan 03 01:56:21 PM PST 24
Finished Jan 03 01:56:35 PM PST 24
Peak memory 216624 kb
Host smart-8dadb6fa-7399-489f-97e6-ad3634afa09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977748765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.3977748765
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2989111663
Short name T929
Test name
Test status
Simulation time 682099495 ps
CPU time 3.72 seconds
Started Jan 03 01:57:24 PM PST 24
Finished Jan 03 01:57:35 PM PST 24
Peak memory 218620 kb
Host smart-b150478c-a5ab-4fcc-b1bd-b544b6734bc3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2989111663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2989111663
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_rx_async_fifo_reset.2198735870
Short name T688
Test name
Test status
Simulation time 215339889 ps
CPU time 0.92 seconds
Started Jan 03 01:57:20 PM PST 24
Finished Jan 03 01:57:26 PM PST 24
Peak memory 208504 kb
Host smart-d991f568-0440-42ff-aa48-5b28ee060040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198735870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_rx_async_fifo_reset.2198735870
Directory /workspace/16.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/16.spi_device_rx_timeout.1352571662
Short name T642
Test name
Test status
Simulation time 570016571 ps
CPU time 5.5 seconds
Started Jan 03 01:56:20 PM PST 24
Finished Jan 03 01:56:39 PM PST 24
Peak memory 216688 kb
Host smart-7badf5ed-265c-404f-96b6-39c9a8c8837d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352571662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_rx_timeout.1352571662
Directory /workspace/16.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/16.spi_device_smoke.2935237864
Short name T1175
Test name
Test status
Simulation time 105873208 ps
CPU time 0.89 seconds
Started Jan 03 01:56:19 PM PST 24
Finished Jan 03 01:56:31 PM PST 24
Peak memory 207904 kb
Host smart-7c8639bd-f23b-49af-8463-c5f0577e8377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935237864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_smoke.2935237864
Directory /workspace/16.spi_device_smoke/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.843858609
Short name T1189
Test name
Test status
Simulation time 7623503029 ps
CPU time 52.6 seconds
Started Jan 03 01:56:20 PM PST 24
Finished Jan 03 01:57:25 PM PST 24
Peak memory 216884 kb
Host smart-ccfb8fed-6e83-4107-b5c4-95bd80910b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843858609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.843858609
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2481481524
Short name T1380
Test name
Test status
Simulation time 5795719456 ps
CPU time 5.12 seconds
Started Jan 03 01:56:20 PM PST 24
Finished Jan 03 01:56:39 PM PST 24
Peak memory 216900 kb
Host smart-18c4aa7d-9c06-49b9-9358-966a37cfab90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481481524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2481481524
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.471530087
Short name T1522
Test name
Test status
Simulation time 15726242 ps
CPU time 0.76 seconds
Started Jan 03 01:57:19 PM PST 24
Finished Jan 03 01:57:22 PM PST 24
Peak memory 206928 kb
Host smart-5d1046e0-e697-47f6-9119-e98c6c3c763d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471530087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.471530087
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1904454200
Short name T1448
Test name
Test status
Simulation time 192723512 ps
CPU time 0.88 seconds
Started Jan 03 01:57:04 PM PST 24
Finished Jan 03 01:57:08 PM PST 24
Peak memory 207012 kb
Host smart-3cd8cedd-251a-4170-8497-1e695b21b0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904454200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1904454200
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_tx_async_fifo_reset.1899475501
Short name T830
Test name
Test status
Simulation time 103690492 ps
CPU time 0.75 seconds
Started Jan 03 01:56:47 PM PST 24
Finished Jan 03 01:56:50 PM PST 24
Peak memory 208452 kb
Host smart-607b1aa0-bb79-4977-821b-6f58c0f138ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899475501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tx_async_fifo_reset.1899475501
Directory /workspace/16.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/16.spi_device_txrx.1292133723
Short name T1319
Test name
Test status
Simulation time 80813122180 ps
CPU time 229.57 seconds
Started Jan 03 01:56:24 PM PST 24
Finished Jan 03 02:00:28 PM PST 24
Peak memory 284036 kb
Host smart-debcdc65-9d7b-4c36-b9fd-d0a1c1285072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292133723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_txrx.1292133723
Directory /workspace/16.spi_device_txrx/latest

Test location /workspace/coverage/default/16.spi_device_upload.3599846167
Short name T1379
Test name
Test status
Simulation time 213233263 ps
CPU time 2.8 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 01:57:36 PM PST 24
Peak memory 226224 kb
Host smart-e4543383-6a3f-44a9-86f7-ede762a25910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599846167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3599846167
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_abort.4070727720
Short name T678
Test name
Test status
Simulation time 17246376 ps
CPU time 0.75 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 01:57:34 PM PST 24
Peak memory 206624 kb
Host smart-3589b0a9-e9dd-438a-888a-dfef2268b01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070727720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_abort.4070727720
Directory /workspace/17.spi_device_abort/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1009184789
Short name T1090
Test name
Test status
Simulation time 15265250 ps
CPU time 0.75 seconds
Started Jan 03 01:56:49 PM PST 24
Finished Jan 03 01:56:52 PM PST 24
Peak memory 206400 kb
Host smart-48d53372-68a3-456c-b3d7-b6e732f797b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009184789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1009184789
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_bit_transfer.2119256948
Short name T1566
Test name
Test status
Simulation time 92322076 ps
CPU time 2.27 seconds
Started Jan 03 01:57:23 PM PST 24
Finished Jan 03 01:57:32 PM PST 24
Peak memory 216780 kb
Host smart-831c0fa4-af35-4460-a47f-31f75a3ff94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119256948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_bit_transfer.2119256948
Directory /workspace/17.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/17.spi_device_byte_transfer.4203171069
Short name T939
Test name
Test status
Simulation time 3228522261 ps
CPU time 3.06 seconds
Started Jan 03 01:57:26 PM PST 24
Finished Jan 03 01:57:38 PM PST 24
Peak memory 216900 kb
Host smart-861c91e6-ec4d-4cea-b7c3-e0d8f6108b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203171069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_byte_transfer.4203171069
Directory /workspace/17.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.120021296
Short name T358
Test name
Test status
Simulation time 6124474882 ps
CPU time 6.73 seconds
Started Jan 03 01:57:21 PM PST 24
Finished Jan 03 01:57:33 PM PST 24
Peak memory 240028 kb
Host smart-697a8120-1340-4bcd-af83-24e834952304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120021296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.120021296
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3139246232
Short name T1689
Test name
Test status
Simulation time 19905323 ps
CPU time 0.75 seconds
Started Jan 03 01:57:27 PM PST 24
Finished Jan 03 01:57:37 PM PST 24
Peak memory 206536 kb
Host smart-1cdea927-5e4d-41af-9398-c40e3309b354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139246232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3139246232
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_dummy_item_extra_dly.3116721414
Short name T1666
Test name
Test status
Simulation time 133011622734 ps
CPU time 509.35 seconds
Started Jan 03 01:57:24 PM PST 24
Finished Jan 03 02:06:01 PM PST 24
Peak memory 301732 kb
Host smart-d2349edd-fd27-46da-afe1-c5680233e96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116721414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_dummy_item_extra_dly.3116721414
Directory /workspace/17.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/17.spi_device_extreme_fifo_size.2485840270
Short name T1653
Test name
Test status
Simulation time 59837229939 ps
CPU time 70.92 seconds
Started Jan 03 01:57:22 PM PST 24
Finished Jan 03 01:58:39 PM PST 24
Peak memory 232060 kb
Host smart-e732a3a7-c0b7-4d74-b409-a4a3c0d0d491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485840270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_extreme_fifo_size.2485840270
Directory /workspace/17.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/17.spi_device_fifo_full.3399387553
Short name T1206
Test name
Test status
Simulation time 15045506774 ps
CPU time 820.28 seconds
Started Jan 03 01:57:27 PM PST 24
Finished Jan 03 02:11:17 PM PST 24
Peak memory 257272 kb
Host smart-179ccd79-12b7-4e35-af0b-cd2fe3d09ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399387553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_fifo_full.3399387553
Directory /workspace/17.spi_device_fifo_full/latest

Test location /workspace/coverage/default/17.spi_device_fifo_underflow_overflow.859486720
Short name T615
Test name
Test status
Simulation time 29336065656 ps
CPU time 332.35 seconds
Started Jan 03 01:57:21 PM PST 24
Finished Jan 03 02:02:58 PM PST 24
Peak memory 399008 kb
Host smart-1579d58b-1462-48f9-986a-2779f58a04ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859486720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_fifo_underflow_overfl
ow.859486720
Directory /workspace/17.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1420566785
Short name T896
Test name
Test status
Simulation time 125239016342 ps
CPU time 153.34 seconds
Started Jan 03 01:56:59 PM PST 24
Finished Jan 03 01:59:35 PM PST 24
Peak memory 251632 kb
Host smart-14fd855a-0395-4d6d-ae5f-944f33148bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420566785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1420566785
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2037572753
Short name T1359
Test name
Test status
Simulation time 35894841984 ps
CPU time 288.84 seconds
Started Jan 03 01:57:03 PM PST 24
Finished Jan 03 02:01:55 PM PST 24
Peak memory 254696 kb
Host smart-936b3740-512a-438d-9007-f846df858f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037572753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2037572753
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3480215042
Short name T1422
Test name
Test status
Simulation time 2282370380 ps
CPU time 13.62 seconds
Started Jan 03 01:57:20 PM PST 24
Finished Jan 03 01:57:38 PM PST 24
Peak memory 234236 kb
Host smart-4803e50f-95ca-443e-b64f-6d2c10e5fc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480215042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3480215042
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.788790941
Short name T940
Test name
Test status
Simulation time 313353085 ps
CPU time 5.28 seconds
Started Jan 03 01:57:23 PM PST 24
Finished Jan 03 01:57:35 PM PST 24
Peak memory 219696 kb
Host smart-c7eb620c-9666-445d-808c-c3b529a0a595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788790941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.788790941
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_intr.3745782975
Short name T764
Test name
Test status
Simulation time 2823351991 ps
CPU time 10.25 seconds
Started Jan 03 01:57:21 PM PST 24
Finished Jan 03 01:57:38 PM PST 24
Peak memory 216960 kb
Host smart-4ab4b7b2-cd8e-40c3-beba-c7628259dbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745782975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intr.3745782975
Directory /workspace/17.spi_device_intr/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2065228195
Short name T40
Test name
Test status
Simulation time 32444554 ps
CPU time 1.12 seconds
Started Jan 03 01:57:22 PM PST 24
Finished Jan 03 01:57:30 PM PST 24
Peak memory 218804 kb
Host smart-34e39101-1fb0-49cb-b8d9-fd206fbbe9f5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065228195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2065228195
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.182113965
Short name T1356
Test name
Test status
Simulation time 9004500778 ps
CPU time 17.73 seconds
Started Jan 03 01:57:27 PM PST 24
Finished Jan 03 01:57:55 PM PST 24
Peak memory 249856 kb
Host smart-cd9f2cc8-78b2-46a1-9be8-58d894769a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182113965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.182113965
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.257535375
Short name T1468
Test name
Test status
Simulation time 802483035 ps
CPU time 4.55 seconds
Started Jan 03 01:57:28 PM PST 24
Finished Jan 03 01:57:43 PM PST 24
Peak memory 218560 kb
Host smart-53404b72-720b-4397-b36d-ef2b0600f218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257535375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.257535375
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_perf.3457641714
Short name T36
Test name
Test status
Simulation time 70639283668 ps
CPU time 297.92 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 02:02:32 PM PST 24
Peak memory 290364 kb
Host smart-6d66397a-ec3f-4357-b1ff-eb9b8da664ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457641714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_perf.3457641714
Directory /workspace/17.spi_device_perf/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.1419595092
Short name T101
Test name
Test status
Simulation time 17323114 ps
CPU time 0.72 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 01:57:33 PM PST 24
Peak memory 216636 kb
Host smart-2a66d00b-8419-4ee8-8403-235af31f0806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419595092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.1419595092
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1911929755
Short name T811
Test name
Test status
Simulation time 460546489 ps
CPU time 4.65 seconds
Started Jan 03 01:57:03 PM PST 24
Finished Jan 03 01:57:11 PM PST 24
Peak memory 234168 kb
Host smart-dd239910-c3c3-4556-8f23-4fd407be1e9f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1911929755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1911929755
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_rx_async_fifo_reset.2343364733
Short name T910
Test name
Test status
Simulation time 154945492 ps
CPU time 0.91 seconds
Started Jan 03 01:57:28 PM PST 24
Finished Jan 03 01:57:39 PM PST 24
Peak memory 208520 kb
Host smart-bde566e1-0bb3-44cb-89e6-98b880141c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343364733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_rx_async_fifo_reset.2343364733
Directory /workspace/17.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/17.spi_device_rx_timeout.2148189313
Short name T1248
Test name
Test status
Simulation time 1681107232 ps
CPU time 7.36 seconds
Started Jan 03 01:57:23 PM PST 24
Finished Jan 03 01:57:37 PM PST 24
Peak memory 216788 kb
Host smart-b646c9aa-7cfb-4117-a25b-263b6477b286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148189313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_rx_timeout.2148189313
Directory /workspace/17.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/17.spi_device_smoke.2581527831
Short name T1103
Test name
Test status
Simulation time 28573984 ps
CPU time 0.95 seconds
Started Jan 03 01:57:20 PM PST 24
Finished Jan 03 01:57:24 PM PST 24
Peak memory 207944 kb
Host smart-a4120553-9aea-47db-bffa-fae63ff71ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581527831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_smoke.2581527831
Directory /workspace/17.spi_device_smoke/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.4050136300
Short name T934
Test name
Test status
Simulation time 271474657892 ps
CPU time 756.51 seconds
Started Jan 03 01:57:18 PM PST 24
Finished Jan 03 02:09:57 PM PST 24
Peak memory 484152 kb
Host smart-b703b3d3-5d7f-4ef2-be48-459ae7648e97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050136300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.4050136300
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1347682750
Short name T63
Test name
Test status
Simulation time 270286998 ps
CPU time 3.31 seconds
Started Jan 03 01:57:21 PM PST 24
Finished Jan 03 01:57:30 PM PST 24
Peak memory 216984 kb
Host smart-cc8e72c6-0669-47d9-a260-fc33f6658a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347682750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1347682750
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2465397809
Short name T582
Test name
Test status
Simulation time 1446545145 ps
CPU time 2.96 seconds
Started Jan 03 01:57:24 PM PST 24
Finished Jan 03 01:57:34 PM PST 24
Peak memory 216944 kb
Host smart-5b9c01e0-20ff-43ea-8a0e-b2c44bdd13c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465397809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2465397809
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2416574604
Short name T1028
Test name
Test status
Simulation time 62715143 ps
CPU time 1.51 seconds
Started Jan 03 01:57:28 PM PST 24
Finished Jan 03 01:57:39 PM PST 24
Peak memory 216800 kb
Host smart-efb03699-334f-4ea7-b5bf-9e446be2443f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416574604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2416574604
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.175523490
Short name T1405
Test name
Test status
Simulation time 631534809 ps
CPU time 1.02 seconds
Started Jan 03 01:57:27 PM PST 24
Finished Jan 03 01:57:37 PM PST 24
Peak memory 208072 kb
Host smart-1b3a7a61-c54f-4f3a-9266-9a38816e1dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175523490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.175523490
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_tx_async_fifo_reset.3850015318
Short name T1011
Test name
Test status
Simulation time 15419799 ps
CPU time 0.76 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 01:57:34 PM PST 24
Peak memory 208456 kb
Host smart-a7c7a743-1b4f-4611-b049-3e0d85871e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850015318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tx_async_fifo_reset.3850015318
Directory /workspace/17.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/17.spi_device_txrx.3487891751
Short name T956
Test name
Test status
Simulation time 22114923371 ps
CPU time 417.56 seconds
Started Jan 03 01:57:22 PM PST 24
Finished Jan 03 02:04:25 PM PST 24
Peak memory 256184 kb
Host smart-b923194f-22de-4fa0-a3fd-79ddf9659fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487891751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_txrx.3487891751
Directory /workspace/17.spi_device_txrx/latest

Test location /workspace/coverage/default/17.spi_device_upload.2746164579
Short name T1752
Test name
Test status
Simulation time 1430082239 ps
CPU time 6.3 seconds
Started Jan 03 01:57:29 PM PST 24
Finished Jan 03 01:57:45 PM PST 24
Peak memory 239836 kb
Host smart-2967ee25-9228-478e-8bff-a5d434317d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746164579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2746164579
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_abort.976650867
Short name T1416
Test name
Test status
Simulation time 15628101 ps
CPU time 0.76 seconds
Started Jan 03 01:57:23 PM PST 24
Finished Jan 03 01:57:30 PM PST 24
Peak memory 206620 kb
Host smart-76f083fc-0ce8-4f6e-b576-ec667bf63641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976650867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_abort.976650867
Directory /workspace/18.spi_device_abort/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.600617282
Short name T922
Test name
Test status
Simulation time 44681995 ps
CPU time 0.73 seconds
Started Jan 03 01:57:24 PM PST 24
Finished Jan 03 01:57:32 PM PST 24
Peak memory 206508 kb
Host smart-1d83dd5c-5ca0-4efc-a50c-cf8f9f5787d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600617282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.600617282
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_bit_transfer.3186770543
Short name T533
Test name
Test status
Simulation time 339791492 ps
CPU time 2.1 seconds
Started Jan 03 01:57:23 PM PST 24
Finished Jan 03 01:57:32 PM PST 24
Peak memory 216792 kb
Host smart-ebc3e183-eac9-4839-a1bc-744306fb5382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186770543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_bit_transfer.3186770543
Directory /workspace/18.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/18.spi_device_byte_transfer.843632658
Short name T1637
Test name
Test status
Simulation time 311364590 ps
CPU time 3.77 seconds
Started Jan 03 01:57:18 PM PST 24
Finished Jan 03 01:57:24 PM PST 24
Peak memory 216724 kb
Host smart-d7bf318d-d565-40bd-a76f-cc3eed783ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843632658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_byte_transfer.843632658
Directory /workspace/18.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.28127558
Short name T1387
Test name
Test status
Simulation time 604305384 ps
CPU time 4.36 seconds
Started Jan 03 01:57:21 PM PST 24
Finished Jan 03 01:57:31 PM PST 24
Peak memory 220172 kb
Host smart-a65bcea9-fab1-426f-b8f6-bfafca87cdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28127558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.28127558
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3868070727
Short name T1083
Test name
Test status
Simulation time 63356042 ps
CPU time 0.78 seconds
Started Jan 03 01:57:21 PM PST 24
Finished Jan 03 01:57:27 PM PST 24
Peak memory 207596 kb
Host smart-2d152b29-afca-4f52-b931-af61c92ba7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868070727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3868070727
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_dummy_item_extra_dly.3479901288
Short name T1605
Test name
Test status
Simulation time 68216864773 ps
CPU time 174.32 seconds
Started Jan 03 01:57:19 PM PST 24
Finished Jan 03 02:00:15 PM PST 24
Peak memory 282656 kb
Host smart-d04d0731-cf56-436e-9cf5-9be4c454fa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479901288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_dummy_item_extra_dly.3479901288
Directory /workspace/18.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/18.spi_device_extreme_fifo_size.1486133546
Short name T927
Test name
Test status
Simulation time 8533070515 ps
CPU time 44.1 seconds
Started Jan 03 01:57:20 PM PST 24
Finished Jan 03 01:58:07 PM PST 24
Peak memory 232716 kb
Host smart-a49bc19f-2f85-4828-893c-2402192e350d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486133546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_extreme_fifo_size.1486133546
Directory /workspace/18.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/18.spi_device_fifo_full.3697428908
Short name T715
Test name
Test status
Simulation time 79954544700 ps
CPU time 388.43 seconds
Started Jan 03 01:57:03 PM PST 24
Finished Jan 03 02:03:35 PM PST 24
Peak memory 283492 kb
Host smart-58ed4ea7-a508-486d-aa99-b878d8b6e966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697428908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_fifo_full.3697428908
Directory /workspace/18.spi_device_fifo_full/latest

Test location /workspace/coverage/default/18.spi_device_fifo_underflow_overflow.2126043554
Short name T1685
Test name
Test status
Simulation time 27818061212 ps
CPU time 90.69 seconds
Started Jan 03 01:57:19 PM PST 24
Finished Jan 03 01:58:52 PM PST 24
Peak memory 282580 kb
Host smart-943de5f1-f700-40e1-9d69-131cd7697eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126043554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_fifo_underflow_overf
low.2126043554
Directory /workspace/18.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1043168640
Short name T1212
Test name
Test status
Simulation time 20468718731 ps
CPU time 132.63 seconds
Started Jan 03 01:57:20 PM PST 24
Finished Jan 03 01:59:35 PM PST 24
Peak memory 258692 kb
Host smart-7c11aac9-2873-4037-a4e9-e838955a1b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043168640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1043168640
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.331006752
Short name T1537
Test name
Test status
Simulation time 84873392528 ps
CPU time 157.51 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 02:00:11 PM PST 24
Peak memory 251172 kb
Host smart-80111f8b-c384-47ad-b9f9-846858b38ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331006752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.331006752
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.784675673
Short name T121
Test name
Test status
Simulation time 6177544888 ps
CPU time 53.55 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 01:58:26 PM PST 24
Peak memory 241476 kb
Host smart-db2fb0af-86c2-4565-8882-c1716d48d56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784675673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.784675673
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3248670875
Short name T1483
Test name
Test status
Simulation time 1505610331 ps
CPU time 13.35 seconds
Started Jan 03 01:57:24 PM PST 24
Finished Jan 03 01:57:44 PM PST 24
Peak memory 227920 kb
Host smart-715c23ce-90ab-434f-adf2-24d067c07154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248670875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3248670875
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2464717696
Short name T1315
Test name
Test status
Simulation time 406609606 ps
CPU time 4.91 seconds
Started Jan 03 01:57:24 PM PST 24
Finished Jan 03 01:57:36 PM PST 24
Peak memory 225040 kb
Host smart-7eed2994-d643-4b17-a9fc-6c3f115c2aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464717696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2464717696
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_intr.2177095683
Short name T1401
Test name
Test status
Simulation time 6877608967 ps
CPU time 29.34 seconds
Started Jan 03 01:57:19 PM PST 24
Finished Jan 03 01:57:51 PM PST 24
Peak memory 225136 kb
Host smart-3b525c0c-6c2a-4709-823a-b1b26404a8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177095683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intr.2177095683
Directory /workspace/18.spi_device_intr/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2592600119
Short name T1698
Test name
Test status
Simulation time 3024465519 ps
CPU time 18.39 seconds
Started Jan 03 01:57:23 PM PST 24
Finished Jan 03 01:57:47 PM PST 24
Peak memory 257808 kb
Host smart-3b5f4cb0-9ee4-4269-bef6-1d792b6b4f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592600119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2592600119
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2257678506
Short name T775
Test name
Test status
Simulation time 129973438 ps
CPU time 1.12 seconds
Started Jan 03 01:57:05 PM PST 24
Finished Jan 03 01:57:08 PM PST 24
Peak memory 218708 kb
Host smart-f64aff09-5c99-42b6-bc40-5c53ceb0ed4d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257678506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2257678506
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1579024712
Short name T1547
Test name
Test status
Simulation time 209068773 ps
CPU time 4.06 seconds
Started Jan 03 01:57:21 PM PST 24
Finished Jan 03 01:57:30 PM PST 24
Peak memory 219236 kb
Host smart-0337261f-b7ba-4242-9217-d80d6123c1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579024712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1579024712
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.4140442354
Short name T1590
Test name
Test status
Simulation time 3842869184 ps
CPU time 4.01 seconds
Started Jan 03 01:57:20 PM PST 24
Finished Jan 03 01:57:28 PM PST 24
Peak memory 239468 kb
Host smart-fdffb690-83ab-4238-8852-9b57652932bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140442354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.4140442354
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_perf.1607188879
Short name T765
Test name
Test status
Simulation time 33995498067 ps
CPU time 324.79 seconds
Started Jan 03 01:57:18 PM PST 24
Finished Jan 03 02:02:46 PM PST 24
Peak memory 299816 kb
Host smart-298e656b-ea1a-4ef2-a7d4-1e9d22677fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607188879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_perf.1607188879
Directory /workspace/18.spi_device_perf/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.560587983
Short name T102
Test name
Test status
Simulation time 38847886 ps
CPU time 0.77 seconds
Started Jan 03 01:57:21 PM PST 24
Finished Jan 03 01:57:28 PM PST 24
Peak memory 216708 kb
Host smart-9a69ea1a-91c0-4a04-a420-d6aacd5bce7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560587983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.560587983
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3388100857
Short name T1335
Test name
Test status
Simulation time 151362670 ps
CPU time 3.68 seconds
Started Jan 03 01:57:21 PM PST 24
Finished Jan 03 01:57:31 PM PST 24
Peak memory 218872 kb
Host smart-f1626a41-5d44-4730-bb23-5f71b74b8f7c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3388100857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3388100857
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_rx_async_fifo_reset.3992499990
Short name T1540
Test name
Test status
Simulation time 52659177 ps
CPU time 0.89 seconds
Started Jan 03 01:57:20 PM PST 24
Finished Jan 03 01:57:26 PM PST 24
Peak memory 208504 kb
Host smart-125d7550-471d-4a8d-9083-ed31359eb178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992499990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_rx_async_fifo_reset.3992499990
Directory /workspace/18.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/18.spi_device_rx_timeout.1946422345
Short name T908
Test name
Test status
Simulation time 10046629431 ps
CPU time 6.78 seconds
Started Jan 03 01:57:26 PM PST 24
Finished Jan 03 01:57:41 PM PST 24
Peak memory 216876 kb
Host smart-dedf977f-6692-4606-9ae9-814f0525dc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946422345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_rx_timeout.1946422345
Directory /workspace/18.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/18.spi_device_smoke.308553440
Short name T1415
Test name
Test status
Simulation time 42140502 ps
CPU time 1.09 seconds
Started Jan 03 01:57:20 PM PST 24
Finished Jan 03 01:57:25 PM PST 24
Peak memory 208380 kb
Host smart-77f51c5f-ca80-4db2-a8db-2ddb6e7aa369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308553440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_smoke.308553440
Directory /workspace/18.spi_device_smoke/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3284860481
Short name T13
Test name
Test status
Simulation time 9662846839 ps
CPU time 23.9 seconds
Started Jan 03 01:57:19 PM PST 24
Finished Jan 03 01:57:45 PM PST 24
Peak memory 216848 kb
Host smart-89f7d16e-0c16-49f1-b9b1-90061f96b3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284860481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3284860481
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1108247216
Short name T1758
Test name
Test status
Simulation time 1250211767 ps
CPU time 6.29 seconds
Started Jan 03 01:57:20 PM PST 24
Finished Jan 03 01:57:30 PM PST 24
Peak memory 216820 kb
Host smart-51925ab1-8661-4308-b295-93c06628de9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108247216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1108247216
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3450147842
Short name T661
Test name
Test status
Simulation time 19018507 ps
CPU time 0.93 seconds
Started Jan 03 01:57:27 PM PST 24
Finished Jan 03 01:57:37 PM PST 24
Peak memory 207916 kb
Host smart-de14bc60-c34d-4b4e-b6fb-e167531d4dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450147842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3450147842
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1489368851
Short name T1473
Test name
Test status
Simulation time 78904953 ps
CPU time 0.94 seconds
Started Jan 03 01:57:22 PM PST 24
Finished Jan 03 01:57:29 PM PST 24
Peak memory 206900 kb
Host smart-1a6cc9bb-8c99-48ee-bc5c-2c8a0e1662f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489368851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1489368851
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_tx_async_fifo_reset.2373143275
Short name T660
Test name
Test status
Simulation time 46753623 ps
CPU time 0.77 seconds
Started Jan 03 01:57:23 PM PST 24
Finished Jan 03 01:57:30 PM PST 24
Peak memory 208372 kb
Host smart-857d2a77-e6b4-4492-8333-810a6a07e17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373143275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tx_async_fifo_reset.2373143275
Directory /workspace/18.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/18.spi_device_txrx.453163055
Short name T1768
Test name
Test status
Simulation time 136794008873 ps
CPU time 312.89 seconds
Started Jan 03 01:57:03 PM PST 24
Finished Jan 03 02:02:20 PM PST 24
Peak memory 335400 kb
Host smart-39a587c6-e66c-4340-9570-b829b4260a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453163055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_txrx.453163055
Directory /workspace/18.spi_device_txrx/latest

Test location /workspace/coverage/default/18.spi_device_upload.2384761161
Short name T1549
Test name
Test status
Simulation time 2011241054 ps
CPU time 11.93 seconds
Started Jan 03 01:57:21 PM PST 24
Finished Jan 03 01:57:38 PM PST 24
Peak memory 240576 kb
Host smart-48fde63e-3b92-4a14-b19d-141eb03b4920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384761161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2384761161
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4269961095
Short name T1777
Test name
Test status
Simulation time 39230911 ps
CPU time 0.72 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 01:57:35 PM PST 24
Peak memory 206540 kb
Host smart-637d6e39-2941-4a83-a248-65b8c654c56d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269961095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4269961095
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_bit_transfer.951169860
Short name T225
Test name
Test status
Simulation time 1129108718 ps
CPU time 2.93 seconds
Started Jan 03 01:57:20 PM PST 24
Finished Jan 03 01:57:27 PM PST 24
Peak memory 216820 kb
Host smart-55f735fd-7334-411b-ad63-0cfadfb98f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951169860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_bit_transfer.951169860
Directory /workspace/19.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/19.spi_device_byte_transfer.2970261071
Short name T625
Test name
Test status
Simulation time 140841219 ps
CPU time 3.13 seconds
Started Jan 03 01:57:24 PM PST 24
Finished Jan 03 01:57:34 PM PST 24
Peak memory 216856 kb
Host smart-b639b6a5-c383-455f-85e3-a1f268521b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970261071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_byte_transfer.2970261071
Directory /workspace/19.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1194331788
Short name T308
Test name
Test status
Simulation time 1173996624 ps
CPU time 2.79 seconds
Started Jan 03 01:57:24 PM PST 24
Finished Jan 03 01:57:34 PM PST 24
Peak memory 218384 kb
Host smart-d5528896-cf1f-4857-a974-35c167ca0388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194331788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1194331788
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3396551676
Short name T594
Test name
Test status
Simulation time 21306858 ps
CPU time 0.75 seconds
Started Jan 03 01:57:24 PM PST 24
Finished Jan 03 01:57:31 PM PST 24
Peak memory 207592 kb
Host smart-b979dd37-b803-487c-aeee-7b93f3516983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396551676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3396551676
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_dummy_item_extra_dly.453782211
Short name T1629
Test name
Test status
Simulation time 119418835615 ps
CPU time 258.69 seconds
Started Jan 03 01:57:24 PM PST 24
Finished Jan 03 02:01:50 PM PST 24
Peak memory 251480 kb
Host smart-ea606499-d318-4f75-835d-3f10b9d9a7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453782211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_dummy_item_extra_dly.453782211
Directory /workspace/19.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/19.spi_device_extreme_fifo_size.3825889256
Short name T1205
Test name
Test status
Simulation time 293309915939 ps
CPU time 955.17 seconds
Started Jan 03 01:57:27 PM PST 24
Finished Jan 03 02:13:31 PM PST 24
Peak memory 219268 kb
Host smart-6aae6e30-c4ee-4e18-a54f-27192332765f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825889256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_extreme_fifo_size.3825889256
Directory /workspace/19.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/19.spi_device_fifo_full.3174425470
Short name T1251
Test name
Test status
Simulation time 131221803977 ps
CPU time 493.76 seconds
Started Jan 03 01:57:24 PM PST 24
Finished Jan 03 02:05:45 PM PST 24
Peak memory 289068 kb
Host smart-9f7e6b29-4474-4052-8c72-821671bbd631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174425470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_fifo_full.3174425470
Directory /workspace/19.spi_device_fifo_full/latest

Test location /workspace/coverage/default/19.spi_device_fifo_underflow_overflow.2746374066
Short name T1361
Test name
Test status
Simulation time 31428800847 ps
CPU time 256.35 seconds
Started Jan 03 01:57:23 PM PST 24
Finished Jan 03 02:01:47 PM PST 24
Peak memory 372572 kb
Host smart-2f973a66-646d-4954-9626-3556f0b099d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746374066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_fifo_underflow_overf
low.2746374066
Directory /workspace/19.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1321763155
Short name T1488
Test name
Test status
Simulation time 17345223853 ps
CPU time 122.34 seconds
Started Jan 03 01:57:26 PM PST 24
Finished Jan 03 01:59:37 PM PST 24
Peak memory 256044 kb
Host smart-5d75382e-ebf1-4ca8-bead-1427cfa50d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321763155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1321763155
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.472905179
Short name T1309
Test name
Test status
Simulation time 57267414182 ps
CPU time 29.19 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 01:58:02 PM PST 24
Peak memory 240980 kb
Host smart-ea73223d-43e4-4762-991b-5bc750a742bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472905179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.472905179
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4155144441
Short name T832
Test name
Test status
Simulation time 1909972255 ps
CPU time 5.66 seconds
Started Jan 03 01:57:24 PM PST 24
Finished Jan 03 01:57:37 PM PST 24
Peak memory 219532 kb
Host smart-82103dbb-4119-499e-ab8c-9d5258c6fc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155144441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4155144441
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_intr.1447459555
Short name T1179
Test name
Test status
Simulation time 67967142503 ps
CPU time 28.26 seconds
Started Jan 03 01:57:23 PM PST 24
Finished Jan 03 01:57:58 PM PST 24
Peak memory 232848 kb
Host smart-4d2edc5f-e600-4018-8208-61358d4c3284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447459555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intr.1447459555
Directory /workspace/19.spi_device_intr/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.360767674
Short name T839
Test name
Test status
Simulation time 13979732708 ps
CPU time 40.63 seconds
Started Jan 03 01:57:23 PM PST 24
Finished Jan 03 01:58:10 PM PST 24
Peak memory 241556 kb
Host smart-c2ec64ca-d2d7-4c14-bc95-e8fab9a73000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360767674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.360767674
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2820042356
Short name T41
Test name
Test status
Simulation time 131358557 ps
CPU time 1.09 seconds
Started Jan 03 01:57:20 PM PST 24
Finished Jan 03 01:57:24 PM PST 24
Peak memory 218784 kb
Host smart-448b7322-9a5e-4caa-bcc6-6057923f4373
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820042356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2820042356
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.672756871
Short name T351
Test name
Test status
Simulation time 37957306747 ps
CPU time 20.92 seconds
Started Jan 03 01:57:21 PM PST 24
Finished Jan 03 01:57:46 PM PST 24
Peak memory 247732 kb
Host smart-d712a8f9-56a9-48df-b6dc-17af17deb48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672756871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.672756871
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.258382783
Short name T1250
Test name
Test status
Simulation time 463669130 ps
CPU time 4.61 seconds
Started Jan 03 01:57:24 PM PST 24
Finished Jan 03 01:57:36 PM PST 24
Peak memory 219368 kb
Host smart-c5df4e16-85bb-47c1-affb-453c4345938f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258382783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.258382783
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_perf.3553374047
Short name T718
Test name
Test status
Simulation time 23191465334 ps
CPU time 458.86 seconds
Started Jan 03 01:57:20 PM PST 24
Finished Jan 03 02:05:03 PM PST 24
Peak memory 249144 kb
Host smart-7ba70023-7f0f-4dfe-859d-ff451d010bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553374047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_perf.3553374047
Directory /workspace/19.spi_device_perf/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.1934632928
Short name T100
Test name
Test status
Simulation time 20988119 ps
CPU time 0.72 seconds
Started Jan 03 01:57:23 PM PST 24
Finished Jan 03 01:57:30 PM PST 24
Peak memory 216736 kb
Host smart-8e7bd37b-7513-469a-851c-d7f8ac3b7ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934632928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.1934632928
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4004242309
Short name T1674
Test name
Test status
Simulation time 602041695 ps
CPU time 4.26 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 01:57:38 PM PST 24
Peak memory 220872 kb
Host smart-f75f01ff-3d11-42dc-892d-2daee16e0b6d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4004242309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4004242309
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_rx_async_fifo_reset.49382612
Short name T684
Test name
Test status
Simulation time 45817993 ps
CPU time 0.95 seconds
Started Jan 03 01:57:23 PM PST 24
Finished Jan 03 01:57:31 PM PST 24
Peak memory 208468 kb
Host smart-913c811a-d32e-4074-a653-1611e9301a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49382612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_rx_async_fifo_reset.49382612
Directory /workspace/19.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/19.spi_device_rx_timeout.3107456170
Short name T1424
Test name
Test status
Simulation time 2721115398 ps
CPU time 5.44 seconds
Started Jan 03 01:57:20 PM PST 24
Finished Jan 03 01:57:30 PM PST 24
Peak memory 216904 kb
Host smart-196e19b1-4e0a-4c00-aab8-ffbab9cb6d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107456170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_rx_timeout.3107456170
Directory /workspace/19.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/19.spi_device_smoke.1708105752
Short name T1351
Test name
Test status
Simulation time 97520054 ps
CPU time 1.02 seconds
Started Jan 03 01:57:20 PM PST 24
Finished Jan 03 01:57:25 PM PST 24
Peak memory 208292 kb
Host smart-4c0e55b8-4ac9-4526-a742-e52523ea3915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708105752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_smoke.1708105752
Directory /workspace/19.spi_device_smoke/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.450443214
Short name T985
Test name
Test status
Simulation time 2283070818 ps
CPU time 38.5 seconds
Started Jan 03 01:57:21 PM PST 24
Finished Jan 03 01:58:05 PM PST 24
Peak memory 217152 kb
Host smart-7a044650-4089-44fc-8e9e-ccd3ca68cdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450443214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.450443214
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2201493832
Short name T618
Test name
Test status
Simulation time 10273021737 ps
CPU time 12.32 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 01:57:45 PM PST 24
Peak memory 216852 kb
Host smart-c5de0c11-ddff-427c-8c1d-439899aeb0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201493832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2201493832
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1209244035
Short name T1584
Test name
Test status
Simulation time 207784823 ps
CPU time 2.08 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 01:57:36 PM PST 24
Peak memory 216844 kb
Host smart-e386fce6-ac9b-4aa9-917d-2bb056bb8b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209244035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1209244035
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1525585073
Short name T1711
Test name
Test status
Simulation time 1627190567 ps
CPU time 1.04 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 01:57:35 PM PST 24
Peak memory 208076 kb
Host smart-fa35f369-8f00-4b1a-ae1b-ad609ccd6783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525585073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1525585073
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_tx_async_fifo_reset.2046919049
Short name T1398
Test name
Test status
Simulation time 19291036 ps
CPU time 0.78 seconds
Started Jan 03 01:57:22 PM PST 24
Finished Jan 03 01:57:29 PM PST 24
Peak memory 208452 kb
Host smart-ba6f2e2f-c128-47f0-813e-bc56b1732afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046919049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tx_async_fifo_reset.2046919049
Directory /workspace/19.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/19.spi_device_txrx.2997797950
Short name T1137
Test name
Test status
Simulation time 52717895658 ps
CPU time 129.97 seconds
Started Jan 03 01:57:22 PM PST 24
Finished Jan 03 01:59:38 PM PST 24
Peak memory 262848 kb
Host smart-29d91392-560b-4678-bd56-bf1d989b52d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997797950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_txrx.2997797950
Directory /workspace/19.spi_device_txrx/latest

Test location /workspace/coverage/default/19.spi_device_upload.1863213548
Short name T942
Test name
Test status
Simulation time 6618712034 ps
CPU time 16.88 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 01:57:50 PM PST 24
Peak memory 238620 kb
Host smart-1ae109ae-2485-4224-80a5-d4e11dae5918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863213548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1863213548
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_abort.1507184311
Short name T1756
Test name
Test status
Simulation time 16032740 ps
CPU time 0.75 seconds
Started Jan 03 01:50:48 PM PST 24
Finished Jan 03 01:50:58 PM PST 24
Peak memory 206676 kb
Host smart-5704f168-a8d3-4c5b-8001-74071a4afa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507184311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_abort.1507184311
Directory /workspace/2.spi_device_abort/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3577255837
Short name T620
Test name
Test status
Simulation time 34991824 ps
CPU time 0.78 seconds
Started Jan 03 01:51:23 PM PST 24
Finished Jan 03 01:51:37 PM PST 24
Peak memory 206504 kb
Host smart-f011e590-aef4-4fd0-869a-945a0d0186ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577255837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
577255837
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_bit_transfer.1964836003
Short name T730
Test name
Test status
Simulation time 1732817857 ps
CPU time 2.56 seconds
Started Jan 03 01:50:46 PM PST 24
Finished Jan 03 01:50:58 PM PST 24
Peak memory 216740 kb
Host smart-ab184da7-6df5-4cf8-ac85-bd585f5461ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964836003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_bit_transfer.1964836003
Directory /workspace/2.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/2.spi_device_byte_transfer.1779311579
Short name T953
Test name
Test status
Simulation time 3247885729 ps
CPU time 2.9 seconds
Started Jan 03 01:50:33 PM PST 24
Finished Jan 03 01:50:44 PM PST 24
Peak memory 216908 kb
Host smart-7682bbf0-06fd-4249-9524-0ac953a289e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779311579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_byte_transfer.1779311579
Directory /workspace/2.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3463749954
Short name T1628
Test name
Test status
Simulation time 2105554870 ps
CPU time 4.08 seconds
Started Jan 03 01:51:02 PM PST 24
Finished Jan 03 01:51:10 PM PST 24
Peak memory 238208 kb
Host smart-302ef82f-e1a5-4eff-b7cd-d59b6e117283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463749954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3463749954
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3184094758
Short name T1512
Test name
Test status
Simulation time 23227693 ps
CPU time 0.84 seconds
Started Jan 03 01:50:57 PM PST 24
Finished Jan 03 01:51:04 PM PST 24
Peak memory 207660 kb
Host smart-d26b7495-be39-4a2b-8e4c-f5bac6e9cdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184094758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3184094758
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_dummy_item_extra_dly.174109904
Short name T1155
Test name
Test status
Simulation time 138183228527 ps
CPU time 224.26 seconds
Started Jan 03 01:50:56 PM PST 24
Finished Jan 03 01:54:47 PM PST 24
Peak memory 276700 kb
Host smart-09eaca10-9e63-4eb0-a27c-733347a32593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174109904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_dummy_item_extra_dly.174109904
Directory /workspace/2.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/2.spi_device_extreme_fifo_size.1636764486
Short name T955
Test name
Test status
Simulation time 24069924076 ps
CPU time 46.55 seconds
Started Jan 03 01:51:01 PM PST 24
Finished Jan 03 01:51:52 PM PST 24
Peak memory 235076 kb
Host smart-83156b53-d5d6-4627-800c-ff55b5b0e254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636764486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_extreme_fifo_size.1636764486
Directory /workspace/2.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/2.spi_device_fifo_full.887152615
Short name T697
Test name
Test status
Simulation time 160915025287 ps
CPU time 474.17 seconds
Started Jan 03 01:50:33 PM PST 24
Finished Jan 03 01:58:35 PM PST 24
Peak memory 281632 kb
Host smart-5e5b3f70-c8d7-4441-b3bc-26e2bed5175d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887152615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_fifo_full.887152615
Directory /workspace/2.spi_device_fifo_full/latest

Test location /workspace/coverage/default/2.spi_device_fifo_underflow_overflow.1411928900
Short name T1646
Test name
Test status
Simulation time 342288269496 ps
CPU time 198.16 seconds
Started Jan 03 01:50:44 PM PST 24
Finished Jan 03 01:54:12 PM PST 24
Peak memory 339292 kb
Host smart-788ad1a8-5386-48ee-b0d7-0e3dc694e1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411928900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_fifo_underflow_overfl
ow.1411928900
Directory /workspace/2.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3276744639
Short name T1491
Test name
Test status
Simulation time 9107650124 ps
CPU time 37.86 seconds
Started Jan 03 01:50:46 PM PST 24
Finished Jan 03 01:51:33 PM PST 24
Peak memory 249732 kb
Host smart-aa0d483e-4fcb-4561-a324-f833589a1e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276744639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3276744639
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3107596786
Short name T199
Test name
Test status
Simulation time 7632302002 ps
CPU time 81.82 seconds
Started Jan 03 01:51:04 PM PST 24
Finished Jan 03 01:52:30 PM PST 24
Peak memory 250692 kb
Host smart-93022e28-9ccf-4f9e-93cc-560c7b2dafae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107596786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3107596786
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2500812006
Short name T1244
Test name
Test status
Simulation time 14310542776 ps
CPU time 14.52 seconds
Started Jan 03 01:50:37 PM PST 24
Finished Jan 03 01:50:58 PM PST 24
Peak memory 236864 kb
Host smart-4c166b14-9871-4f27-8946-21199e86d12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500812006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2500812006
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3267221811
Short name T1408
Test name
Test status
Simulation time 5048317855 ps
CPU time 8.19 seconds
Started Jan 03 01:50:48 PM PST 24
Finished Jan 03 01:51:06 PM PST 24
Peak memory 219596 kb
Host smart-f4446ad0-5735-4e38-9944-fe120e1ec1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267221811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3267221811
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_intr.960694672
Short name T1702
Test name
Test status
Simulation time 23592582001 ps
CPU time 92.48 seconds
Started Jan 03 01:50:44 PM PST 24
Finished Jan 03 01:52:26 PM PST 24
Peak memory 240948 kb
Host smart-367d3bdc-793f-4099-8c7c-20e89f1fba7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960694672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intr.960694672
Directory /workspace/2.spi_device_intr/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1902597049
Short name T1125
Test name
Test status
Simulation time 63887183709 ps
CPU time 52.16 seconds
Started Jan 03 01:50:57 PM PST 24
Finished Jan 03 01:51:55 PM PST 24
Peak memory 249744 kb
Host smart-34121e0f-90e0-49f4-b778-2770a9222fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902597049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1902597049
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3239222573
Short name T769
Test name
Test status
Simulation time 33928117 ps
CPU time 1.12 seconds
Started Jan 03 01:50:58 PM PST 24
Finished Jan 03 01:51:04 PM PST 24
Peak memory 218856 kb
Host smart-70d848fd-885e-4d0b-8674-5326df5ba5e6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239222573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3239222573
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1759700226
Short name T1530
Test name
Test status
Simulation time 2700673402 ps
CPU time 4.87 seconds
Started Jan 03 01:51:01 PM PST 24
Finished Jan 03 01:51:10 PM PST 24
Peak memory 218340 kb
Host smart-d68dc491-4c7a-49a8-bbc4-bd1786e39fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759700226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1759700226
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.316654106
Short name T321
Test name
Test status
Simulation time 7720131832 ps
CPU time 10.25 seconds
Started Jan 03 01:50:55 PM PST 24
Finished Jan 03 01:51:12 PM PST 24
Peak memory 249704 kb
Host smart-e6d4b284-e275-4669-867a-14ad3abd669e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316654106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.316654106
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_perf.2092341667
Short name T784
Test name
Test status
Simulation time 23101435064 ps
CPU time 598.21 seconds
Started Jan 03 01:50:56 PM PST 24
Finished Jan 03 02:01:00 PM PST 24
Peak memory 249768 kb
Host smart-54ac2000-393a-4666-b062-3dbf56a79cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092341667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_perf.2092341667
Directory /workspace/2.spi_device_perf/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.1677758281
Short name T1209
Test name
Test status
Simulation time 40015957 ps
CPU time 0.74 seconds
Started Jan 03 01:51:06 PM PST 24
Finished Jan 03 01:51:15 PM PST 24
Peak memory 216660 kb
Host smart-4d559af7-b692-470e-aeb1-41f9a0955ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677758281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.1677758281
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2552522506
Short name T1124
Test name
Test status
Simulation time 315660439 ps
CPU time 4.67 seconds
Started Jan 03 01:50:57 PM PST 24
Finished Jan 03 01:51:08 PM PST 24
Peak memory 235100 kb
Host smart-91f3fe5c-9953-4620-8ca1-9742c201c728
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2552522506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2552522506
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_rx_timeout.31625255
Short name T1492
Test name
Test status
Simulation time 3106901397 ps
CPU time 5.64 seconds
Started Jan 03 01:51:00 PM PST 24
Finished Jan 03 01:51:10 PM PST 24
Peak memory 216964 kb
Host smart-c30aa1af-2ddd-4edb-a558-06464b987105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31625255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_rx_timeout.31625255
Directory /workspace/2.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.275713812
Short name T105
Test name
Test status
Simulation time 86692219 ps
CPU time 1.2 seconds
Started Jan 03 01:51:25 PM PST 24
Finished Jan 03 01:51:45 PM PST 24
Peak memory 238072 kb
Host smart-78e4e42b-466d-4f9f-bb72-9174de5e723b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275713812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.275713812
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_smoke.1923574794
Short name T713
Test name
Test status
Simulation time 194343048 ps
CPU time 1.18 seconds
Started Jan 03 01:50:46 PM PST 24
Finished Jan 03 01:50:57 PM PST 24
Peak memory 216772 kb
Host smart-4b679f9b-e62a-4ebb-a584-1fc2793688d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923574794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_smoke.1923574794
Directory /workspace/2.spi_device_smoke/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2828214919
Short name T381
Test name
Test status
Simulation time 32382846176 ps
CPU time 303.11 seconds
Started Jan 03 01:51:08 PM PST 24
Finished Jan 03 01:56:20 PM PST 24
Peak memory 273936 kb
Host smart-f3c1322e-4bb3-44da-ab66-4db33441126d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828214919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2828214919
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1967793189
Short name T393
Test name
Test status
Simulation time 3283121990 ps
CPU time 60.28 seconds
Started Jan 03 01:51:00 PM PST 24
Finished Jan 03 01:52:05 PM PST 24
Peak memory 217128 kb
Host smart-28a6d62f-8c4f-414b-ad9d-9a351ddceb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967793189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1967793189
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1805860865
Short name T638
Test name
Test status
Simulation time 11966237956 ps
CPU time 31.26 seconds
Started Jan 03 01:50:44 PM PST 24
Finished Jan 03 01:51:24 PM PST 24
Peak memory 216820 kb
Host smart-a0e1828b-71cb-4e54-aab7-ada93c4087b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805860865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1805860865
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2210636606
Short name T1475
Test name
Test status
Simulation time 98066360 ps
CPU time 2.2 seconds
Started Jan 03 01:50:47 PM PST 24
Finished Jan 03 01:50:58 PM PST 24
Peak memory 216820 kb
Host smart-22e79e19-b5f2-4e0a-90aa-3730955efc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210636606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2210636606
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.4228157270
Short name T1236
Test name
Test status
Simulation time 180110804 ps
CPU time 0.96 seconds
Started Jan 03 01:51:05 PM PST 24
Finished Jan 03 01:51:10 PM PST 24
Peak memory 208004 kb
Host smart-612d0230-8b30-44a1-925c-594541069eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228157270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4228157270
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_tx_async_fifo_reset.3313374202
Short name T997
Test name
Test status
Simulation time 29628631 ps
CPU time 0.77 seconds
Started Jan 03 01:51:06 PM PST 24
Finished Jan 03 01:51:13 PM PST 24
Peak memory 208464 kb
Host smart-bc5625eb-63f4-471a-b24f-84d566bb8004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313374202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tx_async_fifo_reset.3313374202
Directory /workspace/2.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/2.spi_device_txrx.320429688
Short name T849
Test name
Test status
Simulation time 48074436514 ps
CPU time 244.57 seconds
Started Jan 03 01:50:33 PM PST 24
Finished Jan 03 01:54:45 PM PST 24
Peak memory 289960 kb
Host smart-9ed680b5-d78c-4401-b1b5-624e5ffde6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320429688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_txrx.320429688
Directory /workspace/2.spi_device_txrx/latest

Test location /workspace/coverage/default/2.spi_device_upload.1707705306
Short name T946
Test name
Test status
Simulation time 1576415762 ps
CPU time 5.94 seconds
Started Jan 03 01:51:07 PM PST 24
Finished Jan 03 01:51:20 PM PST 24
Peak memory 219388 kb
Host smart-bd8edddb-6d85-49b2-b787-5e53cf1d17d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707705306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1707705306
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_abort.2312445394
Short name T1554
Test name
Test status
Simulation time 17732057 ps
CPU time 0.75 seconds
Started Jan 03 01:57:46 PM PST 24
Finished Jan 03 01:57:48 PM PST 24
Peak memory 206612 kb
Host smart-b50c7dc2-37b2-40d9-924d-57bec49c866a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312445394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_abort.2312445394
Directory /workspace/20.spi_device_abort/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1119980340
Short name T681
Test name
Test status
Simulation time 13434814 ps
CPU time 0.72 seconds
Started Jan 03 01:57:47 PM PST 24
Finished Jan 03 01:57:50 PM PST 24
Peak memory 206520 kb
Host smart-b8d6a879-de16-4d8f-8883-4fa66547d35a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119980340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1119980340
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_bit_transfer.3344893754
Short name T641
Test name
Test status
Simulation time 199900699 ps
CPU time 2.42 seconds
Started Jan 03 01:57:25 PM PST 24
Finished Jan 03 01:57:35 PM PST 24
Peak memory 216716 kb
Host smart-f0b786d0-6f36-4907-9b41-6235ec3e3658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344893754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_bit_transfer.3344893754
Directory /workspace/20.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/20.spi_device_byte_transfer.35067776
Short name T864
Test name
Test status
Simulation time 182015214 ps
CPU time 3.09 seconds
Started Jan 03 01:57:28 PM PST 24
Finished Jan 03 01:57:41 PM PST 24
Peak memory 216988 kb
Host smart-90abc246-95fc-44ed-b291-230556d5b4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35067776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_byte_transfer.35067776
Directory /workspace/20.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3786538155
Short name T1346
Test name
Test status
Simulation time 1604157180 ps
CPU time 4.38 seconds
Started Jan 03 01:57:48 PM PST 24
Finished Jan 03 01:57:55 PM PST 24
Peak memory 240316 kb
Host smart-63289c29-7230-4e3f-8b29-51d3a6594c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786538155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3786538155
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3445763945
Short name T1307
Test name
Test status
Simulation time 26257114 ps
CPU time 0.75 seconds
Started Jan 03 01:57:27 PM PST 24
Finished Jan 03 01:57:38 PM PST 24
Peak memory 206612 kb
Host smart-b03e9bed-5b0c-47fb-8653-21ce7a2d2d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445763945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3445763945
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_dummy_item_extra_dly.1120824969
Short name T1757
Test name
Test status
Simulation time 131033338944 ps
CPU time 3199.78 seconds
Started Jan 03 01:57:28 PM PST 24
Finished Jan 03 02:50:58 PM PST 24
Peak memory 288636 kb
Host smart-058a6589-62e6-4446-b754-8052d5ea056c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120824969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_dummy_item_extra_dly.1120824969
Directory /workspace/20.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/20.spi_device_extreme_fifo_size.339704159
Short name T1429
Test name
Test status
Simulation time 4627089638 ps
CPU time 97.41 seconds
Started Jan 03 01:57:28 PM PST 24
Finished Jan 03 01:59:15 PM PST 24
Peak memory 225020 kb
Host smart-1ff656ae-bd68-49e8-b3d0-e6cdc665f359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339704159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_extreme_fifo_size.339704159
Directory /workspace/20.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/20.spi_device_fifo_full.494690603
Short name T606
Test name
Test status
Simulation time 150658040136 ps
CPU time 615.36 seconds
Started Jan 03 01:57:23 PM PST 24
Finished Jan 03 02:07:46 PM PST 24
Peak memory 282040 kb
Host smart-c918e439-4050-410f-8505-0a918659c5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494690603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_fifo_full.494690603
Directory /workspace/20.spi_device_fifo_full/latest

Test location /workspace/coverage/default/20.spi_device_fifo_underflow_overflow.1416953848
Short name T51
Test name
Test status
Simulation time 26622767073 ps
CPU time 253.82 seconds
Started Jan 03 01:57:28 PM PST 24
Finished Jan 03 02:01:52 PM PST 24
Peak memory 386424 kb
Host smart-e8388a96-ab75-4011-a68b-0927c0b43e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416953848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_fifo_underflow_overf
low.1416953848
Directory /workspace/20.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3672882935
Short name T1166
Test name
Test status
Simulation time 15695520865 ps
CPU time 39.54 seconds
Started Jan 03 01:57:49 PM PST 24
Finished Jan 03 01:58:33 PM PST 24
Peak memory 251136 kb
Host smart-4f941acb-942e-419c-b9e3-7cbcbc9e2b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672882935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3672882935
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2059464027
Short name T376
Test name
Test status
Simulation time 278351126139 ps
CPU time 396.97 seconds
Started Jan 03 01:57:50 PM PST 24
Finished Jan 03 02:04:32 PM PST 24
Peak memory 265100 kb
Host smart-b76e1328-f266-45d5-ab0b-49bd0b8e3a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059464027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2059464027
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3047809397
Short name T43
Test name
Test status
Simulation time 109347194198 ps
CPU time 178.54 seconds
Started Jan 03 01:57:46 PM PST 24
Finished Jan 03 02:00:47 PM PST 24
Peak memory 266064 kb
Host smart-d3d6bf40-1e17-4764-a54d-95e2592e2e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047809397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3047809397
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2871197046
Short name T1534
Test name
Test status
Simulation time 717004398 ps
CPU time 11.85 seconds
Started Jan 03 01:57:50 PM PST 24
Finished Jan 03 01:58:07 PM PST 24
Peak memory 233228 kb
Host smart-6f225b30-dcc1-4c7b-b833-bd45d767cc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871197046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2871197046
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.722416017
Short name T243
Test name
Test status
Simulation time 37690977 ps
CPU time 3.02 seconds
Started Jan 03 01:57:50 PM PST 24
Finished Jan 03 01:57:58 PM PST 24
Peak memory 234360 kb
Host smart-88d50197-dac0-403b-86ab-c518f82fb685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722416017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.722416017
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_intr.804749450
Short name T1036
Test name
Test status
Simulation time 24010394412 ps
CPU time 63.94 seconds
Started Jan 03 01:57:27 PM PST 24
Finished Jan 03 01:58:41 PM PST 24
Peak memory 240700 kb
Host smart-833f1468-06b1-4034-b1e1-45d95972f0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804749450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intr.804749450
Directory /workspace/20.spi_device_intr/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1605293553
Short name T1466
Test name
Test status
Simulation time 568048844 ps
CPU time 7.65 seconds
Started Jan 03 01:57:50 PM PST 24
Finished Jan 03 01:58:03 PM PST 24
Peak memory 246140 kb
Host smart-9432e563-6704-4da7-84e8-2c876a7320fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605293553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1605293553
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3539202939
Short name T1744
Test name
Test status
Simulation time 1667085653 ps
CPU time 5 seconds
Started Jan 03 01:57:46 PM PST 24
Finished Jan 03 01:57:53 PM PST 24
Peak memory 230932 kb
Host smart-6c70b2f1-b622-4fa0-ac21-6d128fdba564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539202939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3539202939
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2831119966
Short name T1044
Test name
Test status
Simulation time 56136842947 ps
CPU time 35.73 seconds
Started Jan 03 01:57:47 PM PST 24
Finished Jan 03 01:58:26 PM PST 24
Peak memory 233336 kb
Host smart-fcd079c0-501a-4133-a55f-5c0216899417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831119966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2831119966
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_perf.2419626759
Short name T155
Test name
Test status
Simulation time 28879185296 ps
CPU time 728.63 seconds
Started Jan 03 01:57:27 PM PST 24
Finished Jan 03 02:09:46 PM PST 24
Peak memory 249848 kb
Host smart-764516fd-71cb-457a-94f3-56b370eec60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419626759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_perf.2419626759
Directory /workspace/20.spi_device_perf/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1698109047
Short name T880
Test name
Test status
Simulation time 333285590 ps
CPU time 4.56 seconds
Started Jan 03 01:57:45 PM PST 24
Finished Jan 03 01:57:51 PM PST 24
Peak memory 218644 kb
Host smart-f60a1f5c-19f3-4827-b0d6-ea5635e13c88
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1698109047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1698109047
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_rx_async_fifo_reset.390243807
Short name T887
Test name
Test status
Simulation time 127047557 ps
CPU time 0.89 seconds
Started Jan 03 01:57:47 PM PST 24
Finished Jan 03 01:57:51 PM PST 24
Peak memory 208600 kb
Host smart-5f6d797a-aa3c-46c0-9848-a48bd848cec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390243807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_rx_async_fifo_reset.390243807
Directory /workspace/20.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/20.spi_device_rx_timeout.3867644566
Short name T1634
Test name
Test status
Simulation time 2746660518 ps
CPU time 5.78 seconds
Started Jan 03 01:57:28 PM PST 24
Finished Jan 03 01:57:44 PM PST 24
Peak memory 217008 kb
Host smart-f8f30554-c690-4f04-9d7a-caae8567296a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867644566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_rx_timeout.3867644566
Directory /workspace/20.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/20.spi_device_smoke.4146214952
Short name T879
Test name
Test status
Simulation time 58192809 ps
CPU time 1.12 seconds
Started Jan 03 01:57:27 PM PST 24
Finished Jan 03 01:57:39 PM PST 24
Peak memory 208240 kb
Host smart-d0ac2038-6340-4dd4-890b-685b25cb1d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146214952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_smoke.4146214952
Directory /workspace/20.spi_device_smoke/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3607592475
Short name T1271
Test name
Test status
Simulation time 3999653854 ps
CPU time 42.78 seconds
Started Jan 03 01:57:22 PM PST 24
Finished Jan 03 01:58:11 PM PST 24
Peak memory 217388 kb
Host smart-929246c2-5cae-4776-ace8-3e4f8fe089df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607592475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3607592475
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3260113068
Short name T1773
Test name
Test status
Simulation time 2900986241 ps
CPU time 5.37 seconds
Started Jan 03 01:57:26 PM PST 24
Finished Jan 03 01:57:40 PM PST 24
Peak memory 216908 kb
Host smart-70f231bc-5f82-46b6-9ec9-4b32a3181e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260113068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3260113068
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2823238885
Short name T1406
Test name
Test status
Simulation time 130782369 ps
CPU time 1.8 seconds
Started Jan 03 01:57:47 PM PST 24
Finished Jan 03 01:57:52 PM PST 24
Peak memory 216852 kb
Host smart-5b638c81-d8b5-4a27-b616-bd7c45d93136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823238885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2823238885
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2955081349
Short name T1117
Test name
Test status
Simulation time 73558690 ps
CPU time 0.89 seconds
Started Jan 03 01:57:48 PM PST 24
Finished Jan 03 01:57:53 PM PST 24
Peak memory 207032 kb
Host smart-27d57c8f-048a-41c8-83b0-64ce0af6c104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955081349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2955081349
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_tx_async_fifo_reset.2212479084
Short name T1130
Test name
Test status
Simulation time 16663904 ps
CPU time 0.8 seconds
Started Jan 03 01:57:49 PM PST 24
Finished Jan 03 01:57:54 PM PST 24
Peak memory 208504 kb
Host smart-03ec13b2-8a0c-4387-9cf0-8f548bac5497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212479084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tx_async_fifo_reset.2212479084
Directory /workspace/20.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/20.spi_device_txrx.397822465
Short name T1259
Test name
Test status
Simulation time 38189477788 ps
CPU time 955.84 seconds
Started Jan 03 01:57:22 PM PST 24
Finished Jan 03 02:13:24 PM PST 24
Peak memory 268300 kb
Host smart-0847f303-7cd0-47f2-b963-832d8532c099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397822465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_txrx.397822465
Directory /workspace/20.spi_device_txrx/latest

Test location /workspace/coverage/default/20.spi_device_upload.3599732474
Short name T1144
Test name
Test status
Simulation time 2534313501 ps
CPU time 13.15 seconds
Started Jan 03 01:57:47 PM PST 24
Finished Jan 03 01:58:02 PM PST 24
Peak memory 249168 kb
Host smart-665aa76a-4468-44f0-a776-435cc07e3517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599732474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3599732474
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_abort.3626710348
Short name T1295
Test name
Test status
Simulation time 63389442 ps
CPU time 0.71 seconds
Started Jan 03 01:57:48 PM PST 24
Finished Jan 03 01:57:52 PM PST 24
Peak memory 206644 kb
Host smart-7bcf4b23-a01c-4be9-a3aa-2aa9f33a69d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626710348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_abort.3626710348
Directory /workspace/21.spi_device_abort/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.4101559341
Short name T1472
Test name
Test status
Simulation time 14157887 ps
CPU time 0.74 seconds
Started Jan 03 01:58:27 PM PST 24
Finished Jan 03 01:58:31 PM PST 24
Peak memory 206412 kb
Host smart-99368a4e-d8bd-4a55-a50f-c05fbd9e3abc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101559341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
4101559341
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_bit_transfer.715564993
Short name T653
Test name
Test status
Simulation time 205837368 ps
CPU time 2.62 seconds
Started Jan 03 01:57:47 PM PST 24
Finished Jan 03 01:57:54 PM PST 24
Peak memory 216804 kb
Host smart-331fc72a-d06a-403a-823b-f6cd9640bc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715564993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_bit_transfer.715564993
Directory /workspace/21.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/21.spi_device_byte_transfer.4178554663
Short name T510
Test name
Test status
Simulation time 656107971 ps
CPU time 2.19 seconds
Started Jan 03 01:57:46 PM PST 24
Finished Jan 03 01:57:50 PM PST 24
Peak memory 216800 kb
Host smart-c0ba133e-fb65-47f4-90d7-f60a7ae94730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178554663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_byte_transfer.4178554663
Directory /workspace/21.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.4256003150
Short name T1270
Test name
Test status
Simulation time 798314443 ps
CPU time 5.26 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:58:51 PM PST 24
Peak memory 241324 kb
Host smart-e6eadc5a-c74e-4fdc-8bda-02749f5d494a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256003150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.4256003150
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2546995786
Short name T1149
Test name
Test status
Simulation time 16229880 ps
CPU time 0.76 seconds
Started Jan 03 01:57:47 PM PST 24
Finished Jan 03 01:57:50 PM PST 24
Peak memory 206500 kb
Host smart-9c057586-5f33-4a87-ada6-41e2637bc2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546995786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2546995786
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_dummy_item_extra_dly.4270639296
Short name T1170
Test name
Test status
Simulation time 78490855963 ps
CPU time 620.14 seconds
Started Jan 03 01:57:47 PM PST 24
Finished Jan 03 02:08:10 PM PST 24
Peak memory 342816 kb
Host smart-003b75b6-7280-415f-a270-ff8700b60c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270639296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_dummy_item_extra_dly.4270639296
Directory /workspace/21.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/21.spi_device_extreme_fifo_size.1068236456
Short name T48
Test name
Test status
Simulation time 351963654507 ps
CPU time 970.6 seconds
Started Jan 03 01:57:46 PM PST 24
Finished Jan 03 02:13:59 PM PST 24
Peak memory 222116 kb
Host smart-7dd007ca-44e0-4efd-b653-71ee33a182da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068236456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_extreme_fifo_size.1068236456
Directory /workspace/21.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/21.spi_device_fifo_full.607318186
Short name T528
Test name
Test status
Simulation time 125087440190 ps
CPU time 329.84 seconds
Started Jan 03 01:57:46 PM PST 24
Finished Jan 03 02:03:18 PM PST 24
Peak memory 270452 kb
Host smart-60fba3ec-53c7-4f96-b468-65be1894bd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607318186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_fifo_full.607318186
Directory /workspace/21.spi_device_fifo_full/latest

Test location /workspace/coverage/default/21.spi_device_fifo_underflow_overflow.4147499008
Short name T725
Test name
Test status
Simulation time 87616069611 ps
CPU time 490.07 seconds
Started Jan 03 01:57:49 PM PST 24
Finished Jan 03 02:06:05 PM PST 24
Peak memory 377612 kb
Host smart-7db3e609-dcf2-40b5-8214-3183ff342b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147499008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_fifo_underflow_overf
low.4147499008
Directory /workspace/21.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2638183748
Short name T1338
Test name
Test status
Simulation time 96206223853 ps
CPU time 195.86 seconds
Started Jan 03 01:58:16 PM PST 24
Finished Jan 03 02:01:35 PM PST 24
Peak memory 257388 kb
Host smart-32a186f4-7ec3-402b-93d8-432fda2b807b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638183748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2638183748
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2789595355
Short name T727
Test name
Test status
Simulation time 2750131693 ps
CPU time 31.41 seconds
Started Jan 03 01:58:01 PM PST 24
Finished Jan 03 01:58:35 PM PST 24
Peak memory 238884 kb
Host smart-44747f3a-8253-470c-824c-76b844435dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789595355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2789595355
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.731905334
Short name T568
Test name
Test status
Simulation time 13540321917 ps
CPU time 70.61 seconds
Started Jan 03 01:58:29 PM PST 24
Finished Jan 03 01:59:43 PM PST 24
Peak memory 256240 kb
Host smart-8331e983-52fc-4341-86d6-16065d2b1433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731905334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.731905334
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.338838196
Short name T248
Test name
Test status
Simulation time 360905384 ps
CPU time 3.89 seconds
Started Jan 03 01:58:04 PM PST 24
Finished Jan 03 01:58:15 PM PST 24
Peak memory 220780 kb
Host smart-aafea5aa-3fb7-4da5-b77e-63215069aa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338838196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.338838196
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_intr.2878420479
Short name T1009
Test name
Test status
Simulation time 39412654233 ps
CPU time 16.52 seconds
Started Jan 03 01:57:48 PM PST 24
Finished Jan 03 01:58:09 PM PST 24
Peak memory 225172 kb
Host smart-1cf33b36-7753-4a87-b72d-211488b80ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878420479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intr.2878420479
Directory /workspace/21.spi_device_intr/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1898372889
Short name T232
Test name
Test status
Simulation time 13868002606 ps
CPU time 37.27 seconds
Started Jan 03 01:57:48 PM PST 24
Finished Jan 03 01:58:29 PM PST 24
Peak memory 233332 kb
Host smart-305a7977-55fa-4a77-8013-d780f7462b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898372889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1898372889
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.452957062
Short name T1039
Test name
Test status
Simulation time 1690191754 ps
CPU time 8.06 seconds
Started Jan 03 01:57:47 PM PST 24
Finished Jan 03 01:57:58 PM PST 24
Peak memory 243528 kb
Host smart-6532c4f0-fdf3-4464-9707-91e7bff2a3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452957062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.452957062
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3752024777
Short name T1194
Test name
Test status
Simulation time 3771378843 ps
CPU time 14.96 seconds
Started Jan 03 01:57:48 PM PST 24
Finished Jan 03 01:58:07 PM PST 24
Peak memory 219952 kb
Host smart-366f9e70-e4ec-47c4-9f9d-43f0daa14491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752024777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3752024777
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_perf.2986465189
Short name T60
Test name
Test status
Simulation time 16047908304 ps
CPU time 385.86 seconds
Started Jan 03 01:57:51 PM PST 24
Finished Jan 03 02:04:22 PM PST 24
Peak memory 269548 kb
Host smart-6f9fd600-974f-4d22-9860-36d8ca4ceb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986465189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_perf.2986465189
Directory /workspace/21.spi_device_perf/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2227287515
Short name T1636
Test name
Test status
Simulation time 1039796149 ps
CPU time 6.92 seconds
Started Jan 03 01:58:16 PM PST 24
Finished Jan 03 01:58:26 PM PST 24
Peak memory 234112 kb
Host smart-239ebb07-fbe5-4342-835b-0480259f1742
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2227287515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2227287515
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_rx_async_fifo_reset.3875933273
Short name T898
Test name
Test status
Simulation time 57645118 ps
CPU time 0.89 seconds
Started Jan 03 01:57:49 PM PST 24
Finished Jan 03 01:57:54 PM PST 24
Peak memory 208400 kb
Host smart-bbb6ea93-e349-44fa-9e33-0218fb4a7754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875933273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_rx_async_fifo_reset.3875933273
Directory /workspace/21.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/21.spi_device_rx_timeout.56173655
Short name T588
Test name
Test status
Simulation time 1039524693 ps
CPU time 6.87 seconds
Started Jan 03 01:57:45 PM PST 24
Finished Jan 03 01:57:54 PM PST 24
Peak memory 216876 kb
Host smart-196c77b3-9381-4d2c-b832-d3bd84e1b4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56173655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_rx_timeout.56173655
Directory /workspace/21.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/21.spi_device_smoke.651911771
Short name T1204
Test name
Test status
Simulation time 703324707 ps
CPU time 1.24 seconds
Started Jan 03 01:57:46 PM PST 24
Finished Jan 03 01:57:50 PM PST 24
Peak memory 216820 kb
Host smart-6d70fd97-fb97-4e60-8faf-92dab7d438fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651911771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_smoke.651911771
Directory /workspace/21.spi_device_smoke/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3015439503
Short name T1151
Test name
Test status
Simulation time 18720069653 ps
CPU time 33.97 seconds
Started Jan 03 01:57:46 PM PST 24
Finished Jan 03 01:58:22 PM PST 24
Peak memory 217156 kb
Host smart-821c5941-e951-4de2-b22f-88dda41575ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015439503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3015439503
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1181017496
Short name T574
Test name
Test status
Simulation time 8699041652 ps
CPU time 6.66 seconds
Started Jan 03 01:57:51 PM PST 24
Finished Jan 03 01:58:03 PM PST 24
Peak memory 217020 kb
Host smart-b8d0a85c-79f4-4429-aa05-3351ea20db61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181017496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1181017496
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2093266431
Short name T1703
Test name
Test status
Simulation time 95673583 ps
CPU time 1.26 seconds
Started Jan 03 01:57:46 PM PST 24
Finished Jan 03 01:57:50 PM PST 24
Peak memory 208604 kb
Host smart-273e030c-e9d4-4a61-914c-99c4526618c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093266431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2093266431
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1775197969
Short name T651
Test name
Test status
Simulation time 43770398 ps
CPU time 0.77 seconds
Started Jan 03 01:57:49 PM PST 24
Finished Jan 03 01:57:54 PM PST 24
Peak memory 206976 kb
Host smart-35a49325-54ae-428a-915f-6f02626fd8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775197969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1775197969
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_tx_async_fifo_reset.1450815194
Short name T983
Test name
Test status
Simulation time 100733715 ps
CPU time 0.78 seconds
Started Jan 03 01:57:46 PM PST 24
Finished Jan 03 01:57:48 PM PST 24
Peak memory 208508 kb
Host smart-02c66fad-0731-4cc0-b1c8-c7ee2710417d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450815194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tx_async_fifo_reset.1450815194
Directory /workspace/21.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/21.spi_device_txrx.2125485929
Short name T1642
Test name
Test status
Simulation time 68813342333 ps
CPU time 1457.75 seconds
Started Jan 03 01:57:47 PM PST 24
Finished Jan 03 02:22:08 PM PST 24
Peak memory 256140 kb
Host smart-7254e568-a8c1-4941-82b9-8efb8e0f2859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125485929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_txrx.2125485929
Directory /workspace/21.spi_device_txrx/latest

Test location /workspace/coverage/default/21.spi_device_upload.1185677526
Short name T1076
Test name
Test status
Simulation time 3993310502 ps
CPU time 15.65 seconds
Started Jan 03 01:58:04 PM PST 24
Finished Jan 03 01:58:30 PM PST 24
Peak memory 227928 kb
Host smart-0de07cb8-150d-4487-973e-b0c81ec8c1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185677526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1185677526
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_abort.103204616
Short name T584
Test name
Test status
Simulation time 57635560 ps
CPU time 0.75 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 01:58:53 PM PST 24
Peak memory 206600 kb
Host smart-da8ec4c8-836d-4037-a521-b5894df7fd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103204616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_abort.103204616
Directory /workspace/22.spi_device_abort/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.194767909
Short name T1494
Test name
Test status
Simulation time 32520114 ps
CPU time 0.74 seconds
Started Jan 03 01:57:50 PM PST 24
Finished Jan 03 01:57:56 PM PST 24
Peak memory 206520 kb
Host smart-7c021736-ee16-40f8-a10e-c542fed9f2fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194767909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.194767909
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_bit_transfer.4070704333
Short name T628
Test name
Test status
Simulation time 163823903 ps
CPU time 2.63 seconds
Started Jan 03 01:58:40 PM PST 24
Finished Jan 03 01:58:56 PM PST 24
Peak memory 216856 kb
Host smart-d58ba38e-724e-4a7e-982c-0669dfc71281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070704333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_bit_transfer.4070704333
Directory /workspace/22.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/22.spi_device_byte_transfer.3109113191
Short name T1580
Test name
Test status
Simulation time 358907121 ps
CPU time 2.77 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 01:58:55 PM PST 24
Peak memory 216772 kb
Host smart-73b8c864-fc91-4715-befe-4f95f60cf382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109113191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_byte_transfer.3109113191
Directory /workspace/22.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.726227373
Short name T1739
Test name
Test status
Simulation time 82075488 ps
CPU time 2.79 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 01:58:57 PM PST 24
Peak memory 234252 kb
Host smart-18820f66-d2eb-45b9-8325-042310ddd74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726227373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.726227373
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2074488154
Short name T1340
Test name
Test status
Simulation time 45812849 ps
CPU time 0.77 seconds
Started Jan 03 01:58:33 PM PST 24
Finished Jan 03 01:58:39 PM PST 24
Peak memory 207616 kb
Host smart-5f4959ec-189a-4575-b0df-b8a669a94d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074488154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2074488154
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_dummy_item_extra_dly.2124035396
Short name T1079
Test name
Test status
Simulation time 129286667128 ps
CPU time 333.25 seconds
Started Jan 03 01:58:30 PM PST 24
Finished Jan 03 02:04:07 PM PST 24
Peak memory 320132 kb
Host smart-36868e05-c4db-4f55-bead-de6928505063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124035396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_dummy_item_extra_dly.2124035396
Directory /workspace/22.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/22.spi_device_extreme_fifo_size.2794367170
Short name T298
Test name
Test status
Simulation time 292727422990 ps
CPU time 862.74 seconds
Started Jan 03 01:58:25 PM PST 24
Finished Jan 03 02:12:51 PM PST 24
Peak memory 225132 kb
Host smart-f5e1fb25-ba37-409a-a34b-1f9f81cc19db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794367170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_extreme_fifo_size.2794367170
Directory /workspace/22.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/22.spi_device_fifo_full.3894443838
Short name T1630
Test name
Test status
Simulation time 7925903245 ps
CPU time 433.26 seconds
Started Jan 03 01:58:32 PM PST 24
Finished Jan 03 02:05:50 PM PST 24
Peak memory 266920 kb
Host smart-2b0e893e-4f1c-473c-9598-96acdbd5fec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894443838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_fifo_full.3894443838
Directory /workspace/22.spi_device_fifo_full/latest

Test location /workspace/coverage/default/22.spi_device_fifo_underflow_overflow.147314580
Short name T1470
Test name
Test status
Simulation time 229066864268 ps
CPU time 1380.51 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 02:21:45 PM PST 24
Peak memory 694380 kb
Host smart-21bc6564-5af6-47fe-916c-d7ecbb57b25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147314580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_fifo_underflow_overfl
ow.147314580
Directory /workspace/22.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.490857649
Short name T1365
Test name
Test status
Simulation time 1557173367 ps
CPU time 24.84 seconds
Started Jan 03 01:58:43 PM PST 24
Finished Jan 03 01:59:21 PM PST 24
Peak memory 241564 kb
Host smart-995bb997-b01c-46ac-b185-dc262cc2a446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490857649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.490857649
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.653583943
Short name T297
Test name
Test status
Simulation time 10719991643 ps
CPU time 110.39 seconds
Started Jan 03 01:57:51 PM PST 24
Finished Jan 03 01:59:47 PM PST 24
Peak memory 252408 kb
Host smart-576055a5-0b72-4f26-9108-1428910001fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653583943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.653583943
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2338187605
Short name T366
Test name
Test status
Simulation time 3101168988 ps
CPU time 15.97 seconds
Started Jan 03 01:57:47 PM PST 24
Finished Jan 03 01:58:07 PM PST 24
Peak memory 225200 kb
Host smart-c72dec2a-75c1-49e5-9d9f-63c5f1c93cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338187605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2338187605
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1469317684
Short name T1471
Test name
Test status
Simulation time 1282678215 ps
CPU time 9.29 seconds
Started Jan 03 01:58:45 PM PST 24
Finished Jan 03 01:59:07 PM PST 24
Peak memory 232904 kb
Host smart-c357d3a3-ca8c-43bd-b18c-1603955498d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469317684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1469317684
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.4164806477
Short name T258
Test name
Test status
Simulation time 133548770 ps
CPU time 4.61 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 01:58:59 PM PST 24
Peak memory 237956 kb
Host smart-c41c6a34-5ffe-4525-a9e1-8d220131ca91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164806477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.4164806477
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_intr.308685687
Short name T797
Test name
Test status
Simulation time 38672424064 ps
CPU time 145.05 seconds
Started Jan 03 01:58:31 PM PST 24
Finished Jan 03 02:01:00 PM PST 24
Peak memory 240660 kb
Host smart-af4b2049-7c78-43f4-9181-271218b2f556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308685687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intr.308685687
Directory /workspace/22.spi_device_intr/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.717820480
Short name T1239
Test name
Test status
Simulation time 534617286 ps
CPU time 10.1 seconds
Started Jan 03 01:58:40 PM PST 24
Finished Jan 03 01:59:03 PM PST 24
Peak memory 232192 kb
Host smart-2a033032-e5ed-448b-b8dc-81f8b6348aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717820480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.717820480
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2699531343
Short name T1502
Test name
Test status
Simulation time 3921689532 ps
CPU time 6.03 seconds
Started Jan 03 01:58:40 PM PST 24
Finished Jan 03 01:58:58 PM PST 24
Peak memory 225188 kb
Host smart-7bad6d43-bd54-42bf-b572-e37cb9d95071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699531343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2699531343
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1003447155
Short name T1489
Test name
Test status
Simulation time 10259990505 ps
CPU time 6.66 seconds
Started Jan 03 01:58:42 PM PST 24
Finished Jan 03 01:59:02 PM PST 24
Peak memory 219456 kb
Host smart-7b78c44f-9970-41d7-89e1-c3bac3218b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003447155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1003447155
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_perf.1750739395
Short name T1437
Test name
Test status
Simulation time 46295860434 ps
CPU time 136.19 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 02:01:04 PM PST 24
Peak memory 258020 kb
Host smart-b51fadfa-2ed0-44bc-a484-02aae0e8beec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750739395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_perf.1750739395
Directory /workspace/22.spi_device_perf/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1062347392
Short name T1736
Test name
Test status
Simulation time 1460314231 ps
CPU time 3.4 seconds
Started Jan 03 01:58:08 PM PST 24
Finished Jan 03 01:58:18 PM PST 24
Peak memory 220192 kb
Host smart-919b5337-1c19-4b65-bd0c-b206592bb6a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1062347392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1062347392
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_rx_async_fifo_reset.1073500694
Short name T984
Test name
Test status
Simulation time 69503204 ps
CPU time 0.89 seconds
Started Jan 03 01:58:35 PM PST 24
Finished Jan 03 01:58:42 PM PST 24
Peak memory 208608 kb
Host smart-866936dc-9be9-4928-8f75-4cf76b4fcc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073500694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_rx_async_fifo_reset.1073500694
Directory /workspace/22.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/22.spi_device_rx_timeout.3580731956
Short name T703
Test name
Test status
Simulation time 864162542 ps
CPU time 4.49 seconds
Started Jan 03 01:58:40 PM PST 24
Finished Jan 03 01:58:57 PM PST 24
Peak memory 216856 kb
Host smart-e4d66d81-0f02-4cf9-a034-85a79c4cbc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580731956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_rx_timeout.3580731956
Directory /workspace/22.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/22.spi_device_smoke.2957440064
Short name T224
Test name
Test status
Simulation time 97285160 ps
CPU time 1.05 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:58:46 PM PST 24
Peak memory 208188 kb
Host smart-9f380dd1-5efa-414b-b70f-be7440b19f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957440064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_smoke.2957440064
Directory /workspace/22.spi_device_smoke/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.4152341072
Short name T794
Test name
Test status
Simulation time 403376067377 ps
CPU time 2580.57 seconds
Started Jan 03 01:57:47 PM PST 24
Finished Jan 03 02:40:50 PM PST 24
Peak memory 393312 kb
Host smart-3f013c27-8340-4888-8470-2ed3983c0d3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152341072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.4152341072
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2508723451
Short name T1597
Test name
Test status
Simulation time 4113124569 ps
CPU time 40.58 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 01:59:31 PM PST 24
Peak memory 217228 kb
Host smart-8c0697b9-1ba3-472a-bd11-b28980be6ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508723451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2508723451
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.990000700
Short name T891
Test name
Test status
Simulation time 109962171088 ps
CPU time 27.9 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 01:59:19 PM PST 24
Peak memory 216920 kb
Host smart-30d7ae74-fa19-4a83-9c73-b07ae53a233b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990000700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.990000700
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3726985266
Short name T871
Test name
Test status
Simulation time 318159159 ps
CPU time 0.93 seconds
Started Jan 03 01:58:46 PM PST 24
Finished Jan 03 01:59:01 PM PST 24
Peak memory 207900 kb
Host smart-d0851f1e-bf1f-46a1-8fad-b37018f7ba0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726985266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3726985266
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3293107061
Short name T1776
Test name
Test status
Simulation time 16182009 ps
CPU time 0.78 seconds
Started Jan 03 01:58:40 PM PST 24
Finished Jan 03 01:58:53 PM PST 24
Peak memory 206928 kb
Host smart-38a072bd-aa0c-44c1-8a29-3cd6e17aaec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293107061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3293107061
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_tx_async_fifo_reset.4150005246
Short name T85
Test name
Test status
Simulation time 18796350 ps
CPU time 0.79 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 01:58:53 PM PST 24
Peak memory 208452 kb
Host smart-4cd7335d-4f85-4c0c-b7af-cabfb7faebca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150005246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tx_async_fifo_reset.4150005246
Directory /workspace/22.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/22.spi_device_txrx.3257894814
Short name T783
Test name
Test status
Simulation time 111384611418 ps
CPU time 345.84 seconds
Started Jan 03 01:58:35 PM PST 24
Finished Jan 03 02:04:27 PM PST 24
Peak memory 268432 kb
Host smart-d4a2252b-83e0-4fc3-aa07-97a47285356e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257894814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_txrx.3257894814
Directory /workspace/22.spi_device_txrx/latest

Test location /workspace/coverage/default/22.spi_device_upload.659425862
Short name T1324
Test name
Test status
Simulation time 36118429138 ps
CPU time 35.35 seconds
Started Jan 03 01:58:42 PM PST 24
Finished Jan 03 01:59:30 PM PST 24
Peak memory 220520 kb
Host smart-bc6561fe-2aeb-498b-93dd-1faecf9207f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659425862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.659425862
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_abort.3736485518
Short name T1603
Test name
Test status
Simulation time 37881242 ps
CPU time 0.73 seconds
Started Jan 03 01:58:30 PM PST 24
Finished Jan 03 01:58:35 PM PST 24
Peak memory 206644 kb
Host smart-9783853e-35a1-45c1-b124-60e8728c283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736485518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_abort.3736485518
Directory /workspace/23.spi_device_abort/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3569532565
Short name T1162
Test name
Test status
Simulation time 12430851 ps
CPU time 0.72 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:58:44 PM PST 24
Peak memory 206532 kb
Host smart-1f10a7d8-37e5-4194-ba28-d205accf3dc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569532565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3569532565
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_bit_transfer.1907610989
Short name T919
Test name
Test status
Simulation time 700776640 ps
CPU time 3.2 seconds
Started Jan 03 01:58:07 PM PST 24
Finished Jan 03 01:58:17 PM PST 24
Peak memory 216748 kb
Host smart-55799a59-aa97-43eb-9ab3-58fc09a51c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907610989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_bit_transfer.1907610989
Directory /workspace/23.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/23.spi_device_byte_transfer.2942775898
Short name T701
Test name
Test status
Simulation time 63665968 ps
CPU time 2.36 seconds
Started Jan 03 01:58:05 PM PST 24
Finished Jan 03 01:58:16 PM PST 24
Peak memory 216844 kb
Host smart-9c3b5213-5e29-4fe9-b6bf-af977df48ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942775898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_byte_transfer.2942775898
Directory /workspace/23.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.671459590
Short name T64
Test name
Test status
Simulation time 1508024157 ps
CPU time 6.32 seconds
Started Jan 03 01:58:40 PM PST 24
Finished Jan 03 01:58:59 PM PST 24
Peak memory 221520 kb
Host smart-b0b0b5e4-de66-4bc4-a36d-d1f56c1d16fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671459590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.671459590
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3095975423
Short name T1369
Test name
Test status
Simulation time 51730661 ps
CPU time 0.76 seconds
Started Jan 03 01:57:47 PM PST 24
Finished Jan 03 01:57:51 PM PST 24
Peak memory 207540 kb
Host smart-df9995b3-4cde-467f-80bb-12eeb7bd3361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095975423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3095975423
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_dummy_item_extra_dly.2908569040
Short name T589
Test name
Test status
Simulation time 437006862565 ps
CPU time 473.26 seconds
Started Jan 03 01:57:48 PM PST 24
Finished Jan 03 02:05:44 PM PST 24
Peak memory 294016 kb
Host smart-5d2c0bac-5ce9-446a-8e94-8b1b5402a319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908569040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_dummy_item_extra_dly.2908569040
Directory /workspace/23.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/23.spi_device_extreme_fifo_size.216743215
Short name T622
Test name
Test status
Simulation time 2997194783 ps
CPU time 52.4 seconds
Started Jan 03 01:57:51 PM PST 24
Finished Jan 03 01:58:49 PM PST 24
Peak memory 240784 kb
Host smart-c7a8ff88-2fc6-4a35-85b4-94cc069a7ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216743215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_extreme_fifo_size.216743215
Directory /workspace/23.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/23.spi_device_fifo_full.1281561147
Short name T1667
Test name
Test status
Simulation time 408952888934 ps
CPU time 849.86 seconds
Started Jan 03 01:57:47 PM PST 24
Finished Jan 03 02:11:59 PM PST 24
Peak memory 252892 kb
Host smart-6a10932d-ec6d-482d-a83b-e2d31989459b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281561147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_fifo_full.1281561147
Directory /workspace/23.spi_device_fifo_full/latest

Test location /workspace/coverage/default/23.spi_device_fifo_underflow_overflow.3513316086
Short name T726
Test name
Test status
Simulation time 28641314225 ps
CPU time 321.4 seconds
Started Jan 03 01:57:52 PM PST 24
Finished Jan 03 02:03:18 PM PST 24
Peak memory 433876 kb
Host smart-fd8c2d9d-54d8-45a0-a81a-811c5a683a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513316086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_fifo_underflow_overf
low.3513316086
Directory /workspace/23.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2758933663
Short name T1723
Test name
Test status
Simulation time 11455173665 ps
CPU time 78.98 seconds
Started Jan 03 01:58:38 PM PST 24
Finished Jan 03 02:00:08 PM PST 24
Peak memory 257664 kb
Host smart-ea133b19-3e17-404e-8480-f438b164324d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758933663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2758933663
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2779855829
Short name T696
Test name
Test status
Simulation time 8059690233 ps
CPU time 88.4 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 02:00:17 PM PST 24
Peak memory 268224 kb
Host smart-900818d6-9ffa-40ba-bf39-d7c95240fe98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779855829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2779855829
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3159074602
Short name T1570
Test name
Test status
Simulation time 1263095493 ps
CPU time 7.12 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:58:50 PM PST 24
Peak memory 234488 kb
Host smart-af18a00d-2960-491b-9c92-b5e6bf313354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159074602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3159074602
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.4103249356
Short name T236
Test name
Test status
Simulation time 244652041 ps
CPU time 3.99 seconds
Started Jan 03 01:58:25 PM PST 24
Finished Jan 03 01:58:32 PM PST 24
Peak memory 219116 kb
Host smart-c855bf85-7241-4f8b-80df-f13c5c0aa723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103249356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.4103249356
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_intr.819192811
Short name T118
Test name
Test status
Simulation time 12960626042 ps
CPU time 24.81 seconds
Started Jan 03 01:57:50 PM PST 24
Finished Jan 03 01:58:20 PM PST 24
Peak memory 218364 kb
Host smart-64f47c4e-ff14-42ef-9304-63abf9613680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819192811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intr.819192811
Directory /workspace/23.spi_device_intr/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2811853202
Short name T1081
Test name
Test status
Simulation time 3718388399 ps
CPU time 5.7 seconds
Started Jan 03 01:58:30 PM PST 24
Finished Jan 03 01:58:39 PM PST 24
Peak memory 218760 kb
Host smart-1f8d7183-1f49-4a1c-a984-a22cf0a9db7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811853202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2811853202
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3131275329
Short name T1440
Test name
Test status
Simulation time 154158545 ps
CPU time 2.69 seconds
Started Jan 03 01:58:30 PM PST 24
Finished Jan 03 01:58:37 PM PST 24
Peak memory 218700 kb
Host smart-608cb85a-ce9b-404b-bb92-adc5ab3411f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131275329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3131275329
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_perf.3856565694
Short name T768
Test name
Test status
Simulation time 9669276686 ps
CPU time 656.51 seconds
Started Jan 03 01:58:06 PM PST 24
Finished Jan 03 02:09:11 PM PST 24
Peak memory 274252 kb
Host smart-d65d118e-c4ec-43c2-84bb-364a6056522c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856565694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_perf.3856565694
Directory /workspace/23.spi_device_perf/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3801478730
Short name T813
Test name
Test status
Simulation time 5012068710 ps
CPU time 6.03 seconds
Started Jan 03 01:58:34 PM PST 24
Finished Jan 03 01:58:44 PM PST 24
Peak memory 219084 kb
Host smart-a55e633b-1c36-4203-b362-4060663a4668
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3801478730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3801478730
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_rx_async_fifo_reset.2585679269
Short name T561
Test name
Test status
Simulation time 22031513 ps
CPU time 0.88 seconds
Started Jan 03 01:58:32 PM PST 24
Finished Jan 03 01:58:37 PM PST 24
Peak memory 208508 kb
Host smart-84e6f1e4-e294-4316-9808-e62df79ab645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585679269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_rx_async_fifo_reset.2585679269
Directory /workspace/23.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/23.spi_device_rx_timeout.1654019757
Short name T1146
Test name
Test status
Simulation time 7499466648 ps
CPU time 6.7 seconds
Started Jan 03 01:58:08 PM PST 24
Finished Jan 03 01:58:21 PM PST 24
Peak memory 216964 kb
Host smart-d5099ac0-911e-44ed-bc1d-0c28b9b99992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654019757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_rx_timeout.1654019757
Directory /workspace/23.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/23.spi_device_smoke.3206281020
Short name T1523
Test name
Test status
Simulation time 41496842 ps
CPU time 0.96 seconds
Started Jan 03 01:57:44 PM PST 24
Finished Jan 03 01:57:46 PM PST 24
Peak memory 207996 kb
Host smart-de5fbd37-4227-4c64-83be-884a5bcfd548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206281020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_smoke.3206281020
Directory /workspace/23.spi_device_smoke/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2449755092
Short name T1197
Test name
Test status
Simulation time 98789956796 ps
CPU time 1241.13 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 02:19:27 PM PST 24
Peak memory 328776 kb
Host smart-5875c84f-bf6e-4e4f-81c6-44e339ca6f43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449755092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2449755092
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1353189806
Short name T1576
Test name
Test status
Simulation time 1523652169 ps
CPU time 14.45 seconds
Started Jan 03 01:58:30 PM PST 24
Finished Jan 03 01:58:48 PM PST 24
Peak memory 216772 kb
Host smart-19d9f4d9-ce32-4188-99d0-0704bb717093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353189806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1353189806
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3484099826
Short name T1018
Test name
Test status
Simulation time 206425985 ps
CPU time 1.85 seconds
Started Jan 03 01:58:08 PM PST 24
Finished Jan 03 01:58:16 PM PST 24
Peak memory 208272 kb
Host smart-6dcd06be-eda9-447e-a1ec-b92f7acc4b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484099826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3484099826
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.4131853011
Short name T1589
Test name
Test status
Simulation time 26083043 ps
CPU time 0.98 seconds
Started Jan 03 01:58:28 PM PST 24
Finished Jan 03 01:58:31 PM PST 24
Peak memory 208304 kb
Host smart-676e604b-3199-4336-80cc-7b5114496454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131853011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.4131853011
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.565771209
Short name T31
Test name
Test status
Simulation time 218248807 ps
CPU time 1.06 seconds
Started Jan 03 01:58:02 PM PST 24
Finished Jan 03 01:58:05 PM PST 24
Peak memory 207944 kb
Host smart-b127313a-3d3a-4fcd-a54c-cd848a988cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565771209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.565771209
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_tx_async_fifo_reset.99503430
Short name T596
Test name
Test status
Simulation time 47648500 ps
CPU time 0.81 seconds
Started Jan 03 01:58:04 PM PST 24
Finished Jan 03 01:58:12 PM PST 24
Peak memory 208384 kb
Host smart-593e0a1a-c995-4849-94ce-9f45331579cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99503430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tx_async_fifo_reset.99503430
Directory /workspace/23.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/23.spi_device_txrx.1110807384
Short name T548
Test name
Test status
Simulation time 24907216407 ps
CPU time 429.62 seconds
Started Jan 03 01:57:48 PM PST 24
Finished Jan 03 02:05:02 PM PST 24
Peak memory 271288 kb
Host smart-94ad6eb7-738e-48e3-b254-a803ffef8e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110807384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_txrx.1110807384
Directory /workspace/23.spi_device_txrx/latest

Test location /workspace/coverage/default/23.spi_device_upload.2255549633
Short name T332
Test name
Test status
Simulation time 5726829806 ps
CPU time 11.89 seconds
Started Jan 03 01:58:35 PM PST 24
Finished Jan 03 01:58:52 PM PST 24
Peak memory 239312 kb
Host smart-96a88ecb-1cf2-47cf-aa71-bdb045a176c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255549633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2255549633
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_abort.2440346237
Short name T1118
Test name
Test status
Simulation time 55285959 ps
CPU time 0.74 seconds
Started Jan 03 01:57:48 PM PST 24
Finished Jan 03 01:57:52 PM PST 24
Peak memory 206608 kb
Host smart-943b3643-5a07-48c3-81af-bc0c490f4a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440346237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_abort.2440346237
Directory /workspace/24.spi_device_abort/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1376074271
Short name T1362
Test name
Test status
Simulation time 14723371 ps
CPU time 0.71 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:58:46 PM PST 24
Peak memory 206508 kb
Host smart-eae0d9ca-91e0-4137-9548-0eafc53fd6ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376074271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1376074271
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_bit_transfer.1417729217
Short name T786
Test name
Test status
Simulation time 122608236 ps
CPU time 2.65 seconds
Started Jan 03 01:57:50 PM PST 24
Finished Jan 03 01:57:58 PM PST 24
Peak memory 216804 kb
Host smart-4d189031-6d3d-4f37-9e36-a1a62ac79331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417729217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_bit_transfer.1417729217
Directory /workspace/24.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/24.spi_device_byte_transfer.1291968955
Short name T1515
Test name
Test status
Simulation time 140626642 ps
CPU time 2.62 seconds
Started Jan 03 01:58:40 PM PST 24
Finished Jan 03 01:58:56 PM PST 24
Peak memory 216848 kb
Host smart-b828e8ce-8f5a-4d77-907d-9f34f443bcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291968955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_byte_transfer.1291968955
Directory /workspace/24.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.748217476
Short name T1439
Test name
Test status
Simulation time 134857245 ps
CPU time 3.11 seconds
Started Jan 03 01:58:34 PM PST 24
Finished Jan 03 01:58:41 PM PST 24
Peak memory 218552 kb
Host smart-1f89ef9e-584d-45f8-9404-75f64f32b8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748217476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.748217476
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3118426861
Short name T868
Test name
Test status
Simulation time 45082202 ps
CPU time 0.76 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 01:58:54 PM PST 24
Peak memory 207528 kb
Host smart-dc5eefc8-dd4f-407c-bd82-048847634974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118426861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3118426861
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_dummy_item_extra_dly.1356990677
Short name T1464
Test name
Test status
Simulation time 163039994241 ps
CPU time 542.35 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 02:07:54 PM PST 24
Peak memory 282956 kb
Host smart-6b214e95-00a0-4e91-8bdd-5984829cc274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356990677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_dummy_item_extra_dly.1356990677
Directory /workspace/24.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/24.spi_device_extreme_fifo_size.4292903091
Short name T937
Test name
Test status
Simulation time 425489998570 ps
CPU time 1737.1 seconds
Started Jan 03 01:58:40 PM PST 24
Finished Jan 03 02:27:50 PM PST 24
Peak memory 217896 kb
Host smart-f17c2685-0767-4bfa-8bb1-e65b25044e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292903091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_extreme_fifo_size.4292903091
Directory /workspace/24.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/24.spi_device_fifo_full.3525990040
Short name T878
Test name
Test status
Simulation time 419556132770 ps
CPU time 1928.39 seconds
Started Jan 03 01:58:38 PM PST 24
Finished Jan 03 02:30:59 PM PST 24
Peak memory 261848 kb
Host smart-1b1a5e6c-4158-4787-8d62-78cfebab0584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525990040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_fifo_full.3525990040
Directory /workspace/24.spi_device_fifo_full/latest

Test location /workspace/coverage/default/24.spi_device_fifo_underflow_overflow.1407463438
Short name T626
Test name
Test status
Simulation time 107465178652 ps
CPU time 166.79 seconds
Started Jan 03 01:58:42 PM PST 24
Finished Jan 03 02:01:42 PM PST 24
Peak memory 338076 kb
Host smart-018e4f97-d5dc-4653-83c3-75eb306f3fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407463438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_fifo_underflow_overf
low.1407463438
Directory /workspace/24.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3555883898
Short name T1084
Test name
Test status
Simulation time 353616069 ps
CPU time 3.92 seconds
Started Jan 03 01:58:32 PM PST 24
Finished Jan 03 01:58:40 PM PST 24
Peak memory 236672 kb
Host smart-939735a4-8362-4f3f-ae5b-26205bb08d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555883898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3555883898
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2666137304
Short name T68
Test name
Test status
Simulation time 9793752556 ps
CPU time 108.44 seconds
Started Jan 03 01:58:26 PM PST 24
Finished Jan 03 02:00:18 PM PST 24
Peak memory 274496 kb
Host smart-3ca8d111-157f-4619-92e7-033bf108a915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666137304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2666137304
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2858940502
Short name T1670
Test name
Test status
Simulation time 6103579545 ps
CPU time 71.91 seconds
Started Jan 03 01:58:30 PM PST 24
Finished Jan 03 01:59:46 PM PST 24
Peak memory 233420 kb
Host smart-a70de843-10d1-434a-84e6-ea586199a728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858940502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2858940502
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1033920123
Short name T1323
Test name
Test status
Simulation time 5345080317 ps
CPU time 6.64 seconds
Started Jan 03 01:57:47 PM PST 24
Finished Jan 03 01:57:57 PM PST 24
Peak memory 238676 kb
Host smart-ac6e9cab-97a8-4a91-b2a9-3387cc13d191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033920123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1033920123
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_intr.3797602565
Short name T686
Test name
Test status
Simulation time 7933609262 ps
CPU time 48.22 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 01:59:40 PM PST 24
Peak memory 232320 kb
Host smart-4d4c2443-5df9-44c8-9677-4eb682cc6c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797602565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intr.3797602565
Directory /workspace/24.spi_device_intr/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2400254824
Short name T1025
Test name
Test status
Simulation time 1067560504 ps
CPU time 9.13 seconds
Started Jan 03 01:57:50 PM PST 24
Finished Jan 03 01:58:05 PM PST 24
Peak memory 229680 kb
Host smart-7d49b834-cce8-4971-8a77-7c11afd51ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400254824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2400254824
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3455541917
Short name T337
Test name
Test status
Simulation time 1317653930 ps
CPU time 6.91 seconds
Started Jan 03 01:57:45 PM PST 24
Finished Jan 03 01:57:54 PM PST 24
Peak memory 238208 kb
Host smart-c00b47cd-1461-4db7-b932-215120d1cdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455541917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3455541917
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1925300774
Short name T1047
Test name
Test status
Simulation time 675705127 ps
CPU time 4.87 seconds
Started Jan 03 01:57:48 PM PST 24
Finished Jan 03 01:57:57 PM PST 24
Peak memory 237020 kb
Host smart-c5194ade-9983-4ecd-87a0-51bab30e78d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925300774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1925300774
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_perf.2135212510
Short name T520
Test name
Test status
Simulation time 185464025026 ps
CPU time 1080.53 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 02:16:53 PM PST 24
Peak memory 257056 kb
Host smart-43126582-b9e0-4881-9324-454562b84ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135212510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_perf.2135212510
Directory /workspace/24.spi_device_perf/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3361927681
Short name T905
Test name
Test status
Simulation time 6711284350 ps
CPU time 7.49 seconds
Started Jan 03 01:58:34 PM PST 24
Finished Jan 03 01:58:46 PM PST 24
Peak memory 234348 kb
Host smart-e278a67b-f445-4de0-8dbf-d92f4cd0f6b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3361927681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3361927681
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_rx_timeout.3094770993
Short name T1320
Test name
Test status
Simulation time 550275962 ps
CPU time 4.68 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 01:58:57 PM PST 24
Peak memory 216800 kb
Host smart-24d30a45-ee75-46e4-b524-bfdc88135f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094770993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_rx_timeout.3094770993
Directory /workspace/24.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/24.spi_device_smoke.4199739867
Short name T516
Test name
Test status
Simulation time 90694420 ps
CPU time 1.07 seconds
Started Jan 03 01:58:35 PM PST 24
Finished Jan 03 01:58:41 PM PST 24
Peak memory 216576 kb
Host smart-b38ec854-c760-43d2-997b-9fc59376684e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199739867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_smoke.4199739867
Directory /workspace/24.spi_device_smoke/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.336561233
Short name T1286
Test name
Test status
Simulation time 77913149707 ps
CPU time 869.02 seconds
Started Jan 03 01:58:35 PM PST 24
Finished Jan 03 02:13:11 PM PST 24
Peak memory 431160 kb
Host smart-1a3a2fe2-f80e-47a2-b69d-d3fcefa8e4b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336561233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.336561233
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1260434348
Short name T995
Test name
Test status
Simulation time 1042047525 ps
CPU time 8.34 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 01:59:03 PM PST 24
Peak memory 219964 kb
Host smart-1238525e-db76-4681-9b43-eea32800928d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260434348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1260434348
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2931710651
Short name T852
Test name
Test status
Simulation time 21676927700 ps
CPU time 19.32 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 01:59:11 PM PST 24
Peak memory 217208 kb
Host smart-13feb66d-fdfe-4f24-bde7-03f8798281dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931710651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2931710651
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3030269682
Short name T747
Test name
Test status
Simulation time 707749263 ps
CPU time 1.12 seconds
Started Jan 03 01:57:51 PM PST 24
Finished Jan 03 01:57:57 PM PST 24
Peak memory 208128 kb
Host smart-dcf0e50a-051f-481d-ae9b-cadc4be9b936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030269682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3030269682
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3789081734
Short name T1285
Test name
Test status
Simulation time 82274604 ps
CPU time 0.93 seconds
Started Jan 03 01:57:49 PM PST 24
Finished Jan 03 01:57:54 PM PST 24
Peak memory 206976 kb
Host smart-e37a7ead-c416-48b1-99d0-3f63073eebd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789081734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3789081734
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_tx_async_fifo_reset.269895271
Short name T865
Test name
Test status
Simulation time 51137824 ps
CPU time 0.76 seconds
Started Jan 03 01:57:45 PM PST 24
Finished Jan 03 01:57:48 PM PST 24
Peak memory 208460 kb
Host smart-f40c4814-8ec8-4b8f-899d-93a6f3c4b2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269895271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tx_async_fifo_reset.269895271
Directory /workspace/24.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/24.spi_device_txrx.3350903361
Short name T1774
Test name
Test status
Simulation time 145841877725 ps
CPU time 270.19 seconds
Started Jan 03 01:58:40 PM PST 24
Finished Jan 03 02:03:23 PM PST 24
Peak memory 241332 kb
Host smart-fd6d91ff-ea3e-4804-b6dd-25515f93c90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350903361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_txrx.3350903361
Directory /workspace/24.spi_device_txrx/latest

Test location /workspace/coverage/default/24.spi_device_upload.1012805581
Short name T1226
Test name
Test status
Simulation time 77765709810 ps
CPU time 71.73 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 01:59:59 PM PST 24
Peak memory 243052 kb
Host smart-fdadfd0a-b621-4ecf-81ab-901b8fe566f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012805581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1012805581
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_abort.992832573
Short name T62
Test name
Test status
Simulation time 15640766 ps
CPU time 0.75 seconds
Started Jan 03 01:58:43 PM PST 24
Finished Jan 03 01:58:58 PM PST 24
Peak memory 206648 kb
Host smart-8a236eb1-8392-4890-beef-a795ddd5de22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992832573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_abort.992832573
Directory /workspace/25.spi_device_abort/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.56898030
Short name T1062
Test name
Test status
Simulation time 53986545 ps
CPU time 0.74 seconds
Started Jan 03 01:58:45 PM PST 24
Finished Jan 03 01:58:59 PM PST 24
Peak memory 206512 kb
Host smart-2d714728-e38f-4f55-bc2d-70bffdc9a9d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56898030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.56898030
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_bit_transfer.187496722
Short name T1654
Test name
Test status
Simulation time 784101008 ps
CPU time 1.98 seconds
Started Jan 03 01:58:38 PM PST 24
Finished Jan 03 01:58:52 PM PST 24
Peak memory 216760 kb
Host smart-67352ffe-10a9-4459-adcd-46d830022efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187496722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_bit_transfer.187496722
Directory /workspace/25.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/25.spi_device_byte_transfer.1666423829
Short name T966
Test name
Test status
Simulation time 228844889 ps
CPU time 3.33 seconds
Started Jan 03 01:58:42 PM PST 24
Finished Jan 03 01:58:58 PM PST 24
Peak memory 216808 kb
Host smart-a2028d70-9161-4cd1-863a-3e179b0dae8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666423829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_byte_transfer.1666423829
Directory /workspace/25.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3592873073
Short name T924
Test name
Test status
Simulation time 5375743216 ps
CPU time 9.28 seconds
Started Jan 03 01:58:44 PM PST 24
Finished Jan 03 01:59:07 PM PST 24
Peak memory 221556 kb
Host smart-28da8615-ea5e-4764-b5e6-d05ddbea1b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592873073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3592873073
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.828521155
Short name T680
Test name
Test status
Simulation time 61623103 ps
CPU time 0.81 seconds
Started Jan 03 01:58:40 PM PST 24
Finished Jan 03 01:58:54 PM PST 24
Peak memory 207592 kb
Host smart-7910693a-7493-4308-a7f4-8925728347cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828521155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.828521155
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_dummy_item_extra_dly.945241156
Short name T1029
Test name
Test status
Simulation time 38873662648 ps
CPU time 295.79 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 02:03:48 PM PST 24
Peak memory 272964 kb
Host smart-8e93934d-c553-4648-9a16-e73f1c89acec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945241156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_dummy_item_extra_dly.945241156
Directory /workspace/25.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/25.spi_device_extreme_fifo_size.115451345
Short name T1093
Test name
Test status
Simulation time 136778324612 ps
CPU time 969.02 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 02:15:04 PM PST 24
Peak memory 220664 kb
Host smart-d15797e6-15aa-46eb-b50a-751938424536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115451345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_extreme_fifo_size.115451345
Directory /workspace/25.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/25.spi_device_fifo_full.1335101623
Short name T746
Test name
Test status
Simulation time 131674832867 ps
CPU time 823.88 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 02:12:30 PM PST 24
Peak memory 301584 kb
Host smart-2fe85ce6-5e73-469b-9fd8-c51ad17fad83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335101623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_fifo_full.1335101623
Directory /workspace/25.spi_device_fifo_full/latest

Test location /workspace/coverage/default/25.spi_device_fifo_underflow_overflow.1795387566
Short name T1528
Test name
Test status
Simulation time 35168812390 ps
CPU time 548.67 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 02:08:00 PM PST 24
Peak memory 444384 kb
Host smart-fdbb0d0f-4005-496e-9835-ace8527b092c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795387566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_fifo_underflow_overf
low.1795387566
Directory /workspace/25.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.288183082
Short name T1717
Test name
Test status
Simulation time 66326204135 ps
CPU time 150.74 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 02:01:18 PM PST 24
Peak memory 250204 kb
Host smart-6a53991c-6c09-40a7-906c-253ed9f99cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288183082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.288183082
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1753944804
Short name T314
Test name
Test status
Simulation time 12559187944 ps
CPU time 122.85 seconds
Started Jan 03 01:58:45 PM PST 24
Finished Jan 03 02:01:02 PM PST 24
Peak memory 257232 kb
Host smart-1bb7980d-f271-4944-845b-f7e518af1343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753944804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1753944804
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3196098225
Short name T189
Test name
Test status
Simulation time 1896884508 ps
CPU time 10.73 seconds
Started Jan 03 01:58:44 PM PST 24
Finished Jan 03 01:59:08 PM PST 24
Peak memory 240128 kb
Host smart-a021e679-57c9-4c1c-869e-cafabaa30475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196098225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3196098225
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.363588146
Short name T1167
Test name
Test status
Simulation time 206106510 ps
CPU time 3.45 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 01:58:58 PM PST 24
Peak memory 218268 kb
Host smart-fc08055a-5878-4869-8f8d-49674b094ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363588146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.363588146
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_intr.948064623
Short name T202
Test name
Test status
Simulation time 77872689067 ps
CPU time 74.39 seconds
Started Jan 03 01:58:40 PM PST 24
Finished Jan 03 02:00:07 PM PST 24
Peak memory 233480 kb
Host smart-df08b7b9-26ec-41a1-b466-665e1c950cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948064623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intr.948064623
Directory /workspace/25.spi_device_intr/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3134298946
Short name T260
Test name
Test status
Simulation time 28258267620 ps
CPU time 28.7 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:59:13 PM PST 24
Peak memory 231480 kb
Host smart-ce0fda31-4413-42f8-bb3a-b9660741969d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134298946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3134298946
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2434362172
Short name T1467
Test name
Test status
Simulation time 10242113292 ps
CPU time 13.89 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 01:59:06 PM PST 24
Peak memory 238684 kb
Host smart-06d750ac-f9f7-4479-bdc4-7d108a484dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434362172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2434362172
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2164665061
Short name T1386
Test name
Test status
Simulation time 426051695 ps
CPU time 5.35 seconds
Started Jan 03 01:58:43 PM PST 24
Finished Jan 03 01:59:02 PM PST 24
Peak memory 241040 kb
Host smart-8dd7c99d-cc23-4b96-99e1-bf01c0505bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164665061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2164665061
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_perf.3319939565
Short name T560
Test name
Test status
Simulation time 19980818514 ps
CPU time 539.92 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 02:07:45 PM PST 24
Peak memory 267288 kb
Host smart-f445fbab-e467-4a49-b3db-1e121ab9643e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319939565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_perf.3319939565
Directory /workspace/25.spi_device_perf/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3466345676
Short name T1199
Test name
Test status
Simulation time 3626513765 ps
CPU time 7.44 seconds
Started Jan 03 01:58:42 PM PST 24
Finished Jan 03 01:59:03 PM PST 24
Peak memory 221068 kb
Host smart-b86c4952-b676-419d-a5f3-4184be5236e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3466345676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3466345676
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_rx_async_fifo_reset.3528773905
Short name T67
Test name
Test status
Simulation time 31432881 ps
CPU time 0.87 seconds
Started Jan 03 01:58:42 PM PST 24
Finished Jan 03 01:58:56 PM PST 24
Peak memory 208524 kb
Host smart-424be3e1-521e-4874-812b-664156d39543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528773905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_rx_async_fifo_reset.3528773905
Directory /workspace/25.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/25.spi_device_rx_timeout.2071263626
Short name T1143
Test name
Test status
Simulation time 596770800 ps
CPU time 5.89 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 01:58:58 PM PST 24
Peak memory 216820 kb
Host smart-2290c90c-6b9a-40e9-9e06-27447dcb4ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071263626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_rx_timeout.2071263626
Directory /workspace/25.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/25.spi_device_smoke.2127290842
Short name T861
Test name
Test status
Simulation time 40520291 ps
CPU time 1.01 seconds
Started Jan 03 01:58:31 PM PST 24
Finished Jan 03 01:58:36 PM PST 24
Peak memory 207996 kb
Host smart-57aced85-d21c-4aa7-9cfa-cdb8829f50f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127290842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_smoke.2127290842
Directory /workspace/25.spi_device_smoke/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1736271647
Short name T1683
Test name
Test status
Simulation time 9256325086 ps
CPU time 44.96 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 01:59:39 PM PST 24
Peak memory 217000 kb
Host smart-a349f795-5c84-4125-8f68-ff68e2fa62a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736271647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1736271647
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2168030222
Short name T535
Test name
Test status
Simulation time 14344863105 ps
CPU time 12.26 seconds
Started Jan 03 01:58:42 PM PST 24
Finished Jan 03 01:59:07 PM PST 24
Peak memory 216836 kb
Host smart-bb466747-8669-4e48-a79a-27c7537eb579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168030222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2168030222
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1906481909
Short name T1622
Test name
Test status
Simulation time 68952083 ps
CPU time 2.49 seconds
Started Jan 03 01:58:42 PM PST 24
Finished Jan 03 01:58:58 PM PST 24
Peak memory 216752 kb
Host smart-05881ce4-1302-4a03-a6af-59cc5f798cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906481909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1906481909
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3152288495
Short name T1426
Test name
Test status
Simulation time 120655929 ps
CPU time 1.05 seconds
Started Jan 03 01:58:42 PM PST 24
Finished Jan 03 01:58:56 PM PST 24
Peak memory 206880 kb
Host smart-c37bb33b-a36b-4bb3-acd0-e01d6296915c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152288495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3152288495
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_tx_async_fifo_reset.508460667
Short name T1532
Test name
Test status
Simulation time 24502564 ps
CPU time 0.75 seconds
Started Jan 03 01:58:45 PM PST 24
Finished Jan 03 01:59:00 PM PST 24
Peak memory 208464 kb
Host smart-6d11dbed-2a6d-447a-a9eb-16002fa60bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508460667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tx_async_fifo_reset.508460667
Directory /workspace/25.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/25.spi_device_txrx.2031279195
Short name T971
Test name
Test status
Simulation time 164456383160 ps
CPU time 354.54 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 02:04:43 PM PST 24
Peak memory 279460 kb
Host smart-03c85410-2908-4503-949c-933a684a0a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031279195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_txrx.2031279195
Directory /workspace/25.spi_device_txrx/latest

Test location /workspace/coverage/default/25.spi_device_upload.1067406216
Short name T1006
Test name
Test status
Simulation time 688114043 ps
CPU time 4.49 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 01:58:59 PM PST 24
Peak memory 218436 kb
Host smart-95083783-40fe-43c9-a51f-c890eff7ea89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067406216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1067406216
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_abort.4285645477
Short name T542
Test name
Test status
Simulation time 15737725 ps
CPU time 0.79 seconds
Started Jan 03 01:58:34 PM PST 24
Finished Jan 03 01:58:39 PM PST 24
Peak memory 206636 kb
Host smart-930db7c7-e1a9-4667-af49-1459e91f964b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285645477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_abort.4285645477
Directory /workspace/26.spi_device_abort/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2591041765
Short name T1020
Test name
Test status
Simulation time 40723646 ps
CPU time 0.72 seconds
Started Jan 03 01:58:31 PM PST 24
Finished Jan 03 01:58:36 PM PST 24
Peak memory 206512 kb
Host smart-6d70a532-bc7b-4dea-acf7-0cbe64c9f089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591041765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2591041765
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_bit_transfer.438123473
Short name T612
Test name
Test status
Simulation time 300226204 ps
CPU time 2.43 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 01:58:50 PM PST 24
Peak memory 216740 kb
Host smart-b8682339-44a1-44fd-8116-2d0919623323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438123473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_bit_transfer.438123473
Directory /workspace/26.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/26.spi_device_byte_transfer.597001905
Short name T222
Test name
Test status
Simulation time 371822642 ps
CPU time 2.9 seconds
Started Jan 03 01:58:34 PM PST 24
Finished Jan 03 01:58:41 PM PST 24
Peak memory 216772 kb
Host smart-ecb39769-8453-4e2a-84c1-b1664979a35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597001905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_byte_transfer.597001905
Directory /workspace/26.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.607464054
Short name T1501
Test name
Test status
Simulation time 2842122335 ps
CPU time 5.68 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:58:50 PM PST 24
Peak memory 236684 kb
Host smart-28c16d37-b48f-48ec-ad41-9167d02ff7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607464054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.607464054
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3886725738
Short name T790
Test name
Test status
Simulation time 46546438 ps
CPU time 0.75 seconds
Started Jan 03 01:58:35 PM PST 24
Finished Jan 03 01:58:42 PM PST 24
Peak memory 206496 kb
Host smart-0d24f0f5-b8f5-4d66-88e3-ed286e895333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886725738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3886725738
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_dummy_item_extra_dly.382689177
Short name T1493
Test name
Test status
Simulation time 223277653381 ps
CPU time 2800.03 seconds
Started Jan 03 01:58:33 PM PST 24
Finished Jan 03 02:45:17 PM PST 24
Peak memory 263120 kb
Host smart-476a18df-1e3e-4415-8a62-0acbad668070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382689177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_dummy_item_extra_dly.382689177
Directory /workspace/26.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/26.spi_device_extreme_fifo_size.56266910
Short name T1410
Test name
Test status
Simulation time 18420417638 ps
CPU time 58.65 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:59:42 PM PST 24
Peak memory 233364 kb
Host smart-70f86cf0-d4c7-4819-b402-70724d22ebea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56266910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_extreme_fifo_size.56266910
Directory /workspace/26.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/26.spi_device_fifo_full.1322071436
Short name T305
Test name
Test status
Simulation time 145786190663 ps
CPU time 1946.6 seconds
Started Jan 03 01:58:45 PM PST 24
Finished Jan 03 02:31:26 PM PST 24
Peak memory 279520 kb
Host smart-8ba21161-8284-4bf4-8e90-3982c061f29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322071436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_fifo_full.1322071436
Directory /workspace/26.spi_device_fifo_full/latest

Test location /workspace/coverage/default/26.spi_device_fifo_underflow_overflow.2476513808
Short name T707
Test name
Test status
Simulation time 225273953577 ps
CPU time 368.79 seconds
Started Jan 03 01:58:44 PM PST 24
Finished Jan 03 02:05:07 PM PST 24
Peak memory 383192 kb
Host smart-7f9729ef-b32d-4910-a2cc-189017c14d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476513808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_fifo_underflow_overf
low.2476513808
Directory /workspace/26.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2480191443
Short name T754
Test name
Test status
Simulation time 16325357580 ps
CPU time 22.85 seconds
Started Jan 03 01:58:35 PM PST 24
Finished Jan 03 01:59:04 PM PST 24
Peak memory 241456 kb
Host smart-d8990645-2253-4269-af43-223ecd6e20b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480191443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2480191443
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2034845718
Short name T1712
Test name
Test status
Simulation time 38071376036 ps
CPU time 46.76 seconds
Started Jan 03 01:58:35 PM PST 24
Finished Jan 03 01:59:27 PM PST 24
Peak memory 239588 kb
Host smart-f86e88b1-9f50-448d-835d-0065c5bf7967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034845718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2034845718
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_intercept.241483517
Short name T354
Test name
Test status
Simulation time 164339992 ps
CPU time 2.72 seconds
Started Jan 03 01:58:33 PM PST 24
Finished Jan 03 01:58:40 PM PST 24
Peak memory 218596 kb
Host smart-cb40801f-6d53-499f-aba3-b6954a02455f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241483517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.241483517
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_intr.1415774973
Short name T1731
Test name
Test status
Simulation time 59640442057 ps
CPU time 59.77 seconds
Started Jan 03 01:58:35 PM PST 24
Finished Jan 03 01:59:42 PM PST 24
Peak memory 222968 kb
Host smart-e65e9f4b-9923-4964-b71f-7210ffc21946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415774973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intr.1415774973
Directory /workspace/26.spi_device_intr/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.4228688880
Short name T1002
Test name
Test status
Simulation time 43647541852 ps
CPU time 32.71 seconds
Started Jan 03 01:58:30 PM PST 24
Finished Jan 03 01:59:06 PM PST 24
Peak memory 249788 kb
Host smart-71a1395a-e904-4912-9e5e-18395e299a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228688880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.4228688880
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3995140570
Short name T342
Test name
Test status
Simulation time 360587855 ps
CPU time 3.86 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:58:48 PM PST 24
Peak memory 219016 kb
Host smart-db6cb4f7-7258-41be-b0e5-a81eaecc7417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995140570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3995140570
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1132804299
Short name T1400
Test name
Test status
Simulation time 56806310497 ps
CPU time 41.5 seconds
Started Jan 03 01:58:35 PM PST 24
Finished Jan 03 01:59:23 PM PST 24
Peak memory 239132 kb
Host smart-e0ad43f2-f964-46e4-ae8f-bbb69753c3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132804299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1132804299
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_perf.2601324291
Short name T870
Test name
Test status
Simulation time 24872235488 ps
CPU time 866.25 seconds
Started Jan 03 01:58:31 PM PST 24
Finished Jan 03 02:13:01 PM PST 24
Peak memory 251928 kb
Host smart-7bc23131-90d1-449e-aaea-6f4b4b4b1722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601324291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_perf.2601324291
Directory /workspace/26.spi_device_perf/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.168773578
Short name T925
Test name
Test status
Simulation time 301644953 ps
CPU time 4.16 seconds
Started Jan 03 01:58:35 PM PST 24
Finished Jan 03 01:58:47 PM PST 24
Peak memory 220356 kb
Host smart-1d3090a5-e875-49bf-95db-6dec33bc3ff5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=168773578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.168773578
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_rx_async_fifo_reset.2939644156
Short name T1535
Test name
Test status
Simulation time 596522711 ps
CPU time 0.9 seconds
Started Jan 03 01:58:35 PM PST 24
Finished Jan 03 01:58:41 PM PST 24
Peak memory 208476 kb
Host smart-63b6a221-b48c-4d45-8383-2889b5cfd6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939644156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_rx_async_fifo_reset.2939644156
Directory /workspace/26.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/26.spi_device_rx_timeout.382946648
Short name T935
Test name
Test status
Simulation time 518295068 ps
CPU time 4.96 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:58:50 PM PST 24
Peak memory 216776 kb
Host smart-766ceaee-33f2-4580-af17-abe7e81fc8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382946648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_rx_timeout.382946648
Directory /workspace/26.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/26.spi_device_smoke.566109049
Short name T555
Test name
Test status
Simulation time 63442936 ps
CPU time 1.03 seconds
Started Jan 03 01:58:40 PM PST 24
Finished Jan 03 01:58:54 PM PST 24
Peak memory 216620 kb
Host smart-fd9b85d7-5a2e-4bd3-975f-332406cd27d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566109049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_smoke.566109049
Directory /workspace/26.spi_device_smoke/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1927755656
Short name T1171
Test name
Test status
Simulation time 512635512888 ps
CPU time 1150.93 seconds
Started Jan 03 01:58:38 PM PST 24
Finished Jan 03 02:18:00 PM PST 24
Peak memory 391764 kb
Host smart-a7bd4993-b0fe-4eea-afed-85532b3a5885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927755656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1927755656
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.168532034
Short name T999
Test name
Test status
Simulation time 3650324841 ps
CPU time 6.5 seconds
Started Jan 03 01:58:32 PM PST 24
Finished Jan 03 01:58:42 PM PST 24
Peak memory 216912 kb
Host smart-6d0a3221-0500-4aee-9b07-f8177fa914a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168532034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.168532034
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1256004150
Short name T1506
Test name
Test status
Simulation time 106506856 ps
CPU time 1.09 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:58:46 PM PST 24
Peak memory 208376 kb
Host smart-c5bff9b4-8281-4e88-9cac-1f0983a38f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256004150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1256004150
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2653005494
Short name T112
Test name
Test status
Simulation time 42708389 ps
CPU time 0.92 seconds
Started Jan 03 01:58:33 PM PST 24
Finished Jan 03 01:58:38 PM PST 24
Peak memory 208008 kb
Host smart-c6a6aadf-8a01-4496-a7a9-a120c47dca6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653005494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2653005494
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_tx_async_fifo_reset.3163829993
Short name T1129
Test name
Test status
Simulation time 17827811 ps
CPU time 0.78 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 01:58:48 PM PST 24
Peak memory 208548 kb
Host smart-364850ce-c642-45f9-bbaf-a5a5b3c6ab42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163829993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tx_async_fifo_reset.3163829993
Directory /workspace/26.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/26.spi_device_txrx.589946085
Short name T585
Test name
Test status
Simulation time 180461047542 ps
CPU time 1079.57 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 02:16:48 PM PST 24
Peak memory 249016 kb
Host smart-8c597508-b4f9-45ca-97f5-840c5b4a8665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589946085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_txrx.589946085
Directory /workspace/26.spi_device_txrx/latest

Test location /workspace/coverage/default/26.spi_device_upload.1674901867
Short name T310
Test name
Test status
Simulation time 4256937000 ps
CPU time 16.51 seconds
Started Jan 03 01:58:32 PM PST 24
Finished Jan 03 01:58:53 PM PST 24
Peak memory 222980 kb
Host smart-f6a7d886-425c-4c54-a7bc-5bed44a64dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674901867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1674901867
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_abort.2440413676
Short name T941
Test name
Test status
Simulation time 18955642 ps
CPU time 0.74 seconds
Started Jan 03 01:58:33 PM PST 24
Finished Jan 03 01:58:39 PM PST 24
Peak memory 206704 kb
Host smart-da648e1a-5742-4d44-8bf1-7265ad803478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440413676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_abort.2440413676
Directory /workspace/27.spi_device_abort/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1539492014
Short name T1082
Test name
Test status
Simulation time 17526686 ps
CPU time 0.72 seconds
Started Jan 03 01:58:38 PM PST 24
Finished Jan 03 01:58:51 PM PST 24
Peak memory 206504 kb
Host smart-0876cef2-b752-4a28-b5b1-ad6173d4bd76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539492014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1539492014
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_bit_transfer.3958349218
Short name T994
Test name
Test status
Simulation time 404903442 ps
CPU time 2.6 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:58:46 PM PST 24
Peak memory 216792 kb
Host smart-1bb889d1-435c-40bb-920b-8a8f64275a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958349218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_bit_transfer.3958349218
Directory /workspace/27.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/27.spi_device_byte_transfer.220934055
Short name T521
Test name
Test status
Simulation time 244992656 ps
CPU time 3.04 seconds
Started Jan 03 01:58:31 PM PST 24
Finished Jan 03 01:58:37 PM PST 24
Peak memory 216948 kb
Host smart-b9eb6dab-1741-44af-9ae0-62aff24b8807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220934055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_byte_transfer.220934055
Directory /workspace/27.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1452929419
Short name T352
Test name
Test status
Simulation time 510807648 ps
CPU time 4.11 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:58:48 PM PST 24
Peak memory 219340 kb
Host smart-cf4ab106-5e74-4285-a4b3-6aa443a9fbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452929419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1452929419
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2603259598
Short name T993
Test name
Test status
Simulation time 14961491 ps
CPU time 0.79 seconds
Started Jan 03 01:58:30 PM PST 24
Finished Jan 03 01:58:35 PM PST 24
Peak memory 206620 kb
Host smart-fbe7cff8-36c3-45b1-a3be-d23d0ce9861f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603259598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2603259598
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_dummy_item_extra_dly.1221298420
Short name T1490
Test name
Test status
Simulation time 45094650293 ps
CPU time 965.37 seconds
Started Jan 03 01:58:34 PM PST 24
Finished Jan 03 02:14:44 PM PST 24
Peak memory 268024 kb
Host smart-76091c74-695e-49b6-b740-934583cdd751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221298420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_dummy_item_extra_dly.1221298420
Directory /workspace/27.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/27.spi_device_extreme_fifo_size.905900222
Short name T1363
Test name
Test status
Simulation time 289044699235 ps
CPU time 847.15 seconds
Started Jan 03 01:58:33 PM PST 24
Finished Jan 03 02:12:44 PM PST 24
Peak memory 225200 kb
Host smart-3c751435-243f-4959-83f3-536c89cabe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905900222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_extreme_fifo_size.905900222
Directory /workspace/27.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/27.spi_device_fifo_full.2451084906
Short name T709
Test name
Test status
Simulation time 147455976124 ps
CPU time 2262.29 seconds
Started Jan 03 01:58:32 PM PST 24
Finished Jan 03 02:36:19 PM PST 24
Peak memory 270236 kb
Host smart-e8508d90-9973-498e-8f1c-b7a5bd556c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451084906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_fifo_full.2451084906
Directory /workspace/27.spi_device_fifo_full/latest

Test location /workspace/coverage/default/27.spi_device_fifo_underflow_overflow.778735899
Short name T55
Test name
Test status
Simulation time 344157165513 ps
CPU time 443.77 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 02:06:12 PM PST 24
Peak memory 401508 kb
Host smart-6d8f5aaf-690f-4736-a4fc-e1f255ea0c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778735899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_fifo_underflow_overfl
ow.778735899
Directory /workspace/27.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2992953909
Short name T1546
Test name
Test status
Simulation time 39526348840 ps
CPU time 309.26 seconds
Started Jan 03 01:58:35 PM PST 24
Finished Jan 03 02:03:50 PM PST 24
Peak memory 254232 kb
Host smart-af8e6cf1-cbac-464d-ab43-24637163f21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992953909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2992953909
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.772658494
Short name T5
Test name
Test status
Simulation time 612697095610 ps
CPU time 552.62 seconds
Started Jan 03 01:58:32 PM PST 24
Finished Jan 03 02:07:49 PM PST 24
Peak memory 269084 kb
Host smart-a58ade9a-0e1b-47da-88bb-44a967d9246f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772658494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.772658494
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3698773175
Short name T1228
Test name
Test status
Simulation time 15612211117 ps
CPU time 27.48 seconds
Started Jan 03 01:58:40 PM PST 24
Finished Jan 03 01:59:20 PM PST 24
Peak memory 257096 kb
Host smart-5499c3d5-1397-4144-a02c-6447bd7f0acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698773175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3698773175
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3001346475
Short name T1352
Test name
Test status
Simulation time 11157258425 ps
CPU time 9.15 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 01:58:57 PM PST 24
Peak memory 219344 kb
Host smart-7a931698-3698-49ef-aa16-3a2902527da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001346475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3001346475
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_intr.4196246432
Short name T1033
Test name
Test status
Simulation time 92546904106 ps
CPU time 71.82 seconds
Started Jan 03 01:58:32 PM PST 24
Finished Jan 03 01:59:48 PM PST 24
Peak memory 233428 kb
Host smart-b42cf6c3-5e23-46f9-89f3-746c48a5c0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196246432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intr.4196246432
Directory /workspace/27.spi_device_intr/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.4165794419
Short name T249
Test name
Test status
Simulation time 1824933695 ps
CPU time 9.22 seconds
Started Jan 03 01:58:34 PM PST 24
Finished Jan 03 01:58:48 PM PST 24
Peak memory 254904 kb
Host smart-38af59f9-8a75-48f1-95d3-7412153c031e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165794419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.4165794419
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.544892694
Short name T235
Test name
Test status
Simulation time 73199418 ps
CPU time 2.94 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:58:47 PM PST 24
Peak memory 238116 kb
Host smart-908620bd-8579-4181-994b-9eae5d1c8bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544892694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.544892694
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2473137071
Short name T349
Test name
Test status
Simulation time 15522334048 ps
CPU time 44.93 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 01:59:31 PM PST 24
Peak memory 249628 kb
Host smart-1e4791b6-db62-4bc5-8dc7-284e976671a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473137071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2473137071
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_perf.2316833486
Short name T536
Test name
Test status
Simulation time 26951875404 ps
CPU time 702.85 seconds
Started Jan 03 01:58:35 PM PST 24
Finished Jan 03 02:10:24 PM PST 24
Peak memory 273664 kb
Host smart-6e8c10fa-32b0-4811-bb13-9daebd148271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316833486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_perf.2316833486
Directory /workspace/27.spi_device_perf/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2506755946
Short name T1601
Test name
Test status
Simulation time 254684740 ps
CPU time 4.28 seconds
Started Jan 03 01:58:29 PM PST 24
Finished Jan 03 01:58:36 PM PST 24
Peak memory 236252 kb
Host smart-73310758-54ad-4b8f-bffc-cb288e3fdcfe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2506755946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2506755946
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_rx_async_fifo_reset.4221765710
Short name T1564
Test name
Test status
Simulation time 36160657 ps
CPU time 0.85 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:58:44 PM PST 24
Peak memory 208404 kb
Host smart-e18e2599-465b-43cb-a642-b33692b9b031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221765710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_rx_async_fifo_reset.4221765710
Directory /workspace/27.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/27.spi_device_rx_timeout.2074868893
Short name T1733
Test name
Test status
Simulation time 785952077 ps
CPU time 6.89 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 01:58:55 PM PST 24
Peak memory 216844 kb
Host smart-cc8cea0c-15da-40e4-a062-38721eae6ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074868893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_rx_timeout.2074868893
Directory /workspace/27.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/27.spi_device_smoke.1906531457
Short name T685
Test name
Test status
Simulation time 27926944 ps
CPU time 1.16 seconds
Started Jan 03 01:58:31 PM PST 24
Finished Jan 03 01:58:36 PM PST 24
Peak memory 208336 kb
Host smart-7f46618b-2d24-417c-85e2-9f79dc146ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906531457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_smoke.1906531457
Directory /workspace/27.spi_device_smoke/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.991673804
Short name T375
Test name
Test status
Simulation time 169581676187 ps
CPU time 2148.46 seconds
Started Jan 03 01:58:32 PM PST 24
Finished Jan 03 02:34:25 PM PST 24
Peak memory 356256 kb
Host smart-6d7d15b3-b65e-418f-b12a-7157c5d6f3ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991673804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.991673804
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2117108701
Short name T1040
Test name
Test status
Simulation time 10042830610 ps
CPU time 78.09 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 02:00:05 PM PST 24
Peak memory 216908 kb
Host smart-a2d60759-dd9b-446a-b3cb-f180d8bbbb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117108701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2117108701
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.158812218
Short name T1417
Test name
Test status
Simulation time 1589423642 ps
CPU time 5.28 seconds
Started Jan 03 01:58:32 PM PST 24
Finished Jan 03 01:58:42 PM PST 24
Peak memory 216804 kb
Host smart-2794d5e2-6489-491c-a768-a9b4bbe99b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158812218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.158812218
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1615026398
Short name T511
Test name
Test status
Simulation time 216194315 ps
CPU time 1.56 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 01:58:50 PM PST 24
Peak memory 216396 kb
Host smart-4214898e-213e-4206-bc27-3e2383395575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615026398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1615026398
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1638941055
Short name T1019
Test name
Test status
Simulation time 20062330 ps
CPU time 0.75 seconds
Started Jan 03 01:58:33 PM PST 24
Finished Jan 03 01:58:39 PM PST 24
Peak memory 206884 kb
Host smart-8e2ff57f-ddfe-4f72-b0fc-d1e00195aecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638941055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1638941055
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_tx_async_fifo_reset.280501220
Short name T1573
Test name
Test status
Simulation time 38415600 ps
CPU time 0.77 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 01:58:48 PM PST 24
Peak memory 208392 kb
Host smart-ffb938f7-d695-4ccc-a7f3-e6bd3cdc1078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280501220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tx_async_fifo_reset.280501220
Directory /workspace/27.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/27.spi_device_txrx.1478705116
Short name T576
Test name
Test status
Simulation time 80357704397 ps
CPU time 897.2 seconds
Started Jan 03 01:58:34 PM PST 24
Finished Jan 03 02:13:35 PM PST 24
Peak memory 251856 kb
Host smart-2de84d50-cc14-4a20-a46f-b1b9a2202607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478705116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_txrx.1478705116
Directory /workspace/27.spi_device_txrx/latest

Test location /workspace/coverage/default/27.spi_device_upload.3381751852
Short name T294
Test name
Test status
Simulation time 2352143277 ps
CPU time 9.35 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 01:58:56 PM PST 24
Peak memory 239884 kb
Host smart-22dae604-49e4-41a2-b675-aa20bae5241f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381751852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3381751852
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_abort.4080051223
Short name T738
Test name
Test status
Simulation time 15921220 ps
CPU time 0.76 seconds
Started Jan 03 01:58:45 PM PST 24
Finished Jan 03 01:58:59 PM PST 24
Peak memory 206680 kb
Host smart-41cf1196-b81c-4162-a3ae-1ec8b664d592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080051223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_abort.4080051223
Directory /workspace/28.spi_device_abort/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3143020476
Short name T513
Test name
Test status
Simulation time 36199904 ps
CPU time 0.72 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 01:58:54 PM PST 24
Peak memory 206528 kb
Host smart-7f94989d-4b05-4411-9782-273c02b55f11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143020476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3143020476
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_bit_transfer.30967030
Short name T1697
Test name
Test status
Simulation time 362923075 ps
CPU time 3.33 seconds
Started Jan 03 01:58:45 PM PST 24
Finished Jan 03 01:59:02 PM PST 24
Peak memory 216880 kb
Host smart-a5cdf7cd-3dd8-4d0a-9fd7-39e431975aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30967030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_bit_transfer.30967030
Directory /workspace/28.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/28.spi_device_byte_transfer.1434846196
Short name T1269
Test name
Test status
Simulation time 779172085 ps
CPU time 2.85 seconds
Started Jan 03 01:58:38 PM PST 24
Finished Jan 03 01:58:53 PM PST 24
Peak memory 216780 kb
Host smart-3c860735-273d-4841-96d1-5b2381119631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434846196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_byte_transfer.1434846196
Directory /workspace/28.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1193032188
Short name T322
Test name
Test status
Simulation time 382428010 ps
CPU time 3.45 seconds
Started Jan 03 01:58:42 PM PST 24
Finished Jan 03 01:58:59 PM PST 24
Peak memory 238152 kb
Host smart-2d036119-e13e-4244-b442-5de16405f71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193032188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1193032188
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4251455695
Short name T1005
Test name
Test status
Simulation time 113193465 ps
CPU time 0.78 seconds
Started Jan 03 01:58:38 PM PST 24
Finished Jan 03 01:58:51 PM PST 24
Peak memory 207572 kb
Host smart-bda033f8-9eda-4e74-a5ee-6e1c20a7deba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251455695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4251455695
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_dummy_item_extra_dly.2106151903
Short name T1650
Test name
Test status
Simulation time 110810211170 ps
CPU time 159.93 seconds
Started Jan 03 01:58:38 PM PST 24
Finished Jan 03 02:01:29 PM PST 24
Peak memory 255996 kb
Host smart-b4d02488-887b-4d6a-a576-3fe9e01321c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106151903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_dummy_item_extra_dly.2106151903
Directory /workspace/28.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/28.spi_device_extreme_fifo_size.526756215
Short name T1222
Test name
Test status
Simulation time 42666660702 ps
CPU time 618.51 seconds
Started Jan 03 01:58:40 PM PST 24
Finished Jan 03 02:09:11 PM PST 24
Peak memory 218012 kb
Host smart-f99b4337-8fb6-40be-82bf-502065ec7aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526756215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_extreme_fifo_size.526756215
Directory /workspace/28.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/28.spi_device_fifo_full.1761824559
Short name T1588
Test name
Test status
Simulation time 42750292262 ps
CPU time 721.9 seconds
Started Jan 03 01:58:38 PM PST 24
Finished Jan 03 02:10:51 PM PST 24
Peak memory 295508 kb
Host smart-b1a96066-d9bd-4e96-9b70-3725f01cd3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761824559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_fifo_full.1761824559
Directory /workspace/28.spi_device_fifo_full/latest

Test location /workspace/coverage/default/28.spi_device_fifo_underflow_overflow.410989834
Short name T1482
Test name
Test status
Simulation time 15715528451 ps
CPU time 212.43 seconds
Started Jan 03 01:58:32 PM PST 24
Finished Jan 03 02:02:08 PM PST 24
Peak memory 320052 kb
Host smart-f9812dac-467b-4ed6-87f3-a1b555cf6054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410989834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_fifo_underflow_overfl
ow.410989834
Directory /workspace/28.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4286600187
Short name T799
Test name
Test status
Simulation time 142934131581 ps
CPU time 299.16 seconds
Started Jan 03 01:58:44 PM PST 24
Finished Jan 03 02:03:57 PM PST 24
Peak memory 264712 kb
Host smart-8b8ae736-ab3b-4e21-8141-d428738b726f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286600187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4286600187
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1668845367
Short name T296
Test name
Test status
Simulation time 69964369948 ps
CPU time 97.36 seconds
Started Jan 03 01:58:46 PM PST 24
Finished Jan 03 02:00:37 PM PST 24
Peak memory 249808 kb
Host smart-aec79ff8-84e6-464c-8da6-caf95dbf1b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668845367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1668845367
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.704060247
Short name T1648
Test name
Test status
Simulation time 774352320 ps
CPU time 13.89 seconds
Started Jan 03 01:58:45 PM PST 24
Finished Jan 03 01:59:13 PM PST 24
Peak memory 234592 kb
Host smart-b5b3d60b-2b06-40c7-914c-3381c541bfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704060247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.704060247
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1940612256
Short name T11
Test name
Test status
Simulation time 4370593714 ps
CPU time 7.49 seconds
Started Jan 03 01:58:45 PM PST 24
Finished Jan 03 01:59:06 PM PST 24
Peak memory 238844 kb
Host smart-5edbf996-3ca0-428c-8166-3245c7bf3ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940612256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1940612256
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_intr.1058899187
Short name T552
Test name
Test status
Simulation time 7279397395 ps
CPU time 51.97 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 01:59:44 PM PST 24
Peak memory 249708 kb
Host smart-81c1bbe5-9f63-455f-8e71-ef18ac7f7989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058899187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intr.1058899187
Directory /workspace/28.spi_device_intr/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3428501697
Short name T1615
Test name
Test status
Simulation time 4048191919 ps
CPU time 19.95 seconds
Started Jan 03 01:58:43 PM PST 24
Finished Jan 03 01:59:17 PM PST 24
Peak memory 232444 kb
Host smart-8671d852-9f0a-44b6-9ae4-be0af7963339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428501697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3428501697
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1709358455
Short name T1012
Test name
Test status
Simulation time 4462328419 ps
CPU time 4.64 seconds
Started Jan 03 01:58:38 PM PST 24
Finished Jan 03 01:58:54 PM PST 24
Peak memory 220608 kb
Host smart-2a1591e5-8cde-4f91-828b-3c1e568a8d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709358455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1709358455
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2783029193
Short name T22
Test name
Test status
Simulation time 2095256621 ps
CPU time 9.3 seconds
Started Jan 03 01:58:44 PM PST 24
Finished Jan 03 01:59:07 PM PST 24
Peak memory 241376 kb
Host smart-01c1569b-f58a-478e-9f0e-5f6669c64223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783029193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2783029193
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_perf.1712618111
Short name T670
Test name
Test status
Simulation time 34106806909 ps
CPU time 695.83 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 02:10:30 PM PST 24
Peak memory 241308 kb
Host smart-1a4fe990-a67a-4094-bc0c-b9df3c765a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712618111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_perf.1712618111
Directory /workspace/28.spi_device_perf/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3663165499
Short name T56
Test name
Test status
Simulation time 977407534 ps
CPU time 5.49 seconds
Started Jan 03 01:58:45 PM PST 24
Finished Jan 03 01:59:04 PM PST 24
Peak memory 221132 kb
Host smart-8f5d856a-2976-4563-9099-011d777a3daa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3663165499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3663165499
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_rx_async_fifo_reset.923541236
Short name T818
Test name
Test status
Simulation time 19135095 ps
CPU time 0.86 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 01:58:55 PM PST 24
Peak memory 208432 kb
Host smart-5804fa81-1624-45c7-8880-6f60250e1300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923541236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_rx_async_fifo_reset.923541236
Directory /workspace/28.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/28.spi_device_rx_timeout.4133993795
Short name T694
Test name
Test status
Simulation time 763887157 ps
CPU time 5.61 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 01:59:00 PM PST 24
Peak memory 216808 kb
Host smart-7b7d8c41-b5f4-4415-a998-be5138f7e0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133993795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_rx_timeout.4133993795
Directory /workspace/28.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/28.spi_device_smoke.125928125
Short name T1737
Test name
Test status
Simulation time 20920420 ps
CPU time 1.11 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 01:58:53 PM PST 24
Peak memory 216468 kb
Host smart-9093fd64-ae9b-4b27-8a91-79451c6101a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125928125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_smoke.125928125
Directory /workspace/28.spi_device_smoke/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1848190797
Short name T1258
Test name
Test status
Simulation time 156829269501 ps
CPU time 522.03 seconds
Started Jan 03 01:58:45 PM PST 24
Finished Jan 03 02:07:40 PM PST 24
Peak memory 300112 kb
Host smart-8bf54156-e54b-41fa-b514-30e97ff8b9a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848190797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1848190797
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2613542
Short name T1526
Test name
Test status
Simulation time 2373701784 ps
CPU time 21.99 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 01:59:17 PM PST 24
Peak memory 216924 kb
Host smart-12d1a88f-455a-4068-860e-4a007d6f9b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2613542
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4056952156
Short name T1114
Test name
Test status
Simulation time 2707305741 ps
CPU time 7.33 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 01:58:59 PM PST 24
Peak memory 216912 kb
Host smart-6fe6d805-62fe-4a91-8b15-482abbcebf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056952156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4056952156
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2592666625
Short name T823
Test name
Test status
Simulation time 110045270 ps
CPU time 1.27 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 01:58:55 PM PST 24
Peak memory 208384 kb
Host smart-bcd0d1cd-5edd-46e1-9c41-42eacfa80e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592666625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2592666625
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.571428827
Short name T607
Test name
Test status
Simulation time 252648873 ps
CPU time 0.8 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 01:58:56 PM PST 24
Peak memory 206004 kb
Host smart-6d2b5e1f-f1a0-4cd9-85a1-66e6729426ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571428827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.571428827
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_tx_async_fifo_reset.4018610175
Short name T1376
Test name
Test status
Simulation time 27345505 ps
CPU time 0.75 seconds
Started Jan 03 01:58:40 PM PST 24
Finished Jan 03 01:58:54 PM PST 24
Peak memory 208384 kb
Host smart-4ca7b534-b328-4705-aade-a529b7585b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018610175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tx_async_fifo_reset.4018610175
Directory /workspace/28.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/28.spi_device_txrx.4231084377
Short name T573
Test name
Test status
Simulation time 26599892555 ps
CPU time 218.75 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 02:02:30 PM PST 24
Peak memory 268228 kb
Host smart-a4f13a2a-fac1-45ef-b1be-ff39335661ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231084377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_txrx.4231084377
Directory /workspace/28.spi_device_txrx/latest

Test location /workspace/coverage/default/28.spi_device_upload.2469799665
Short name T1454
Test name
Test status
Simulation time 370777433 ps
CPU time 4.55 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 01:58:56 PM PST 24
Peak memory 225044 kb
Host smart-42123a81-a14a-4bba-a9e1-b760485417e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469799665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2469799665
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_abort.2588228151
Short name T705
Test name
Test status
Simulation time 38664508 ps
CPU time 0.79 seconds
Started Jan 03 01:58:35 PM PST 24
Finished Jan 03 01:58:41 PM PST 24
Peak memory 206620 kb
Host smart-5157a2ab-1761-4b75-8cf5-4cbd63a9c607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588228151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_abort.2588228151
Directory /workspace/29.spi_device_abort/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.4275975964
Short name T824
Test name
Test status
Simulation time 14812105 ps
CPU time 0.72 seconds
Started Jan 03 01:58:42 PM PST 24
Finished Jan 03 01:58:57 PM PST 24
Peak memory 206516 kb
Host smart-dd84727c-d587-4899-84e2-e3bd4ca7ec31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275975964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
4275975964
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_bit_transfer.976519054
Short name T1104
Test name
Test status
Simulation time 172187399 ps
CPU time 2.24 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:58:46 PM PST 24
Peak memory 216860 kb
Host smart-9bda66ed-f0d4-456e-965e-226447702270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976519054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_bit_transfer.976519054
Directory /workspace/29.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/29.spi_device_byte_transfer.3753676797
Short name T1687
Test name
Test status
Simulation time 311061184 ps
CPU time 2.46 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:58:46 PM PST 24
Peak memory 216792 kb
Host smart-6995d21e-0730-44a4-9754-94c6e2953d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753676797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_byte_transfer.3753676797
Directory /workspace/29.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2659631561
Short name T307
Test name
Test status
Simulation time 484709613 ps
CPU time 4.4 seconds
Started Jan 03 01:58:42 PM PST 24
Finished Jan 03 01:59:00 PM PST 24
Peak memory 241324 kb
Host smart-a4a17444-cbf3-4231-bcac-a760f389e2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659631561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2659631561
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.429962648
Short name T1058
Test name
Test status
Simulation time 35189965 ps
CPU time 0.77 seconds
Started Jan 03 01:58:34 PM PST 24
Finished Jan 03 01:58:40 PM PST 24
Peak memory 207604 kb
Host smart-b89452d4-dd87-4bfb-97b9-5e3a55771e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429962648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.429962648
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_dummy_item_extra_dly.4285980050
Short name T587
Test name
Test status
Simulation time 46885024362 ps
CPU time 343.99 seconds
Started Jan 03 01:58:44 PM PST 24
Finished Jan 03 02:04:42 PM PST 24
Peak memory 293920 kb
Host smart-916c9da8-3bf8-47bd-a5c1-ecb626013bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285980050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_dummy_item_extra_dly.4285980050
Directory /workspace/29.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/29.spi_device_extreme_fifo_size.1377870135
Short name T1397
Test name
Test status
Simulation time 822473806009 ps
CPU time 1004.8 seconds
Started Jan 03 01:58:44 PM PST 24
Finished Jan 03 02:15:42 PM PST 24
Peak memory 220052 kb
Host smart-fc66821a-eab3-4652-9617-c051a960a40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377870135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_extreme_fifo_size.1377870135
Directory /workspace/29.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/29.spi_device_fifo_full.2734249834
Short name T1452
Test name
Test status
Simulation time 67025520761 ps
CPU time 1668.92 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 02:26:41 PM PST 24
Peak memory 288196 kb
Host smart-8a8c6d65-fbc3-4155-b397-222972a2e599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734249834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_fifo_full.2734249834
Directory /workspace/29.spi_device_fifo_full/latest

Test location /workspace/coverage/default/29.spi_device_fifo_underflow_overflow.3442524232
Short name T1745
Test name
Test status
Simulation time 108971843129 ps
CPU time 255.95 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 02:03:05 PM PST 24
Peak memory 309468 kb
Host smart-21bb4507-5d16-435c-8992-06969ebdcd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442524232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_fifo_underflow_overf
low.3442524232
Directory /workspace/29.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3021526126
Short name T608
Test name
Test status
Simulation time 9066146899 ps
CPU time 67.76 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 02:00:02 PM PST 24
Peak memory 257220 kb
Host smart-848a6323-a784-4948-8197-db5599962886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021526126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3021526126
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2960887662
Short name T363
Test name
Test status
Simulation time 2910252086 ps
CPU time 61.18 seconds
Started Jan 03 01:58:43 PM PST 24
Finished Jan 03 01:59:58 PM PST 24
Peak memory 255944 kb
Host smart-60744299-69e1-4628-a27b-4f468e89756d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960887662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2960887662
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2310956691
Short name T386
Test name
Test status
Simulation time 5134134140 ps
CPU time 93.01 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 02:00:27 PM PST 24
Peak memory 256544 kb
Host smart-e60016c6-e86a-4318-a522-5dee0835214d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310956691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2310956691
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.4047778419
Short name T739
Test name
Test status
Simulation time 5139831944 ps
CPU time 17.99 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 01:59:10 PM PST 24
Peak memory 249676 kb
Host smart-42f3d0bf-a847-49ec-9dd0-28e3d9c5a462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047778419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.4047778419
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3651409041
Short name T320
Test name
Test status
Simulation time 180390298 ps
CPU time 4.11 seconds
Started Jan 03 01:58:43 PM PST 24
Finished Jan 03 01:59:01 PM PST 24
Peak memory 238520 kb
Host smart-dd228040-78a4-4b76-b555-eb959ffd054d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651409041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3651409041
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_intr.1125938098
Short name T611
Test name
Test status
Simulation time 4012472346 ps
CPU time 12.48 seconds
Started Jan 03 01:58:44 PM PST 24
Finished Jan 03 01:59:10 PM PST 24
Peak memory 216908 kb
Host smart-fb04526a-5f53-46a9-8893-74190da31ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125938098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intr.1125938098
Directory /workspace/29.spi_device_intr/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1884775031
Short name T9
Test name
Test status
Simulation time 5371648087 ps
CPU time 22.06 seconds
Started Jan 03 01:58:34 PM PST 24
Finished Jan 03 01:59:01 PM PST 24
Peak memory 246428 kb
Host smart-872a42c4-eb62-451d-b3dc-c77ad184f8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884775031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1884775031
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1357883572
Short name T1518
Test name
Test status
Simulation time 2406191276 ps
CPU time 8.37 seconds
Started Jan 03 01:58:38 PM PST 24
Finished Jan 03 01:58:58 PM PST 24
Peak memory 249716 kb
Host smart-b0216753-ab83-44d4-aecf-e14be96c8702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357883572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1357883572
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2138857470
Short name T1007
Test name
Test status
Simulation time 4209974195 ps
CPU time 6.33 seconds
Started Jan 03 01:58:38 PM PST 24
Finished Jan 03 01:58:55 PM PST 24
Peak memory 219568 kb
Host smart-9a45572d-de6a-47f2-b4e9-40bb9de6f35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138857470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2138857470
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_perf.1465914764
Short name T704
Test name
Test status
Simulation time 67887155533 ps
CPU time 882.83 seconds
Started Jan 03 01:58:34 PM PST 24
Finished Jan 03 02:13:22 PM PST 24
Peak memory 241172 kb
Host smart-435ebdec-0f2e-48b6-be46-d25ba5073870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465914764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_perf.1465914764
Directory /workspace/29.spi_device_perf/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3675127716
Short name T1599
Test name
Test status
Simulation time 769590353 ps
CPU time 5.25 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 01:58:56 PM PST 24
Peak memory 234492 kb
Host smart-88667adb-1851-4696-b668-400033c8469f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3675127716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3675127716
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_rx_async_fifo_reset.407500720
Short name T1705
Test name
Test status
Simulation time 26428437 ps
CPU time 0.87 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:58:46 PM PST 24
Peak memory 208580 kb
Host smart-10ba537b-d896-4df9-9116-f3925aeda7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407500720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_rx_async_fifo_reset.407500720
Directory /workspace/29.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/29.spi_device_rx_timeout.2226293463
Short name T600
Test name
Test status
Simulation time 1814464344 ps
CPU time 6.95 seconds
Started Jan 03 01:58:37 PM PST 24
Finished Jan 03 01:58:54 PM PST 24
Peak memory 216984 kb
Host smart-14906ee6-779e-4e38-9d7d-0b759513b068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226293463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_rx_timeout.2226293463
Directory /workspace/29.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/29.spi_device_smoke.450190181
Short name T791
Test name
Test status
Simulation time 99873486 ps
CPU time 1.03 seconds
Started Jan 03 01:58:43 PM PST 24
Finished Jan 03 01:58:58 PM PST 24
Peak memory 208100 kb
Host smart-1732cf5f-1bd4-433e-8788-f37c9d85a8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450190181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_smoke.450190181
Directory /workspace/29.spi_device_smoke/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2393812192
Short name T1132
Test name
Test status
Simulation time 148896151318 ps
CPU time 1535.74 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 02:24:29 PM PST 24
Peak memory 694244 kb
Host smart-d7b6ae32-210d-44bb-a68f-c7aa480f6bbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393812192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2393812192
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4005411329
Short name T549
Test name
Test status
Simulation time 5345614576 ps
CPU time 79.55 seconds
Started Jan 03 01:58:35 PM PST 24
Finished Jan 03 02:00:00 PM PST 24
Peak memory 218200 kb
Host smart-aa2c863f-9d23-47b7-9ca0-a273e891fbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005411329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4005411329
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2495844588
Short name T1107
Test name
Test status
Simulation time 3675140656 ps
CPU time 3.64 seconds
Started Jan 03 01:58:38 PM PST 24
Finished Jan 03 01:58:53 PM PST 24
Peak memory 216928 kb
Host smart-0aba10d4-cd6b-4bfa-a56b-fb1f858fee67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495844588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2495844588
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1755521593
Short name T1682
Test name
Test status
Simulation time 2237120707 ps
CPU time 4.78 seconds
Started Jan 03 01:58:34 PM PST 24
Finished Jan 03 01:58:44 PM PST 24
Peak memory 216880 kb
Host smart-82d19644-14f6-43c6-b698-77bb163f5e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755521593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1755521593
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1268726103
Short name T114
Test name
Test status
Simulation time 27952230 ps
CPU time 0.78 seconds
Started Jan 03 01:58:35 PM PST 24
Finished Jan 03 01:58:41 PM PST 24
Peak memory 206968 kb
Host smart-9bfcbf3d-b0d5-4b2b-bf73-c31d885d1af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268726103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1268726103
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_tx_async_fifo_reset.1474110406
Short name T1438
Test name
Test status
Simulation time 57646700 ps
CPU time 0.76 seconds
Started Jan 03 01:58:36 PM PST 24
Finished Jan 03 01:58:45 PM PST 24
Peak memory 208424 kb
Host smart-c75079e2-7f50-4823-a42a-aac8299562be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474110406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tx_async_fifo_reset.1474110406
Directory /workspace/29.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/29.spi_device_txrx.2256694979
Short name T821
Test name
Test status
Simulation time 47343649159 ps
CPU time 343.2 seconds
Started Jan 03 01:58:39 PM PST 24
Finished Jan 03 02:04:34 PM PST 24
Peak memory 296824 kb
Host smart-3266f1a8-facc-4b56-9d9e-e1daef1b01d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256694979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_txrx.2256694979
Directory /workspace/29.spi_device_txrx/latest

Test location /workspace/coverage/default/29.spi_device_upload.2318014941
Short name T843
Test name
Test status
Simulation time 8294451690 ps
CPU time 24.41 seconds
Started Jan 03 01:58:40 PM PST 24
Finished Jan 03 01:59:17 PM PST 24
Peak memory 241504 kb
Host smart-e548d784-715e-4790-8b65-2f92a8b33778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318014941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2318014941
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_abort.2774242003
Short name T1665
Test name
Test status
Simulation time 16084043 ps
CPU time 0.75 seconds
Started Jan 03 01:51:26 PM PST 24
Finished Jan 03 01:51:44 PM PST 24
Peak memory 206616 kb
Host smart-c0372b2b-da22-4d39-9bca-3db0287e0c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774242003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_abort.2774242003
Directory /workspace/3.spi_device_abort/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3117268724
Short name T524
Test name
Test status
Simulation time 41836963 ps
CPU time 0.74 seconds
Started Jan 03 01:51:30 PM PST 24
Finished Jan 03 01:51:52 PM PST 24
Peak memory 206508 kb
Host smart-7467e724-aa87-4a6c-b9c9-91c4a9ee33fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117268724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
117268724
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_bit_transfer.650197699
Short name T563
Test name
Test status
Simulation time 179383832 ps
CPU time 2.5 seconds
Started Jan 03 01:51:29 PM PST 24
Finished Jan 03 01:51:54 PM PST 24
Peak memory 216812 kb
Host smart-7e7c6076-5ef8-4325-931d-ea34683af0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650197699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_bit_transfer.650197699
Directory /workspace/3.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/3.spi_device_byte_transfer.3014001458
Short name T669
Test name
Test status
Simulation time 135857429 ps
CPU time 2.85 seconds
Started Jan 03 01:51:24 PM PST 24
Finished Jan 03 01:51:43 PM PST 24
Peak memory 216864 kb
Host smart-d4fe81ab-f074-4e2a-a546-fedfd0446f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014001458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_byte_transfer.3014001458
Directory /workspace/3.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3308653306
Short name T1035
Test name
Test status
Simulation time 80830221 ps
CPU time 2.93 seconds
Started Jan 03 01:51:30 PM PST 24
Finished Jan 03 01:51:55 PM PST 24
Peak memory 218628 kb
Host smart-bba68268-cded-4a1f-907d-eb5d61b9e494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308653306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3308653306
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.380462756
Short name T90
Test name
Test status
Simulation time 17626475 ps
CPU time 0.77 seconds
Started Jan 03 01:51:28 PM PST 24
Finished Jan 03 01:51:50 PM PST 24
Peak memory 206600 kb
Host smart-13061b6c-4699-4f48-ad2a-5c398c9e8138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380462756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.380462756
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_dummy_item_extra_dly.1793243519
Short name T1662
Test name
Test status
Simulation time 165558189733 ps
CPU time 2634.57 seconds
Started Jan 03 01:51:28 PM PST 24
Finished Jan 03 02:35:44 PM PST 24
Peak memory 266832 kb
Host smart-17a91fd1-9cd3-459d-8da3-a7da5fba30b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793243519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_dummy_item_extra_dly.1793243519
Directory /workspace/3.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/3.spi_device_extreme_fifo_size.2454105243
Short name T1092
Test name
Test status
Simulation time 54167537164 ps
CPU time 372.94 seconds
Started Jan 03 01:51:22 PM PST 24
Finished Jan 03 01:57:46 PM PST 24
Peak memory 217920 kb
Host smart-8889381e-4790-426e-8110-f9a0bdf36fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454105243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_extreme_fifo_size.2454105243
Directory /workspace/3.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/3.spi_device_fifo_full.3197940113
Short name T1256
Test name
Test status
Simulation time 157939931537 ps
CPU time 759.82 seconds
Started Jan 03 01:51:05 PM PST 24
Finished Jan 03 02:03:49 PM PST 24
Peak memory 304680 kb
Host smart-bb894ba7-3222-4838-aa4e-a5a34d792b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197940113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_fifo_full.3197940113
Directory /workspace/3.spi_device_fifo_full/latest

Test location /workspace/coverage/default/3.spi_device_fifo_underflow_overflow.2851539850
Short name T1087
Test name
Test status
Simulation time 211304279090 ps
CPU time 346.21 seconds
Started Jan 03 01:51:26 PM PST 24
Finished Jan 03 01:57:32 PM PST 24
Peak memory 423836 kb
Host smart-52bb6f04-66af-494a-8c2a-f105c0328229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851539850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_fifo_underflow_overfl
ow.2851539850
Directory /workspace/3.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1235691639
Short name T1446
Test name
Test status
Simulation time 4817633472 ps
CPU time 26.03 seconds
Started Jan 03 01:51:29 PM PST 24
Finished Jan 03 01:52:17 PM PST 24
Peak memory 257800 kb
Host smart-4e38de3a-f26d-488f-8f61-85219ca38392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235691639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1235691639
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.90319892
Short name T214
Test name
Test status
Simulation time 64264963588 ps
CPU time 242.5 seconds
Started Jan 03 01:51:30 PM PST 24
Finished Jan 03 01:55:54 PM PST 24
Peak memory 249764 kb
Host smart-e5390794-8658-4425-9d74-a94f02d281d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90319892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.90319892
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3457155617
Short name T787
Test name
Test status
Simulation time 367254730117 ps
CPU time 135.5 seconds
Started Jan 03 01:51:30 PM PST 24
Finished Jan 03 01:54:08 PM PST 24
Peak memory 253380 kb
Host smart-6500d63c-a9b1-46fe-963e-ea54b2dbe9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457155617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3457155617
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3280886773
Short name T283
Test name
Test status
Simulation time 19587539961 ps
CPU time 27.57 seconds
Started Jan 03 01:51:31 PM PST 24
Finished Jan 03 01:52:20 PM PST 24
Peak memory 233096 kb
Host smart-7e792f80-debd-422f-8edf-7aef157fa79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280886773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3280886773
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.270474622
Short name T1720
Test name
Test status
Simulation time 2267034390 ps
CPU time 11.21 seconds
Started Jan 03 01:51:27 PM PST 24
Finished Jan 03 01:51:59 PM PST 24
Peak memory 236120 kb
Host smart-56a1d690-ff09-4722-8326-47e2d4433951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270474622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.270474622
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_intr.1023868317
Short name T740
Test name
Test status
Simulation time 7234922518 ps
CPU time 20.53 seconds
Started Jan 03 01:51:21 PM PST 24
Finished Jan 03 01:51:51 PM PST 24
Peak memory 219420 kb
Host smart-e8ec17c4-3906-4f04-bbe7-a060d58718c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023868317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intr.1023868317
Directory /workspace/3.spi_device_intr/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2270188903
Short name T333
Test name
Test status
Simulation time 5197750274 ps
CPU time 17.76 seconds
Started Jan 03 01:51:26 PM PST 24
Finished Jan 03 01:52:03 PM PST 24
Peak memory 244756 kb
Host smart-6ff2774a-9560-4edd-b211-8131a2e59594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270188903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2270188903
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2140417663
Short name T836
Test name
Test status
Simulation time 69938578 ps
CPU time 1.02 seconds
Started Jan 03 01:51:20 PM PST 24
Finished Jan 03 01:51:31 PM PST 24
Peak memory 218804 kb
Host smart-cf1fed8b-55bc-4f24-9fb6-ce40513008b6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140417663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2140417663
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3256340872
Short name T1742
Test name
Test status
Simulation time 18820060472 ps
CPU time 28.42 seconds
Started Jan 03 01:51:25 PM PST 24
Finished Jan 03 01:52:10 PM PST 24
Peak memory 241324 kb
Host smart-c66107fd-5f61-4338-8dd9-71fff1b74751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256340872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3256340872
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3520535689
Short name T23
Test name
Test status
Simulation time 7315567564 ps
CPU time 8.11 seconds
Started Jan 03 01:51:27 PM PST 24
Finished Jan 03 01:51:55 PM PST 24
Peak memory 233408 kb
Host smart-51afe469-4512-43de-85da-e84b4a72631b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520535689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3520535689
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_perf.994105582
Short name T918
Test name
Test status
Simulation time 70887349673 ps
CPU time 1821.74 seconds
Started Jan 03 01:51:24 PM PST 24
Finished Jan 03 02:21:59 PM PST 24
Peak memory 261352 kb
Host smart-1ca596ad-7a8e-40e3-b207-253b1402f9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994105582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_perf.994105582
Directory /workspace/3.spi_device_perf/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.3222364231
Short name T833
Test name
Test status
Simulation time 16243307 ps
CPU time 0.76 seconds
Started Jan 03 01:51:31 PM PST 24
Finished Jan 03 01:51:54 PM PST 24
Peak memory 216724 kb
Host smart-9cd082cb-778b-4af7-9a44-8074bef83b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222364231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.3222364231
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2717180310
Short name T186
Test name
Test status
Simulation time 116505571 ps
CPU time 3.86 seconds
Started Jan 03 01:51:31 PM PST 24
Finished Jan 03 01:51:57 PM PST 24
Peak memory 234316 kb
Host smart-6fdee043-531b-41d9-8de6-4a2b918ce288
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2717180310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2717180310
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_rx_async_fifo_reset.3978892079
Short name T1460
Test name
Test status
Simulation time 95743519 ps
CPU time 0.96 seconds
Started Jan 03 01:51:24 PM PST 24
Finished Jan 03 01:51:39 PM PST 24
Peak memory 208492 kb
Host smart-4a938404-3225-45b2-9c71-cb171635eba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978892079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_rx_async_fifo_reset.3978892079
Directory /workspace/3.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/3.spi_device_rx_timeout.2324382909
Short name T736
Test name
Test status
Simulation time 2346389102 ps
CPU time 5.46 seconds
Started Jan 03 01:51:24 PM PST 24
Finished Jan 03 01:51:43 PM PST 24
Peak memory 216912 kb
Host smart-f0f38c3e-d1ce-4cfd-9433-e9be232f0648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324382909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_rx_timeout.2324382909
Directory /workspace/3.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.190402258
Short name T107
Test name
Test status
Simulation time 63327352 ps
CPU time 1.11 seconds
Started Jan 03 01:51:30 PM PST 24
Finished Jan 03 01:51:53 PM PST 24
Peak memory 238228 kb
Host smart-a382f86e-ea73-408b-acf9-f834af872f64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190402258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.190402258
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_smoke.2279060405
Short name T1230
Test name
Test status
Simulation time 181423536 ps
CPU time 1.24 seconds
Started Jan 03 01:51:08 PM PST 24
Finished Jan 03 01:51:18 PM PST 24
Peak memory 216540 kb
Host smart-ae5141e5-7260-474e-b716-71deb707167e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279060405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_smoke.2279060405
Directory /workspace/3.spi_device_smoke/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3322941977
Short name T1372
Test name
Test status
Simulation time 13403307228 ps
CPU time 63.73 seconds
Started Jan 03 01:51:30 PM PST 24
Finished Jan 03 01:52:56 PM PST 24
Peak memory 217136 kb
Host smart-56931662-25f2-4ec1-beaa-b8228d9defe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322941977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3322941977
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1935243572
Short name T851
Test name
Test status
Simulation time 5284932787 ps
CPU time 10.56 seconds
Started Jan 03 01:51:23 PM PST 24
Finished Jan 03 01:51:46 PM PST 24
Peak memory 216788 kb
Host smart-999c641b-0043-49e2-9bce-ce3c111949b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935243572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1935243572
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1962984507
Short name T916
Test name
Test status
Simulation time 39909304 ps
CPU time 0.93 seconds
Started Jan 03 01:51:25 PM PST 24
Finished Jan 03 01:51:41 PM PST 24
Peak memory 208116 kb
Host smart-c200c131-6561-4d58-8b0f-fd139cb827a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962984507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1962984507
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1915294032
Short name T1049
Test name
Test status
Simulation time 269180823 ps
CPU time 0.97 seconds
Started Jan 03 01:51:25 PM PST 24
Finished Jan 03 01:51:42 PM PST 24
Peak memory 206924 kb
Host smart-f3a2bd8c-8e18-4783-be84-28d57b77d097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915294032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1915294032
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_tx_async_fifo_reset.2003271853
Short name T1213
Test name
Test status
Simulation time 22722702 ps
CPU time 0.76 seconds
Started Jan 03 01:51:32 PM PST 24
Finished Jan 03 01:51:55 PM PST 24
Peak memory 208428 kb
Host smart-ec826b6c-51bb-40a2-a4dd-c5ba106ff2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003271853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tx_async_fifo_reset.2003271853
Directory /workspace/3.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/3.spi_device_txrx.4005150798
Short name T1443
Test name
Test status
Simulation time 36177297267 ps
CPU time 303.39 seconds
Started Jan 03 01:51:25 PM PST 24
Finished Jan 03 01:56:46 PM PST 24
Peak memory 288560 kb
Host smart-5dbbee28-cc90-4cdd-9e10-84c4be26cb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005150798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_txrx.4005150798
Directory /workspace/3.spi_device_txrx/latest

Test location /workspace/coverage/default/3.spi_device_upload.2863821535
Short name T1017
Test name
Test status
Simulation time 13260097744 ps
CPU time 11.88 seconds
Started Jan 03 01:51:27 PM PST 24
Finished Jan 03 01:51:59 PM PST 24
Peak memory 219828 kb
Host smart-9e53584f-f3a8-44f4-8223-b2f84660eca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863821535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2863821535
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_abort.458780088
Short name T1392
Test name
Test status
Simulation time 46894865 ps
CPU time 0.75 seconds
Started Jan 03 01:59:34 PM PST 24
Finished Jan 03 01:59:42 PM PST 24
Peak memory 206624 kb
Host smart-65084ff7-3730-4d43-bc15-fbc6d2a766f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458780088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_abort.458780088
Directory /workspace/30.spi_device_abort/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1844256624
Short name T616
Test name
Test status
Simulation time 17574348 ps
CPU time 0.74 seconds
Started Jan 03 01:59:34 PM PST 24
Finished Jan 03 01:59:42 PM PST 24
Peak memory 206508 kb
Host smart-95b6f675-d456-4026-9c4b-52a50c9212ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844256624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1844256624
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_bit_transfer.1082621552
Short name T1000
Test name
Test status
Simulation time 841730271 ps
CPU time 2.63 seconds
Started Jan 03 01:59:31 PM PST 24
Finished Jan 03 01:59:38 PM PST 24
Peak memory 216864 kb
Host smart-b197dc18-3ed0-480a-9f26-cfc0fc727aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082621552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_bit_transfer.1082621552
Directory /workspace/30.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/30.spi_device_byte_transfer.3120143548
Short name T1312
Test name
Test status
Simulation time 314568771 ps
CPU time 2.37 seconds
Started Jan 03 01:59:11 PM PST 24
Finished Jan 03 01:59:14 PM PST 24
Peak memory 216836 kb
Host smart-d08982fc-e53c-4f84-9a01-e3b02d2ab72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120143548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_byte_transfer.3120143548
Directory /workspace/30.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3012047479
Short name T1097
Test name
Test status
Simulation time 293350796 ps
CPU time 4.15 seconds
Started Jan 03 01:59:30 PM PST 24
Finished Jan 03 01:59:38 PM PST 24
Peak memory 238132 kb
Host smart-50ce3e0e-47e0-4436-ac1e-2598e25790b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012047479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3012047479
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.804752451
Short name T1664
Test name
Test status
Simulation time 17887130 ps
CPU time 0.78 seconds
Started Jan 03 01:59:34 PM PST 24
Finished Jan 03 01:59:43 PM PST 24
Peak memory 206604 kb
Host smart-f8abd9b3-2e79-40e9-9df2-4e9fe78dc361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804752451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.804752451
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_dummy_item_extra_dly.1833632131
Short name T1243
Test name
Test status
Simulation time 10790202625 ps
CPU time 122.46 seconds
Started Jan 03 01:59:31 PM PST 24
Finished Jan 03 02:01:38 PM PST 24
Peak memory 241480 kb
Host smart-6fd6a945-07ab-40a8-9726-a52d9579a4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833632131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_dummy_item_extra_dly.1833632131
Directory /workspace/30.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/30.spi_device_extreme_fifo_size.3740498821
Short name T1048
Test name
Test status
Simulation time 412344723370 ps
CPU time 1732.62 seconds
Started Jan 03 01:59:38 PM PST 24
Finished Jan 03 02:28:39 PM PST 24
Peak memory 223212 kb
Host smart-b09034b9-5205-429d-98f2-a61189af4303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740498821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_extreme_fifo_size.3740498821
Directory /workspace/30.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/30.spi_device_fifo_full.416346421
Short name T815
Test name
Test status
Simulation time 37011427572 ps
CPU time 1081.92 seconds
Started Jan 03 01:59:33 PM PST 24
Finished Jan 03 02:17:40 PM PST 24
Peak memory 268384 kb
Host smart-1c0a0954-2f4b-4cb3-bc15-1a5a41a757f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416346421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_fifo_full.416346421
Directory /workspace/30.spi_device_fifo_full/latest

Test location /workspace/coverage/default/30.spi_device_fifo_underflow_overflow.4147928461
Short name T1257
Test name
Test status
Simulation time 110561450744 ps
CPU time 367.73 seconds
Started Jan 03 01:59:23 PM PST 24
Finished Jan 03 02:05:33 PM PST 24
Peak memory 361724 kb
Host smart-e4a8a48b-b017-49c3-89f6-16c52b88af57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147928461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_fifo_underflow_overf
low.4147928461
Directory /workspace/30.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3811251978
Short name T338
Test name
Test status
Simulation time 26131952275 ps
CPU time 98.96 seconds
Started Jan 03 01:59:23 PM PST 24
Finished Jan 03 02:01:04 PM PST 24
Peak memory 256348 kb
Host smart-4af2b28b-73da-482b-b13e-eb6e38c9fd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811251978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3811251978
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.528432838
Short name T279
Test name
Test status
Simulation time 148359828793 ps
CPU time 568.7 seconds
Started Jan 03 01:59:37 PM PST 24
Finished Jan 03 02:09:13 PM PST 24
Peak memory 270736 kb
Host smart-fffdcd33-3795-44c7-a4b9-01570bbfa694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528432838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.528432838
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2636496478
Short name T188
Test name
Test status
Simulation time 619412116 ps
CPU time 12.59 seconds
Started Jan 03 01:59:23 PM PST 24
Finished Jan 03 01:59:38 PM PST 24
Peak memory 245800 kb
Host smart-80cafcf4-44d7-44a0-a4ca-cb6cbec05c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636496478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2636496478
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2349727487
Short name T324
Test name
Test status
Simulation time 1340025004 ps
CPU time 2.59 seconds
Started Jan 03 01:59:31 PM PST 24
Finished Jan 03 01:59:39 PM PST 24
Peak memory 225064 kb
Host smart-258f1be4-3f8c-4bc5-835a-7f12750bf490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349727487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2349727487
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_intr.3100751909
Short name T1686
Test name
Test status
Simulation time 19198953477 ps
CPU time 38.18 seconds
Started Jan 03 01:59:30 PM PST 24
Finished Jan 03 02:00:13 PM PST 24
Peak memory 220140 kb
Host smart-1c06581b-77d2-4b1f-9c4d-9380d1e8a20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100751909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intr.3100751909
Directory /workspace/30.spi_device_intr/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2457083252
Short name T1321
Test name
Test status
Simulation time 1380868986 ps
CPU time 6.52 seconds
Started Jan 03 01:59:24 PM PST 24
Finished Jan 03 01:59:33 PM PST 24
Peak memory 221452 kb
Host smart-b64dd47a-7028-454c-aff2-a76e82f72f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457083252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2457083252
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2612522025
Short name T270
Test name
Test status
Simulation time 827216131 ps
CPU time 8.67 seconds
Started Jan 03 01:59:36 PM PST 24
Finished Jan 03 01:59:53 PM PST 24
Peak memory 222352 kb
Host smart-1060ceb8-766b-425d-ae4e-e2806529f632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612522025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2612522025
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.871808052
Short name T1411
Test name
Test status
Simulation time 42411863155 ps
CPU time 14.7 seconds
Started Jan 03 01:59:24 PM PST 24
Finished Jan 03 01:59:41 PM PST 24
Peak memory 218716 kb
Host smart-0402746a-d742-489f-bbef-f62cef5e15fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871808052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.871808052
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_perf.79498854
Short name T1504
Test name
Test status
Simulation time 37493696955 ps
CPU time 2293.23 seconds
Started Jan 03 01:59:26 PM PST 24
Finished Jan 03 02:37:42 PM PST 24
Peak memory 289520 kb
Host smart-af2cdc9d-dad6-42d9-9879-0d8521227c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79498854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_perf.79498854
Directory /workspace/30.spi_device_perf/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.13686923
Short name T1560
Test name
Test status
Simulation time 285579793 ps
CPU time 3.83 seconds
Started Jan 03 01:59:34 PM PST 24
Finished Jan 03 01:59:44 PM PST 24
Peak memory 219936 kb
Host smart-67f7312f-6ac4-434c-8682-4e96d158334f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=13686923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direc
t.13686923
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_rx_async_fifo_reset.306282749
Short name T1766
Test name
Test status
Simulation time 45831381 ps
CPU time 0.95 seconds
Started Jan 03 01:59:33 PM PST 24
Finished Jan 03 01:59:41 PM PST 24
Peak memory 208508 kb
Host smart-cd99f1a0-f625-4b10-a497-1822798fc657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306282749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_rx_async_fifo_reset.306282749
Directory /workspace/30.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/30.spi_device_rx_timeout.3133806848
Short name T1052
Test name
Test status
Simulation time 2625829835 ps
CPU time 6.16 seconds
Started Jan 03 01:59:37 PM PST 24
Finished Jan 03 01:59:51 PM PST 24
Peak memory 216820 kb
Host smart-6bff59f4-3066-436b-8508-042b82ca8429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133806848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_rx_timeout.3133806848
Directory /workspace/30.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/30.spi_device_smoke.1313902547
Short name T1591
Test name
Test status
Simulation time 144764129 ps
CPU time 1.03 seconds
Started Jan 03 01:58:44 PM PST 24
Finished Jan 03 01:58:58 PM PST 24
Peak memory 208420 kb
Host smart-5242c8f9-bd28-4014-8c43-c90f62d96e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313902547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_smoke.1313902547
Directory /workspace/30.spi_device_smoke/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1049593226
Short name T1645
Test name
Test status
Simulation time 578031102522 ps
CPU time 1855.17 seconds
Started Jan 03 01:59:33 PM PST 24
Finished Jan 03 02:30:35 PM PST 24
Peak memory 327628 kb
Host smart-c2239e9f-de6b-44f7-b9d1-fd29c9ecb76d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049593226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1049593226
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3377664628
Short name T1100
Test name
Test status
Simulation time 12928486394 ps
CPU time 51.95 seconds
Started Jan 03 01:59:32 PM PST 24
Finished Jan 03 02:00:29 PM PST 24
Peak memory 217200 kb
Host smart-af76f2db-5b97-4b7d-bbeb-a228bda3a22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377664628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3377664628
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1202520733
Short name T1715
Test name
Test status
Simulation time 1736241730 ps
CPU time 11.29 seconds
Started Jan 03 01:59:30 PM PST 24
Finished Jan 03 01:59:46 PM PST 24
Peak memory 216816 kb
Host smart-6a7f4d2b-1f00-4deb-9366-3f5bd50fa79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202520733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1202520733
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.540066614
Short name T1769
Test name
Test status
Simulation time 668785033 ps
CPU time 7.78 seconds
Started Jan 03 01:59:34 PM PST 24
Finished Jan 03 01:59:48 PM PST 24
Peak memory 216796 kb
Host smart-b43b0e27-7a0a-4e83-9be2-c26fc384bcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540066614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.540066614
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.4030475655
Short name T534
Test name
Test status
Simulation time 105295749 ps
CPU time 1.06 seconds
Started Jan 03 01:59:12 PM PST 24
Finished Jan 03 01:59:15 PM PST 24
Peak memory 208056 kb
Host smart-7154d224-a0ee-4c86-a7e5-768933a1a2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030475655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.4030475655
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_tx_async_fifo_reset.1793605844
Short name T1225
Test name
Test status
Simulation time 17039736 ps
CPU time 0.78 seconds
Started Jan 03 01:59:34 PM PST 24
Finished Jan 03 01:59:42 PM PST 24
Peak memory 208512 kb
Host smart-25d53298-9bd6-4abe-98de-ada72b8bd58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793605844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tx_async_fifo_reset.1793605844
Directory /workspace/30.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/30.spi_device_txrx.586353369
Short name T636
Test name
Test status
Simulation time 167313731290 ps
CPU time 243.7 seconds
Started Jan 03 01:58:41 PM PST 24
Finished Jan 03 02:02:57 PM PST 24
Peak memory 266248 kb
Host smart-0b077e95-8be6-4ad6-9fbc-115ed73312b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586353369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_txrx.586353369
Directory /workspace/30.spi_device_txrx/latest

Test location /workspace/coverage/default/30.spi_device_upload.3603392606
Short name T1649
Test name
Test status
Simulation time 880188060 ps
CPU time 4.49 seconds
Started Jan 03 01:59:26 PM PST 24
Finished Jan 03 01:59:33 PM PST 24
Peak memory 240300 kb
Host smart-5258ca26-77c9-4d3f-abdc-a4118bf5f2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603392606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3603392606
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_abort.3198042280
Short name T1106
Test name
Test status
Simulation time 15247079 ps
CPU time 0.76 seconds
Started Jan 03 01:59:34 PM PST 24
Finished Jan 03 01:59:42 PM PST 24
Peak memory 206648 kb
Host smart-cf2c2c1a-deb0-4713-b838-68a48db82cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198042280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_abort.3198042280
Directory /workspace/31.spi_device_abort/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.565673208
Short name T1037
Test name
Test status
Simulation time 11697865 ps
CPU time 0.7 seconds
Started Jan 03 01:59:31 PM PST 24
Finished Jan 03 01:59:37 PM PST 24
Peak memory 206616 kb
Host smart-3deb3b75-eb34-499a-96a5-9a0045c7a2cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565673208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.565673208
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_bit_transfer.2852814851
Short name T1499
Test name
Test status
Simulation time 152068752 ps
CPU time 2.37 seconds
Started Jan 03 01:59:26 PM PST 24
Finished Jan 03 01:59:31 PM PST 24
Peak memory 216808 kb
Host smart-80d18b5c-1cfb-4a5e-9e6a-5ff7a0e5c70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852814851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_bit_transfer.2852814851
Directory /workspace/31.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/31.spi_device_byte_transfer.2952303774
Short name T1348
Test name
Test status
Simulation time 250755234 ps
CPU time 3.28 seconds
Started Jan 03 01:59:10 PM PST 24
Finished Jan 03 01:59:15 PM PST 24
Peak memory 216740 kb
Host smart-226f07a2-fcfe-4819-90a6-6dc7622c24a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952303774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_byte_transfer.2952303774
Directory /workspace/31.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2295926084
Short name T949
Test name
Test status
Simulation time 820586409 ps
CPU time 3.69 seconds
Started Jan 03 01:59:30 PM PST 24
Finished Jan 03 01:59:38 PM PST 24
Peak memory 224976 kb
Host smart-4518cdf4-ff15-412e-a906-17983f6edbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295926084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2295926084
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1535573090
Short name T752
Test name
Test status
Simulation time 14480960 ps
CPU time 0.75 seconds
Started Jan 03 01:59:30 PM PST 24
Finished Jan 03 01:59:35 PM PST 24
Peak memory 206608 kb
Host smart-8012d1bf-0564-47ee-bb8b-9042793f8e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535573090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1535573090
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_dummy_item_extra_dly.1224696437
Short name T1451
Test name
Test status
Simulation time 108971663881 ps
CPU time 1049.56 seconds
Started Jan 03 01:59:17 PM PST 24
Finished Jan 03 02:16:48 PM PST 24
Peak memory 249748 kb
Host smart-07e0bdbd-7ec7-4041-b07e-d59eca8d58f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224696437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_dummy_item_extra_dly.1224696437
Directory /workspace/31.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/31.spi_device_extreme_fifo_size.2298467574
Short name T301
Test name
Test status
Simulation time 64564891968 ps
CPU time 808.5 seconds
Started Jan 03 01:59:34 PM PST 24
Finished Jan 03 02:13:10 PM PST 24
Peak memory 219804 kb
Host smart-616d8f56-66c0-47df-9db4-eb06eeaea6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298467574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_extreme_fifo_size.2298467574
Directory /workspace/31.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/31.spi_device_fifo_full.3661016232
Short name T841
Test name
Test status
Simulation time 31598247552 ps
CPU time 687.01 seconds
Started Jan 03 01:59:25 PM PST 24
Finished Jan 03 02:10:55 PM PST 24
Peak memory 269236 kb
Host smart-df20884e-3df9-4e44-aa6a-577c85500c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661016232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_fifo_full.3661016232
Directory /workspace/31.spi_device_fifo_full/latest

Test location /workspace/coverage/default/31.spi_device_fifo_underflow_overflow.191340537
Short name T1496
Test name
Test status
Simulation time 145951842488 ps
CPU time 440.09 seconds
Started Jan 03 01:59:24 PM PST 24
Finished Jan 03 02:06:46 PM PST 24
Peak memory 533828 kb
Host smart-8e4a3830-bd6b-43cf-bf12-4466474ad98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191340537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_fifo_underflow_overfl
ow.191340537
Directory /workspace/31.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3067418677
Short name T371
Test name
Test status
Simulation time 62285909448 ps
CPU time 170.41 seconds
Started Jan 03 01:59:33 PM PST 24
Finished Jan 03 02:02:29 PM PST 24
Peak memory 255356 kb
Host smart-b589a22b-0ecf-4e0f-aa28-1694d27f7c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067418677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3067418677
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1863438987
Short name T227
Test name
Test status
Simulation time 45946175710 ps
CPU time 352.12 seconds
Started Jan 03 01:59:37 PM PST 24
Finished Jan 03 02:05:37 PM PST 24
Peak memory 252808 kb
Host smart-88aafe89-8354-478a-9730-f3f403481aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863438987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1863438987
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.132584967
Short name T973
Test name
Test status
Simulation time 14206069698 ps
CPU time 19.95 seconds
Started Jan 03 01:59:32 PM PST 24
Finished Jan 03 01:59:58 PM PST 24
Peak memory 225312 kb
Host smart-b63d5296-d078-49f4-85ba-2680ec83e740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132584967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.132584967
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.341455969
Short name T1193
Test name
Test status
Simulation time 1101459714 ps
CPU time 3.56 seconds
Started Jan 03 01:59:30 PM PST 24
Finished Jan 03 01:59:38 PM PST 24
Peak memory 219868 kb
Host smart-323e0825-6449-4422-9fed-a948df03b746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341455969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.341455969
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_intr.3519028306
Short name T666
Test name
Test status
Simulation time 3104815542 ps
CPU time 12.77 seconds
Started Jan 03 01:59:29 PM PST 24
Finished Jan 03 01:59:46 PM PST 24
Peak memory 217052 kb
Host smart-6f48bc34-ab84-485f-aa2f-e676801feab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519028306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intr.3519028306
Directory /workspace/31.spi_device_intr/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.598548683
Short name T1730
Test name
Test status
Simulation time 10258093607 ps
CPU time 22.19 seconds
Started Jan 03 01:59:33 PM PST 24
Finished Jan 03 02:00:00 PM PST 24
Peak memory 256772 kb
Host smart-2d55fe8e-1524-404d-a29e-effe98b02c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598548683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.598548683
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.926718004
Short name T1498
Test name
Test status
Simulation time 39794155708 ps
CPU time 31.06 seconds
Started Jan 03 01:59:25 PM PST 24
Finished Jan 03 01:59:59 PM PST 24
Peak memory 232108 kb
Host smart-3936ebbf-30cf-43b0-8d91-bad888412e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926718004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.926718004
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2182213709
Short name T273
Test name
Test status
Simulation time 11476984272 ps
CPU time 11.81 seconds
Started Jan 03 01:59:34 PM PST 24
Finished Jan 03 01:59:52 PM PST 24
Peak memory 239628 kb
Host smart-cb1a8083-2ca6-4f6e-81fb-eb3a3c0d8543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182213709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2182213709
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_perf.514353758
Short name T518
Test name
Test status
Simulation time 250771507708 ps
CPU time 1192 seconds
Started Jan 03 01:59:10 PM PST 24
Finished Jan 03 02:19:04 PM PST 24
Peak memory 267720 kb
Host smart-90a3f4f5-1386-4dff-98f9-e4cf94e12fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514353758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_perf.514353758
Directory /workspace/31.spi_device_perf/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3303394474
Short name T770
Test name
Test status
Simulation time 324502607 ps
CPU time 3.91 seconds
Started Jan 03 01:59:31 PM PST 24
Finished Jan 03 01:59:39 PM PST 24
Peak memory 218988 kb
Host smart-4f517e00-5b77-4de4-8e53-751a52f70773
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3303394474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3303394474
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_rx_async_fifo_reset.3382213382
Short name T663
Test name
Test status
Simulation time 18522347 ps
CPU time 0.85 seconds
Started Jan 03 01:59:29 PM PST 24
Finished Jan 03 01:59:34 PM PST 24
Peak memory 208476 kb
Host smart-b8f8ce7f-7276-46e9-ace1-84c6aebb0d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382213382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_rx_async_fifo_reset.3382213382
Directory /workspace/31.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/31.spi_device_rx_timeout.2104165438
Short name T1142
Test name
Test status
Simulation time 668285728 ps
CPU time 5.02 seconds
Started Jan 03 01:59:30 PM PST 24
Finished Jan 03 01:59:40 PM PST 24
Peak memory 216880 kb
Host smart-13b25aa6-6611-418d-bb95-5c9e8bde3c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104165438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_rx_timeout.2104165438
Directory /workspace/31.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/31.spi_device_smoke.3423096748
Short name T780
Test name
Test status
Simulation time 104399410 ps
CPU time 1.05 seconds
Started Jan 03 01:59:33 PM PST 24
Finished Jan 03 01:59:41 PM PST 24
Peak memory 216532 kb
Host smart-39c235bf-8730-43b5-bcde-498224c11177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423096748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_smoke.3423096748
Directory /workspace/31.spi_device_smoke/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2044151846
Short name T1661
Test name
Test status
Simulation time 7865069978 ps
CPU time 32.9 seconds
Started Jan 03 01:59:23 PM PST 24
Finished Jan 03 01:59:59 PM PST 24
Peak memory 216976 kb
Host smart-15d9cad8-17b6-4185-964f-b813d2f1a0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044151846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2044151846
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3696181121
Short name T1191
Test name
Test status
Simulation time 28382663045 ps
CPU time 23.13 seconds
Started Jan 03 01:59:13 PM PST 24
Finished Jan 03 01:59:38 PM PST 24
Peak memory 217864 kb
Host smart-0897d4ba-3020-42d5-a8f9-3cd2bf9537a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696181121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3696181121
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1564340278
Short name T1108
Test name
Test status
Simulation time 56703744 ps
CPU time 1.79 seconds
Started Jan 03 01:59:25 PM PST 24
Finished Jan 03 01:59:30 PM PST 24
Peak memory 216920 kb
Host smart-7c2de18c-40bf-4d2b-a4af-483753c158bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564340278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1564340278
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.971169468
Short name T717
Test name
Test status
Simulation time 432248747 ps
CPU time 0.84 seconds
Started Jan 03 01:59:25 PM PST 24
Finished Jan 03 01:59:29 PM PST 24
Peak memory 206924 kb
Host smart-d3338cc4-bc22-4116-b2a6-957ff3cc2951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971169468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.971169468
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_tx_async_fifo_reset.3790927416
Short name T1445
Test name
Test status
Simulation time 19364777 ps
CPU time 0.79 seconds
Started Jan 03 01:59:24 PM PST 24
Finished Jan 03 01:59:28 PM PST 24
Peak memory 208460 kb
Host smart-9aadac9b-e2f0-48a3-ab35-472b53d0e16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790927416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tx_async_fifo_reset.3790927416
Directory /workspace/31.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/31.spi_device_txrx.233184272
Short name T1163
Test name
Test status
Simulation time 28055853862 ps
CPU time 287.1 seconds
Started Jan 03 01:59:34 PM PST 24
Finished Jan 03 02:04:27 PM PST 24
Peak memory 249808 kb
Host smart-d8dc69a3-5e31-4502-995b-26b58bace995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233184272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_txrx.233184272
Directory /workspace/31.spi_device_txrx/latest

Test location /workspace/coverage/default/31.spi_device_upload.1752946248
Short name T233
Test name
Test status
Simulation time 6695003611 ps
CPU time 14.39 seconds
Started Jan 03 01:59:37 PM PST 24
Finished Jan 03 01:59:59 PM PST 24
Peak memory 225136 kb
Host smart-248901e8-3bba-4e0b-9d1e-e270f037554a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752946248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1752946248
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_abort.2214675195
Short name T875
Test name
Test status
Simulation time 58749953 ps
CPU time 0.74 seconds
Started Jan 03 01:59:35 PM PST 24
Finished Jan 03 01:59:44 PM PST 24
Peak memory 206604 kb
Host smart-947a7d55-a1b9-4a0b-932d-0bfd1225214a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214675195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_abort.2214675195
Directory /workspace/32.spi_device_abort/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2143907889
Short name T1659
Test name
Test status
Simulation time 117060233 ps
CPU time 0.7 seconds
Started Jan 03 01:59:25 PM PST 24
Finished Jan 03 01:59:29 PM PST 24
Peak memory 206616 kb
Host smart-b511d228-baa1-42c0-a17a-9e33c0856557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143907889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2143907889
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_bit_transfer.2946437710
Short name T1283
Test name
Test status
Simulation time 84573328 ps
CPU time 2.55 seconds
Started Jan 03 01:59:39 PM PST 24
Finished Jan 03 01:59:49 PM PST 24
Peak memory 216792 kb
Host smart-0b84bc17-e57a-4edd-a681-589887305b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946437710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_bit_transfer.2946437710
Directory /workspace/32.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/32.spi_device_byte_transfer.626291239
Short name T1672
Test name
Test status
Simulation time 1410735355 ps
CPU time 3.29 seconds
Started Jan 03 01:59:38 PM PST 24
Finished Jan 03 01:59:50 PM PST 24
Peak memory 216748 kb
Host smart-dce5ad89-110d-48f7-8639-561503267459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626291239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_byte_transfer.626291239
Directory /workspace/32.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.132707950
Short name T890
Test name
Test status
Simulation time 139379746 ps
CPU time 3.28 seconds
Started Jan 03 01:59:55 PM PST 24
Finished Jan 03 02:00:02 PM PST 24
Peak memory 241520 kb
Host smart-47da86f4-8424-4f67-86d0-d0662ecd95c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132707950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.132707950
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.52079880
Short name T643
Test name
Test status
Simulation time 26915544 ps
CPU time 0.76 seconds
Started Jan 03 01:59:33 PM PST 24
Finished Jan 03 01:59:40 PM PST 24
Peak memory 206560 kb
Host smart-edee5946-9866-4928-a2b5-494498f331ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52079880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.52079880
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_dummy_item_extra_dly.2413594227
Short name T7
Test name
Test status
Simulation time 99986804237 ps
CPU time 528.58 seconds
Started Jan 03 01:59:36 PM PST 24
Finished Jan 03 02:08:32 PM PST 24
Peak memory 239968 kb
Host smart-a753bee8-e900-4e11-95fd-8b0432781736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413594227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_dummy_item_extra_dly.2413594227
Directory /workspace/32.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/32.spi_device_extreme_fifo_size.1554808486
Short name T1023
Test name
Test status
Simulation time 61304162190 ps
CPU time 812.29 seconds
Started Jan 03 01:59:35 PM PST 24
Finished Jan 03 02:13:15 PM PST 24
Peak memory 220580 kb
Host smart-51370540-321a-463e-a08e-a48e59714a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554808486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_extreme_fifo_size.1554808486
Directory /workspace/32.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/32.spi_device_fifo_full.1555585363
Short name T1396
Test name
Test status
Simulation time 96327060144 ps
CPU time 966.59 seconds
Started Jan 03 01:59:38 PM PST 24
Finished Jan 03 02:15:53 PM PST 24
Peak memory 300048 kb
Host smart-b9801caa-7956-42d1-b9f9-11ef8e9bfe41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555585363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_fifo_full.1555585363
Directory /workspace/32.spi_device_fifo_full/latest

Test location /workspace/coverage/default/32.spi_device_fifo_underflow_overflow.3042032498
Short name T1094
Test name
Test status
Simulation time 68972502875 ps
CPU time 282.1 seconds
Started Jan 03 01:59:32 PM PST 24
Finished Jan 03 02:04:20 PM PST 24
Peak memory 363660 kb
Host smart-96650f72-a510-47d8-a478-c8ec6e6918d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042032498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_fifo_underflow_overf
low.3042032498
Directory /workspace/32.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2630892708
Short name T1623
Test name
Test status
Simulation time 3076180051 ps
CPU time 29.83 seconds
Started Jan 03 01:59:37 PM PST 24
Finished Jan 03 02:00:15 PM PST 24
Peak memory 221944 kb
Host smart-7f32edf2-771f-48a9-89e5-f60b7a73eedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630892708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2630892708
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3230625828
Short name T962
Test name
Test status
Simulation time 5367562700 ps
CPU time 118.52 seconds
Started Jan 03 01:59:38 PM PST 24
Finished Jan 03 02:01:45 PM PST 24
Peak memory 274172 kb
Host smart-49e7f340-a3f2-43f4-b2a7-bc6eb6c6e588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230625828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3230625828
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3324630766
Short name T1428
Test name
Test status
Simulation time 8760556262 ps
CPU time 35.33 seconds
Started Jan 03 01:59:57 PM PST 24
Finished Jan 03 02:00:38 PM PST 24
Peak memory 229720 kb
Host smart-817c4406-763f-4d59-8b5d-cb738a578d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324630766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3324630766
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2948428230
Short name T16
Test name
Test status
Simulation time 5383379023 ps
CPU time 9.5 seconds
Started Jan 03 01:59:38 PM PST 24
Finished Jan 03 01:59:56 PM PST 24
Peak memory 224996 kb
Host smart-7703b523-2f1b-4450-a625-f3345190d102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948428230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2948428230
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_intr.995469753
Short name T1110
Test name
Test status
Simulation time 25192853235 ps
CPU time 44.7 seconds
Started Jan 03 01:59:37 PM PST 24
Finished Jan 03 02:00:30 PM PST 24
Peak memory 233324 kb
Host smart-feb99f6a-fa7c-4039-a04d-dfedff45f1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995469753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intr.995469753
Directory /workspace/32.spi_device_intr/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1746268410
Short name T353
Test name
Test status
Simulation time 786781737 ps
CPU time 3.16 seconds
Started Jan 03 01:59:55 PM PST 24
Finished Jan 03 02:00:00 PM PST 24
Peak memory 218200 kb
Host smart-ab38c2d9-def1-467e-acb9-1e1152c12f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746268410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1746268410
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3262627541
Short name T211
Test name
Test status
Simulation time 7317120689 ps
CPU time 19.47 seconds
Started Jan 03 01:59:38 PM PST 24
Finished Jan 03 02:00:06 PM PST 24
Peak memory 241552 kb
Host smart-b58919d9-b4fa-4254-bed8-43057cfb8bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262627541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3262627541
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.751004743
Short name T1080
Test name
Test status
Simulation time 65574749537 ps
CPU time 26.53 seconds
Started Jan 03 01:59:58 PM PST 24
Finished Jan 03 02:00:29 PM PST 24
Peak memory 232608 kb
Host smart-446417d9-b56e-4dbc-a73b-235faeb87d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751004743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.751004743
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_perf.1141951729
Short name T793
Test name
Test status
Simulation time 53521087583 ps
CPU time 1254.7 seconds
Started Jan 03 01:59:37 PM PST 24
Finished Jan 03 02:20:40 PM PST 24
Peak memory 249764 kb
Host smart-dc905ef2-28aa-4021-9dea-2f34d71031c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141951729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_perf.1141951729
Directory /workspace/32.spi_device_perf/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3470681115
Short name T1633
Test name
Test status
Simulation time 1025261620 ps
CPU time 3.99 seconds
Started Jan 03 01:59:54 PM PST 24
Finished Jan 03 02:00:00 PM PST 24
Peak memory 218584 kb
Host smart-85ec06cd-ae4b-4117-9fe8-fff53f9df99f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3470681115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3470681115
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_rx_async_fifo_reset.2719168126
Short name T1764
Test name
Test status
Simulation time 72866054 ps
CPU time 0.95 seconds
Started Jan 03 01:59:39 PM PST 24
Finished Jan 03 01:59:48 PM PST 24
Peak memory 208516 kb
Host smart-d8814038-e3e3-489a-bdf1-2a76f1f81c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719168126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_rx_async_fifo_reset.2719168126
Directory /workspace/32.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/32.spi_device_rx_timeout.2341258191
Short name T834
Test name
Test status
Simulation time 1561544624 ps
CPU time 6.14 seconds
Started Jan 03 01:59:38 PM PST 24
Finished Jan 03 01:59:53 PM PST 24
Peak memory 216848 kb
Host smart-359d48ec-0ad9-4614-8f00-241a86646788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341258191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_rx_timeout.2341258191
Directory /workspace/32.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/32.spi_device_smoke.3020341264
Short name T1339
Test name
Test status
Simulation time 104952129 ps
CPU time 0.93 seconds
Started Jan 03 01:59:37 PM PST 24
Finished Jan 03 01:59:46 PM PST 24
Peak memory 207784 kb
Host smart-f6e6b6e7-3c38-4df8-80c1-aaef5449f8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020341264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_smoke.3020341264
Directory /workspace/32.spi_device_smoke/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1361203627
Short name T1631
Test name
Test status
Simulation time 157815393605 ps
CPU time 180.12 seconds
Started Jan 03 01:59:41 PM PST 24
Finished Jan 03 02:02:52 PM PST 24
Peak memory 266608 kb
Host smart-4f35a62a-da11-45a5-a6b8-b4effb4777c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361203627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1361203627
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3237510420
Short name T928
Test name
Test status
Simulation time 9525453654 ps
CPU time 21.82 seconds
Started Jan 03 01:59:38 PM PST 24
Finished Jan 03 02:00:08 PM PST 24
Peak memory 216860 kb
Host smart-65a30034-92e3-4cbc-ba32-fe988d153b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237510420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3237510420
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3909593887
Short name T737
Test name
Test status
Simulation time 9877944406 ps
CPU time 21.31 seconds
Started Jan 03 01:59:38 PM PST 24
Finished Jan 03 02:00:08 PM PST 24
Peak memory 216888 kb
Host smart-203177d6-6c29-4ac1-91fa-e3ba231099c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909593887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3909593887
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.853900903
Short name T1301
Test name
Test status
Simulation time 2355751867 ps
CPU time 6.31 seconds
Started Jan 03 01:59:56 PM PST 24
Finished Jan 03 02:00:08 PM PST 24
Peak memory 216836 kb
Host smart-27805e56-d461-44bc-9492-68ec6ffe9e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853900903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.853900903
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.564512440
Short name T1726
Test name
Test status
Simulation time 27233899 ps
CPU time 0.77 seconds
Started Jan 03 01:59:39 PM PST 24
Finished Jan 03 01:59:48 PM PST 24
Peak memory 206856 kb
Host smart-7a1be4f3-d3bc-4140-819f-5061e5d60948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564512440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.564512440
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_tx_async_fifo_reset.3699013788
Short name T652
Test name
Test status
Simulation time 129360171 ps
CPU time 0.8 seconds
Started Jan 03 01:59:38 PM PST 24
Finished Jan 03 01:59:47 PM PST 24
Peak memory 208488 kb
Host smart-07a253cc-18e2-4525-9e60-08e16dddc1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699013788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tx_async_fifo_reset.3699013788
Directory /workspace/32.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/32.spi_device_txrx.936282476
Short name T1513
Test name
Test status
Simulation time 4363053293 ps
CPU time 51.96 seconds
Started Jan 03 01:59:38 PM PST 24
Finished Jan 03 02:00:38 PM PST 24
Peak memory 249696 kb
Host smart-254454c3-921e-42ec-84c5-4b0b24ec94df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936282476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_txrx.936282476
Directory /workspace/32.spi_device_txrx/latest

Test location /workspace/coverage/default/32.spi_device_upload.660775614
Short name T346
Test name
Test status
Simulation time 15828818925 ps
CPU time 13.99 seconds
Started Jan 03 02:00:07 PM PST 24
Finished Jan 03 02:00:21 PM PST 24
Peak memory 241588 kb
Host smart-97d90800-43f1-4310-ae5c-35c38b1718b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660775614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.660775614
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_abort.3297203090
Short name T1620
Test name
Test status
Simulation time 72361456 ps
CPU time 0.73 seconds
Started Jan 03 02:00:21 PM PST 24
Finished Jan 03 02:00:32 PM PST 24
Peak memory 206652 kb
Host smart-8eba17b3-a94f-4c65-a651-a89c39c38dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297203090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_abort.3297203090
Directory /workspace/33.spi_device_abort/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1450888166
Short name T593
Test name
Test status
Simulation time 11912166 ps
CPU time 0.73 seconds
Started Jan 03 02:00:19 PM PST 24
Finished Jan 03 02:00:27 PM PST 24
Peak memory 206492 kb
Host smart-4f7178f9-1e01-4bee-a210-5b95972cfd23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450888166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1450888166
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_bit_transfer.3889393491
Short name T1572
Test name
Test status
Simulation time 868919510 ps
CPU time 3.01 seconds
Started Jan 03 02:00:24 PM PST 24
Finished Jan 03 02:00:39 PM PST 24
Peak memory 216832 kb
Host smart-c3d88ad8-9559-44f5-9b67-44c0f8f723fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889393491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_bit_transfer.3889393491
Directory /workspace/33.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/33.spi_device_byte_transfer.3470423283
Short name T1444
Test name
Test status
Simulation time 177895213 ps
CPU time 3.25 seconds
Started Jan 03 01:59:30 PM PST 24
Finished Jan 03 01:59:38 PM PST 24
Peak memory 216684 kb
Host smart-5be68e4e-92b6-408c-b936-315e31bd07b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470423283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_byte_transfer.3470423283
Directory /workspace/33.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1922456952
Short name T326
Test name
Test status
Simulation time 1449158055 ps
CPU time 5.29 seconds
Started Jan 03 02:00:21 PM PST 24
Finished Jan 03 02:00:36 PM PST 24
Peak memory 238896 kb
Host smart-74e32210-b8bc-4e2e-b137-2ee38ce8ffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922456952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1922456952
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1856001368
Short name T773
Test name
Test status
Simulation time 41097129 ps
CPU time 0.81 seconds
Started Jan 03 01:59:28 PM PST 24
Finished Jan 03 01:59:31 PM PST 24
Peak memory 207600 kb
Host smart-29fd5f3d-0faa-49b5-9bea-cadd5a3ba9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856001368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1856001368
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_dummy_item_extra_dly.1823929715
Short name T1638
Test name
Test status
Simulation time 37510007455 ps
CPU time 184.13 seconds
Started Jan 03 01:59:33 PM PST 24
Finished Jan 03 02:02:43 PM PST 24
Peak memory 291744 kb
Host smart-dae02876-7909-45d8-a4db-ab0109c0f002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823929715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_dummy_item_extra_dly.1823929715
Directory /workspace/33.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/33.spi_device_extreme_fifo_size.1006291565
Short name T762
Test name
Test status
Simulation time 254465878459 ps
CPU time 2568.46 seconds
Started Jan 03 01:59:24 PM PST 24
Finished Jan 03 02:42:15 PM PST 24
Peak memory 225200 kb
Host smart-2fa04e6a-2f08-46dc-8d5a-6f181dfef31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006291565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_extreme_fifo_size.1006291565
Directory /workspace/33.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/33.spi_device_fifo_full.1727064023
Short name T1407
Test name
Test status
Simulation time 87581904993 ps
CPU time 415.66 seconds
Started Jan 03 01:59:32 PM PST 24
Finished Jan 03 02:06:33 PM PST 24
Peak memory 298660 kb
Host smart-8b9743a7-c192-47b3-b3b6-f9568322d73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727064023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_fifo_full.1727064023
Directory /workspace/33.spi_device_fifo_full/latest

Test location /workspace/coverage/default/33.spi_device_fifo_underflow_overflow.1901673278
Short name T66
Test name
Test status
Simulation time 80574827186 ps
CPU time 480.27 seconds
Started Jan 03 01:59:33 PM PST 24
Finished Jan 03 02:07:40 PM PST 24
Peak memory 429044 kb
Host smart-480c2bf1-fa3e-420b-9ee5-75d17529621c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901673278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_fifo_underflow_overf
low.1901673278
Directory /workspace/33.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3900825854
Short name T379
Test name
Test status
Simulation time 146838078765 ps
CPU time 182.77 seconds
Started Jan 03 02:00:20 PM PST 24
Finished Jan 03 02:03:31 PM PST 24
Peak memory 257956 kb
Host smart-fc2440c0-eb1e-41aa-a001-f92e3230182d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900825854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3900825854
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.158857809
Short name T664
Test name
Test status
Simulation time 1765685937 ps
CPU time 18.97 seconds
Started Jan 03 02:00:22 PM PST 24
Finished Jan 03 02:00:52 PM PST 24
Peak memory 250620 kb
Host smart-2c3e3a9a-02c1-44be-84d4-7a6171aa348b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158857809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.158857809
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.4091575066
Short name T913
Test name
Test status
Simulation time 290397801 ps
CPU time 3.16 seconds
Started Jan 03 02:00:17 PM PST 24
Finished Jan 03 02:00:25 PM PST 24
Peak memory 225000 kb
Host smart-3475677f-589b-41a2-9bec-664a45e52cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091575066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4091575066
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_intr.2172895050
Short name T804
Test name
Test status
Simulation time 99116087116 ps
CPU time 42.57 seconds
Started Jan 03 01:59:27 PM PST 24
Finished Jan 03 02:00:12 PM PST 24
Peak memory 238772 kb
Host smart-548f88db-87cf-4d22-b2ef-cdbd88958152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172895050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intr.2172895050
Directory /workspace/33.spi_device_intr/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1497348189
Short name T285
Test name
Test status
Simulation time 1903382000 ps
CPU time 17.55 seconds
Started Jan 03 02:00:34 PM PST 24
Finished Jan 03 02:01:05 PM PST 24
Peak memory 257792 kb
Host smart-85721f29-1650-4441-ac4f-dcad63643667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497348189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1497348189
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.162741068
Short name T1302
Test name
Test status
Simulation time 1883461710 ps
CPU time 10.42 seconds
Started Jan 03 02:00:18 PM PST 24
Finished Jan 03 02:00:35 PM PST 24
Peak memory 249692 kb
Host smart-598a775e-2224-467b-a1db-ccd4f929ce05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162741068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.162741068
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3246580353
Short name T1186
Test name
Test status
Simulation time 43054639298 ps
CPU time 33.93 seconds
Started Jan 03 02:00:19 PM PST 24
Finished Jan 03 02:01:00 PM PST 24
Peak memory 241268 kb
Host smart-c6dde7f5-0e9d-46bf-920d-ad531d2dda55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246580353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3246580353
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_perf.2597157792
Short name T553
Test name
Test status
Simulation time 34097955840 ps
CPU time 151.67 seconds
Started Jan 03 01:59:34 PM PST 24
Finished Jan 03 02:02:12 PM PST 24
Peak memory 237672 kb
Host smart-3a753392-56c8-4f30-aeca-5c61be31b904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597157792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_perf.2597157792
Directory /workspace/33.spi_device_perf/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3449762597
Short name T1072
Test name
Test status
Simulation time 164217023 ps
CPU time 3.8 seconds
Started Jan 03 02:00:20 PM PST 24
Finished Jan 03 02:00:31 PM PST 24
Peak memory 220712 kb
Host smart-ccf8c3ec-ef18-45f8-ae92-423b430e4d5a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3449762597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3449762597
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_rx_async_fifo_reset.1593376911
Short name T822
Test name
Test status
Simulation time 56726688 ps
CPU time 0.85 seconds
Started Jan 03 02:00:49 PM PST 24
Finished Jan 03 02:01:00 PM PST 24
Peak memory 208572 kb
Host smart-88e09421-2228-4f1a-8029-811d60232fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593376911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_rx_async_fifo_reset.1593376911
Directory /workspace/33.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/33.spi_device_rx_timeout.3302945039
Short name T129
Test name
Test status
Simulation time 1257990344 ps
CPU time 6.11 seconds
Started Jan 03 02:00:25 PM PST 24
Finished Jan 03 02:00:44 PM PST 24
Peak memory 216808 kb
Host smart-84928ae1-b097-4a90-abd2-0a9b3019d056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302945039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_rx_timeout.3302945039
Directory /workspace/33.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/33.spi_device_smoke.776302357
Short name T1063
Test name
Test status
Simulation time 67131088 ps
CPU time 0.97 seconds
Started Jan 03 01:59:56 PM PST 24
Finished Jan 03 02:00:00 PM PST 24
Peak memory 208000 kb
Host smart-14cd33a6-58ed-4e0f-8737-185bf213ff4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776302357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_smoke.776302357
Directory /workspace/33.spi_device_smoke/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2824361774
Short name T275
Test name
Test status
Simulation time 371667911280 ps
CPU time 932.48 seconds
Started Jan 03 02:00:14 PM PST 24
Finished Jan 03 02:15:49 PM PST 24
Peak memory 293440 kb
Host smart-47e25dd8-f946-4922-9744-fcf48335eff7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824361774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2824361774
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2975674322
Short name T108
Test name
Test status
Simulation time 14853358800 ps
CPU time 58.58 seconds
Started Jan 03 02:00:23 PM PST 24
Finished Jan 03 02:01:34 PM PST 24
Peak memory 221032 kb
Host smart-29252ee8-9754-429c-bafe-4f48c77779bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975674322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2975674322
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1774121515
Short name T977
Test name
Test status
Simulation time 12854573717 ps
CPU time 10.85 seconds
Started Jan 03 02:00:21 PM PST 24
Finished Jan 03 02:00:41 PM PST 24
Peak memory 216816 kb
Host smart-f7a3e288-a5b5-437a-9a17-6dd69b32f86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774121515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1774121515
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2668209340
Short name T1246
Test name
Test status
Simulation time 21405650 ps
CPU time 0.76 seconds
Started Jan 03 02:00:18 PM PST 24
Finished Jan 03 02:00:24 PM PST 24
Peak memory 206944 kb
Host smart-832fd261-b45b-4da0-b09a-48665ad99773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668209340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2668209340
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2885368716
Short name T554
Test name
Test status
Simulation time 183890263 ps
CPU time 0.92 seconds
Started Jan 03 02:00:15 PM PST 24
Finished Jan 03 02:00:19 PM PST 24
Peak memory 206968 kb
Host smart-b987646f-70b3-441f-aa4d-f0086be6ae49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885368716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2885368716
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_tx_async_fifo_reset.1679469796
Short name T1676
Test name
Test status
Simulation time 58119547 ps
CPU time 0.76 seconds
Started Jan 03 02:00:16 PM PST 24
Finished Jan 03 02:00:20 PM PST 24
Peak memory 208516 kb
Host smart-bee9b8ff-0c9f-4f9a-9a35-ca811fbcba71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679469796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tx_async_fifo_reset.1679469796
Directory /workspace/33.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/33.spi_device_txrx.3658412674
Short name T734
Test name
Test status
Simulation time 46583426191 ps
CPU time 795.28 seconds
Started Jan 03 01:59:33 PM PST 24
Finished Jan 03 02:12:55 PM PST 24
Peak memory 296372 kb
Host smart-c7dc8d3f-727f-4b8e-badd-92fc53d5ac9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658412674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_txrx.3658412674
Directory /workspace/33.spi_device_txrx/latest

Test location /workspace/coverage/default/33.spi_device_upload.1054596780
Short name T1010
Test name
Test status
Simulation time 1870469951 ps
CPU time 9.12 seconds
Started Jan 03 02:00:33 PM PST 24
Finished Jan 03 02:00:54 PM PST 24
Peak memory 236016 kb
Host smart-6dd15cff-aff3-439e-955b-51d6eb7ed606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054596780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1054596780
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_abort.3359398724
Short name T551
Test name
Test status
Simulation time 42592688 ps
CPU time 0.74 seconds
Started Jan 03 02:00:23 PM PST 24
Finished Jan 03 02:00:35 PM PST 24
Peak memory 206644 kb
Host smart-39e0d886-6ec0-49af-b2cc-48399a6b9cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359398724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_abort.3359398724
Directory /workspace/34.spi_device_abort/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2875161520
Short name T1538
Test name
Test status
Simulation time 44408651 ps
CPU time 0.73 seconds
Started Jan 03 02:00:52 PM PST 24
Finished Jan 03 02:01:07 PM PST 24
Peak memory 206460 kb
Host smart-b75d16c2-2f4b-4e64-81e6-8cff2dcd62ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875161520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2875161520
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_bit_transfer.116394190
Short name T808
Test name
Test status
Simulation time 143395427 ps
CPU time 2.44 seconds
Started Jan 03 02:00:21 PM PST 24
Finished Jan 03 02:00:33 PM PST 24
Peak memory 216904 kb
Host smart-0951d968-911b-4b0a-886f-bcd4425c23f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116394190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_bit_transfer.116394190
Directory /workspace/34.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/34.spi_device_byte_transfer.1352014818
Short name T1461
Test name
Test status
Simulation time 153009929 ps
CPU time 2.69 seconds
Started Jan 03 02:00:15 PM PST 24
Finished Jan 03 02:00:20 PM PST 24
Peak memory 216776 kb
Host smart-1ebe1d69-65b0-40bb-861e-f3520e4b3e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352014818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_byte_transfer.1352014818
Directory /workspace/34.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.4290483543
Short name T1091
Test name
Test status
Simulation time 235578722 ps
CPU time 2.92 seconds
Started Jan 03 02:00:52 PM PST 24
Finished Jan 03 02:01:09 PM PST 24
Peak memory 218236 kb
Host smart-926292a1-2f15-42dc-93ae-fc9103dc27a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290483543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.4290483543
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.776165523
Short name T91
Test name
Test status
Simulation time 15617729 ps
CPU time 0.75 seconds
Started Jan 03 02:00:20 PM PST 24
Finished Jan 03 02:00:29 PM PST 24
Peak memory 206520 kb
Host smart-4539c54f-6c05-41cb-8abd-d9e36f153811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776165523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.776165523
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_dummy_item_extra_dly.3305401509
Short name T566
Test name
Test status
Simulation time 49451617186 ps
CPU time 398.88 seconds
Started Jan 03 02:00:25 PM PST 24
Finished Jan 03 02:07:16 PM PST 24
Peak memory 271760 kb
Host smart-bc442d8e-08c1-48aa-9fc1-cb1db5957733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305401509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_dummy_item_extra_dly.3305401509
Directory /workspace/34.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/34.spi_device_extreme_fifo_size.2628154826
Short name T1431
Test name
Test status
Simulation time 92761983719 ps
CPU time 1654.72 seconds
Started Jan 03 02:00:20 PM PST 24
Finished Jan 03 02:28:02 PM PST 24
Peak memory 224900 kb
Host smart-b37a6194-65a6-4f3d-8807-dbb2b39f2c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628154826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_extreme_fifo_size.2628154826
Directory /workspace/34.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/34.spi_device_fifo_full.981059342
Short name T710
Test name
Test status
Simulation time 53648540224 ps
CPU time 3069 seconds
Started Jan 03 02:00:35 PM PST 24
Finished Jan 03 02:51:57 PM PST 24
Peak memory 274044 kb
Host smart-d4c29815-f41f-427b-ace9-598609e11b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981059342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_fifo_full.981059342
Directory /workspace/34.spi_device_fifo_full/latest

Test location /workspace/coverage/default/34.spi_device_fifo_underflow_overflow.3705600625
Short name T1421
Test name
Test status
Simulation time 213577916132 ps
CPU time 276.61 seconds
Started Jan 03 02:00:24 PM PST 24
Finished Jan 03 02:05:13 PM PST 24
Peak memory 314212 kb
Host smart-a89d11a6-1221-4678-89a5-ba178456cd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705600625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_fifo_underflow_overf
low.3705600625
Directory /workspace/34.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2328855813
Short name T384
Test name
Test status
Simulation time 40717593956 ps
CPU time 193.24 seconds
Started Jan 03 02:00:24 PM PST 24
Finished Jan 03 02:03:50 PM PST 24
Peak memory 252784 kb
Host smart-b4460b9c-3264-43f5-b2c2-fb2ac0ed35a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328855813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2328855813
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2286367120
Short name T885
Test name
Test status
Simulation time 4662468131 ps
CPU time 95.99 seconds
Started Jan 03 02:00:53 PM PST 24
Finished Jan 03 02:02:43 PM PST 24
Peak memory 266052 kb
Host smart-7c4c9251-1be2-4c07-8ab9-007a4da4bef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286367120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2286367120
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.272365447
Short name T1208
Test name
Test status
Simulation time 2958605954 ps
CPU time 46.07 seconds
Started Jan 03 02:01:21 PM PST 24
Finished Jan 03 02:02:23 PM PST 24
Peak memory 241664 kb
Host smart-ee837f66-2357-408f-88d4-b3910f509e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272365447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.272365447
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.4106634574
Short name T1555
Test name
Test status
Simulation time 2977798686 ps
CPU time 23.22 seconds
Started Jan 03 02:00:34 PM PST 24
Finished Jan 03 02:01:09 PM PST 24
Peak memory 243520 kb
Host smart-7513a7ac-2ff0-4b3c-8714-332f213310e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106634574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.4106634574
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.819548562
Short name T1168
Test name
Test status
Simulation time 3758167362 ps
CPU time 7.75 seconds
Started Jan 03 02:00:25 PM PST 24
Finished Jan 03 02:00:46 PM PST 24
Peak memory 219788 kb
Host smart-9f8d40a8-e471-4176-a7e7-46786f18954f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819548562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.819548562
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_intr.1181205660
Short name T1105
Test name
Test status
Simulation time 77936555284 ps
CPU time 70.69 seconds
Started Jan 03 02:00:20 PM PST 24
Finished Jan 03 02:01:40 PM PST 24
Peak memory 249624 kb
Host smart-746aa497-a780-4d6d-b54f-ce45503987ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181205660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intr.1181205660
Directory /workspace/34.spi_device_intr/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1750174892
Short name T24
Test name
Test status
Simulation time 10454121516 ps
CPU time 34.14 seconds
Started Jan 03 02:00:28 PM PST 24
Finished Jan 03 02:01:15 PM PST 24
Peak memory 249472 kb
Host smart-afd9832d-63ea-4fc6-8e69-9e819054b849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750174892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1750174892
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3574759624
Short name T1441
Test name
Test status
Simulation time 8962521692 ps
CPU time 27.78 seconds
Started Jan 03 02:00:49 PM PST 24
Finished Jan 03 02:01:27 PM PST 24
Peak memory 241352 kb
Host smart-a440e17f-f7dc-444d-bc15-c9e992d31cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574759624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3574759624
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.4663188
Short name T1367
Test name
Test status
Simulation time 1304969172 ps
CPU time 6.86 seconds
Started Jan 03 02:00:23 PM PST 24
Finished Jan 03 02:00:42 PM PST 24
Peak memory 241424 kb
Host smart-f53f3b8c-57ae-4cf0-9725-1934a5025535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4663188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4663188
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_perf.3208978477
Short name T649
Test name
Test status
Simulation time 90861631515 ps
CPU time 2971.1 seconds
Started Jan 03 02:00:16 PM PST 24
Finished Jan 03 02:49:51 PM PST 24
Peak memory 298732 kb
Host smart-c65c5e61-6541-4752-be79-5db8216b06d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208978477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_perf.3208978477
Directory /workspace/34.spi_device_perf/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2759258527
Short name T901
Test name
Test status
Simulation time 4987681207 ps
CPU time 6.32 seconds
Started Jan 03 02:00:26 PM PST 24
Finished Jan 03 02:00:45 PM PST 24
Peak memory 220716 kb
Host smart-ea28b722-334f-4da3-b2d4-9f564cd9d8d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2759258527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2759258527
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_rx_async_fifo_reset.3951844775
Short name T876
Test name
Test status
Simulation time 51412569 ps
CPU time 0.94 seconds
Started Jan 03 02:00:50 PM PST 24
Finished Jan 03 02:01:02 PM PST 24
Peak memory 208460 kb
Host smart-f7750990-fbed-40aa-82aa-95f562a1798a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951844775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_rx_async_fifo_reset.3951844775
Directory /workspace/34.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/34.spi_device_rx_timeout.983626588
Short name T1260
Test name
Test status
Simulation time 1808023907 ps
CPU time 7.21 seconds
Started Jan 03 02:00:25 PM PST 24
Finished Jan 03 02:00:45 PM PST 24
Peak memory 216924 kb
Host smart-f607d6dd-0875-460d-a81b-73521e5ffe78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983626588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_rx_timeout.983626588
Directory /workspace/34.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/34.spi_device_smoke.3553486830
Short name T1326
Test name
Test status
Simulation time 25121896 ps
CPU time 1.12 seconds
Started Jan 03 02:00:24 PM PST 24
Finished Jan 03 02:00:37 PM PST 24
Peak memory 216776 kb
Host smart-7b3ad5ec-362f-4740-aa3f-2e2279080db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553486830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_smoke.3553486830
Directory /workspace/34.spi_device_smoke/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.4294543309
Short name T1486
Test name
Test status
Simulation time 6390096457 ps
CPU time 24.6 seconds
Started Jan 03 02:00:20 PM PST 24
Finished Jan 03 02:00:51 PM PST 24
Peak memory 216932 kb
Host smart-c50f3440-94a6-40f1-b24f-bf53b3708ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294543309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.4294543309
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.26517300
Short name T722
Test name
Test status
Simulation time 10661067287 ps
CPU time 32.84 seconds
Started Jan 03 02:00:50 PM PST 24
Finished Jan 03 02:01:35 PM PST 24
Peak memory 216844 kb
Host smart-a86e2fc7-7a6b-4f10-9a5e-906860212bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26517300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.26517300
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2693374789
Short name T539
Test name
Test status
Simulation time 569865296 ps
CPU time 9.43 seconds
Started Jan 03 02:00:41 PM PST 24
Finished Jan 03 02:01:01 PM PST 24
Peak memory 216904 kb
Host smart-ca06e684-8b0e-4635-bb9b-71a363754ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693374789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2693374789
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.4133244153
Short name T912
Test name
Test status
Simulation time 305247687 ps
CPU time 0.91 seconds
Started Jan 03 02:00:25 PM PST 24
Finished Jan 03 02:00:39 PM PST 24
Peak memory 207040 kb
Host smart-7a6984fe-8c10-49f1-b307-25e25ff4dc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133244153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.4133244153
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_tx_async_fifo_reset.1537111527
Short name T1176
Test name
Test status
Simulation time 15557948 ps
CPU time 0.77 seconds
Started Jan 03 02:00:20 PM PST 24
Finished Jan 03 02:00:28 PM PST 24
Peak memory 208416 kb
Host smart-5fd86360-1382-40ae-9114-9960fea97891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537111527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tx_async_fifo_reset.1537111527
Directory /workspace/34.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/34.spi_device_txrx.3790780001
Short name T1748
Test name
Test status
Simulation time 27981097508 ps
CPU time 274.59 seconds
Started Jan 03 02:00:21 PM PST 24
Finished Jan 03 02:05:04 PM PST 24
Peak memory 296576 kb
Host smart-4c625724-f452-4827-92e5-9eb5a77360ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790780001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_txrx.3790780001
Directory /workspace/34.spi_device_txrx/latest

Test location /workspace/coverage/default/34.spi_device_upload.2345750334
Short name T1375
Test name
Test status
Simulation time 872521418 ps
CPU time 4.38 seconds
Started Jan 03 02:00:23 PM PST 24
Finished Jan 03 02:00:40 PM PST 24
Peak memory 219260 kb
Host smart-07b274d3-5b5b-425f-bd94-0f134dbf2526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345750334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2345750334
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_abort.3890562529
Short name T658
Test name
Test status
Simulation time 38201665 ps
CPU time 0.79 seconds
Started Jan 03 02:00:21 PM PST 24
Finished Jan 03 02:00:31 PM PST 24
Peak memory 206624 kb
Host smart-4df6c4a4-e77e-47ae-830f-ac0d6c55ed7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890562529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_abort.3890562529
Directory /workspace/35.spi_device_abort/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.356206052
Short name T92
Test name
Test status
Simulation time 25289398 ps
CPU time 0.78 seconds
Started Jan 03 02:00:19 PM PST 24
Finished Jan 03 02:00:27 PM PST 24
Peak memory 206528 kb
Host smart-6285f19c-a762-4c9c-ad65-0a6d23f28768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356206052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.356206052
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_bit_transfer.3477176933
Short name T1054
Test name
Test status
Simulation time 891352859 ps
CPU time 2.25 seconds
Started Jan 03 02:01:34 PM PST 24
Finished Jan 03 02:01:53 PM PST 24
Peak memory 216900 kb
Host smart-06b116ae-2630-4ccd-840a-2ba7b2894557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477176933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_bit_transfer.3477176933
Directory /workspace/35.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/35.spi_device_byte_transfer.3447057687
Short name T854
Test name
Test status
Simulation time 122109507 ps
CPU time 2.57 seconds
Started Jan 03 02:01:10 PM PST 24
Finished Jan 03 02:01:23 PM PST 24
Peak memory 216832 kb
Host smart-4b06c64e-3231-4250-9a76-0c8dd354ee6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447057687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_byte_transfer.3447057687
Directory /workspace/35.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2218773515
Short name T515
Test name
Test status
Simulation time 573845083 ps
CPU time 3.6 seconds
Started Jan 03 02:00:23 PM PST 24
Finished Jan 03 02:00:39 PM PST 24
Peak memory 240228 kb
Host smart-ee8cddda-6556-4a5c-93e0-80194e7605b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218773515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2218773515
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1023045653
Short name T976
Test name
Test status
Simulation time 21298417 ps
CPU time 0.82 seconds
Started Jan 03 02:00:20 PM PST 24
Finished Jan 03 02:00:28 PM PST 24
Peak memory 207524 kb
Host smart-974c1a5c-093a-4419-96f8-81b7f718de6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023045653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1023045653
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_dummy_item_extra_dly.748077916
Short name T744
Test name
Test status
Simulation time 167177212448 ps
CPU time 722.7 seconds
Started Jan 03 02:01:38 PM PST 24
Finished Jan 03 02:13:58 PM PST 24
Peak memory 268356 kb
Host smart-fd541643-124d-4adc-9d2d-37c1074a92ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748077916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_dummy_item_extra_dly.748077916
Directory /workspace/35.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/35.spi_device_extreme_fifo_size.3119952497
Short name T1567
Test name
Test status
Simulation time 36687487389 ps
CPU time 1449.49 seconds
Started Jan 03 02:01:23 PM PST 24
Finished Jan 03 02:25:48 PM PST 24
Peak memory 223696 kb
Host smart-a691fa25-a400-4de5-a621-556818b87dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119952497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_extreme_fifo_size.3119952497
Directory /workspace/35.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/35.spi_device_fifo_full.4074055594
Short name T1442
Test name
Test status
Simulation time 55971950847 ps
CPU time 3182.94 seconds
Started Jan 03 02:01:12 PM PST 24
Finished Jan 03 02:54:25 PM PST 24
Peak memory 256548 kb
Host smart-e9d57c9b-d325-432a-b913-890894f15d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074055594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_fifo_full.4074055594
Directory /workspace/35.spi_device_fifo_full/latest

Test location /workspace/coverage/default/35.spi_device_fifo_underflow_overflow.1314996061
Short name T50
Test name
Test status
Simulation time 17498434678 ps
CPU time 159.92 seconds
Started Jan 03 02:01:06 PM PST 24
Finished Jan 03 02:03:57 PM PST 24
Peak memory 299928 kb
Host smart-674a7b46-f36e-46c4-9803-2ea5caa1b2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314996061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_fifo_underflow_overf
low.1314996061
Directory /workspace/35.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3838750115
Short name T894
Test name
Test status
Simulation time 78706940676 ps
CPU time 77.05 seconds
Started Jan 03 02:00:25 PM PST 24
Finished Jan 03 02:01:55 PM PST 24
Peak memory 249696 kb
Host smart-6d695806-0bbc-41a5-8be7-2f8007b417f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838750115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3838750115
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3577587722
Short name T382
Test name
Test status
Simulation time 33006936535 ps
CPU time 99.59 seconds
Started Jan 03 02:00:33 PM PST 24
Finished Jan 03 02:02:25 PM PST 24
Peak memory 240904 kb
Host smart-348dac49-dc96-4322-9cf0-fd6bbf6b795f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577587722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3577587722
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1695478390
Short name T1360
Test name
Test status
Simulation time 14562989928 ps
CPU time 97.81 seconds
Started Jan 03 02:00:33 PM PST 24
Finished Jan 03 02:02:23 PM PST 24
Peak memory 241916 kb
Host smart-f25f8954-3da1-45a5-a932-1da4e24a52b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695478390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1695478390
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.4244504138
Short name T1455
Test name
Test status
Simulation time 12531400953 ps
CPU time 23.04 seconds
Started Jan 03 02:00:21 PM PST 24
Finished Jan 03 02:00:54 PM PST 24
Peak memory 241124 kb
Host smart-b537fec4-173b-4ae6-9b85-aa77c3fcb169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244504138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.4244504138
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.4000728804
Short name T1220
Test name
Test status
Simulation time 2987587307 ps
CPU time 7.03 seconds
Started Jan 03 02:00:15 PM PST 24
Finished Jan 03 02:00:24 PM PST 24
Peak memory 236496 kb
Host smart-94fce542-e314-4555-9504-977e31b88db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000728804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.4000728804
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_intr.2493801960
Short name T1275
Test name
Test status
Simulation time 7887188312 ps
CPU time 41.71 seconds
Started Jan 03 02:01:31 PM PST 24
Finished Jan 03 02:02:28 PM PST 24
Peak memory 224180 kb
Host smart-0926c746-0cb9-48fd-aea8-b096f8f27c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493801960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intr.2493801960
Directory /workspace/35.spi_device_intr/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2053089191
Short name T350
Test name
Test status
Simulation time 954030469 ps
CPU time 6.74 seconds
Started Jan 03 02:00:20 PM PST 24
Finished Jan 03 02:00:35 PM PST 24
Peak memory 238512 kb
Host smart-b9ed71c5-2819-4793-b2da-114c1c910e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053089191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2053089191
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.722650735
Short name T132
Test name
Test status
Simulation time 9213219511 ps
CPU time 33.3 seconds
Started Jan 03 02:00:19 PM PST 24
Finished Jan 03 02:00:58 PM PST 24
Peak memory 241496 kb
Host smart-0e4edab0-1180-46df-9e69-7c6f36f34f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722650735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.722650735
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3161116635
Short name T1656
Test name
Test status
Simulation time 68241093749 ps
CPU time 31.76 seconds
Started Jan 03 02:00:22 PM PST 24
Finished Jan 03 02:01:03 PM PST 24
Peak memory 229488 kb
Host smart-c0f053ab-8111-49cd-a594-9ab4825c42f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161116635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3161116635
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_perf.3327080966
Short name T1563
Test name
Test status
Simulation time 21382484125 ps
CPU time 449.69 seconds
Started Jan 03 02:01:12 PM PST 24
Finished Jan 03 02:08:52 PM PST 24
Peak memory 282180 kb
Host smart-822f5f28-8b6b-476d-8959-b627ed68844d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327080966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_perf.3327080966
Directory /workspace/35.spi_device_perf/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.951363579
Short name T1595
Test name
Test status
Simulation time 114135383 ps
CPU time 4.27 seconds
Started Jan 03 02:00:23 PM PST 24
Finished Jan 03 02:00:39 PM PST 24
Peak memory 234292 kb
Host smart-37168ec7-267b-4851-bb57-ad0c0e61ad51
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=951363579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.951363579
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_rx_async_fifo_reset.3250574026
Short name T1330
Test name
Test status
Simulation time 100812463 ps
CPU time 0.89 seconds
Started Jan 03 02:01:30 PM PST 24
Finished Jan 03 02:01:46 PM PST 24
Peak memory 208588 kb
Host smart-09bb0294-567f-465a-9ffd-871bde56fdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250574026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_rx_async_fifo_reset.3250574026
Directory /workspace/35.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/35.spi_device_rx_timeout.481790215
Short name T1536
Test name
Test status
Simulation time 797419428 ps
CPU time 4.76 seconds
Started Jan 03 02:01:34 PM PST 24
Finished Jan 03 02:01:57 PM PST 24
Peak memory 216796 kb
Host smart-bf0cedee-2b14-46a8-8b3a-4058ae3d69cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481790215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_rx_timeout.481790215
Directory /workspace/35.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/35.spi_device_smoke.473160117
Short name T1249
Test name
Test status
Simulation time 219199346 ps
CPU time 1.2 seconds
Started Jan 03 02:00:53 PM PST 24
Finished Jan 03 02:01:08 PM PST 24
Peak memory 216492 kb
Host smart-4833e86e-8036-4a95-8aee-eaf20d6d7213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473160117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_smoke.473160117
Directory /workspace/35.spi_device_smoke/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1826950898
Short name T1139
Test name
Test status
Simulation time 65079183274 ps
CPU time 641.48 seconds
Started Jan 03 02:00:24 PM PST 24
Finished Jan 03 02:11:17 PM PST 24
Peak memory 282756 kb
Host smart-6bb3da28-4db1-457d-aaee-96f60781bd2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826950898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1826950898
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2703203700
Short name T892
Test name
Test status
Simulation time 1899356753 ps
CPU time 17.66 seconds
Started Jan 03 02:01:01 PM PST 24
Finished Jan 03 02:01:32 PM PST 24
Peak memory 218116 kb
Host smart-d92945b1-3761-4225-be93-f6132eb478b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703203700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2703203700
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3943874577
Short name T1202
Test name
Test status
Simulation time 1936682834 ps
CPU time 4.77 seconds
Started Jan 03 02:01:05 PM PST 24
Finished Jan 03 02:01:22 PM PST 24
Peak memory 216788 kb
Host smart-754f139b-d72a-4c39-8390-0a533783c6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943874577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3943874577
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1579692486
Short name T974
Test name
Test status
Simulation time 179499540 ps
CPU time 2.27 seconds
Started Jan 03 02:01:33 PM PST 24
Finished Jan 03 02:01:53 PM PST 24
Peak memory 216772 kb
Host smart-0badb870-8f18-4f55-be34-995179703ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579692486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1579692486
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1947110572
Short name T1178
Test name
Test status
Simulation time 205265582 ps
CPU time 0.86 seconds
Started Jan 03 02:01:24 PM PST 24
Finished Jan 03 02:01:41 PM PST 24
Peak memory 207052 kb
Host smart-e3ddfcd8-c0d7-428e-a8c2-2fa8d1a905ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947110572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1947110572
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_tx_async_fifo_reset.3878731813
Short name T1034
Test name
Test status
Simulation time 17410421 ps
CPU time 0.76 seconds
Started Jan 03 02:01:10 PM PST 24
Finished Jan 03 02:01:21 PM PST 24
Peak memory 208412 kb
Host smart-0cd3298b-21e3-4d81-aa99-6bd5219a4a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878731813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tx_async_fifo_reset.3878731813
Directory /workspace/35.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/35.spi_device_txrx.2357773794
Short name T1263
Test name
Test status
Simulation time 44949200575 ps
CPU time 499.04 seconds
Started Jan 03 02:00:50 PM PST 24
Finished Jan 03 02:09:21 PM PST 24
Peak memory 324696 kb
Host smart-ec4cb247-66f0-4c09-b45b-6c9d6089d4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357773794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_txrx.2357773794
Directory /workspace/35.spi_device_txrx/latest

Test location /workspace/coverage/default/35.spi_device_upload.1599687631
Short name T1164
Test name
Test status
Simulation time 12977915369 ps
CPU time 10.45 seconds
Started Jan 03 02:00:35 PM PST 24
Finished Jan 03 02:00:58 PM PST 24
Peak memory 225036 kb
Host smart-21661f68-2775-4fd5-94d3-3237700ac702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599687631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1599687631
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_abort.939159903
Short name T1669
Test name
Test status
Simulation time 15010911 ps
CPU time 0.75 seconds
Started Jan 03 02:01:23 PM PST 24
Finished Jan 03 02:01:39 PM PST 24
Peak memory 206608 kb
Host smart-e23ee8e6-7ac0-4f80-a33b-25db82634420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939159903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_abort.939159903
Directory /workspace/36.spi_device_abort/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.4198224983
Short name T950
Test name
Test status
Simulation time 56820504 ps
CPU time 0.75 seconds
Started Jan 03 02:01:42 PM PST 24
Finished Jan 03 02:02:02 PM PST 24
Peak memory 206500 kb
Host smart-ce97dfab-55cb-42eb-9db0-9945436fb497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198224983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
4198224983
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_bit_transfer.4291753584
Short name T858
Test name
Test status
Simulation time 70204581 ps
CPU time 2.11 seconds
Started Jan 03 02:01:30 PM PST 24
Finished Jan 03 02:01:47 PM PST 24
Peak memory 216896 kb
Host smart-8fba0422-6da7-455f-b69a-6e785624ea21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291753584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_bit_transfer.4291753584
Directory /workspace/36.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/36.spi_device_byte_transfer.3500195524
Short name T998
Test name
Test status
Simulation time 169150698 ps
CPU time 3.18 seconds
Started Jan 03 02:01:02 PM PST 24
Finished Jan 03 02:01:18 PM PST 24
Peak memory 216856 kb
Host smart-e44e67fc-e09e-4937-bead-86880a26c048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500195524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_byte_transfer.3500195524
Directory /workspace/36.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2385406669
Short name T65
Test name
Test status
Simulation time 539003754 ps
CPU time 4.12 seconds
Started Jan 03 02:01:30 PM PST 24
Finished Jan 03 02:01:49 PM PST 24
Peak memory 241432 kb
Host smart-74d4c7df-1e71-460c-a8db-8c88f0e63095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385406669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2385406669
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.55579220
Short name T1635
Test name
Test status
Simulation time 72627734 ps
CPU time 0.79 seconds
Started Jan 03 02:00:56 PM PST 24
Finished Jan 03 02:01:10 PM PST 24
Peak memory 207600 kb
Host smart-bd0549e4-0c0f-43dc-812d-55263205d57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55579220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.55579220
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_dummy_item_extra_dly.209177942
Short name T1030
Test name
Test status
Simulation time 73687817837 ps
CPU time 279.48 seconds
Started Jan 03 02:00:51 PM PST 24
Finished Jan 03 02:05:43 PM PST 24
Peak memory 273744 kb
Host smart-93f31229-81b7-44c7-ae23-88eca1e238b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209177942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_dummy_item_extra_dly.209177942
Directory /workspace/36.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/36.spi_device_extreme_fifo_size.626754774
Short name T829
Test name
Test status
Simulation time 188051674318 ps
CPU time 2315.37 seconds
Started Jan 03 02:00:47 PM PST 24
Finished Jan 03 02:39:34 PM PST 24
Peak memory 219272 kb
Host smart-b9cd415f-3857-431a-9eb4-026297af07ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626754774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_extreme_fifo_size.626754774
Directory /workspace/36.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/36.spi_device_fifo_full.2717146631
Short name T1430
Test name
Test status
Simulation time 178666912679 ps
CPU time 798.75 seconds
Started Jan 03 02:00:35 PM PST 24
Finished Jan 03 02:14:06 PM PST 24
Peak memory 283052 kb
Host smart-2c11ee2a-dd6c-4db0-986d-2c58af396ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717146631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_fifo_full.2717146631
Directory /workspace/36.spi_device_fifo_full/latest

Test location /workspace/coverage/default/36.spi_device_fifo_underflow_overflow.2928038187
Short name T49
Test name
Test status
Simulation time 32583774063 ps
CPU time 290.22 seconds
Started Jan 03 02:00:56 PM PST 24
Finished Jan 03 02:06:00 PM PST 24
Peak memory 385432 kb
Host smart-b2a315b1-dad8-4511-a1ce-96fd615a9ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928038187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_fifo_underflow_overf
low.2928038187
Directory /workspace/36.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1757357967
Short name T1165
Test name
Test status
Simulation time 2248150363 ps
CPU time 13.74 seconds
Started Jan 03 02:01:34 PM PST 24
Finished Jan 03 02:02:06 PM PST 24
Peak memory 230948 kb
Host smart-f3cf1f9a-611b-4a7d-b0aa-79716f4a363c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757357967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1757357967
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3695346533
Short name T1266
Test name
Test status
Simulation time 28808872737 ps
CPU time 63.53 seconds
Started Jan 03 02:01:33 PM PST 24
Finished Jan 03 02:02:53 PM PST 24
Peak memory 234352 kb
Host smart-e9e10fd4-1d94-4622-ad06-7647421094de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695346533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3695346533
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.416887099
Short name T268
Test name
Test status
Simulation time 989884657 ps
CPU time 10.85 seconds
Started Jan 03 02:01:31 PM PST 24
Finished Jan 03 02:01:57 PM PST 24
Peak memory 236200 kb
Host smart-70552aea-31ff-4afa-ac11-31f131cd0c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416887099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.416887099
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1244993890
Short name T259
Test name
Test status
Simulation time 2409800032 ps
CPU time 8.56 seconds
Started Jan 03 02:01:21 PM PST 24
Finished Jan 03 02:01:45 PM PST 24
Peak memory 219132 kb
Host smart-c0de7ab0-f996-4afe-8cfb-9720019edd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244993890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1244993890
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_intr.3027065379
Short name T1553
Test name
Test status
Simulation time 34703661998 ps
CPU time 68.36 seconds
Started Jan 03 02:00:49 PM PST 24
Finished Jan 03 02:02:08 PM PST 24
Peak memory 235444 kb
Host smart-d5bd3ad1-27c0-4f36-a0b2-0dd3007f84c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027065379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intr.3027065379
Directory /workspace/36.spi_device_intr/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1761175114
Short name T1727
Test name
Test status
Simulation time 56479880927 ps
CPU time 39.8 seconds
Started Jan 03 02:01:40 PM PST 24
Finished Jan 03 02:02:38 PM PST 24
Peak memory 250724 kb
Host smart-7e04732c-25be-4827-9df1-7df4c6b8bc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761175114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1761175114
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.354925583
Short name T359
Test name
Test status
Simulation time 117704606369 ps
CPU time 43.41 seconds
Started Jan 03 02:01:23 PM PST 24
Finished Jan 03 02:02:22 PM PST 24
Peak memory 256116 kb
Host smart-b4d6ce84-0f91-4e54-bc35-274154f871a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354925583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.354925583
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2834714607
Short name T1714
Test name
Test status
Simulation time 3169392769 ps
CPU time 13.92 seconds
Started Jan 03 02:01:10 PM PST 24
Finished Jan 03 02:01:34 PM PST 24
Peak memory 230384 kb
Host smart-2ac5805c-4eda-4a3f-a1fe-e8972ff1a55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834714607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2834714607
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_perf.2473641792
Short name T1412
Test name
Test status
Simulation time 22396427140 ps
CPU time 455.28 seconds
Started Jan 03 02:00:53 PM PST 24
Finished Jan 03 02:08:42 PM PST 24
Peak memory 259784 kb
Host smart-144deb3d-7778-46cc-a010-2508eb23e676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473641792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_perf.2473641792
Directory /workspace/36.spi_device_perf/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1909832249
Short name T996
Test name
Test status
Simulation time 1668972115 ps
CPU time 5.01 seconds
Started Jan 03 02:01:34 PM PST 24
Finished Jan 03 02:01:56 PM PST 24
Peak memory 218928 kb
Host smart-1920cd56-c022-4993-8840-a72b921fdff2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1909832249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1909832249
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_rx_async_fifo_reset.4036859865
Short name T87
Test name
Test status
Simulation time 68187561 ps
CPU time 0.87 seconds
Started Jan 03 02:01:22 PM PST 24
Finished Jan 03 02:01:39 PM PST 24
Peak memory 208500 kb
Host smart-1f06a047-adcd-474d-95e2-50d2e915d819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036859865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_rx_async_fifo_reset.4036859865
Directory /workspace/36.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/36.spi_device_rx_timeout.624737817
Short name T1310
Test name
Test status
Simulation time 2555460124 ps
CPU time 5.32 seconds
Started Jan 03 02:00:51 PM PST 24
Finished Jan 03 02:01:08 PM PST 24
Peak memory 216864 kb
Host smart-e960cc2b-aec3-4c07-acb2-e21188bd5573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624737817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_rx_timeout.624737817
Directory /workspace/36.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/36.spi_device_smoke.635304692
Short name T772
Test name
Test status
Simulation time 55343970 ps
CPU time 1.02 seconds
Started Jan 03 02:00:56 PM PST 24
Finished Jan 03 02:01:10 PM PST 24
Peak memory 208172 kb
Host smart-2ffbe324-584d-479f-bc38-04bc847060b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635304692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_smoke.635304692
Directory /workspace/36.spi_device_smoke/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3742684797
Short name T1577
Test name
Test status
Simulation time 916073617 ps
CPU time 17.44 seconds
Started Jan 03 02:01:22 PM PST 24
Finished Jan 03 02:01:55 PM PST 24
Peak memory 216912 kb
Host smart-08fe7447-63a6-405c-a203-2ee2349cf9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742684797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3742684797
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.653355802
Short name T1385
Test name
Test status
Simulation time 50018149461 ps
CPU time 15.39 seconds
Started Jan 03 02:01:24 PM PST 24
Finished Jan 03 02:01:55 PM PST 24
Peak memory 216836 kb
Host smart-7274f492-d11c-4b42-9b63-71a076d58c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653355802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.653355802
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2069221927
Short name T586
Test name
Test status
Simulation time 133551007 ps
CPU time 4.62 seconds
Started Jan 03 02:01:30 PM PST 24
Finished Jan 03 02:01:49 PM PST 24
Peak memory 216816 kb
Host smart-6f41dc94-b4bb-4126-a891-aa552331df2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069221927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2069221927
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2171983893
Short name T1746
Test name
Test status
Simulation time 68745468 ps
CPU time 0.9 seconds
Started Jan 03 02:01:21 PM PST 24
Finished Jan 03 02:01:38 PM PST 24
Peak memory 206944 kb
Host smart-dc29b5bf-5eb1-4e49-b0f4-3750c91d6334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171983893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2171983893
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_tx_async_fifo_reset.449744447
Short name T828
Test name
Test status
Simulation time 16914903 ps
CPU time 0.77 seconds
Started Jan 03 02:01:09 PM PST 24
Finished Jan 03 02:01:20 PM PST 24
Peak memory 208524 kb
Host smart-64f607e8-04d5-4048-85a9-82f9d0da2a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449744447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tx_async_fifo_reset.449744447
Directory /workspace/36.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/36.spi_device_txrx.3894522960
Short name T874
Test name
Test status
Simulation time 71325094656 ps
CPU time 214.96 seconds
Started Jan 03 02:00:25 PM PST 24
Finished Jan 03 02:04:13 PM PST 24
Peak memory 240608 kb
Host smart-c6b6e1d6-dc2e-43f6-be49-88e93c80b75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894522960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_txrx.3894522960
Directory /workspace/36.spi_device_txrx/latest

Test location /workspace/coverage/default/36.spi_device_upload.1785261696
Short name T213
Test name
Test status
Simulation time 478797404 ps
CPU time 5.35 seconds
Started Jan 03 02:01:31 PM PST 24
Finished Jan 03 02:01:51 PM PST 24
Peak memory 238368 kb
Host smart-6af3e248-f33e-4c7e-acd0-14f6bacf3214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785261696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1785261696
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_abort.1670213288
Short name T980
Test name
Test status
Simulation time 15483955 ps
CPU time 0.75 seconds
Started Jan 03 02:00:20 PM PST 24
Finished Jan 03 02:00:28 PM PST 24
Peak memory 206524 kb
Host smart-32ae52d1-21e7-40ad-a2a3-ada21638227c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670213288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_abort.1670213288
Directory /workspace/37.spi_device_abort/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.214015562
Short name T1060
Test name
Test status
Simulation time 13114618 ps
CPU time 0.71 seconds
Started Jan 03 02:01:24 PM PST 24
Finished Jan 03 02:01:40 PM PST 24
Peak memory 206516 kb
Host smart-cd3954a3-5023-48a3-8be3-cbfa2917f6c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214015562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.214015562
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_bit_transfer.2496063796
Short name T889
Test name
Test status
Simulation time 398590887 ps
CPU time 2.8 seconds
Started Jan 03 02:00:21 PM PST 24
Finished Jan 03 02:00:34 PM PST 24
Peak memory 216976 kb
Host smart-1b3903e2-64ba-4df5-8d07-6c9f84876e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496063796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_bit_transfer.2496063796
Directory /workspace/37.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/37.spi_device_byte_transfer.3430944594
Short name T798
Test name
Test status
Simulation time 199225627 ps
CPU time 2.92 seconds
Started Jan 03 02:00:15 PM PST 24
Finished Jan 03 02:00:20 PM PST 24
Peak memory 216880 kb
Host smart-dce31766-3044-466f-9dac-e4c1604a1046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430944594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_byte_transfer.3430944594
Directory /workspace/37.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.131433554
Short name T325
Test name
Test status
Simulation time 208844159 ps
CPU time 3.45 seconds
Started Jan 03 02:00:48 PM PST 24
Finished Jan 03 02:01:02 PM PST 24
Peak memory 239796 kb
Host smart-bf7bbd1e-fc8d-4ba4-8e26-4a764bf7b984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131433554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.131433554
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2342912620
Short name T1026
Test name
Test status
Simulation time 70033730 ps
CPU time 0.8 seconds
Started Jan 03 02:00:24 PM PST 24
Finished Jan 03 02:00:37 PM PST 24
Peak memory 206588 kb
Host smart-f454366a-e46c-48fd-94e3-5763c6ac98f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342912620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2342912620
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_dummy_item_extra_dly.3454316146
Short name T720
Test name
Test status
Simulation time 35657262180 ps
CPU time 886.08 seconds
Started Jan 03 02:00:20 PM PST 24
Finished Jan 03 02:15:15 PM PST 24
Peak memory 237496 kb
Host smart-e9d538a1-fcc1-45c2-80ea-d8c3ad163e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454316146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_dummy_item_extra_dly.3454316146
Directory /workspace/37.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/37.spi_device_extreme_fifo_size.670058628
Short name T1050
Test name
Test status
Simulation time 204054737264 ps
CPU time 795.42 seconds
Started Jan 03 02:00:14 PM PST 24
Finished Jan 03 02:13:32 PM PST 24
Peak memory 217052 kb
Host smart-37b0c8a1-9154-4e4b-acbd-b1d8c43db22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670058628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_extreme_fifo_size.670058628
Directory /workspace/37.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/37.spi_device_fifo_full.939085534
Short name T1586
Test name
Test status
Simulation time 28433352591 ps
CPU time 651.64 seconds
Started Jan 03 02:00:23 PM PST 24
Finished Jan 03 02:11:26 PM PST 24
Peak memory 271336 kb
Host smart-3aeabd29-41a4-49ac-9a91-102b6f48f468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939085534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_fifo_full.939085534
Directory /workspace/37.spi_device_fifo_full/latest

Test location /workspace/coverage/default/37.spi_device_fifo_underflow_overflow.1341704115
Short name T1128
Test name
Test status
Simulation time 32851372759 ps
CPU time 354.46 seconds
Started Jan 03 02:01:48 PM PST 24
Finished Jan 03 02:08:00 PM PST 24
Peak memory 371668 kb
Host smart-4533f2c0-dffe-4160-a85d-7e07eac25e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341704115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_fifo_underflow_overf
low.1341704115
Directory /workspace/37.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3726884986
Short name T1096
Test name
Test status
Simulation time 1319315369 ps
CPU time 8.04 seconds
Started Jan 03 02:01:03 PM PST 24
Finished Jan 03 02:01:23 PM PST 24
Peak memory 236412 kb
Host smart-764ab8fc-a2ac-43f1-b6fb-8f773737e52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726884986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3726884986
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2573625299
Short name T364
Test name
Test status
Simulation time 32937696543 ps
CPU time 117.57 seconds
Started Jan 03 02:01:01 PM PST 24
Finished Jan 03 02:03:12 PM PST 24
Peak memory 249864 kb
Host smart-5778a5de-64d5-4344-bae3-e9f68dae9da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573625299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2573625299
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1044270745
Short name T388
Test name
Test status
Simulation time 14194411437 ps
CPU time 100.45 seconds
Started Jan 03 02:01:09 PM PST 24
Finished Jan 03 02:03:00 PM PST 24
Peak memory 257548 kb
Host smart-f7110904-1bb1-451e-b7a2-59856fad3359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044270745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1044270745
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1802636601
Short name T1224
Test name
Test status
Simulation time 3543989357 ps
CPU time 10.83 seconds
Started Jan 03 02:00:48 PM PST 24
Finished Jan 03 02:01:10 PM PST 24
Peak memory 231292 kb
Host smart-fa57c39a-2f95-4dc4-9cf8-9cd50540bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802636601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1802636601
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2951097683
Short name T1480
Test name
Test status
Simulation time 6323123157 ps
CPU time 4.43 seconds
Started Jan 03 02:00:25 PM PST 24
Finished Jan 03 02:00:43 PM PST 24
Peak memory 219328 kb
Host smart-7d36162c-95ab-4b53-a1b1-19133a234190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951097683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2951097683
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_intr.3149310986
Short name T1014
Test name
Test status
Simulation time 9021918203 ps
CPU time 47.25 seconds
Started Jan 03 02:00:20 PM PST 24
Finished Jan 03 02:01:16 PM PST 24
Peak memory 232648 kb
Host smart-e2e7faea-30a3-4788-af71-c8339fe7d460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149310986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intr.3149310986
Directory /workspace/37.spi_device_intr/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2392484040
Short name T241
Test name
Test status
Simulation time 31517489641 ps
CPU time 24 seconds
Started Jan 03 02:00:48 PM PST 24
Finished Jan 03 02:01:23 PM PST 24
Peak memory 249652 kb
Host smart-21012d07-ad9c-4525-b16a-3ee356aefe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392484040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2392484040
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.768815997
Short name T1332
Test name
Test status
Simulation time 9832947633 ps
CPU time 15.27 seconds
Started Jan 03 02:00:51 PM PST 24
Finished Jan 03 02:01:18 PM PST 24
Peak memory 239912 kb
Host smart-1de2d261-87b7-411f-9ae4-ec587744e41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768815997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.768815997
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3206565744
Short name T1600
Test name
Test status
Simulation time 235473073 ps
CPU time 5.38 seconds
Started Jan 03 02:00:34 PM PST 24
Finished Jan 03 02:00:52 PM PST 24
Peak memory 241408 kb
Host smart-52d98452-e65d-46d6-b36e-4a399455d4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206565744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3206565744
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_perf.3494301770
Short name T1517
Test name
Test status
Simulation time 8685694793 ps
CPU time 611.38 seconds
Started Jan 03 02:00:19 PM PST 24
Finished Jan 03 02:10:38 PM PST 24
Peak memory 241180 kb
Host smart-9255bd19-0948-428c-bd1f-29271c1a452e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494301770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_perf.3494301770
Directory /workspace/37.spi_device_perf/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1261013999
Short name T1214
Test name
Test status
Simulation time 731426620 ps
CPU time 5.06 seconds
Started Jan 03 02:01:26 PM PST 24
Finished Jan 03 02:01:46 PM PST 24
Peak memory 218924 kb
Host smart-5777b84d-15d9-4def-9d6d-7068ca5ebe98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1261013999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1261013999
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_rx_async_fifo_reset.3443647659
Short name T1003
Test name
Test status
Simulation time 71564005 ps
CPU time 0.9 seconds
Started Jan 03 02:00:33 PM PST 24
Finished Jan 03 02:00:46 PM PST 24
Peak memory 208436 kb
Host smart-273daab6-a0c2-4211-b40c-f66fe550eeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443647659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_rx_async_fifo_reset.3443647659
Directory /workspace/37.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/37.spi_device_rx_timeout.488515691
Short name T1374
Test name
Test status
Simulation time 626124979 ps
CPU time 4.99 seconds
Started Jan 03 02:00:17 PM PST 24
Finished Jan 03 02:00:26 PM PST 24
Peak memory 216724 kb
Host smart-a5a966be-535a-4667-91af-6c26d61f64ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488515691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_rx_timeout.488515691
Directory /workspace/37.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/37.spi_device_smoke.1580639934
Short name T1643
Test name
Test status
Simulation time 39945924 ps
CPU time 0.87 seconds
Started Jan 03 02:01:42 PM PST 24
Finished Jan 03 02:02:03 PM PST 24
Peak memory 207836 kb
Host smart-6ea3e61d-2755-4505-8ff4-b69a7c8804d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580639934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_smoke.1580639934
Directory /workspace/37.spi_device_smoke/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1026048379
Short name T1254
Test name
Test status
Simulation time 388641546399 ps
CPU time 741.17 seconds
Started Jan 03 02:01:21 PM PST 24
Finished Jan 03 02:13:58 PM PST 24
Peak memory 541588 kb
Host smart-809d58f3-cb7a-4a61-97d8-5b971eba8d6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026048379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1026048379
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1325330071
Short name T1639
Test name
Test status
Simulation time 50981541687 ps
CPU time 196.92 seconds
Started Jan 03 02:00:22 PM PST 24
Finished Jan 03 02:03:48 PM PST 24
Peak memory 221764 kb
Host smart-dce17603-561f-49cf-a39e-7f39d356dd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325330071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1325330071
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3735249056
Short name T1042
Test name
Test status
Simulation time 5045204178 ps
CPU time 16.02 seconds
Started Jan 03 02:00:22 PM PST 24
Finished Jan 03 02:00:47 PM PST 24
Peak memory 216820 kb
Host smart-85a1b01a-d138-45dd-a895-015e14d96fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735249056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3735249056
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1122929316
Short name T1343
Test name
Test status
Simulation time 801228846 ps
CPU time 7.91 seconds
Started Jan 03 02:00:51 PM PST 24
Finished Jan 03 02:01:12 PM PST 24
Peak memory 216816 kb
Host smart-d0e78b9b-8fbc-4f71-9dc4-b34f2f39b342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122929316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1122929316
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1274431541
Short name T1198
Test name
Test status
Simulation time 72138540 ps
CPU time 1.04 seconds
Started Jan 03 02:00:35 PM PST 24
Finished Jan 03 02:00:49 PM PST 24
Peak memory 206876 kb
Host smart-77400ef2-e2b7-41d6-a83e-44c2145a22eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274431541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1274431541
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_tx_async_fifo_reset.3794222567
Short name T820
Test name
Test status
Simulation time 26864395 ps
CPU time 0.81 seconds
Started Jan 03 02:00:23 PM PST 24
Finished Jan 03 02:00:36 PM PST 24
Peak memory 208476 kb
Host smart-82395660-1aa7-4b85-b579-6c0cc767e93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794222567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tx_async_fifo_reset.3794222567
Directory /workspace/37.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/37.spi_device_txrx.918494742
Short name T1345
Test name
Test status
Simulation time 115815581410 ps
CPU time 516.68 seconds
Started Jan 03 02:01:45 PM PST 24
Finished Jan 03 02:10:41 PM PST 24
Peak memory 262276 kb
Host smart-f125000c-51b6-4fd6-9abf-20e571e1d26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918494742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_txrx.918494742
Directory /workspace/37.spi_device_txrx/latest

Test location /workspace/coverage/default/37.spi_device_upload.3580025375
Short name T1159
Test name
Test status
Simulation time 602013538 ps
CPU time 4.02 seconds
Started Jan 03 02:00:52 PM PST 24
Finished Jan 03 02:01:10 PM PST 24
Peak memory 240460 kb
Host smart-0312e338-b632-484d-a43a-677a498885eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580025375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3580025375
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_abort.3295493210
Short name T1305
Test name
Test status
Simulation time 74062814 ps
CPU time 0.76 seconds
Started Jan 03 02:01:34 PM PST 24
Finished Jan 03 02:01:52 PM PST 24
Peak memory 206552 kb
Host smart-86ca3946-3cb7-41fb-a946-dbf2ea626397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295493210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_abort.3295493210
Directory /workspace/38.spi_device_abort/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1424370020
Short name T1038
Test name
Test status
Simulation time 16255617 ps
CPU time 0.73 seconds
Started Jan 03 02:00:28 PM PST 24
Finished Jan 03 02:00:42 PM PST 24
Peak memory 206488 kb
Host smart-245ce235-63c6-4281-9b56-9b62bb633220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424370020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1424370020
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_bit_transfer.4240015477
Short name T1447
Test name
Test status
Simulation time 98400373 ps
CPU time 2.33 seconds
Started Jan 03 02:01:38 PM PST 24
Finished Jan 03 02:01:57 PM PST 24
Peak memory 216792 kb
Host smart-abe6815a-b6b6-4fbf-bc38-722d1cc36238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240015477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_bit_transfer.4240015477
Directory /workspace/38.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/38.spi_device_byte_transfer.1432965146
Short name T1231
Test name
Test status
Simulation time 443206677 ps
CPU time 3.01 seconds
Started Jan 03 02:01:39 PM PST 24
Finished Jan 03 02:02:01 PM PST 24
Peak memory 216816 kb
Host smart-59964ebb-1393-445e-8a19-399bfdc45be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432965146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_byte_transfer.1432965146
Directory /workspace/38.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2345399875
Short name T317
Test name
Test status
Simulation time 930754027 ps
CPU time 5.65 seconds
Started Jan 03 02:00:22 PM PST 24
Finished Jan 03 02:00:38 PM PST 24
Peak memory 233348 kb
Host smart-05351de2-021d-4474-8600-4e49536ff683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345399875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2345399875
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.191013436
Short name T1651
Test name
Test status
Simulation time 50163522 ps
CPU time 0.76 seconds
Started Jan 03 02:01:22 PM PST 24
Finished Jan 03 02:01:38 PM PST 24
Peak memory 206608 kb
Host smart-8e0cbbd4-93d1-4818-a25a-430ba69b14a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191013436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.191013436
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_dummy_item_extra_dly.1205216309
Short name T1627
Test name
Test status
Simulation time 64194616089 ps
CPU time 506.29 seconds
Started Jan 03 02:01:24 PM PST 24
Finished Jan 03 02:10:06 PM PST 24
Peak memory 285432 kb
Host smart-91ce55da-e7a2-4b71-a539-3d6099b82277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205216309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_dummy_item_extra_dly.1205216309
Directory /workspace/38.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/38.spi_device_extreme_fifo_size.507449598
Short name T1247
Test name
Test status
Simulation time 4014241969 ps
CPU time 51.2 seconds
Started Jan 03 02:01:33 PM PST 24
Finished Jan 03 02:02:42 PM PST 24
Peak memory 234308 kb
Host smart-d47c75a1-c9f1-488e-8e15-ce2dd51e1eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507449598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_extreme_fifo_size.507449598
Directory /workspace/38.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/38.spi_device_fifo_full.3555426968
Short name T1673
Test name
Test status
Simulation time 25191800701 ps
CPU time 432.65 seconds
Started Jan 03 02:01:09 PM PST 24
Finished Jan 03 02:08:32 PM PST 24
Peak memory 282368 kb
Host smart-8ab597ee-7a54-4ab5-8901-b0cb044dbfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555426968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_fifo_full.3555426968
Directory /workspace/38.spi_device_fifo_full/latest

Test location /workspace/coverage/default/38.spi_device_fifo_underflow_overflow.1280655463
Short name T1507
Test name
Test status
Simulation time 113835347667 ps
CPU time 341.58 seconds
Started Jan 03 02:01:21 PM PST 24
Finished Jan 03 02:07:18 PM PST 24
Peak memory 437824 kb
Host smart-8b3171fc-fd3e-4305-935c-0186c109cba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280655463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_fifo_underflow_overf
low.1280655463
Directory /workspace/38.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4229096225
Short name T766
Test name
Test status
Simulation time 110687130786 ps
CPU time 269.52 seconds
Started Jan 03 02:00:42 PM PST 24
Finished Jan 03 02:05:25 PM PST 24
Peak memory 261172 kb
Host smart-c4ad080d-909f-492f-8135-59150821ac17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229096225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4229096225
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3873678461
Short name T674
Test name
Test status
Simulation time 47793903239 ps
CPU time 147.23 seconds
Started Jan 03 02:00:27 PM PST 24
Finished Jan 03 02:03:08 PM PST 24
Peak memory 257984 kb
Host smart-785a4c05-a34f-481d-a3ae-9d9f143c58a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873678461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3873678461
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1219232008
Short name T1325
Test name
Test status
Simulation time 7328959801 ps
CPU time 42.54 seconds
Started Jan 03 02:00:21 PM PST 24
Finished Jan 03 02:01:13 PM PST 24
Peak memory 257108 kb
Host smart-19f3cf3f-893e-4aef-838d-f94824f9c321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219232008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1219232008
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3154061371
Short name T276
Test name
Test status
Simulation time 2824373685 ps
CPU time 6.12 seconds
Started Jan 03 02:01:43 PM PST 24
Finished Jan 03 02:02:08 PM PST 24
Peak memory 220804 kb
Host smart-2a5470e2-efe3-439d-8d5c-5c970dd1e9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154061371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3154061371
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_intr.460347175
Short name T1583
Test name
Test status
Simulation time 16553934438 ps
CPU time 58.76 seconds
Started Jan 03 02:01:09 PM PST 24
Finished Jan 03 02:02:18 PM PST 24
Peak memory 231148 kb
Host smart-267c2ba4-c41a-4e89-8dab-b22934f30ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460347175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intr.460347175
Directory /workspace/38.spi_device_intr/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2124150440
Short name T1235
Test name
Test status
Simulation time 20726203988 ps
CPU time 38.51 seconds
Started Jan 03 02:00:22 PM PST 24
Finished Jan 03 02:01:10 PM PST 24
Peak memory 230856 kb
Host smart-9b52f83d-0702-418d-97cf-1592d9a6e89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124150440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2124150440
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2786095436
Short name T234
Test name
Test status
Simulation time 45231739632 ps
CPU time 14.27 seconds
Started Jan 03 02:00:35 PM PST 24
Finished Jan 03 02:01:02 PM PST 24
Peak memory 219300 kb
Host smart-f20faf2e-78d9-4de9-b413-aeddabf7292b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786095436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2786095436
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2431114786
Short name T1574
Test name
Test status
Simulation time 92821891 ps
CPU time 2.68 seconds
Started Jan 03 02:01:47 PM PST 24
Finished Jan 03 02:02:08 PM PST 24
Peak memory 218608 kb
Host smart-3681bb42-3139-4d97-a767-298b07b39d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431114786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2431114786
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_perf.4013841887
Short name T1618
Test name
Test status
Simulation time 115864163748 ps
CPU time 1673.36 seconds
Started Jan 03 02:01:30 PM PST 24
Finished Jan 03 02:29:38 PM PST 24
Peak memory 274248 kb
Host smart-01e6f3fe-b3c6-4c7a-90cb-4640bde098c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013841887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_perf.4013841887
Directory /workspace/38.spi_device_perf/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1992839237
Short name T906
Test name
Test status
Simulation time 1499847520 ps
CPU time 7.06 seconds
Started Jan 03 02:00:26 PM PST 24
Finished Jan 03 02:00:47 PM PST 24
Peak memory 234400 kb
Host smart-08b9ec4f-3b2d-4c1c-8579-0e7ef57939f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1992839237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1992839237
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_rx_async_fifo_reset.912594578
Short name T1423
Test name
Test status
Simulation time 18513975 ps
CPU time 0.84 seconds
Started Jan 03 02:01:38 PM PST 24
Finished Jan 03 02:01:56 PM PST 24
Peak memory 208524 kb
Host smart-50aad811-186f-46cc-b7ad-0f416151587f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912594578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_rx_async_fifo_reset.912594578
Directory /workspace/38.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/38.spi_device_rx_timeout.3239559169
Short name T1722
Test name
Test status
Simulation time 493745633 ps
CPU time 5.05 seconds
Started Jan 03 02:01:33 PM PST 24
Finished Jan 03 02:01:55 PM PST 24
Peak memory 216712 kb
Host smart-bcf2fe63-46bb-41e9-98bb-3e7058bb0c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239559169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_rx_timeout.3239559169
Directory /workspace/38.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/38.spi_device_smoke.1957235350
Short name T952
Test name
Test status
Simulation time 20549649 ps
CPU time 1.07 seconds
Started Jan 03 02:01:09 PM PST 24
Finished Jan 03 02:01:21 PM PST 24
Peak memory 216624 kb
Host smart-747641d6-9212-44bb-b2b9-adab4151119f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957235350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_smoke.1957235350
Directory /workspace/38.spi_device_smoke/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.94680142
Short name T229
Test name
Test status
Simulation time 148357018584 ps
CPU time 2930.82 seconds
Started Jan 03 02:00:22 PM PST 24
Finished Jan 03 02:49:24 PM PST 24
Peak memory 573900 kb
Host smart-a2ec8fd4-092f-4912-b45d-9c2ce30fa8cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94680142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress
_all.94680142
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4072301295
Short name T569
Test name
Test status
Simulation time 361319850 ps
CPU time 2.5 seconds
Started Jan 03 02:01:35 PM PST 24
Finished Jan 03 02:01:55 PM PST 24
Peak memory 217176 kb
Host smart-66850c19-7173-4abd-8962-c69eb45b82f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072301295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4072301295
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.267396293
Short name T1432
Test name
Test status
Simulation time 2219528469 ps
CPU time 12.83 seconds
Started Jan 03 02:01:38 PM PST 24
Finished Jan 03 02:02:08 PM PST 24
Peak memory 216836 kb
Host smart-4093cd3c-8daf-46e4-8507-df2fd7339f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267396293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.267396293
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.4257311126
Short name T712
Test name
Test status
Simulation time 203123898 ps
CPU time 0.91 seconds
Started Jan 03 02:01:33 PM PST 24
Finished Jan 03 02:01:51 PM PST 24
Peak memory 206912 kb
Host smart-5db50bff-600e-48b3-bdd3-cccdb471b37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257311126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4257311126
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1313693718
Short name T1354
Test name
Test status
Simulation time 120868267 ps
CPU time 1 seconds
Started Jan 03 02:01:52 PM PST 24
Finished Jan 03 02:02:09 PM PST 24
Peak memory 208128 kb
Host smart-c2213374-878d-4ad4-8a3f-468b624e043d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313693718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1313693718
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_tx_async_fifo_reset.536959828
Short name T1602
Test name
Test status
Simulation time 50136816 ps
CPU time 0.77 seconds
Started Jan 03 02:01:33 PM PST 24
Finished Jan 03 02:01:50 PM PST 24
Peak memory 208384 kb
Host smart-75db9c9a-abd6-40c0-b4d8-6afcbe947f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536959828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tx_async_fifo_reset.536959828
Directory /workspace/38.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/38.spi_device_txrx.943975121
Short name T1751
Test name
Test status
Simulation time 71244847809 ps
CPU time 179.95 seconds
Started Jan 03 02:01:23 PM PST 24
Finished Jan 03 02:04:39 PM PST 24
Peak memory 249016 kb
Host smart-a69f417e-4c7f-432b-aa54-2866609d303a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943975121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_txrx.943975121
Directory /workspace/38.spi_device_txrx/latest

Test location /workspace/coverage/default/38.spi_device_upload.3835276331
Short name T1521
Test name
Test status
Simulation time 22687367552 ps
CPU time 19 seconds
Started Jan 03 02:00:24 PM PST 24
Finished Jan 03 02:00:55 PM PST 24
Peak memory 239356 kb
Host smart-d1c5c1cc-9168-415f-a9e5-6c2d409f2a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835276331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3835276331
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_abort.1410850601
Short name T565
Test name
Test status
Simulation time 27835907 ps
CPU time 0.73 seconds
Started Jan 03 02:00:34 PM PST 24
Finished Jan 03 02:00:47 PM PST 24
Peak memory 206640 kb
Host smart-d0ded15b-fd1a-4332-b434-787def159d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410850601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_abort.1410850601
Directory /workspace/39.spi_device_abort/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3631517897
Short name T1568
Test name
Test status
Simulation time 11613804 ps
CPU time 0.71 seconds
Started Jan 03 02:01:25 PM PST 24
Finished Jan 03 02:01:41 PM PST 24
Peak memory 206464 kb
Host smart-43a5a687-f5eb-462c-8cfa-46dc467454a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631517897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3631517897
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_bit_transfer.1218260580
Short name T1111
Test name
Test status
Simulation time 223295467 ps
CPU time 2.32 seconds
Started Jan 03 02:00:34 PM PST 24
Finished Jan 03 02:00:49 PM PST 24
Peak memory 216808 kb
Host smart-77c6bdeb-01c3-465e-832b-a07054254f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218260580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_bit_transfer.1218260580
Directory /workspace/39.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/39.spi_device_byte_transfer.3403834408
Short name T12
Test name
Test status
Simulation time 470821486 ps
CPU time 2.84 seconds
Started Jan 03 02:00:49 PM PST 24
Finished Jan 03 02:01:03 PM PST 24
Peak memory 216684 kb
Host smart-3317c630-b8c3-4f71-8647-c1a83fa68d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403834408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_byte_transfer.3403834408
Directory /workspace/39.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2238706625
Short name T1135
Test name
Test status
Simulation time 12953354471 ps
CPU time 5.81 seconds
Started Jan 03 02:01:12 PM PST 24
Finished Jan 03 02:01:28 PM PST 24
Peak memory 221092 kb
Host smart-5bdc980e-06e0-4b5c-a01a-82a8c7588509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238706625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2238706625
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.4148585734
Short name T1342
Test name
Test status
Simulation time 277370320 ps
CPU time 0.78 seconds
Started Jan 03 02:00:27 PM PST 24
Finished Jan 03 02:00:41 PM PST 24
Peak memory 207652 kb
Host smart-6d5c4fc7-957e-4df7-99fe-66ec5bca74bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148585734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4148585734
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_dummy_item_extra_dly.324011022
Short name T1161
Test name
Test status
Simulation time 37460439019 ps
CPU time 166.65 seconds
Started Jan 03 02:00:41 PM PST 24
Finished Jan 03 02:03:40 PM PST 24
Peak memory 289632 kb
Host smart-b18b30d8-0128-4e32-9c6a-68a7a21041b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324011022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_dummy_item_extra_dly.324011022
Directory /workspace/39.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/39.spi_device_extreme_fifo_size.1255046415
Short name T792
Test name
Test status
Simulation time 2423077769 ps
CPU time 38.13 seconds
Started Jan 03 02:00:48 PM PST 24
Finished Jan 03 02:01:37 PM PST 24
Peak memory 233072 kb
Host smart-62e6721f-7643-48ac-a7aa-72199c2b97ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255046415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_extreme_fifo_size.1255046415
Directory /workspace/39.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/39.spi_device_fifo_full.2646973358
Short name T1394
Test name
Test status
Simulation time 74668300344 ps
CPU time 473.97 seconds
Started Jan 03 02:00:26 PM PST 24
Finished Jan 03 02:08:33 PM PST 24
Peak memory 285652 kb
Host smart-f220c7bb-5922-4c3c-9296-bcb590615f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646973358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_fifo_full.2646973358
Directory /workspace/39.spi_device_fifo_full/latest

Test location /workspace/coverage/default/39.spi_device_fifo_underflow_overflow.2673046698
Short name T1389
Test name
Test status
Simulation time 24972939997 ps
CPU time 264.67 seconds
Started Jan 03 02:00:28 PM PST 24
Finished Jan 03 02:05:06 PM PST 24
Peak memory 405836 kb
Host smart-de94b58f-5749-4841-99bf-4e9e4e33130c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673046698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_fifo_underflow_overf
low.2673046698
Directory /workspace/39.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1577400114
Short name T377
Test name
Test status
Simulation time 106493846161 ps
CPU time 513.23 seconds
Started Jan 03 02:01:43 PM PST 24
Finished Jan 03 02:10:36 PM PST 24
Peak memory 269380 kb
Host smart-5b8ef890-c8df-4609-a713-801f43cda62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577400114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1577400114
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2233822209
Short name T1134
Test name
Test status
Simulation time 37792093545 ps
CPU time 92.33 seconds
Started Jan 03 02:01:05 PM PST 24
Finished Jan 03 02:02:50 PM PST 24
Peak memory 241552 kb
Host smart-aa5610e7-9d2b-4c72-8789-472c02a7f53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233822209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2233822209
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.4012619807
Short name T29
Test name
Test status
Simulation time 7996590943 ps
CPU time 106.67 seconds
Started Jan 03 02:01:39 PM PST 24
Finished Jan 03 02:03:43 PM PST 24
Peak memory 253584 kb
Host smart-ceb49742-19c2-446b-9a6d-fa75a896b9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012619807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.4012619807
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3879274209
Short name T389
Test name
Test status
Simulation time 40078351921 ps
CPU time 53.4 seconds
Started Jan 03 02:01:31 PM PST 24
Finished Jan 03 02:02:39 PM PST 24
Peak memory 246960 kb
Host smart-5ab1fb76-c25b-4e78-beeb-06798e70748f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879274209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3879274209
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.163939443
Short name T1150
Test name
Test status
Simulation time 600609888 ps
CPU time 4.45 seconds
Started Jan 03 02:01:06 PM PST 24
Finished Jan 03 02:01:22 PM PST 24
Peak memory 220904 kb
Host smart-9899fbfe-3877-441e-a3b0-b0f2da520b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163939443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.163939443
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_intr.3050808023
Short name T119
Test name
Test status
Simulation time 4098685616 ps
CPU time 29.51 seconds
Started Jan 03 02:00:27 PM PST 24
Finished Jan 03 02:01:10 PM PST 24
Peak memory 233344 kb
Host smart-a7f88c07-574b-44d7-a15c-f23819613576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050808023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intr.3050808023
Directory /workspace/39.spi_device_intr/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4172401827
Short name T330
Test name
Test status
Simulation time 11992216737 ps
CPU time 25.44 seconds
Started Jan 03 02:01:24 PM PST 24
Finished Jan 03 02:02:05 PM PST 24
Peak memory 236052 kb
Host smart-4d1c76d7-a2b0-4f1e-a68e-5a966d981c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172401827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4172401827
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3880967060
Short name T1658
Test name
Test status
Simulation time 553564744 ps
CPU time 6.63 seconds
Started Jan 03 02:01:04 PM PST 24
Finished Jan 03 02:01:23 PM PST 24
Peak memory 218832 kb
Host smart-c84c3e6f-a08d-4134-a411-c4610dcbfbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880967060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3880967060
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3814385316
Short name T240
Test name
Test status
Simulation time 1898735853 ps
CPU time 9.31 seconds
Started Jan 03 02:01:23 PM PST 24
Finished Jan 03 02:01:48 PM PST 24
Peak memory 231740 kb
Host smart-06915b0a-8f0d-4e0e-9fb6-c687a7835275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814385316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3814385316
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_perf.1976425260
Short name T1016
Test name
Test status
Simulation time 7461023895 ps
CPU time 232.38 seconds
Started Jan 03 02:00:28 PM PST 24
Finished Jan 03 02:04:34 PM PST 24
Peak memory 306764 kb
Host smart-0876d4a5-6218-49f1-9304-5018a19d8991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976425260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_perf.1976425260
Directory /workspace/39.spi_device_perf/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.91263890
Short name T1255
Test name
Test status
Simulation time 657616750 ps
CPU time 3.72 seconds
Started Jan 03 02:01:23 PM PST 24
Finished Jan 03 02:01:42 PM PST 24
Peak memory 220872 kb
Host smart-8f6b2557-2e1d-423d-9970-c76c072744b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=91263890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direc
t.91263890
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_rx_async_fifo_reset.2620737271
Short name T810
Test name
Test status
Simulation time 21818012 ps
CPU time 0.85 seconds
Started Jan 03 02:01:05 PM PST 24
Finished Jan 03 02:01:18 PM PST 24
Peak memory 208396 kb
Host smart-30081762-1cde-4650-bc33-8428f0dc0ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620737271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_rx_async_fifo_reset.2620737271
Directory /workspace/39.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/39.spi_device_rx_timeout.3374006666
Short name T1545
Test name
Test status
Simulation time 1243036786 ps
CPU time 5.83 seconds
Started Jan 03 02:00:52 PM PST 24
Finished Jan 03 02:01:12 PM PST 24
Peak memory 216880 kb
Host smart-1f16c930-faa5-478f-9247-1e0908445d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374006666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_rx_timeout.3374006666
Directory /workspace/39.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/39.spi_device_smoke.278255258
Short name T1713
Test name
Test status
Simulation time 123771962 ps
CPU time 1.3 seconds
Started Jan 03 02:00:52 PM PST 24
Finished Jan 03 02:01:08 PM PST 24
Peak memory 216760 kb
Host smart-62eda3e9-f6bb-4d18-9451-bc2053bffcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278255258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_smoke.278255258
Directory /workspace/39.spi_device_smoke/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2516366492
Short name T846
Test name
Test status
Simulation time 10069724813 ps
CPU time 36.42 seconds
Started Jan 03 02:00:51 PM PST 24
Finished Jan 03 02:01:41 PM PST 24
Peak memory 216884 kb
Host smart-e7f0dd12-8bcf-4392-b8c9-93c8bbd7f1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516366492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2516366492
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3658911422
Short name T668
Test name
Test status
Simulation time 4261743282 ps
CPU time 12.6 seconds
Started Jan 03 02:00:33 PM PST 24
Finished Jan 03 02:00:58 PM PST 24
Peak memory 216904 kb
Host smart-9f5b0a54-7d37-45c4-97de-6cbc23c56f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658911422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3658911422
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1436737547
Short name T904
Test name
Test status
Simulation time 134314921 ps
CPU time 2.22 seconds
Started Jan 03 02:00:53 PM PST 24
Finished Jan 03 02:01:09 PM PST 24
Peak memory 216748 kb
Host smart-897bb5dd-e5a8-46aa-a960-4469451b86a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436737547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1436737547
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1601928491
Short name T759
Test name
Test status
Simulation time 114188215 ps
CPU time 1.08 seconds
Started Jan 03 02:00:34 PM PST 24
Finished Jan 03 02:00:47 PM PST 24
Peak memory 208012 kb
Host smart-f5ac7c2e-2f85-475d-9902-3b026fa11268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601928491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1601928491
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_tx_async_fifo_reset.1301542338
Short name T1763
Test name
Test status
Simulation time 54866594 ps
CPU time 0.78 seconds
Started Jan 03 02:00:53 PM PST 24
Finished Jan 03 02:01:07 PM PST 24
Peak memory 208412 kb
Host smart-32b257db-612f-429a-8c0e-1c8f72de5a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301542338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tx_async_fifo_reset.1301542338
Directory /workspace/39.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/39.spi_device_txrx.3534289269
Short name T1068
Test name
Test status
Simulation time 66629592597 ps
CPU time 205.53 seconds
Started Jan 03 02:00:28 PM PST 24
Finished Jan 03 02:04:07 PM PST 24
Peak memory 295716 kb
Host smart-198c9f15-d2c4-4275-8bd0-b63c980d60b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534289269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_txrx.3534289269
Directory /workspace/39.spi_device_txrx/latest

Test location /workspace/coverage/default/39.spi_device_upload.3320651552
Short name T21
Test name
Test status
Simulation time 7523430904 ps
CPU time 7.53 seconds
Started Jan 03 02:01:24 PM PST 24
Finished Jan 03 02:01:47 PM PST 24
Peak memory 220252 kb
Host smart-6c0883a3-ddf7-49f0-aff0-fbd6f495d27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320651552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3320651552
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_abort.1710175428
Short name T1238
Test name
Test status
Simulation time 72025280 ps
CPU time 0.75 seconds
Started Jan 03 01:51:23 PM PST 24
Finished Jan 03 01:51:37 PM PST 24
Peak memory 206564 kb
Host smart-2a5e3f6e-33b1-42fb-befa-6325b786c9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710175428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_abort.1710175428
Directory /workspace/4.spi_device_abort/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2893020008
Short name T1688
Test name
Test status
Simulation time 25117389 ps
CPU time 0.73 seconds
Started Jan 03 01:51:21 PM PST 24
Finished Jan 03 01:51:32 PM PST 24
Peak memory 206512 kb
Host smart-ece162ff-40ed-4a0f-a05a-1b20e39d35a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893020008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
893020008
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_bit_transfer.3736797148
Short name T609
Test name
Test status
Simulation time 184623886 ps
CPU time 2.33 seconds
Started Jan 03 01:50:49 PM PST 24
Finished Jan 03 01:51:01 PM PST 24
Peak memory 216844 kb
Host smart-6450233f-f656-4126-9bf3-55da3c18b102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736797148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_bit_transfer.3736797148
Directory /workspace/4.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/4.spi_device_byte_transfer.582919762
Short name T1414
Test name
Test status
Simulation time 444972095 ps
CPU time 2.53 seconds
Started Jan 03 01:51:04 PM PST 24
Finished Jan 03 01:51:10 PM PST 24
Peak memory 216816 kb
Host smart-025f2b32-15b8-4de1-a0b1-24b15c404b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582919762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_byte_transfer.582919762
Directory /workspace/4.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.4264031207
Short name T1328
Test name
Test status
Simulation time 2297058811 ps
CPU time 9.17 seconds
Started Jan 03 01:51:26 PM PST 24
Finished Jan 03 01:51:53 PM PST 24
Peak memory 236064 kb
Host smart-d71dea79-ff4a-4cf5-8e23-26429a547ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264031207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4264031207
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2644461376
Short name T1729
Test name
Test status
Simulation time 27818071 ps
CPU time 0.78 seconds
Started Jan 03 01:50:46 PM PST 24
Finished Jan 03 01:50:56 PM PST 24
Peak memory 207524 kb
Host smart-e95a390b-8d8b-45ec-8932-6ef40405adc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644461376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2644461376
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_dummy_item_extra_dly.3697963790
Short name T1613
Test name
Test status
Simulation time 62629365541 ps
CPU time 137.86 seconds
Started Jan 03 01:51:23 PM PST 24
Finished Jan 03 01:53:55 PM PST 24
Peak memory 278504 kb
Host smart-f61ad39b-a3bb-484a-b69e-b7b5b3a9609e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697963790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_dummy_item_extra_dly.3697963790
Directory /workspace/4.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/4.spi_device_extreme_fifo_size.1459530708
Short name T1585
Test name
Test status
Simulation time 392177810588 ps
CPU time 2043.62 seconds
Started Jan 03 01:51:02 PM PST 24
Finished Jan 03 02:25:10 PM PST 24
Peak memory 217932 kb
Host smart-5e9fc2c4-6ca9-4795-adfd-5207a1b45250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459530708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_extreme_fifo_size.1459530708
Directory /workspace/4.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/4.spi_device_fifo_full.29585431
Short name T719
Test name
Test status
Simulation time 73631270431 ps
CPU time 586.09 seconds
Started Jan 03 01:51:02 PM PST 24
Finished Jan 03 02:00:52 PM PST 24
Peak memory 309316 kb
Host smart-20da2a98-891c-4f1e-8f99-03ac9990cbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29585431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_fifo_full.29585431
Directory /workspace/4.spi_device_fifo_full/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.527234976
Short name T1119
Test name
Test status
Simulation time 39216294337 ps
CPU time 273.63 seconds
Started Jan 03 01:51:21 PM PST 24
Finished Jan 03 01:56:06 PM PST 24
Peak memory 255476 kb
Host smart-c9dfb33f-6857-494a-9da7-b60c71c66515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527234976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.527234976
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.642508615
Short name T378
Test name
Test status
Simulation time 9285978627 ps
CPU time 129.62 seconds
Started Jan 03 01:51:21 PM PST 24
Finished Jan 03 01:53:40 PM PST 24
Peak memory 274396 kb
Host smart-e2002857-c552-46c4-acff-9ef400add0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642508615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
642508615
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2795674412
Short name T187
Test name
Test status
Simulation time 607875015 ps
CPU time 11.52 seconds
Started Jan 03 01:51:29 PM PST 24
Finished Jan 03 01:52:02 PM PST 24
Peak memory 250720 kb
Host smart-c86ffe8d-51ed-49a0-85c0-c2691b7dd621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795674412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2795674412
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.754061454
Short name T59
Test name
Test status
Simulation time 9198993128 ps
CPU time 9.68 seconds
Started Jan 03 01:51:22 PM PST 24
Finished Jan 03 01:51:44 PM PST 24
Peak memory 225028 kb
Host smart-da42ea7a-942f-462b-8bd3-6676176e6abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754061454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.754061454
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_intr.1494005068
Short name T578
Test name
Test status
Simulation time 5665658079 ps
CPU time 33.55 seconds
Started Jan 03 01:50:57 PM PST 24
Finished Jan 03 01:51:36 PM PST 24
Peak memory 223228 kb
Host smart-0954e7a2-4b5a-43d7-ac98-3e4522843a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494005068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intr.1494005068
Directory /workspace/4.spi_device_intr/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1772976919
Short name T1693
Test name
Test status
Simulation time 4593441876 ps
CPU time 9.29 seconds
Started Jan 03 01:51:22 PM PST 24
Finished Jan 03 01:51:43 PM PST 24
Peak memory 238136 kb
Host smart-87bc0396-99f0-4422-b917-3a339811bf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772976919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1772976919
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.336593949
Short name T39
Test name
Test status
Simulation time 71428573 ps
CPU time 1.04 seconds
Started Jan 03 01:51:05 PM PST 24
Finished Jan 03 01:51:12 PM PST 24
Peak memory 218968 kb
Host smart-a1cd93d4-7efe-4437-9d76-9af2f8695ded
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336593949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.336593949
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.840379243
Short name T1265
Test name
Test status
Simulation time 8038561652 ps
CPU time 27.79 seconds
Started Jan 03 01:51:20 PM PST 24
Finished Jan 03 01:51:57 PM PST 24
Peak memory 233284 kb
Host smart-16005aca-f59b-4405-a374-1add08c24b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840379243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
840379243
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3014431803
Short name T1300
Test name
Test status
Simulation time 3178143731 ps
CPU time 9.91 seconds
Started Jan 03 01:51:23 PM PST 24
Finished Jan 03 01:51:45 PM PST 24
Peak memory 219520 kb
Host smart-a28c2ea6-b67c-4b95-b5ce-13cf297547db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014431803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3014431803
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_perf.1933616145
Short name T1059
Test name
Test status
Simulation time 95274561701 ps
CPU time 600.81 seconds
Started Jan 03 01:50:58 PM PST 24
Finished Jan 03 02:01:04 PM PST 24
Peak memory 306652 kb
Host smart-fbf5bdfa-fb48-4941-b6d4-7fdff2c79eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933616145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_perf.1933616145
Directory /workspace/4.spi_device_perf/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.2331635503
Short name T1413
Test name
Test status
Simulation time 15511531 ps
CPU time 0.77 seconds
Started Jan 03 01:50:35 PM PST 24
Finished Jan 03 01:50:43 PM PST 24
Peak memory 216756 kb
Host smart-bc50ab47-4ce1-45e0-89fd-f773f99e8fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331635503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.2331635503
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.4243328708
Short name T1181
Test name
Test status
Simulation time 83717275 ps
CPU time 3.63 seconds
Started Jan 03 01:51:24 PM PST 24
Finished Jan 03 01:51:41 PM PST 24
Peak memory 220488 kb
Host smart-53479811-39aa-4500-a2c3-395efcc1b9ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4243328708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.4243328708
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_rx_async_fifo_reset.3946921073
Short name T1677
Test name
Test status
Simulation time 58539657 ps
CPU time 0.95 seconds
Started Jan 03 01:51:27 PM PST 24
Finished Jan 03 01:51:49 PM PST 24
Peak memory 208524 kb
Host smart-3d9eaddf-9092-4e17-9381-542a8e761365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946921073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_rx_async_fifo_reset.3946921073
Directory /workspace/4.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/4.spi_device_rx_timeout.3763654728
Short name T634
Test name
Test status
Simulation time 1885831060 ps
CPU time 5.89 seconds
Started Jan 03 01:50:46 PM PST 24
Finished Jan 03 01:51:01 PM PST 24
Peak memory 216844 kb
Host smart-82279d0d-cf55-4888-adee-d4493d35eec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763654728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_rx_timeout.3763654728
Directory /workspace/4.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1218285648
Short name T106
Test name
Test status
Simulation time 131292525 ps
CPU time 1 seconds
Started Jan 03 01:51:07 PM PST 24
Finished Jan 03 01:51:16 PM PST 24
Peak memory 235756 kb
Host smart-8abcdc95-bf7b-4945-8075-6774474c2eb8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218285648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1218285648
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_smoke.2333025487
Short name T1187
Test name
Test status
Simulation time 29890659 ps
CPU time 0.95 seconds
Started Jan 03 01:51:28 PM PST 24
Finished Jan 03 01:51:51 PM PST 24
Peak memory 207840 kb
Host smart-7294a5f1-ab6c-4e09-89cb-c8528aeddc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333025487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_smoke.2333025487
Directory /workspace/4.spi_device_smoke/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1672634672
Short name T151
Test name
Test status
Simulation time 530364367473 ps
CPU time 5859.22 seconds
Started Jan 03 01:51:21 PM PST 24
Finished Jan 03 03:29:12 PM PST 24
Peak memory 301148 kb
Host smart-e3b98fe4-0ed8-4ff2-8fc1-1c8db7452d92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672634672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1672634672
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1537087204
Short name T117
Test name
Test status
Simulation time 442292715 ps
CPU time 3.94 seconds
Started Jan 03 01:51:05 PM PST 24
Finished Jan 03 01:51:13 PM PST 24
Peak memory 218620 kb
Host smart-7ffd55f1-ee57-4040-92fb-785dfcfdd0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537087204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1537087204
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.150993250
Short name T662
Test name
Test status
Simulation time 13201139897 ps
CPU time 40.4 seconds
Started Jan 03 01:51:01 PM PST 24
Finished Jan 03 01:51:46 PM PST 24
Peak memory 216832 kb
Host smart-4d2e75ad-1d44-4a65-90b7-ba5448af6323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150993250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.150993250
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.31635356
Short name T1089
Test name
Test status
Simulation time 119566273 ps
CPU time 4.91 seconds
Started Jan 03 01:51:29 PM PST 24
Finished Jan 03 01:51:56 PM PST 24
Peak memory 216904 kb
Host smart-375404be-5deb-423f-aba5-b9e7914c27ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31635356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.31635356
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1803851338
Short name T1064
Test name
Test status
Simulation time 48783034 ps
CPU time 0.86 seconds
Started Jan 03 01:51:28 PM PST 24
Finished Jan 03 01:51:51 PM PST 24
Peak memory 206884 kb
Host smart-8d3045ff-45f4-468c-9c29-8b147dc0eaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803851338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1803851338
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_tx_async_fifo_reset.4161157465
Short name T154
Test name
Test status
Simulation time 132846031 ps
CPU time 0.79 seconds
Started Jan 03 01:51:22 PM PST 24
Finished Jan 03 01:51:35 PM PST 24
Peak memory 208420 kb
Host smart-ee8a31c0-fb4c-4895-8ff2-1ca87d8e3181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161157465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tx_async_fifo_reset.4161157465
Directory /workspace/4.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/4.spi_device_txrx.3935907914
Short name T200
Test name
Test status
Simulation time 51015190481 ps
CPU time 131.06 seconds
Started Jan 03 01:51:00 PM PST 24
Finished Jan 03 01:53:15 PM PST 24
Peak memory 269488 kb
Host smart-128f7e72-8d4c-41aa-9724-1abbefca4a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935907914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_txrx.3935907914
Directory /workspace/4.spi_device_txrx/latest

Test location /workspace/coverage/default/4.spi_device_upload.657881383
Short name T1624
Test name
Test status
Simulation time 424957236 ps
CPU time 2.62 seconds
Started Jan 03 01:51:22 PM PST 24
Finished Jan 03 01:51:36 PM PST 24
Peak memory 218780 kb
Host smart-fb50f546-e639-4609-86fb-e5bfbb82194a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657881383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.657881383
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_abort.1877475153
Short name T838
Test name
Test status
Simulation time 43574820 ps
CPU time 0.74 seconds
Started Jan 03 02:00:29 PM PST 24
Finished Jan 03 02:00:42 PM PST 24
Peak memory 206616 kb
Host smart-3f92f520-c2cd-43ab-b992-3fabfec45b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877475153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_abort.1877475153
Directory /workspace/40.spi_device_abort/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.832922915
Short name T602
Test name
Test status
Simulation time 32176873 ps
CPU time 0.69 seconds
Started Jan 03 02:00:42 PM PST 24
Finished Jan 03 02:00:55 PM PST 24
Peak memory 206536 kb
Host smart-c0e0e5b8-1322-4f6f-a58f-92b0be5c3b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832922915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.832922915
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_bit_transfer.457457909
Short name T731
Test name
Test status
Simulation time 1709022321 ps
CPU time 3.28 seconds
Started Jan 03 02:01:34 PM PST 24
Finished Jan 03 02:01:55 PM PST 24
Peak memory 216904 kb
Host smart-c1e32018-7bea-4289-af00-2d4fac220e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457457909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_bit_transfer.457457909
Directory /workspace/40.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/40.spi_device_byte_transfer.275492531
Short name T1474
Test name
Test status
Simulation time 100128954 ps
CPU time 2.86 seconds
Started Jan 03 02:01:45 PM PST 24
Finished Jan 03 02:02:07 PM PST 24
Peak memory 216808 kb
Host smart-c8d55ee2-872e-49ae-9c3d-1851d2672eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275492531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_byte_transfer.275492531
Directory /workspace/40.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2940120264
Short name T1232
Test name
Test status
Simulation time 114148639 ps
CPU time 3.26 seconds
Started Jan 03 02:00:27 PM PST 24
Finished Jan 03 02:00:44 PM PST 24
Peak memory 219536 kb
Host smart-d30b2d85-2aea-4acd-b801-3f09d7fc1554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940120264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2940120264
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.305972943
Short name T597
Test name
Test status
Simulation time 17901867 ps
CPU time 0.78 seconds
Started Jan 03 02:01:30 PM PST 24
Finished Jan 03 02:01:45 PM PST 24
Peak memory 207560 kb
Host smart-d6a08f2f-a31e-4e6f-86f3-d7ff1b45d7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305972943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.305972943
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_dummy_item_extra_dly.3718361480
Short name T1418
Test name
Test status
Simulation time 321860381861 ps
CPU time 245 seconds
Started Jan 03 02:01:38 PM PST 24
Finished Jan 03 02:06:01 PM PST 24
Peak memory 265908 kb
Host smart-74176211-6125-4cab-97be-5b62bbf9799b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718361480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_dummy_item_extra_dly.3718361480
Directory /workspace/40.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/40.spi_device_extreme_fifo_size.2557775609
Short name T1760
Test name
Test status
Simulation time 186363627312 ps
CPU time 1773.75 seconds
Started Jan 03 02:01:38 PM PST 24
Finished Jan 03 02:31:30 PM PST 24
Peak memory 218040 kb
Host smart-46f01ced-ffb8-4823-8d09-10321e9f1309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557775609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_extreme_fifo_size.2557775609
Directory /workspace/40.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/40.spi_device_fifo_full.1118409662
Short name T1781
Test name
Test status
Simulation time 15816854088 ps
CPU time 924.98 seconds
Started Jan 03 02:01:32 PM PST 24
Finished Jan 03 02:17:14 PM PST 24
Peak memory 297828 kb
Host smart-4ad76faa-7c3e-4f65-a033-b432a9bde084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118409662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_fifo_full.1118409662
Directory /workspace/40.spi_device_fifo_full/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2332074435
Short name T835
Test name
Test status
Simulation time 590721559 ps
CPU time 5.69 seconds
Started Jan 03 02:00:52 PM PST 24
Finished Jan 03 02:01:12 PM PST 24
Peak memory 220368 kb
Host smart-9865a71a-7e9b-48af-8608-ee1b877af104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332074435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2332074435
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.4105252419
Short name T1663
Test name
Test status
Simulation time 8198672802 ps
CPU time 95.11 seconds
Started Jan 03 02:00:27 PM PST 24
Finished Jan 03 02:02:15 PM PST 24
Peak memory 274088 kb
Host smart-87526e39-af35-4724-acba-00eafb06ed22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105252419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.4105252419
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.600990283
Short name T267
Test name
Test status
Simulation time 20533966085 ps
CPU time 41.31 seconds
Started Jan 03 02:00:27 PM PST 24
Finished Jan 03 02:01:22 PM PST 24
Peak memory 248752 kb
Host smart-588d33bc-c0f1-4328-8959-61d91105ae0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600990283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.600990283
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3114567426
Short name T250
Test name
Test status
Simulation time 507845952 ps
CPU time 4.97 seconds
Started Jan 03 02:00:26 PM PST 24
Finished Jan 03 02:00:45 PM PST 24
Peak memory 238484 kb
Host smart-c641dcc9-7578-4052-a2ec-2e944b07002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114567426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3114567426
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_intr.1243539581
Short name T147
Test name
Test status
Simulation time 24866725473 ps
CPU time 94.5 seconds
Started Jan 03 02:01:45 PM PST 24
Finished Jan 03 02:03:39 PM PST 24
Peak memory 241436 kb
Host smart-19ec74b5-935d-444e-8233-f14913088ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243539581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intr.1243539581
Directory /workspace/40.spi_device_intr/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2840508783
Short name T1719
Test name
Test status
Simulation time 7895961592 ps
CPU time 24.58 seconds
Started Jan 03 02:00:25 PM PST 24
Finished Jan 03 02:01:02 PM PST 24
Peak memory 233264 kb
Host smart-8a153d7f-0ddb-49a7-9449-eaae5b2f10f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840508783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2840508783
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.392878520
Short name T383
Test name
Test status
Simulation time 24434003595 ps
CPU time 36.47 seconds
Started Jan 03 02:00:35 PM PST 24
Finished Jan 03 02:01:24 PM PST 24
Peak memory 229256 kb
Host smart-649eb855-a13b-406c-be5e-63f2a8a052a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392878520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.392878520
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1036856967
Short name T1463
Test name
Test status
Simulation time 33921699910 ps
CPU time 25.93 seconds
Started Jan 03 02:00:28 PM PST 24
Finished Jan 03 02:01:07 PM PST 24
Peak memory 249796 kb
Host smart-319d6021-bedb-4464-a3a5-b9e7e880409b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036856967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1036856967
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_perf.3823766942
Short name T1551
Test name
Test status
Simulation time 27707374234 ps
CPU time 744.95 seconds
Started Jan 03 02:01:34 PM PST 24
Finished Jan 03 02:14:17 PM PST 24
Peak memory 291640 kb
Host smart-a18fb864-9f64-48e1-9389-67254d9c67f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823766942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_perf.3823766942
Directory /workspace/40.spi_device_perf/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3824331530
Short name T1148
Test name
Test status
Simulation time 1129513919 ps
CPU time 3.66 seconds
Started Jan 03 02:00:29 PM PST 24
Finished Jan 03 02:00:45 PM PST 24
Peak memory 220308 kb
Host smart-20446c41-a478-46dc-a737-66f63d2d7a04
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3824331530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3824331530
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_rx_async_fifo_reset.2662545139
Short name T595
Test name
Test status
Simulation time 99162527 ps
CPU time 0.97 seconds
Started Jan 03 02:01:46 PM PST 24
Finished Jan 03 02:02:05 PM PST 24
Peak memory 208532 kb
Host smart-3e4c63d6-f633-46b6-8167-5db7225b4212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662545139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_rx_async_fifo_reset.2662545139
Directory /workspace/40.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/40.spi_device_rx_timeout.905289232
Short name T1327
Test name
Test status
Simulation time 1067119631 ps
CPU time 5.37 seconds
Started Jan 03 02:01:48 PM PST 24
Finished Jan 03 02:02:11 PM PST 24
Peak memory 216952 kb
Host smart-1c97af50-f7e6-478b-9bb0-821e432b0b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905289232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_rx_timeout.905289232
Directory /workspace/40.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/40.spi_device_smoke.1050079141
Short name T745
Test name
Test status
Simulation time 130320616 ps
CPU time 1.25 seconds
Started Jan 03 02:01:06 PM PST 24
Finished Jan 03 02:01:19 PM PST 24
Peak memory 216932 kb
Host smart-a1b598b3-eede-4854-987d-c298395bc320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050079141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_smoke.1050079141
Directory /workspace/40.spi_device_smoke/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2672472998
Short name T992
Test name
Test status
Simulation time 554733736596 ps
CPU time 1796.9 seconds
Started Jan 03 02:00:50 PM PST 24
Finished Jan 03 02:30:58 PM PST 24
Peak memory 299128 kb
Host smart-3338f2bc-7f2b-4bf9-97ff-3a4360d412f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672472998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2672472998
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1042632718
Short name T801
Test name
Test status
Simulation time 20411394123 ps
CPU time 37.37 seconds
Started Jan 03 02:01:35 PM PST 24
Finished Jan 03 02:02:30 PM PST 24
Peak memory 216916 kb
Host smart-de8ca966-cdc7-4a13-9433-69c097e6e7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042632718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1042632718
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3098705595
Short name T1123
Test name
Test status
Simulation time 14967307682 ps
CPU time 24.79 seconds
Started Jan 03 02:01:44 PM PST 24
Finished Jan 03 02:02:28 PM PST 24
Peak memory 216728 kb
Host smart-ca4939d4-6c2f-48de-93b8-df5bbc10a10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098705595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3098705595
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.286604462
Short name T761
Test name
Test status
Simulation time 191806694 ps
CPU time 1.54 seconds
Started Jan 03 02:00:27 PM PST 24
Finished Jan 03 02:00:42 PM PST 24
Peak memory 216832 kb
Host smart-f8485bbb-02d7-4998-ab62-d3602ad2e34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286604462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.286604462
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1096651797
Short name T650
Test name
Test status
Simulation time 63001389 ps
CPU time 0.78 seconds
Started Jan 03 02:00:52 PM PST 24
Finished Jan 03 02:01:06 PM PST 24
Peak memory 206924 kb
Host smart-e6643557-2c70-4e34-b78b-ab2c83dd6004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096651797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1096651797
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_tx_async_fifo_reset.3216724017
Short name T1116
Test name
Test status
Simulation time 29445059 ps
CPU time 0.77 seconds
Started Jan 03 02:01:45 PM PST 24
Finished Jan 03 02:02:04 PM PST 24
Peak memory 208552 kb
Host smart-263a0d16-43e8-4972-9d1b-8355d51d4832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216724017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tx_async_fifo_reset.3216724017
Directory /workspace/40.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/40.spi_device_txrx.494586498
Short name T1172
Test name
Test status
Simulation time 70288735188 ps
CPU time 171.2 seconds
Started Jan 03 02:01:34 PM PST 24
Finished Jan 03 02:04:43 PM PST 24
Peak memory 277512 kb
Host smart-5d2a53ae-1521-4333-8e01-52cafe204bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494586498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_txrx.494586498
Directory /workspace/40.spi_device_txrx/latest

Test location /workspace/coverage/default/40.spi_device_upload.304594521
Short name T1708
Test name
Test status
Simulation time 10597741776 ps
CPU time 5.19 seconds
Started Jan 03 02:00:22 PM PST 24
Finished Jan 03 02:00:37 PM PST 24
Peak memory 240772 kb
Host smart-7109e336-18ac-42a9-9ea1-7ef120d837f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304594521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.304594521
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_abort.1101582466
Short name T590
Test name
Test status
Simulation time 16240196 ps
CPU time 0.75 seconds
Started Jan 03 02:00:33 PM PST 24
Finished Jan 03 02:00:46 PM PST 24
Peak memory 206612 kb
Host smart-af8c2a98-62d7-4849-bbc9-59dbac5208b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101582466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_abort.1101582466
Directory /workspace/41.spi_device_abort/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3084125162
Short name T872
Test name
Test status
Simulation time 99234472 ps
CPU time 0.74 seconds
Started Jan 03 02:01:24 PM PST 24
Finished Jan 03 02:01:40 PM PST 24
Peak memory 206540 kb
Host smart-add8d70b-c8c7-4792-94cf-d277f898fdf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084125162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3084125162
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_bit_transfer.863733659
Short name T987
Test name
Test status
Simulation time 894340169 ps
CPU time 2.53 seconds
Started Jan 03 02:00:51 PM PST 24
Finished Jan 03 02:01:07 PM PST 24
Peak memory 216760 kb
Host smart-d89ec56c-5ee1-419c-a269-fd96343783bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863733659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_bit_transfer.863733659
Directory /workspace/41.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/41.spi_device_byte_transfer.2789010393
Short name T1294
Test name
Test status
Simulation time 2681388885 ps
CPU time 3.13 seconds
Started Jan 03 02:00:27 PM PST 24
Finished Jan 03 02:00:43 PM PST 24
Peak memory 216896 kb
Host smart-6692cb46-15d4-4fd9-b2c6-2d2f068a09e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789010393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_byte_transfer.2789010393
Directory /workspace/41.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.780025032
Short name T1196
Test name
Test status
Simulation time 144170599 ps
CPU time 2.21 seconds
Started Jan 03 02:01:12 PM PST 24
Finished Jan 03 02:01:24 PM PST 24
Peak memory 218504 kb
Host smart-f901596e-281e-4018-b146-218c60364802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780025032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.780025032
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.469341783
Short name T1358
Test name
Test status
Simulation time 74278174 ps
CPU time 0.83 seconds
Started Jan 03 02:00:26 PM PST 24
Finished Jan 03 02:00:40 PM PST 24
Peak memory 207628 kb
Host smart-4665fb14-3d0c-48b4-aa2c-fbcb8897c9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469341783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.469341783
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_dummy_item_extra_dly.914928802
Short name T1449
Test name
Test status
Simulation time 178114309155 ps
CPU time 442.23 seconds
Started Jan 03 02:00:26 PM PST 24
Finished Jan 03 02:08:02 PM PST 24
Peak memory 241460 kb
Host smart-3b38bf72-06b6-4da8-a57f-4a16a672ba63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914928802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_dummy_item_extra_dly.914928802
Directory /workspace/41.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/41.spi_device_extreme_fifo_size.3528096718
Short name T645
Test name
Test status
Simulation time 40899619540 ps
CPU time 182.07 seconds
Started Jan 03 02:00:42 PM PST 24
Finished Jan 03 02:03:56 PM PST 24
Peak memory 224980 kb
Host smart-2c9e7039-d0db-4467-b6e3-8cefae64a9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528096718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_extreme_fifo_size.3528096718
Directory /workspace/41.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/41.spi_device_fifo_full.2424052167
Short name T1484
Test name
Test status
Simulation time 367342123311 ps
CPU time 727.6 seconds
Started Jan 03 02:00:48 PM PST 24
Finished Jan 03 02:13:06 PM PST 24
Peak memory 258656 kb
Host smart-a16c6518-8c2f-4eb4-93df-e8412c041158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424052167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_fifo_full.2424052167
Directory /workspace/41.spi_device_fifo_full/latest

Test location /workspace/coverage/default/41.spi_device_fifo_underflow_overflow.4009811530
Short name T624
Test name
Test status
Simulation time 273318667294 ps
CPU time 450.65 seconds
Started Jan 03 02:00:34 PM PST 24
Finished Jan 03 02:08:18 PM PST 24
Peak memory 426220 kb
Host smart-66ce2d0d-cec8-4325-b3dd-268e990d1af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009811530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_fifo_underflow_overf
low.4009811530
Directory /workspace/41.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3682402499
Short name T255
Test name
Test status
Simulation time 1396804084 ps
CPU time 9.23 seconds
Started Jan 03 02:01:06 PM PST 24
Finished Jan 03 02:01:27 PM PST 24
Peak memory 225012 kb
Host smart-4097ddfe-ca24-424e-be6d-4f5496789029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682402499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3682402499
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1473520448
Short name T1469
Test name
Test status
Simulation time 14102064494 ps
CPU time 55.64 seconds
Started Jan 03 02:01:32 PM PST 24
Finished Jan 03 02:02:45 PM PST 24
Peak memory 249512 kb
Host smart-8e1dc6ed-78b5-4d28-a290-03035415b00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473520448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1473520448
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.4163994758
Short name T957
Test name
Test status
Simulation time 2922243968 ps
CPU time 14.04 seconds
Started Jan 03 02:01:06 PM PST 24
Finished Jan 03 02:01:31 PM PST 24
Peak memory 251424 kb
Host smart-add138d8-294f-461f-bbf3-2e59ddaaab03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163994758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.4163994758
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.881242339
Short name T1741
Test name
Test status
Simulation time 252291991 ps
CPU time 4.72 seconds
Started Jan 03 02:00:56 PM PST 24
Finished Jan 03 02:01:14 PM PST 24
Peak memory 225056 kb
Host smart-05604925-20fb-4b87-8557-c7360ca8e9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881242339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.881242339
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_intr.3718896786
Short name T120
Test name
Test status
Simulation time 28729725245 ps
CPU time 57.54 seconds
Started Jan 03 02:00:50 PM PST 24
Finished Jan 03 02:02:00 PM PST 24
Peak memory 233296 kb
Host smart-5fda083d-78cd-4921-9f4f-eea5ff2dde64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718896786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intr.3718896786
Directory /workspace/41.spi_device_intr/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.431936014
Short name T272
Test name
Test status
Simulation time 2330580966 ps
CPU time 9.24 seconds
Started Jan 03 02:01:20 PM PST 24
Finished Jan 03 02:01:44 PM PST 24
Peak memory 233324 kb
Host smart-0be87184-bc22-4405-8347-98018a0709fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431936014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.431936014
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3771477278
Short name T25
Test name
Test status
Simulation time 1174502825 ps
CPU time 5.83 seconds
Started Jan 03 02:01:05 PM PST 24
Finished Jan 03 02:01:23 PM PST 24
Peak memory 227404 kb
Host smart-91126f0f-48ea-43f9-9a3d-4ce960d94a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771477278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3771477278
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.58616427
Short name T1606
Test name
Test status
Simulation time 97148888076 ps
CPU time 60.24 seconds
Started Jan 03 02:01:23 PM PST 24
Finished Jan 03 02:02:38 PM PST 24
Peak memory 232164 kb
Host smart-0a9e6c64-7997-406c-8af3-16527e5cf628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58616427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.58616427
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_perf.1327267961
Short name T1368
Test name
Test status
Simulation time 360473598021 ps
CPU time 1718.26 seconds
Started Jan 03 02:00:51 PM PST 24
Finished Jan 03 02:29:41 PM PST 24
Peak memory 270984 kb
Host smart-d833aa71-9566-4cd9-8561-98f9fb332948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327267961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_perf.1327267961
Directory /workspace/41.spi_device_perf/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1578539516
Short name T613
Test name
Test status
Simulation time 88029741 ps
CPU time 3.5 seconds
Started Jan 03 02:01:05 PM PST 24
Finished Jan 03 02:01:20 PM PST 24
Peak memory 220740 kb
Host smart-b735dfda-c263-443c-9d14-618f6c4563c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1578539516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1578539516
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_rx_async_fifo_reset.2835475737
Short name T990
Test name
Test status
Simulation time 81519772 ps
CPU time 0.81 seconds
Started Jan 03 02:01:20 PM PST 24
Finished Jan 03 02:01:37 PM PST 24
Peak memory 208488 kb
Host smart-da00196d-3301-41f4-80a5-88fa17054ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835475737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_rx_async_fifo_reset.2835475737
Directory /workspace/41.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/41.spi_device_rx_timeout.1658453896
Short name T127
Test name
Test status
Simulation time 1837837458 ps
CPU time 5.04 seconds
Started Jan 03 02:00:50 PM PST 24
Finished Jan 03 02:01:06 PM PST 24
Peak memory 216840 kb
Host smart-1e93f5da-be1c-4998-87d7-bf7a8cbdf5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658453896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_rx_timeout.1658453896
Directory /workspace/41.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/41.spi_device_smoke.554543822
Short name T223
Test name
Test status
Simulation time 200857054 ps
CPU time 1.15 seconds
Started Jan 03 02:00:42 PM PST 24
Finished Jan 03 02:00:56 PM PST 24
Peak memory 208404 kb
Host smart-2f644e31-6cce-450b-8c0e-a61c2715718a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554543822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_smoke.554543822
Directory /workspace/41.spi_device_smoke/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2886562886
Short name T343
Test name
Test status
Simulation time 5008456261 ps
CPU time 55.37 seconds
Started Jan 03 02:01:27 PM PST 24
Finished Jan 03 02:02:37 PM PST 24
Peak memory 273184 kb
Host smart-4401746c-2632-4661-9e73-29e61416fe41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886562886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2886562886
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.975697757
Short name T1022
Test name
Test status
Simulation time 28332595266 ps
CPU time 71.2 seconds
Started Jan 03 02:00:36 PM PST 24
Finished Jan 03 02:02:00 PM PST 24
Peak memory 216888 kb
Host smart-997be325-27cb-4898-92d8-318cac2d0782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975697757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.975697757
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3585580372
Short name T1182
Test name
Test status
Simulation time 61089695183 ps
CPU time 24.26 seconds
Started Jan 03 02:00:30 PM PST 24
Finished Jan 03 02:01:06 PM PST 24
Peak memory 216880 kb
Host smart-4853c9e5-46c5-40c9-bf3c-26c9cb5a137f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585580372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3585580372
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2998481246
Short name T1177
Test name
Test status
Simulation time 32377941 ps
CPU time 0.82 seconds
Started Jan 03 02:00:37 PM PST 24
Finished Jan 03 02:00:50 PM PST 24
Peak memory 206892 kb
Host smart-571f70e9-4c47-4807-9628-c15d3aa725e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998481246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2998481246
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2999089624
Short name T1750
Test name
Test status
Simulation time 38294855 ps
CPU time 0.79 seconds
Started Jan 03 02:00:51 PM PST 24
Finished Jan 03 02:01:05 PM PST 24
Peak memory 206928 kb
Host smart-2a28eee5-66f6-4ca9-b85f-acf5addd269e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999089624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2999089624
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_tx_async_fifo_reset.2158016210
Short name T689
Test name
Test status
Simulation time 28227158 ps
CPU time 0.77 seconds
Started Jan 03 02:00:51 PM PST 24
Finished Jan 03 02:01:04 PM PST 24
Peak memory 208456 kb
Host smart-5fd52d32-3027-4548-8577-3ae7f6cc38b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158016210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tx_async_fifo_reset.2158016210
Directory /workspace/41.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/41.spi_device_txrx.656302702
Short name T1102
Test name
Test status
Simulation time 101840010450 ps
CPU time 226.38 seconds
Started Jan 03 02:00:23 PM PST 24
Finished Jan 03 02:04:21 PM PST 24
Peak memory 256832 kb
Host smart-5577c043-78b5-444e-91f2-8836925ebcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656302702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_txrx.656302702
Directory /workspace/41.spi_device_txrx/latest

Test location /workspace/coverage/default/41.spi_device_upload.705102025
Short name T1333
Test name
Test status
Simulation time 1861672227 ps
CPU time 12.87 seconds
Started Jan 03 02:01:23 PM PST 24
Finished Jan 03 02:01:52 PM PST 24
Peak memory 240472 kb
Host smart-8acf8787-700d-49ff-9bc8-ac35a07fafe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705102025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.705102025
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_abort.3439413668
Short name T1331
Test name
Test status
Simulation time 47724227 ps
CPU time 0.74 seconds
Started Jan 03 02:01:31 PM PST 24
Finished Jan 03 02:01:47 PM PST 24
Peak memory 206592 kb
Host smart-4ef115ea-69f6-4947-94af-3912162f516d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439413668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_abort.3439413668
Directory /workspace/42.spi_device_abort/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2696902273
Short name T1604
Test name
Test status
Simulation time 12223723 ps
CPU time 0.74 seconds
Started Jan 03 02:01:35 PM PST 24
Finished Jan 03 02:01:53 PM PST 24
Peak memory 206484 kb
Host smart-e3df8fc8-3138-4a5a-a4a9-f2a2e9091224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696902273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2696902273
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_byte_transfer.4241426070
Short name T58
Test name
Test status
Simulation time 643476458 ps
CPU time 3.12 seconds
Started Jan 03 02:01:10 PM PST 24
Finished Jan 03 02:01:23 PM PST 24
Peak memory 216904 kb
Host smart-12ed5331-91b5-439c-80b9-3b98cf650f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241426070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_byte_transfer.4241426070
Directory /workspace/42.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3092415898
Short name T331
Test name
Test status
Simulation time 306670953 ps
CPU time 2.64 seconds
Started Jan 03 02:01:32 PM PST 24
Finished Jan 03 02:01:50 PM PST 24
Peak memory 218888 kb
Host smart-c960c804-f992-4f5e-83a7-53da54c01556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092415898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3092415898
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2704924790
Short name T728
Test name
Test status
Simulation time 22259220 ps
CPU time 0.81 seconds
Started Jan 03 02:01:22 PM PST 24
Finished Jan 03 02:01:38 PM PST 24
Peak memory 207708 kb
Host smart-a8d4f593-657b-4280-99b8-4fcf7f771fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704924790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2704924790
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_dummy_item_extra_dly.287799901
Short name T673
Test name
Test status
Simulation time 134125195580 ps
CPU time 258.02 seconds
Started Jan 03 02:01:33 PM PST 24
Finished Jan 03 02:06:08 PM PST 24
Peak memory 249732 kb
Host smart-d06d66fa-a542-42e2-bd2a-2a6bbee8cb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287799901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_dummy_item_extra_dly.287799901
Directory /workspace/42.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/42.spi_device_extreme_fifo_size.1140860323
Short name T572
Test name
Test status
Simulation time 25443377611 ps
CPU time 48.9 seconds
Started Jan 03 02:01:27 PM PST 24
Finished Jan 03 02:02:31 PM PST 24
Peak memory 233508 kb
Host smart-a35c5e42-67e0-4215-86dc-f1e20ebc9f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140860323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_extreme_fifo_size.1140860323
Directory /workspace/42.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/42.spi_device_fifo_full.1197963760
Short name T721
Test name
Test status
Simulation time 37863435452 ps
CPU time 497.35 seconds
Started Jan 03 02:01:09 PM PST 24
Finished Jan 03 02:09:37 PM PST 24
Peak memory 282648 kb
Host smart-e9e1dbb7-5c58-4612-b713-06db3f5c0bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197963760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_fifo_full.1197963760
Directory /workspace/42.spi_device_fifo_full/latest

Test location /workspace/coverage/default/42.spi_device_fifo_underflow_overflow.1344986530
Short name T203
Test name
Test status
Simulation time 294649420957 ps
CPU time 418.17 seconds
Started Jan 03 02:01:04 PM PST 24
Finished Jan 03 02:08:15 PM PST 24
Peak memory 477980 kb
Host smart-6377714d-3ee5-4de1-8e3c-778c16efd8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344986530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_fifo_underflow_overf
low.1344986530
Directory /workspace/42.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2579034027
Short name T1298
Test name
Test status
Simulation time 8364826628 ps
CPU time 80.88 seconds
Started Jan 03 02:01:31 PM PST 24
Finished Jan 03 02:03:06 PM PST 24
Peak memory 253924 kb
Host smart-ef1b4152-2a60-40ef-8b90-6a01712d1957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579034027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2579034027
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2155820204
Short name T788
Test name
Test status
Simulation time 6639976453 ps
CPU time 73.3 seconds
Started Jan 03 02:01:34 PM PST 24
Finished Jan 03 02:03:05 PM PST 24
Peak memory 249848 kb
Host smart-637da120-1a26-477f-93d1-e9dc8c95cfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155820204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2155820204
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3948430943
Short name T909
Test name
Test status
Simulation time 6837580800 ps
CPU time 36.75 seconds
Started Jan 03 02:01:39 PM PST 24
Finished Jan 03 02:02:34 PM PST 24
Peak memory 230028 kb
Host smart-731a32a4-4de5-4c9d-bfba-bdf3678e9600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948430943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3948430943
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2252546250
Short name T1679
Test name
Test status
Simulation time 187111433 ps
CPU time 3.75 seconds
Started Jan 03 02:01:32 PM PST 24
Finished Jan 03 02:01:51 PM PST 24
Peak memory 240164 kb
Host smart-b8297c76-7202-4fe8-8aba-02b5effcae82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252546250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2252546250
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_intr.3614255362
Short name T1350
Test name
Test status
Simulation time 27799589509 ps
CPU time 56.97 seconds
Started Jan 03 02:01:09 PM PST 24
Finished Jan 03 02:02:16 PM PST 24
Peak memory 234376 kb
Host smart-f4a01d16-78e6-448e-b393-e9a905b85835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614255362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intr.3614255362
Directory /workspace/42.spi_device_intr/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3642479406
Short name T309
Test name
Test status
Simulation time 7284236297 ps
CPU time 33.16 seconds
Started Jan 03 02:01:34 PM PST 24
Finished Jan 03 02:02:25 PM PST 24
Peak memory 256960 kb
Host smart-d1cc9c6b-2f14-485b-906a-157fa64de4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642479406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3642479406
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2612143893
Short name T1395
Test name
Test status
Simulation time 75997549 ps
CPU time 2.94 seconds
Started Jan 03 02:01:32 PM PST 24
Finished Jan 03 02:01:50 PM PST 24
Peak memory 234292 kb
Host smart-14e59fc6-8553-453f-91a0-f5b79623739c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612143893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2612143893
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2664292877
Short name T1313
Test name
Test status
Simulation time 2615425806 ps
CPU time 7.17 seconds
Started Jan 03 02:01:33 PM PST 24
Finished Jan 03 02:01:58 PM PST 24
Peak memory 241516 kb
Host smart-af3373df-e4ed-4d73-bb38-09e3a958e519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664292877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2664292877
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_perf.1974826517
Short name T1497
Test name
Test status
Simulation time 25360757894 ps
CPU time 557.08 seconds
Started Jan 03 02:01:30 PM PST 24
Finished Jan 03 02:11:02 PM PST 24
Peak memory 251872 kb
Host smart-b22ac168-286c-40a9-8641-8f1fa1f3f2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974826517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_perf.1974826517
Directory /workspace/42.spi_device_perf/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1481903188
Short name T562
Test name
Test status
Simulation time 2530593237 ps
CPU time 5.18 seconds
Started Jan 03 02:01:33 PM PST 24
Finished Jan 03 02:01:55 PM PST 24
Peak memory 234732 kb
Host smart-ce83c230-72c3-44ed-b2c8-68a65418d0d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1481903188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1481903188
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_rx_async_fifo_reset.3176968875
Short name T1533
Test name
Test status
Simulation time 55874655 ps
CPU time 0.87 seconds
Started Jan 03 02:01:39 PM PST 24
Finished Jan 03 02:01:57 PM PST 24
Peak memory 208376 kb
Host smart-fda8c5f4-94ed-4121-a92a-0d5651b44afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176968875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_rx_async_fifo_reset.3176968875
Directory /workspace/42.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/42.spi_device_rx_timeout.2852201114
Short name T1514
Test name
Test status
Simulation time 662764381 ps
CPU time 6.58 seconds
Started Jan 03 02:01:25 PM PST 24
Finished Jan 03 02:01:47 PM PST 24
Peak memory 216880 kb
Host smart-d720516f-5e5b-4772-a918-a9eb2ec298a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852201114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_rx_timeout.2852201114
Directory /workspace/42.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/42.spi_device_smoke.2055105388
Short name T1695
Test name
Test status
Simulation time 16987118 ps
CPU time 1.02 seconds
Started Jan 03 02:01:22 PM PST 24
Finished Jan 03 02:01:39 PM PST 24
Peak memory 208336 kb
Host smart-0e5d94e8-895b-4ad1-b359-38bce6086f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055105388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_smoke.2055105388
Directory /workspace/42.spi_device_smoke/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3759610119
Short name T883
Test name
Test status
Simulation time 393609820770 ps
CPU time 468.15 seconds
Started Jan 03 02:01:30 PM PST 24
Finished Jan 03 02:09:33 PM PST 24
Peak memory 312100 kb
Host smart-f51a43d5-495c-4a53-867e-0976fcd16d91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759610119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3759610119
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2878746460
Short name T113
Test name
Test status
Simulation time 86052978520 ps
CPU time 109.76 seconds
Started Jan 03 02:01:40 PM PST 24
Finished Jan 03 02:03:48 PM PST 24
Peak memory 216804 kb
Host smart-b5ac4104-dc33-463b-b817-620ec4a46d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878746460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2878746460
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.147159642
Short name T947
Test name
Test status
Simulation time 44265633804 ps
CPU time 19.81 seconds
Started Jan 03 02:01:32 PM PST 24
Finished Jan 03 02:02:07 PM PST 24
Peak memory 216948 kb
Host smart-03fda8c1-2064-4447-84cd-40b4f2fa260a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147159642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.147159642
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3039683206
Short name T648
Test name
Test status
Simulation time 87150541 ps
CPU time 1.36 seconds
Started Jan 03 02:01:29 PM PST 24
Finished Jan 03 02:01:46 PM PST 24
Peak memory 216856 kb
Host smart-15aad94b-2252-4894-870d-42f2e6874f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039683206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3039683206
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2312462795
Short name T126
Test name
Test status
Simulation time 689391079 ps
CPU time 1.24 seconds
Started Jan 03 02:01:34 PM PST 24
Finished Jan 03 02:01:52 PM PST 24
Peak memory 207964 kb
Host smart-d887d2ea-bd2c-4494-b786-1c3b029e11fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312462795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2312462795
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_tx_async_fifo_reset.985817107
Short name T1120
Test name
Test status
Simulation time 32806994 ps
CPU time 0.76 seconds
Started Jan 03 02:01:35 PM PST 24
Finished Jan 03 02:01:53 PM PST 24
Peak memory 208480 kb
Host smart-9fa9557e-46a3-41b6-9ae6-d382319dda85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985817107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tx_async_fifo_reset.985817107
Directory /workspace/42.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/42.spi_device_txrx.1447841610
Short name T644
Test name
Test status
Simulation time 20448293942 ps
CPU time 126.88 seconds
Started Jan 03 02:01:23 PM PST 24
Finished Jan 03 02:03:46 PM PST 24
Peak memory 276500 kb
Host smart-48daa916-12b8-492a-ba45-6dc0b5d0ab10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447841610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_txrx.1447841610
Directory /workspace/42.spi_device_txrx/latest

Test location /workspace/coverage/default/42.spi_device_upload.1021650929
Short name T943
Test name
Test status
Simulation time 1225332490 ps
CPU time 17.53 seconds
Started Jan 03 02:01:33 PM PST 24
Finished Jan 03 02:02:08 PM PST 24
Peak memory 248880 kb
Host smart-0372d27a-b526-4c93-adfc-bbeb7d951f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021650929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1021650929
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_abort.2925234662
Short name T1539
Test name
Test status
Simulation time 13736212 ps
CPU time 0.74 seconds
Started Jan 03 02:01:31 PM PST 24
Finished Jan 03 02:01:47 PM PST 24
Peak memory 206608 kb
Host smart-2dd839e8-b310-477f-9641-44912bf72a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925234662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_abort.2925234662
Directory /workspace/43.spi_device_abort/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2095727986
Short name T1311
Test name
Test status
Simulation time 14286371 ps
CPU time 0.74 seconds
Started Jan 03 02:01:31 PM PST 24
Finished Jan 03 02:01:47 PM PST 24
Peak memory 206472 kb
Host smart-e06bd774-1350-4a7c-b834-7e520ad2876c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095727986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2095727986
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_bit_transfer.3360104057
Short name T1252
Test name
Test status
Simulation time 238169488 ps
CPU time 2.62 seconds
Started Jan 03 02:01:38 PM PST 24
Finished Jan 03 02:01:58 PM PST 24
Peak memory 216820 kb
Host smart-f25b6b74-bb37-4ef1-9f81-8bc2b6819e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360104057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_bit_transfer.3360104057
Directory /workspace/43.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/43.spi_device_byte_transfer.321702668
Short name T1329
Test name
Test status
Simulation time 230573090 ps
CPU time 3.1 seconds
Started Jan 03 02:01:39 PM PST 24
Finished Jan 03 02:02:00 PM PST 24
Peak memory 216712 kb
Host smart-f543e7c3-4c47-4558-b57b-9b994688a201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321702668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_byte_transfer.321702668
Directory /workspace/43.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2224926197
Short name T1183
Test name
Test status
Simulation time 307741011 ps
CPU time 2.64 seconds
Started Jan 03 02:01:34 PM PST 24
Finished Jan 03 02:01:55 PM PST 24
Peak memory 218824 kb
Host smart-a5ea3c33-3cfb-4d52-bcdf-32ca9b43e1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224926197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2224926197
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.317636588
Short name T1770
Test name
Test status
Simulation time 19761228 ps
CPU time 0.82 seconds
Started Jan 03 02:01:35 PM PST 24
Finished Jan 03 02:01:53 PM PST 24
Peak memory 207540 kb
Host smart-7c1f2198-f9f8-43ca-af82-61dbd28df729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317636588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.317636588
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_dummy_item_extra_dly.264995356
Short name T219
Test name
Test status
Simulation time 56935255155 ps
CPU time 121.72 seconds
Started Jan 03 02:01:29 PM PST 24
Finished Jan 03 02:03:45 PM PST 24
Peak memory 241064 kb
Host smart-468cdfcc-ad6c-403f-8a1a-44abcf9ea17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264995356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_dummy_item_extra_dly.264995356
Directory /workspace/43.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/43.spi_device_extreme_fifo_size.1980588233
Short name T302
Test name
Test status
Simulation time 89424998367 ps
CPU time 942.82 seconds
Started Jan 03 02:01:31 PM PST 24
Finished Jan 03 02:17:29 PM PST 24
Peak memory 220080 kb
Host smart-5f629591-8491-4f23-9c4a-10b4572b4eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980588233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_extreme_fifo_size.1980588233
Directory /workspace/43.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/43.spi_device_fifo_full.3152066159
Short name T1098
Test name
Test status
Simulation time 55678537664 ps
CPU time 498.71 seconds
Started Jan 03 02:01:31 PM PST 24
Finished Jan 03 02:10:05 PM PST 24
Peak memory 288276 kb
Host smart-cacad29b-fe42-4e43-91b6-b0920426968d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152066159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_fifo_full.3152066159
Directory /workspace/43.spi_device_fifo_full/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1802288569
Short name T245
Test name
Test status
Simulation time 6701571914 ps
CPU time 120.47 seconds
Started Jan 03 02:01:34 PM PST 24
Finished Jan 03 02:03:51 PM PST 24
Peak memory 268120 kb
Host smart-9c7018f3-40cd-42bd-a57a-df3ad560f26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802288569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1802288569
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1177010113
Short name T380
Test name
Test status
Simulation time 54685930848 ps
CPU time 375.21 seconds
Started Jan 03 02:01:32 PM PST 24
Finished Jan 03 02:08:04 PM PST 24
Peak memory 263520 kb
Host smart-020014ca-6e2a-498d-a0d5-ba2b45eb0fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177010113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1177010113
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1732212835
Short name T1245
Test name
Test status
Simulation time 412136073 ps
CPU time 8.45 seconds
Started Jan 03 02:01:33 PM PST 24
Finished Jan 03 02:02:00 PM PST 24
Peak memory 236244 kb
Host smart-7d098eca-fd67-44bb-9fd1-73f5ae5b7af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732212835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1732212835
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1312765852
Short name T348
Test name
Test status
Simulation time 644420013 ps
CPU time 4.91 seconds
Started Jan 03 02:01:34 PM PST 24
Finished Jan 03 02:01:56 PM PST 24
Peak memory 241460 kb
Host smart-a68590b9-6450-4b23-b873-08b9b18a849e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312765852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1312765852
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_intr.1428079617
Short name T743
Test name
Test status
Simulation time 27996516421 ps
CPU time 23.22 seconds
Started Jan 03 02:01:33 PM PST 24
Finished Jan 03 02:02:14 PM PST 24
Peak memory 224700 kb
Host smart-b301df13-6964-4bb4-b920-dbf6af7844f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428079617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intr.1428079617
Directory /workspace/43.spi_device_intr/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2194900789
Short name T345
Test name
Test status
Simulation time 16723484929 ps
CPU time 13.22 seconds
Started Jan 03 02:01:31 PM PST 24
Finished Jan 03 02:01:59 PM PST 24
Peak memory 221748 kb
Host smart-c5de3f35-abd5-42df-8c0f-d1580a561d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194900789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2194900789
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.4035880229
Short name T370
Test name
Test status
Simulation time 59688837038 ps
CPU time 55.38 seconds
Started Jan 03 02:01:32 PM PST 24
Finished Jan 03 02:02:43 PM PST 24
Peak memory 256340 kb
Host smart-6894659a-dd61-41cb-9bf1-694486b57d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035880229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.4035880229
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3823591470
Short name T948
Test name
Test status
Simulation time 7096690889 ps
CPU time 21.43 seconds
Started Jan 03 02:01:38 PM PST 24
Finished Jan 03 02:02:17 PM PST 24
Peak memory 218288 kb
Host smart-de815e63-bae7-4a71-a4c4-097c55b5d905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823591470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3823591470
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_perf.1411979743
Short name T304
Test name
Test status
Simulation time 44706454790 ps
CPU time 926.55 seconds
Started Jan 03 02:01:32 PM PST 24
Finished Jan 03 02:17:14 PM PST 24
Peak memory 298092 kb
Host smart-595cb583-0ed5-4add-84d9-0f1d9b3fe1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411979743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_perf.1411979743
Directory /workspace/43.spi_device_perf/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3763257971
Short name T1024
Test name
Test status
Simulation time 1275284757 ps
CPU time 5.49 seconds
Started Jan 03 02:01:32 PM PST 24
Finished Jan 03 02:01:54 PM PST 24
Peak memory 236840 kb
Host smart-7821e5fd-579c-420d-9093-35feb11e6d22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3763257971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3763257971
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_rx_async_fifo_reset.1843327959
Short name T1203
Test name
Test status
Simulation time 209498802 ps
CPU time 0.91 seconds
Started Jan 03 02:01:38 PM PST 24
Finished Jan 03 02:01:57 PM PST 24
Peak memory 208480 kb
Host smart-f857402d-f545-49db-adb2-c4b3257b2253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843327959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_rx_async_fifo_reset.1843327959
Directory /workspace/43.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/43.spi_device_rx_timeout.2468698420
Short name T128
Test name
Test status
Simulation time 667451982 ps
CPU time 5.73 seconds
Started Jan 03 02:01:37 PM PST 24
Finished Jan 03 02:02:00 PM PST 24
Peak memory 216836 kb
Host smart-4800fd15-bc52-46b7-be62-c48db6518d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468698420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_rx_timeout.2468698420
Directory /workspace/43.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/43.spi_device_smoke.906724913
Short name T1157
Test name
Test status
Simulation time 55696155 ps
CPU time 1.09 seconds
Started Jan 03 02:01:31 PM PST 24
Finished Jan 03 02:01:46 PM PST 24
Peak memory 216524 kb
Host smart-3472b887-15d6-4800-be35-734d4fe18809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906724913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_smoke.906724913
Directory /workspace/43.spi_device_smoke/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2980781891
Short name T923
Test name
Test status
Simulation time 310446420965 ps
CPU time 1425.74 seconds
Started Jan 03 02:01:34 PM PST 24
Finished Jan 03 02:25:38 PM PST 24
Peak memory 454392 kb
Host smart-9e4a7d33-ada0-4bc1-a1fd-c1ffc15df865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980781891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2980781891
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1087450967
Short name T1780
Test name
Test status
Simulation time 10848355594 ps
CPU time 21.75 seconds
Started Jan 03 02:01:32 PM PST 24
Finished Jan 03 02:02:09 PM PST 24
Peak memory 221540 kb
Host smart-2af32d75-f70d-4912-9639-f533f439067e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087450967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1087450967
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.26687375
Short name T1747
Test name
Test status
Simulation time 1084291240 ps
CPU time 4.02 seconds
Started Jan 03 02:01:32 PM PST 24
Finished Jan 03 02:01:51 PM PST 24
Peak memory 216700 kb
Host smart-3c2bceaf-3195-4df7-a232-d97288c8e9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26687375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.26687375
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1205327780
Short name T1420
Test name
Test status
Simulation time 93724353 ps
CPU time 1.4 seconds
Started Jan 03 02:01:30 PM PST 24
Finished Jan 03 02:01:46 PM PST 24
Peak memory 216804 kb
Host smart-eaa5f09f-b283-416d-b5d5-d51e32c89b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205327780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1205327780
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1905130290
Short name T989
Test name
Test status
Simulation time 104260510 ps
CPU time 0.81 seconds
Started Jan 03 02:01:30 PM PST 24
Finished Jan 03 02:01:45 PM PST 24
Peak memory 206936 kb
Host smart-d65c74b8-97b0-4870-a116-57cb0bd1434d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905130290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1905130290
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_tx_async_fifo_reset.2695072340
Short name T1383
Test name
Test status
Simulation time 24382203 ps
CPU time 0.75 seconds
Started Jan 03 02:01:32 PM PST 24
Finished Jan 03 02:01:50 PM PST 24
Peak memory 208512 kb
Host smart-dc5d68a9-8ef1-4d9e-9d08-2eb7a7f03c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695072340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tx_async_fifo_reset.2695072340
Directory /workspace/43.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/43.spi_device_txrx.128175630
Short name T1377
Test name
Test status
Simulation time 63949675166 ps
CPU time 298.96 seconds
Started Jan 03 02:01:39 PM PST 24
Finished Jan 03 02:06:56 PM PST 24
Peak memory 287620 kb
Host smart-7a7116e9-053a-4bfe-87c1-ad8ec5ac7033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128175630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_txrx.128175630
Directory /workspace/43.spi_device_txrx/latest

Test location /workspace/coverage/default/43.spi_device_upload.365397750
Short name T209
Test name
Test status
Simulation time 1698575535 ps
CPU time 5.32 seconds
Started Jan 03 02:01:33 PM PST 24
Finished Jan 03 02:01:56 PM PST 24
Peak memory 240064 kb
Host smart-f0b00c6c-ad5e-461a-ad6a-9d12f72fded8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365397750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.365397750
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_abort.3366904475
Short name T1234
Test name
Test status
Simulation time 17344418 ps
CPU time 0.73 seconds
Started Jan 03 02:01:50 PM PST 24
Finished Jan 03 02:02:08 PM PST 24
Peak memory 206648 kb
Host smart-b830f75f-2d4a-4cfd-a3f5-8c53ba8cd1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366904475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_abort.3366904475
Directory /workspace/44.spi_device_abort/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1045779845
Short name T1684
Test name
Test status
Simulation time 48620894 ps
CPU time 0.76 seconds
Started Jan 03 02:01:53 PM PST 24
Finished Jan 03 02:02:10 PM PST 24
Peak memory 206460 kb
Host smart-35c96bf2-f2f4-4e41-83b9-e930c98167f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045779845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1045779845
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_bit_transfer.717965765
Short name T632
Test name
Test status
Simulation time 84600503 ps
CPU time 2.48 seconds
Started Jan 03 02:01:45 PM PST 24
Finished Jan 03 02:02:07 PM PST 24
Peak memory 216784 kb
Host smart-7760d9fd-d1e8-4e75-8855-3374f78bac93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717965765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_bit_transfer.717965765
Directory /workspace/44.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/44.spi_device_byte_transfer.4089353965
Short name T57
Test name
Test status
Simulation time 393809214 ps
CPU time 2.9 seconds
Started Jan 03 02:01:35 PM PST 24
Finished Jan 03 02:01:55 PM PST 24
Peak memory 216832 kb
Host smart-e3295cd4-8ad8-4bcf-8184-3a18d9c55ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089353965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_byte_transfer.4089353965
Directory /workspace/44.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3627127281
Short name T111
Test name
Test status
Simulation time 1184052954 ps
CPU time 5.47 seconds
Started Jan 03 02:01:48 PM PST 24
Finished Jan 03 02:02:11 PM PST 24
Peak memory 221652 kb
Host smart-dc88bb19-9f9d-4e72-9a40-5052d9a847ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627127281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3627127281
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2029087581
Short name T508
Test name
Test status
Simulation time 55667977 ps
CPU time 0.76 seconds
Started Jan 03 02:01:47 PM PST 24
Finished Jan 03 02:02:06 PM PST 24
Peak memory 207652 kb
Host smart-def961d2-e9c3-4b8d-b74d-fc965642eef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029087581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2029087581
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_dummy_item_extra_dly.1762139431
Short name T1173
Test name
Test status
Simulation time 50144813638 ps
CPU time 1080.81 seconds
Started Jan 03 02:01:46 PM PST 24
Finished Jan 03 02:20:05 PM PST 24
Peak memory 252820 kb
Host smart-fc1e2100-3760-4081-87eb-06d8a9a6367c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762139431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_dummy_item_extra_dly.1762139431
Directory /workspace/44.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/44.spi_device_extreme_fifo_size.3979509369
Short name T619
Test name
Test status
Simulation time 438556972361 ps
CPU time 2927.67 seconds
Started Jan 03 02:01:42 PM PST 24
Finished Jan 03 02:50:50 PM PST 24
Peak memory 225096 kb
Host smart-31c31fb7-b93a-4823-a12b-5feeb8cd3598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979509369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_extreme_fifo_size.3979509369
Directory /workspace/44.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/44.spi_device_fifo_full.52556560
Short name T1459
Test name
Test status
Simulation time 252985176358 ps
CPU time 1243.63 seconds
Started Jan 03 02:01:44 PM PST 24
Finished Jan 03 02:22:46 PM PST 24
Peak memory 274244 kb
Host smart-22e4f9ec-6316-4b71-866f-390eae2c5d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52556560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_fifo_full.52556560
Directory /workspace/44.spi_device_fifo_full/latest

Test location /workspace/coverage/default/44.spi_device_fifo_underflow_overflow.1132142364
Short name T54
Test name
Test status
Simulation time 73616112359 ps
CPU time 230.56 seconds
Started Jan 03 02:01:33 PM PST 24
Finished Jan 03 02:05:40 PM PST 24
Peak memory 417184 kb
Host smart-17ce2c4f-46c4-4b53-abb5-f5a31ed1d0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132142364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_fifo_underflow_overf
low.1132142364
Directory /workspace/44.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1031819934
Short name T265
Test name
Test status
Simulation time 2857283384 ps
CPU time 36.49 seconds
Started Jan 03 02:01:53 PM PST 24
Finished Jan 03 02:02:45 PM PST 24
Peak memory 251796 kb
Host smart-3a501200-4612-459c-944f-c48ab4b12492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031819934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1031819934
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.525651698
Short name T145
Test name
Test status
Simulation time 17307508738 ps
CPU time 43.9 seconds
Started Jan 03 02:01:52 PM PST 24
Finished Jan 03 02:02:52 PM PST 24
Peak memory 237636 kb
Host smart-99b3fb8d-e72f-4302-8b09-11a4cb53e6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525651698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.525651698
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.540733476
Short name T357
Test name
Test status
Simulation time 2073460601 ps
CPU time 4.68 seconds
Started Jan 03 02:01:50 PM PST 24
Finished Jan 03 02:02:12 PM PST 24
Peak memory 238924 kb
Host smart-01ecc5eb-4823-40fe-9571-0774517ec3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540733476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.540733476
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_intr.1914214706
Short name T1611
Test name
Test status
Simulation time 54590841938 ps
CPU time 45.71 seconds
Started Jan 03 02:01:44 PM PST 24
Finished Jan 03 02:02:49 PM PST 24
Peak memory 233432 kb
Host smart-af6e0fb4-02a6-4c4e-b1e4-1c1253296e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914214706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intr.1914214706
Directory /workspace/44.spi_device_intr/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3758426771
Short name T1210
Test name
Test status
Simulation time 553486162 ps
CPU time 8.41 seconds
Started Jan 03 02:01:52 PM PST 24
Finished Jan 03 02:02:17 PM PST 24
Peak memory 241264 kb
Host smart-4d16561e-6271-46cc-a751-3676027869d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758426771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3758426771
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3217543773
Short name T274
Test name
Test status
Simulation time 4856361372 ps
CPU time 18.37 seconds
Started Jan 03 02:01:53 PM PST 24
Finished Jan 03 02:02:28 PM PST 24
Peak memory 220412 kb
Host smart-07d654d9-9c2f-4165-b16a-e1e4e597085a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217543773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3217543773
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3036582333
Short name T327
Test name
Test status
Simulation time 1997810170 ps
CPU time 6.41 seconds
Started Jan 03 02:01:46 PM PST 24
Finished Jan 03 02:02:11 PM PST 24
Peak memory 220188 kb
Host smart-41ab3fcd-dbfb-4668-83b7-beee9fb439d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036582333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3036582333
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_perf.2487345482
Short name T1
Test name
Test status
Simulation time 16492994823 ps
CPU time 196.82 seconds
Started Jan 03 02:01:52 PM PST 24
Finished Jan 03 02:05:25 PM PST 24
Peak memory 282412 kb
Host smart-4018276a-73ed-4c7a-8250-4768e14c1fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487345482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_perf.2487345482
Directory /workspace/44.spi_device_perf/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.289827451
Short name T38
Test name
Test status
Simulation time 1438414334 ps
CPU time 4.85 seconds
Started Jan 03 02:01:46 PM PST 24
Finished Jan 03 02:02:09 PM PST 24
Peak memory 218708 kb
Host smart-b2045568-46ff-4e9c-bd9b-e97eed4538b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=289827451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.289827451
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_rx_async_fifo_reset.566102482
Short name T812
Test name
Test status
Simulation time 19949500 ps
CPU time 0.87 seconds
Started Jan 03 02:01:52 PM PST 24
Finished Jan 03 02:02:10 PM PST 24
Peak memory 208364 kb
Host smart-2f34136c-fa8f-4fd5-a527-3489552444ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566102482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_rx_async_fifo_reset.566102482
Directory /workspace/44.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/44.spi_device_rx_timeout.203438878
Short name T1070
Test name
Test status
Simulation time 1214781521 ps
CPU time 5.56 seconds
Started Jan 03 02:01:35 PM PST 24
Finished Jan 03 02:01:58 PM PST 24
Peak memory 216796 kb
Host smart-ac7ea17d-65a7-442d-8dfd-9a9f7f8182e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203438878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_rx_timeout.203438878
Directory /workspace/44.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/44.spi_device_smoke.3633308492
Short name T530
Test name
Test status
Simulation time 130843515 ps
CPU time 1.31 seconds
Started Jan 03 02:01:33 PM PST 24
Finished Jan 03 02:01:52 PM PST 24
Peak memory 216868 kb
Host smart-250e50fe-5df1-47cc-9502-f087a68f1071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633308492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_smoke.3633308492
Directory /workspace/44.spi_device_smoke/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.714958137
Short name T80
Test name
Test status
Simulation time 88598041428 ps
CPU time 624.95 seconds
Started Jan 03 02:01:52 PM PST 24
Finished Jan 03 02:12:33 PM PST 24
Peak memory 413884 kb
Host smart-fe629d24-d3fd-4afb-a3d1-5b4453cc1f27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714958137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.714958137
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.4151821520
Short name T1690
Test name
Test status
Simulation time 3003648465 ps
CPU time 38.69 seconds
Started Jan 03 02:01:52 PM PST 24
Finished Jan 03 02:02:47 PM PST 24
Peak memory 216740 kb
Host smart-d85fd917-efb6-4f98-ac9e-d36781c14ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151821520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.4151821520
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2029443177
Short name T895
Test name
Test status
Simulation time 415640393 ps
CPU time 3.99 seconds
Started Jan 03 02:01:47 PM PST 24
Finished Jan 03 02:02:09 PM PST 24
Peak memory 216784 kb
Host smart-c6cfec38-08a0-434c-8290-19a8e6f84ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029443177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2029443177
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1656923217
Short name T711
Test name
Test status
Simulation time 422711559 ps
CPU time 11.02 seconds
Started Jan 03 02:01:52 PM PST 24
Finished Jan 03 02:02:19 PM PST 24
Peak memory 216672 kb
Host smart-881c265d-5739-4dd2-8680-67ece5a49932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656923217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1656923217
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.151829824
Short name T1552
Test name
Test status
Simulation time 43052293 ps
CPU time 0.98 seconds
Started Jan 03 02:01:52 PM PST 24
Finished Jan 03 02:02:10 PM PST 24
Peak memory 207912 kb
Host smart-8ee34093-d6e9-4d37-b994-3847fb9cdfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151829824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.151829824
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_tx_async_fifo_reset.2824362715
Short name T866
Test name
Test status
Simulation time 16839980 ps
CPU time 0.78 seconds
Started Jan 03 02:01:44 PM PST 24
Finished Jan 03 02:02:04 PM PST 24
Peak memory 208476 kb
Host smart-3ef81436-0cb8-4626-a4fd-7b52d5ec673a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824362715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tx_async_fifo_reset.2824362715
Directory /workspace/44.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/44.spi_device_txrx.1940121346
Short name T1371
Test name
Test status
Simulation time 5744715411 ps
CPU time 125.42 seconds
Started Jan 03 02:01:38 PM PST 24
Finished Jan 03 02:04:01 PM PST 24
Peak memory 255408 kb
Host smart-59e633e1-7f62-4be3-9462-c38621eac808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940121346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_txrx.1940121346
Directory /workspace/44.spi_device_txrx/latest

Test location /workspace/coverage/default/44.spi_device_upload.1726589308
Short name T1190
Test name
Test status
Simulation time 4349674678 ps
CPU time 7.49 seconds
Started Jan 03 02:01:47 PM PST 24
Finished Jan 03 02:02:12 PM PST 24
Peak memory 225160 kb
Host smart-f195a012-6557-44fa-899f-760c03ee051b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726589308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1726589308
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_abort.97210406
Short name T82
Test name
Test status
Simulation time 42516613 ps
CPU time 0.73 seconds
Started Jan 03 02:02:50 PM PST 24
Finished Jan 03 02:03:00 PM PST 24
Peak memory 206768 kb
Host smart-fe8f5d3a-ffe7-4184-87c0-2f178965ee51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97210406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_abort.97210406
Directory /workspace/45.spi_device_abort/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2756075387
Short name T982
Test name
Test status
Simulation time 18938895 ps
CPU time 0.72 seconds
Started Jan 03 02:02:50 PM PST 24
Finished Jan 03 02:03:00 PM PST 24
Peak memory 206448 kb
Host smart-47365b6f-bfa5-404d-9bf8-cbeb44a63b5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756075387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2756075387
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_bit_transfer.4097739458
Short name T1216
Test name
Test status
Simulation time 167021733 ps
CPU time 2.17 seconds
Started Jan 03 02:02:56 PM PST 24
Finished Jan 03 02:03:11 PM PST 24
Peak memory 216780 kb
Host smart-ad5f368e-3cfb-40ad-a3a2-23477e9e811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097739458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_bit_transfer.4097739458
Directory /workspace/45.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/45.spi_device_byte_transfer.1100453349
Short name T1127
Test name
Test status
Simulation time 887855164 ps
CPU time 3.34 seconds
Started Jan 03 02:02:51 PM PST 24
Finished Jan 03 02:03:03 PM PST 24
Peak memory 216892 kb
Host smart-5651fa60-e932-4c32-995d-281ee2958742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100453349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_byte_transfer.1100453349
Directory /workspace/45.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.971075797
Short name T19
Test name
Test status
Simulation time 237364067 ps
CPU time 2.94 seconds
Started Jan 03 02:02:52 PM PST 24
Finished Jan 03 02:03:07 PM PST 24
Peak memory 239656 kb
Host smart-d4e5282e-7b0a-47aa-a64f-a0b8a83df1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971075797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.971075797
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2564822759
Short name T1765
Test name
Test status
Simulation time 46712748 ps
CPU time 0.74 seconds
Started Jan 03 02:03:13 PM PST 24
Finished Jan 03 02:03:23 PM PST 24
Peak memory 206588 kb
Host smart-2f1e0be5-5b85-4e63-b247-f9fcdc1abb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564822759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2564822759
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_dummy_item_extra_dly.2374073862
Short name T1709
Test name
Test status
Simulation time 245497119442 ps
CPU time 1380.69 seconds
Started Jan 03 02:02:56 PM PST 24
Finished Jan 03 02:26:09 PM PST 24
Peak memory 251984 kb
Host smart-64347314-6d07-482d-beda-73fab86eaa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374073862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_dummy_item_extra_dly.2374073862
Directory /workspace/45.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/45.spi_device_extreme_fifo_size.434647126
Short name T640
Test name
Test status
Simulation time 178223496246 ps
CPU time 496.36 seconds
Started Jan 03 02:02:54 PM PST 24
Finished Jan 03 02:11:23 PM PST 24
Peak memory 218172 kb
Host smart-560ffafd-d3ae-44be-8382-9e8590022f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434647126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_extreme_fifo_size.434647126
Directory /workspace/45.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/45.spi_device_fifo_full.930978563
Short name T306
Test name
Test status
Simulation time 325283838483 ps
CPU time 2447.76 seconds
Started Jan 03 02:01:47 PM PST 24
Finished Jan 03 02:42:53 PM PST 24
Peak memory 249772 kb
Host smart-ca671343-7eb5-465e-9b5e-8e00729764f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930978563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_fifo_full.930978563
Directory /workspace/45.spi_device_fifo_full/latest

Test location /workspace/coverage/default/45.spi_device_fifo_underflow_overflow.4081954886
Short name T1032
Test name
Test status
Simulation time 281932816511 ps
CPU time 384.73 seconds
Started Jan 03 02:02:54 PM PST 24
Finished Jan 03 02:09:32 PM PST 24
Peak memory 516888 kb
Host smart-1e71b35e-e8d9-4e85-a3ba-49bc213272ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081954886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_fifo_underflow_overf
low.4081954886
Directory /workspace/45.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.4076033189
Short name T266
Test name
Test status
Simulation time 1633643232 ps
CPU time 36.71 seconds
Started Jan 03 02:02:56 PM PST 24
Finished Jan 03 02:03:46 PM PST 24
Peak memory 253440 kb
Host smart-df02ce22-f171-433b-962b-794663270d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076033189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.4076033189
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2605175300
Short name T1754
Test name
Test status
Simulation time 277103091615 ps
CPU time 249.45 seconds
Started Jan 03 02:02:52 PM PST 24
Finished Jan 03 02:07:12 PM PST 24
Peak memory 261848 kb
Host smart-a8a5c070-1ffd-46d9-af3d-0d5a6810d9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605175300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2605175300
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1519574390
Short name T1616
Test name
Test status
Simulation time 3920786074 ps
CPU time 26.95 seconds
Started Jan 03 02:03:14 PM PST 24
Finished Jan 03 02:03:51 PM PST 24
Peak memory 257460 kb
Host smart-285c4155-ec86-4075-9c15-e01595338c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519574390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1519574390
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2430626657
Short name T228
Test name
Test status
Simulation time 1001116300 ps
CPU time 4.2 seconds
Started Jan 03 02:06:54 PM PST 24
Finished Jan 03 02:07:00 PM PST 24
Peak memory 239740 kb
Host smart-90b70483-ab4e-47fd-a51e-12956963bfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430626657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2430626657
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_intr.738504383
Short name T204
Test name
Test status
Simulation time 21795854910 ps
CPU time 88.84 seconds
Started Jan 03 02:03:10 PM PST 24
Finished Jan 03 02:04:48 PM PST 24
Peak memory 240564 kb
Host smart-4fb97b02-0fe4-4971-80c1-b1d9ef083c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738504383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intr.738504383
Directory /workspace/45.spi_device_intr/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2779509877
Short name T886
Test name
Test status
Simulation time 2207037009 ps
CPU time 11.08 seconds
Started Jan 03 02:02:54 PM PST 24
Finished Jan 03 02:03:18 PM PST 24
Peak memory 239568 kb
Host smart-88e9fb6e-ea46-434e-a364-1198e51ce673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779509877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2779509877
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1254643411
Short name T1195
Test name
Test status
Simulation time 618700669 ps
CPU time 8.1 seconds
Started Jan 03 02:02:55 PM PST 24
Finished Jan 03 02:03:16 PM PST 24
Peak memory 247036 kb
Host smart-973a5a6f-ab7d-426b-b193-26c92a6fd4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254643411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1254643411
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1410330464
Short name T1476
Test name
Test status
Simulation time 877542063 ps
CPU time 8.57 seconds
Started Jan 03 02:02:56 PM PST 24
Finished Jan 03 02:03:17 PM PST 24
Peak memory 238352 kb
Host smart-c3747c3c-9997-4411-b97f-018a6382a6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410330464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1410330464
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_perf.2737830175
Short name T603
Test name
Test status
Simulation time 45286462495 ps
CPU time 2780.99 seconds
Started Jan 03 02:02:56 PM PST 24
Finished Jan 03 02:49:30 PM PST 24
Peak memory 306016 kb
Host smart-86939a73-fa52-4a83-a978-b00a00eff253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737830175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_perf.2737830175
Directory /workspace/45.spi_device_perf/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.672604612
Short name T1544
Test name
Test status
Simulation time 389165461 ps
CPU time 4.37 seconds
Started Jan 03 02:02:54 PM PST 24
Finished Jan 03 02:03:11 PM PST 24
Peak memory 234216 kb
Host smart-f389a66b-f4c1-4221-99d9-631fd046eb46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=672604612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.672604612
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_rx_async_fifo_reset.4124327010
Short name T1610
Test name
Test status
Simulation time 76258212 ps
CPU time 0.89 seconds
Started Jan 03 02:03:11 PM PST 24
Finished Jan 03 02:03:20 PM PST 24
Peak memory 208536 kb
Host smart-89909851-93e0-4e9e-a29c-3185297d9336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124327010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_rx_async_fifo_reset.4124327010
Directory /workspace/45.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/45.spi_device_rx_timeout.2848559133
Short name T1505
Test name
Test status
Simulation time 543046451 ps
CPU time 5.17 seconds
Started Jan 03 02:03:09 PM PST 24
Finished Jan 03 02:03:24 PM PST 24
Peak memory 216992 kb
Host smart-9ecc2c9b-e9c0-46d3-94c8-4f9396e78dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848559133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_rx_timeout.2848559133
Directory /workspace/45.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/45.spi_device_smoke.696769313
Short name T667
Test name
Test status
Simulation time 42758027 ps
CPU time 1.23 seconds
Started Jan 03 02:01:48 PM PST 24
Finished Jan 03 02:02:07 PM PST 24
Peak memory 216856 kb
Host smart-c1178a66-fe18-4813-ae55-d656e8f6f5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696769313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_smoke.696769313
Directory /workspace/45.spi_device_smoke/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.812639487
Short name T1487
Test name
Test status
Simulation time 5559051174 ps
CPU time 42.98 seconds
Started Jan 03 02:02:30 PM PST 24
Finished Jan 03 02:03:15 PM PST 24
Peak memory 217032 kb
Host smart-7befb8c7-b315-464e-b563-21aa3975c41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812639487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.812639487
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3654720435
Short name T1180
Test name
Test status
Simulation time 2093019183 ps
CPU time 5 seconds
Started Jan 03 02:03:13 PM PST 24
Finished Jan 03 02:03:27 PM PST 24
Peak memory 216928 kb
Host smart-73f7f55b-e0b8-4925-9624-ecc03b142cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654720435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3654720435
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.4154928500
Short name T559
Test name
Test status
Simulation time 39450268 ps
CPU time 0.98 seconds
Started Jan 03 02:02:29 PM PST 24
Finished Jan 03 02:02:32 PM PST 24
Peak memory 208152 kb
Host smart-5d1631ef-6a08-4db4-9a57-3134ca0cc6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154928500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.4154928500
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1634330076
Short name T873
Test name
Test status
Simulation time 44792940 ps
CPU time 0.87 seconds
Started Jan 03 02:02:56 PM PST 24
Finished Jan 03 02:03:10 PM PST 24
Peak memory 206692 kb
Host smart-dca8f6a8-55e1-4e19-b9ba-d77c882e43ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634330076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1634330076
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_tx_async_fifo_reset.963836974
Short name T867
Test name
Test status
Simulation time 19161064 ps
CPU time 0.77 seconds
Started Jan 03 02:02:58 PM PST 24
Finished Jan 03 02:03:11 PM PST 24
Peak memory 208484 kb
Host smart-4a7397a1-125e-448e-8cab-30e8b753fd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963836974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tx_async_fifo_reset.963836974
Directory /workspace/45.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/45.spi_device_txrx.16222622
Short name T1136
Test name
Test status
Simulation time 60615937295 ps
CPU time 275.73 seconds
Started Jan 03 02:01:53 PM PST 24
Finished Jan 03 02:06:45 PM PST 24
Peak memory 299996 kb
Host smart-d50fa9ac-5a4a-426a-a717-ea5f9011edbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16222622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_txrx.16222622
Directory /workspace/45.spi_device_txrx/latest

Test location /workspace/coverage/default/45.spi_device_upload.1953974591
Short name T289
Test name
Test status
Simulation time 664640088 ps
CPU time 6.77 seconds
Started Jan 03 02:02:54 PM PST 24
Finished Jan 03 02:03:14 PM PST 24
Peak memory 220512 kb
Host smart-221e808d-ec60-423c-a6da-864c2311cd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953974591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1953974591
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_abort.2864447330
Short name T1322
Test name
Test status
Simulation time 13438238 ps
CPU time 0.74 seconds
Started Jan 03 02:03:18 PM PST 24
Finished Jan 03 02:03:37 PM PST 24
Peak memory 206588 kb
Host smart-b37072b3-14ed-460d-81ed-1dc6392b4f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864447330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_abort.2864447330
Directory /workspace/46.spi_device_abort/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.978050956
Short name T94
Test name
Test status
Simulation time 35327354 ps
CPU time 0.74 seconds
Started Jan 03 02:02:50 PM PST 24
Finished Jan 03 02:03:00 PM PST 24
Peak memory 206512 kb
Host smart-8335534d-fb5a-4fde-8aaa-875600e327dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978050956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.978050956
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_bit_transfer.1075668016
Short name T682
Test name
Test status
Simulation time 113981656 ps
CPU time 2.26 seconds
Started Jan 03 02:03:11 PM PST 24
Finished Jan 03 02:03:22 PM PST 24
Peak memory 216804 kb
Host smart-911c046b-64bb-4ada-a5da-398af142e79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075668016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_bit_transfer.1075668016
Directory /workspace/46.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/46.spi_device_byte_transfer.3485886950
Short name T509
Test name
Test status
Simulation time 142255504 ps
CPU time 2.95 seconds
Started Jan 03 02:03:13 PM PST 24
Finished Jan 03 02:03:26 PM PST 24
Peak memory 216808 kb
Host smart-463f1ad9-a8c0-4ac9-81ac-980f5d448c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485886950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_byte_transfer.3485886950
Directory /workspace/46.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2618828293
Short name T1433
Test name
Test status
Simulation time 415722238 ps
CPU time 3.61 seconds
Started Jan 03 02:02:50 PM PST 24
Finished Jan 03 02:03:03 PM PST 24
Peak memory 225144 kb
Host smart-a61f6929-c934-4b77-a03b-15bd31d2ead6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618828293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2618828293
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2803752188
Short name T1500
Test name
Test status
Simulation time 48789035 ps
CPU time 0.8 seconds
Started Jan 03 02:02:54 PM PST 24
Finished Jan 03 02:03:08 PM PST 24
Peak memory 206684 kb
Host smart-72eb27ed-7abb-4b08-bade-d595d37a5a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803752188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2803752188
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_dummy_item_extra_dly.354760824
Short name T567
Test name
Test status
Simulation time 341397164489 ps
CPU time 1664.52 seconds
Started Jan 03 02:02:52 PM PST 24
Finished Jan 03 02:30:48 PM PST 24
Peak memory 278396 kb
Host smart-dc27c858-22f1-48d6-9e5b-8670b97299b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354760824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_dummy_item_extra_dly.354760824
Directory /workspace/46.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/46.spi_device_extreme_fifo_size.465973606
Short name T592
Test name
Test status
Simulation time 66841897427 ps
CPU time 2774.12 seconds
Started Jan 03 02:02:56 PM PST 24
Finished Jan 03 02:49:23 PM PST 24
Peak memory 220036 kb
Host smart-202cdde8-9560-498f-af7d-81a5a2fadd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465973606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_extreme_fifo_size.465973606
Directory /workspace/46.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/46.spi_device_fifo_full.2205707344
Short name T814
Test name
Test status
Simulation time 146236955945 ps
CPU time 1346.32 seconds
Started Jan 03 02:03:11 PM PST 24
Finished Jan 03 02:25:47 PM PST 24
Peak memory 261976 kb
Host smart-dcea793a-10c6-45c5-938c-c14abe052381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205707344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_fifo_full.2205707344
Directory /workspace/46.spi_device_fifo_full/latest

Test location /workspace/coverage/default/46.spi_device_fifo_underflow_overflow.3036175857
Short name T1133
Test name
Test status
Simulation time 80284249861 ps
CPU time 148.17 seconds
Started Jan 03 02:03:15 PM PST 24
Finished Jan 03 02:05:55 PM PST 24
Peak memory 333032 kb
Host smart-d78aae99-a03f-4fd3-a4a1-16973a1ea565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036175857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_fifo_underflow_overf
low.3036175857
Directory /workspace/46.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2953543738
Short name T215
Test name
Test status
Simulation time 77372561510 ps
CPU time 192.88 seconds
Started Jan 03 02:02:55 PM PST 24
Finished Jan 03 02:06:21 PM PST 24
Peak memory 269620 kb
Host smart-3a1018c8-e4d8-4b93-a352-357d0d22ae47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953543738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2953543738
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.4238455351
Short name T1280
Test name
Test status
Simulation time 18835236560 ps
CPU time 103.26 seconds
Started Jan 03 02:02:55 PM PST 24
Finished Jan 03 02:04:52 PM PST 24
Peak memory 266288 kb
Host smart-21bb64cd-a434-4138-a3ac-9b554602a7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238455351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.4238455351
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2790022958
Short name T271
Test name
Test status
Simulation time 5494307152 ps
CPU time 85.52 seconds
Started Jan 03 02:02:33 PM PST 24
Finished Jan 03 02:04:05 PM PST 24
Peak memory 253468 kb
Host smart-5306d015-d526-4042-addd-a1be0f152aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790022958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2790022958
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.677266336
Short name T623
Test name
Test status
Simulation time 358263680 ps
CPU time 9.16 seconds
Started Jan 03 02:02:56 PM PST 24
Finished Jan 03 02:03:18 PM PST 24
Peak memory 238348 kb
Host smart-2742793d-a678-4d06-8cd6-1655e1b59dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677266336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.677266336
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2178843370
Short name T1057
Test name
Test status
Simulation time 1820255061 ps
CPU time 5.76 seconds
Started Jan 03 02:03:15 PM PST 24
Finished Jan 03 02:03:32 PM PST 24
Peak memory 238172 kb
Host smart-36932e1c-2cf7-41e4-9976-371dc54f8ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178843370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2178843370
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_intr.1836741397
Short name T1013
Test name
Test status
Simulation time 5228525932 ps
CPU time 19.64 seconds
Started Jan 03 02:02:54 PM PST 24
Finished Jan 03 02:03:26 PM PST 24
Peak memory 218220 kb
Host smart-49955360-7213-49db-a4c3-0d2f27677742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836741397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intr.1836741397
Directory /workspace/46.spi_device_intr/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1985218677
Short name T1525
Test name
Test status
Simulation time 3342868046 ps
CPU time 13.3 seconds
Started Jan 03 02:03:28 PM PST 24
Finished Jan 03 02:04:08 PM PST 24
Peak memory 233396 kb
Host smart-753fda53-cefe-44c3-bd1c-60b93bf7e62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985218677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1985218677
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3021174170
Short name T238
Test name
Test status
Simulation time 731997151 ps
CPU time 3.68 seconds
Started Jan 03 02:03:16 PM PST 24
Finished Jan 03 02:03:32 PM PST 24
Peak memory 218640 kb
Host smart-08d45637-6089-4029-965f-b93b93dcd0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021174170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3021174170
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2178742330
Short name T1450
Test name
Test status
Simulation time 818196647 ps
CPU time 3.94 seconds
Started Jan 03 02:03:23 PM PST 24
Finished Jan 03 02:03:56 PM PST 24
Peak memory 218372 kb
Host smart-2c0c4d9b-d8ae-4133-8eb6-1717ab4d2cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178742330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2178742330
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_perf.1129344133
Short name T1268
Test name
Test status
Simulation time 8443311494 ps
CPU time 197.36 seconds
Started Jan 03 02:02:58 PM PST 24
Finished Jan 03 02:06:28 PM PST 24
Peak memory 253524 kb
Host smart-60e1de6c-3870-441b-9874-7ca0fc788cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129344133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_perf.1129344133
Directory /workspace/46.spi_device_perf/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2984537728
Short name T1425
Test name
Test status
Simulation time 957973217 ps
CPU time 5.56 seconds
Started Jan 03 02:02:56 PM PST 24
Finished Jan 03 02:03:14 PM PST 24
Peak memory 218636 kb
Host smart-e0345900-f66c-4f3e-920c-bb26105b0afb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2984537728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2984537728
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_rx_async_fifo_reset.1596887865
Short name T541
Test name
Test status
Simulation time 36148792 ps
CPU time 0.88 seconds
Started Jan 03 02:03:23 PM PST 24
Finished Jan 03 02:03:52 PM PST 24
Peak memory 208476 kb
Host smart-176d1755-d61d-47cd-a013-5e95dd146409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596887865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_rx_async_fifo_reset.1596887865
Directory /workspace/46.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/46.spi_device_rx_timeout.2777815336
Short name T1069
Test name
Test status
Simulation time 2097200142 ps
CPU time 5.11 seconds
Started Jan 03 02:03:18 PM PST 24
Finished Jan 03 02:03:41 PM PST 24
Peak memory 216780 kb
Host smart-e6d313de-0731-455f-a118-2cba5786ae7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777815336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_rx_timeout.2777815336
Directory /workspace/46.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/46.spi_device_smoke.2688065535
Short name T687
Test name
Test status
Simulation time 87031538 ps
CPU time 0.98 seconds
Started Jan 03 02:02:56 PM PST 24
Finished Jan 03 02:03:09 PM PST 24
Peak memory 207848 kb
Host smart-c10e5203-94d3-4616-9959-e4a955e2a875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688065535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_smoke.2688065535
Directory /workspace/46.spi_device_smoke/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.55271479
Short name T1366
Test name
Test status
Simulation time 4719422685 ps
CPU time 20.04 seconds
Started Jan 03 02:03:22 PM PST 24
Finished Jan 03 02:04:11 PM PST 24
Peak memory 217008 kb
Host smart-9057e5ba-4180-4216-a83e-02164e8cbd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55271479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.55271479
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3347508790
Short name T1293
Test name
Test status
Simulation time 2248645255 ps
CPU time 12.79 seconds
Started Jan 03 02:02:56 PM PST 24
Finished Jan 03 02:03:22 PM PST 24
Peak memory 216776 kb
Host smart-015f4aee-7a6c-45e0-bd6a-0be9d62484ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347508790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3347508790
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2435139721
Short name T869
Test name
Test status
Simulation time 172497072 ps
CPU time 1.66 seconds
Started Jan 03 02:03:23 PM PST 24
Finished Jan 03 02:03:53 PM PST 24
Peak memory 216828 kb
Host smart-23168db2-3a7d-4e8b-8eab-72e3766180e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435139721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2435139721
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.137497744
Short name T1015
Test name
Test status
Simulation time 87929723 ps
CPU time 0.89 seconds
Started Jan 03 02:03:13 PM PST 24
Finished Jan 03 02:03:23 PM PST 24
Peak memory 208016 kb
Host smart-849f94c5-2666-44af-9a21-4fdbc08b315a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137497744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.137497744
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_tx_async_fifo_reset.3473308703
Short name T779
Test name
Test status
Simulation time 43885200 ps
CPU time 0.75 seconds
Started Jan 03 02:03:24 PM PST 24
Finished Jan 03 02:03:53 PM PST 24
Peak memory 208504 kb
Host smart-69909497-262e-476c-a5cd-50502ba3b33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473308703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tx_async_fifo_reset.3473308703
Directory /workspace/46.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/46.spi_device_txrx.506615292
Short name T882
Test name
Test status
Simulation time 48170829263 ps
CPU time 168.4 seconds
Started Jan 03 02:02:29 PM PST 24
Finished Jan 03 02:05:19 PM PST 24
Peak memory 294736 kb
Host smart-70205eb8-2bf5-40dd-a3ad-15fce23a6cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506615292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_txrx.506615292
Directory /workspace/46.spi_device_txrx/latest

Test location /workspace/coverage/default/46.spi_device_upload.4055787378
Short name T1115
Test name
Test status
Simulation time 3570068183 ps
CPU time 10.7 seconds
Started Jan 03 02:03:26 PM PST 24
Finished Jan 03 02:04:05 PM PST 24
Peak memory 231080 kb
Host smart-8a9e8f6b-2062-4c90-b03f-aeeb74a74196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055787378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.4055787378
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_abort.2249417498
Short name T695
Test name
Test status
Simulation time 53377372 ps
CPU time 0.71 seconds
Started Jan 03 02:03:17 PM PST 24
Finished Jan 03 02:03:31 PM PST 24
Peak memory 206600 kb
Host smart-bec12e9f-9b3d-4fd7-a55f-ef75957d25d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249417498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_abort.2249417498
Directory /workspace/47.spi_device_abort/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.785125083
Short name T1453
Test name
Test status
Simulation time 27237627 ps
CPU time 0.72 seconds
Started Jan 03 02:03:34 PM PST 24
Finished Jan 03 02:04:40 PM PST 24
Peak memory 206424 kb
Host smart-073aacb9-447b-459a-9677-8e06c7f4c9db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785125083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.785125083
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_bit_transfer.479407554
Short name T538
Test name
Test status
Simulation time 184628227 ps
CPU time 2.86 seconds
Started Jan 03 02:03:14 PM PST 24
Finished Jan 03 02:03:27 PM PST 24
Peak memory 216792 kb
Host smart-14fc96d8-be7e-48e3-9a66-eaf49471bd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479407554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_bit_transfer.479407554
Directory /workspace/47.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/47.spi_device_byte_transfer.2250467461
Short name T527
Test name
Test status
Simulation time 594804141 ps
CPU time 2.79 seconds
Started Jan 03 02:03:16 PM PST 24
Finished Jan 03 02:03:32 PM PST 24
Peak memory 216792 kb
Host smart-27b0da99-bc3b-49d8-b3d2-341ee6a18448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250467461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_byte_transfer.2250467461
Directory /workspace/47.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1508015492
Short name T1276
Test name
Test status
Simulation time 253878191 ps
CPU time 4.38 seconds
Started Jan 03 02:03:31 PM PST 24
Finished Jan 03 02:04:01 PM PST 24
Peak memory 238616 kb
Host smart-1933a859-a6e2-4052-9066-8902af2ff262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508015492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1508015492
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3950279697
Short name T991
Test name
Test status
Simulation time 57771867 ps
CPU time 0.8 seconds
Started Jan 03 02:03:23 PM PST 24
Finished Jan 03 02:03:52 PM PST 24
Peak memory 206500 kb
Host smart-005ed2c9-220a-46fc-a13b-b8943b8d9d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950279697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3950279697
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_dummy_item_extra_dly.3835731381
Short name T1021
Test name
Test status
Simulation time 257586101618 ps
CPU time 630.75 seconds
Started Jan 03 02:03:19 PM PST 24
Finished Jan 03 02:14:11 PM PST 24
Peak memory 252864 kb
Host smart-409765e4-ca45-4ed7-ab91-2630ad808f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835731381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_dummy_item_extra_dly.3835731381
Directory /workspace/47.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/47.spi_device_extreme_fifo_size.1859938288
Short name T83
Test name
Test status
Simulation time 983714325314 ps
CPU time 631.96 seconds
Started Jan 03 02:02:57 PM PST 24
Finished Jan 03 02:13:42 PM PST 24
Peak memory 225016 kb
Host smart-a557b98e-e68a-4c68-9fad-1db29b093a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859938288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_extreme_fifo_size.1859938288
Directory /workspace/47.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/47.spi_device_fifo_full.555595279
Short name T936
Test name
Test status
Simulation time 163528499342 ps
CPU time 491.31 seconds
Started Jan 03 02:03:15 PM PST 24
Finished Jan 03 02:11:37 PM PST 24
Peak memory 283752 kb
Host smart-2c19999e-6cce-4303-a011-5d8623fb8f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555595279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_fifo_full.555595279
Directory /workspace/47.spi_device_fifo_full/latest

Test location /workspace/coverage/default/47.spi_device_fifo_underflow_overflow.1940714730
Short name T1565
Test name
Test status
Simulation time 65029921288 ps
CPU time 255.88 seconds
Started Jan 03 02:02:58 PM PST 24
Finished Jan 03 02:07:27 PM PST 24
Peak memory 355384 kb
Host smart-5577982d-c99a-413b-aeb1-5c9c20f3086d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940714730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_fifo_underflow_overf
low.1940714730
Directory /workspace/47.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.770144895
Short name T216
Test name
Test status
Simulation time 15351457660 ps
CPU time 114.83 seconds
Started Jan 03 02:03:32 PM PST 24
Finished Jan 03 02:05:52 PM PST 24
Peak memory 266360 kb
Host smart-4adbfeea-4f1c-48b7-a275-7665b74e93cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770144895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.770144895
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3014038518
Short name T692
Test name
Test status
Simulation time 16623561388 ps
CPU time 23.41 seconds
Started Jan 03 02:03:37 PM PST 24
Finished Jan 03 02:05:05 PM PST 24
Peak memory 225192 kb
Host smart-18f7720c-f94f-4fb4-bc15-791a1bd0830b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014038518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3014038518
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.678188980
Short name T287
Test name
Test status
Simulation time 13370699404 ps
CPU time 13.1 seconds
Started Jan 03 02:03:31 PM PST 24
Finished Jan 03 02:04:10 PM PST 24
Peak memory 222832 kb
Host smart-85281c10-1585-4caf-8cf7-254217cc46a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678188980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.678188980
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_intr.547186232
Short name T657
Test name
Test status
Simulation time 17969026509 ps
CPU time 19.62 seconds
Started Jan 03 02:03:22 PM PST 24
Finished Jan 03 02:04:08 PM PST 24
Peak memory 225064 kb
Host smart-adc90334-ec79-4b58-ac37-c4b1ef082785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547186232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intr.547186232
Directory /workspace/47.spi_device_intr/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1699797247
Short name T1262
Test name
Test status
Simulation time 85332582 ps
CPU time 2.59 seconds
Started Jan 03 02:03:29 PM PST 24
Finished Jan 03 02:03:58 PM PST 24
Peak memory 239100 kb
Host smart-ccd6135c-24f3-4317-a51d-290ff172d53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699797247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1699797247
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2107273668
Short name T1073
Test name
Test status
Simulation time 6986056518 ps
CPU time 19.77 seconds
Started Jan 03 02:03:27 PM PST 24
Finished Jan 03 02:04:15 PM PST 24
Peak memory 219096 kb
Host smart-186eeb80-503c-4180-b693-ccb815adc55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107273668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2107273668
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2738279120
Short name T1303
Test name
Test status
Simulation time 169450945 ps
CPU time 2.79 seconds
Started Jan 03 02:03:30 PM PST 24
Finished Jan 03 02:03:59 PM PST 24
Peak memory 218756 kb
Host smart-0db27677-ae52-47fd-876d-14946474e7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738279120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2738279120
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_perf.3793221514
Short name T1088
Test name
Test status
Simulation time 8080058931 ps
CPU time 223.6 seconds
Started Jan 03 02:03:25 PM PST 24
Finished Jan 03 02:07:38 PM PST 24
Peak memory 268892 kb
Host smart-cbc36de1-60ec-4a1d-9eea-7584c33d9894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793221514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_perf.3793221514
Directory /workspace/47.spi_device_perf/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3489268952
Short name T1680
Test name
Test status
Simulation time 334440498 ps
CPU time 3.43 seconds
Started Jan 03 02:03:31 PM PST 24
Finished Jan 03 02:04:00 PM PST 24
Peak memory 220068 kb
Host smart-f5b9a75f-f08d-4ddf-b7bb-8887c04f305d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3489268952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3489268952
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_rx_async_fifo_reset.2406895988
Short name T863
Test name
Test status
Simulation time 44288330 ps
CPU time 0.89 seconds
Started Jan 03 02:03:25 PM PST 24
Finished Jan 03 02:03:55 PM PST 24
Peak memory 208540 kb
Host smart-2ac46fc7-3b29-4dc5-a95c-e9e466217f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406895988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_rx_async_fifo_reset.2406895988
Directory /workspace/47.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/47.spi_device_rx_timeout.3429275195
Short name T859
Test name
Test status
Simulation time 2314451264 ps
CPU time 5.82 seconds
Started Jan 03 02:03:10 PM PST 24
Finished Jan 03 02:03:25 PM PST 24
Peak memory 216868 kb
Host smart-97e9f159-4f71-4b8b-86b0-1592eccef1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429275195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_rx_timeout.3429275195
Directory /workspace/47.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/47.spi_device_smoke.2463729892
Short name T931
Test name
Test status
Simulation time 18446231 ps
CPU time 0.92 seconds
Started Jan 03 02:02:56 PM PST 24
Finished Jan 03 02:03:10 PM PST 24
Peak memory 207660 kb
Host smart-1d8e2113-18a7-407b-a835-09dcbad96dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463729892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_smoke.2463729892
Directory /workspace/47.spi_device_smoke/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.769352669
Short name T1427
Test name
Test status
Simulation time 126077571584 ps
CPU time 1903.35 seconds
Started Jan 03 02:03:38 PM PST 24
Finished Jan 03 02:36:24 PM PST 24
Peak memory 315700 kb
Host smart-f9c95e00-1c76-40ec-8073-dc810cf9df59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769352669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.769352669
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.739656331
Short name T1223
Test name
Test status
Simulation time 533039763 ps
CPU time 5.82 seconds
Started Jan 03 02:03:11 PM PST 24
Finished Jan 03 02:03:26 PM PST 24
Peak memory 216768 kb
Host smart-6f20542e-72d2-426f-aa1a-97a7c1e290ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739656331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.739656331
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3274654005
Short name T767
Test name
Test status
Simulation time 81973460 ps
CPU time 0.99 seconds
Started Jan 03 02:03:24 PM PST 24
Finished Jan 03 02:03:54 PM PST 24
Peak memory 207512 kb
Host smart-b13d7dc7-536b-4204-a4e2-a0cdf1993f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274654005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3274654005
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.488714954
Short name T1435
Test name
Test status
Simulation time 502243642 ps
CPU time 1.08 seconds
Started Jan 03 02:03:21 PM PST 24
Finished Jan 03 02:03:49 PM PST 24
Peak memory 207940 kb
Host smart-d6779588-3cef-44b8-9398-5553c35dd592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488714954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.488714954
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_tx_async_fifo_reset.2315340095
Short name T1671
Test name
Test status
Simulation time 50153579 ps
CPU time 0.84 seconds
Started Jan 03 02:03:11 PM PST 24
Finished Jan 03 02:03:20 PM PST 24
Peak memory 208332 kb
Host smart-c9100059-fbb6-4ab5-a149-5acbf545fd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315340095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tx_async_fifo_reset.2315340095
Directory /workspace/47.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/47.spi_device_txrx.544094007
Short name T932
Test name
Test status
Simulation time 29093099338 ps
CPU time 179.98 seconds
Started Jan 03 02:02:55 PM PST 24
Finished Jan 03 02:06:08 PM PST 24
Peak memory 266644 kb
Host smart-bafc1319-fd19-4980-9067-37f2a3592802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544094007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_txrx.544094007
Directory /workspace/47.spi_device_txrx/latest

Test location /workspace/coverage/default/47.spi_device_upload.3246108675
Short name T1287
Test name
Test status
Simulation time 10029772122 ps
CPU time 20.79 seconds
Started Jan 03 02:03:34 PM PST 24
Finished Jan 03 02:05:05 PM PST 24
Peak memory 246936 kb
Host smart-781024d1-6aa2-466e-a94f-9cdee1a03450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246108675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3246108675
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_abort.3908665570
Short name T1519
Test name
Test status
Simulation time 25500547 ps
CPU time 0.77 seconds
Started Jan 03 02:02:49 PM PST 24
Finished Jan 03 02:02:58 PM PST 24
Peak memory 206716 kb
Host smart-f2d6f4b7-6fee-46f7-b6a5-e2f12a57c54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908665570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_abort.3908665570
Directory /workspace/48.spi_device_abort/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2509318712
Short name T1660
Test name
Test status
Simulation time 41234873 ps
CPU time 0.71 seconds
Started Jan 03 02:03:33 PM PST 24
Finished Jan 03 02:04:08 PM PST 24
Peak memory 206532 kb
Host smart-bcf57bd0-7108-4c60-9af2-d60556afe7cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509318712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2509318712
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_bit_transfer.3562452360
Short name T800
Test name
Test status
Simulation time 148669486 ps
CPU time 2.59 seconds
Started Jan 03 02:02:29 PM PST 24
Finished Jan 03 02:02:34 PM PST 24
Peak memory 216896 kb
Host smart-9dfb8fea-2ca9-45e7-ad31-c33e3b1c047c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562452360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_bit_transfer.3562452360
Directory /workspace/48.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/48.spi_device_byte_transfer.732034281
Short name T1085
Test name
Test status
Simulation time 805060007 ps
CPU time 2.9 seconds
Started Jan 03 02:03:14 PM PST 24
Finished Jan 03 02:03:27 PM PST 24
Peak memory 216900 kb
Host smart-33cf1d56-6cb9-45f6-97e6-b324f1b21310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732034281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_byte_transfer.732034281
Directory /workspace/48.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2175168163
Short name T986
Test name
Test status
Simulation time 4619869548 ps
CPU time 8.77 seconds
Started Jan 03 02:03:09 PM PST 24
Finished Jan 03 02:03:27 PM PST 24
Peak memory 240572 kb
Host smart-a737924e-400f-4d3b-9708-38b999a36590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175168163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2175168163
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1446558842
Short name T1364
Test name
Test status
Simulation time 61388989 ps
CPU time 0.79 seconds
Started Jan 03 02:03:34 PM PST 24
Finished Jan 03 02:04:40 PM PST 24
Peak memory 207460 kb
Host smart-9be6d86a-2d8a-445d-ba21-745cd15a9125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446558842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1446558842
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_dummy_item_extra_dly.4007507617
Short name T605
Test name
Test status
Simulation time 35713578159 ps
CPU time 136.88 seconds
Started Jan 03 02:03:36 PM PST 24
Finished Jan 03 02:06:59 PM PST 24
Peak memory 240656 kb
Host smart-dd99fac9-488f-4cc3-80c3-0a718473a059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007507617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_dummy_item_extra_dly.4007507617
Directory /workspace/48.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/48.spi_device_fifo_full.2979906161
Short name T856
Test name
Test status
Simulation time 152873901109 ps
CPU time 635.62 seconds
Started Jan 03 02:03:36 PM PST 24
Finished Jan 03 02:15:18 PM PST 24
Peak memory 254136 kb
Host smart-8b362de0-b68a-4df7-98ca-7d30b606a6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979906161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_fifo_full.2979906161
Directory /workspace/48.spi_device_fifo_full/latest

Test location /workspace/coverage/default/48.spi_device_fifo_underflow_overflow.1267272657
Short name T1436
Test name
Test status
Simulation time 397513871510 ps
CPU time 524.5 seconds
Started Jan 03 02:03:34 PM PST 24
Finished Jan 03 02:13:25 PM PST 24
Peak memory 431884 kb
Host smart-6f5549d8-5e19-4a3f-818f-b2f3035751ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267272657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_fifo_underflow_overf
low.1267272657
Directory /workspace/48.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2473855266
Short name T390
Test name
Test status
Simulation time 3331662720 ps
CPU time 54.32 seconds
Started Jan 03 02:03:22 PM PST 24
Finished Jan 03 02:04:44 PM PST 24
Peak memory 241384 kb
Host smart-fd1e4685-f6c9-40c7-a13b-b0c642f5e1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473855266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2473855266
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.181240953
Short name T282
Test name
Test status
Simulation time 12644763197 ps
CPU time 55.76 seconds
Started Jan 03 02:03:25 PM PST 24
Finished Jan 03 02:04:49 PM PST 24
Peak memory 250864 kb
Host smart-44cf8d7a-f716-477d-9e97-271ac2533b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181240953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.181240953
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3086502120
Short name T1233
Test name
Test status
Simulation time 2979409773 ps
CPU time 22.32 seconds
Started Jan 03 02:03:25 PM PST 24
Finished Jan 03 02:04:16 PM PST 24
Peak memory 240584 kb
Host smart-66aa3cd2-8bfd-46e0-a04d-92f9c341b032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086502120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3086502120
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.882932956
Short name T1609
Test name
Test status
Simulation time 5850151570 ps
CPU time 6.71 seconds
Started Jan 03 02:02:57 PM PST 24
Finished Jan 03 02:03:16 PM PST 24
Peak memory 222104 kb
Host smart-cf99672c-43e2-43da-8eea-7e00a37160b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882932956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.882932956
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_intr.1526731359
Short name T1041
Test name
Test status
Simulation time 16165485631 ps
CPU time 68.73 seconds
Started Jan 03 02:03:40 PM PST 24
Finished Jan 03 02:05:51 PM PST 24
Peak memory 241644 kb
Host smart-a85d5013-d75f-4db2-be5d-afd6fde77912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526731359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intr.1526731359
Directory /workspace/48.spi_device_intr/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1109630505
Short name T313
Test name
Test status
Simulation time 2781517593 ps
CPU time 12.79 seconds
Started Jan 03 02:03:23 PM PST 24
Finished Jan 03 02:04:03 PM PST 24
Peak memory 249652 kb
Host smart-d01b52f6-6c97-43df-992b-509156cef307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109630505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1109630505
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3311098480
Short name T334
Test name
Test status
Simulation time 903621746 ps
CPU time 7.04 seconds
Started Jan 03 02:03:18 PM PST 24
Finished Jan 03 02:03:43 PM PST 24
Peak memory 218312 kb
Host smart-b74972a8-aaed-4b13-a595-c1716dc7aa48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311098480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3311098480
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2310683694
Short name T1201
Test name
Test status
Simulation time 4482484601 ps
CPU time 17.46 seconds
Started Jan 03 02:03:11 PM PST 24
Finished Jan 03 02:03:37 PM PST 24
Peak memory 241104 kb
Host smart-84e6ef89-5070-4aea-beeb-0c0c081883dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310683694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2310683694
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_perf.1005820054
Short name T156
Test name
Test status
Simulation time 32967049817 ps
CPU time 666.62 seconds
Started Jan 03 02:03:38 PM PST 24
Finished Jan 03 02:15:47 PM PST 24
Peak memory 304292 kb
Host smart-2bb68772-9383-4003-8f69-6b368424ef6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005820054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_perf.1005820054
Directory /workspace/48.spi_device_perf/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1572264105
Short name T1596
Test name
Test status
Simulation time 921533770 ps
CPU time 5.14 seconds
Started Jan 03 02:03:24 PM PST 24
Finished Jan 03 02:03:58 PM PST 24
Peak memory 220864 kb
Host smart-5babd641-fc50-4798-9446-b114fb808911
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1572264105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1572264105
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_rx_async_fifo_reset.1345267682
Short name T763
Test name
Test status
Simulation time 20665797 ps
CPU time 0.89 seconds
Started Jan 03 02:02:55 PM PST 24
Finished Jan 03 02:03:09 PM PST 24
Peak memory 208400 kb
Host smart-909db060-9ae3-4785-859d-2563ae52cb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345267682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_rx_async_fifo_reset.1345267682
Directory /workspace/48.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/48.spi_device_rx_timeout.904120907
Short name T1304
Test name
Test status
Simulation time 563889414 ps
CPU time 4.71 seconds
Started Jan 03 02:03:38 PM PST 24
Finished Jan 03 02:04:46 PM PST 24
Peak memory 216732 kb
Host smart-69637c99-7144-4b72-947d-b8f96343598a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904120907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_rx_timeout.904120907
Directory /workspace/48.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/48.spi_device_smoke.728426516
Short name T1282
Test name
Test status
Simulation time 28935608 ps
CPU time 1.06 seconds
Started Jan 03 02:03:39 PM PST 24
Finished Jan 03 02:04:40 PM PST 24
Peak memory 216520 kb
Host smart-735b51b7-b007-4af8-9809-accbd884771c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728426516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_smoke.728426516
Directory /workspace/48.spi_device_smoke/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3769556690
Short name T182
Test name
Test status
Simulation time 248117522256 ps
CPU time 1397.04 seconds
Started Jan 03 02:03:30 PM PST 24
Finished Jan 03 02:27:13 PM PST 24
Peak memory 321396 kb
Host smart-07f30710-28e0-4cf6-bb17-5eb549bfd34e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769556690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3769556690
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.833645993
Short name T1055
Test name
Test status
Simulation time 2217427430 ps
CPU time 35.74 seconds
Started Jan 03 02:03:12 PM PST 24
Finished Jan 03 02:03:56 PM PST 24
Peak memory 217140 kb
Host smart-d04326ec-b8a1-44ff-85f3-3e98267b7963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833645993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.833645993
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2333380587
Short name T1109
Test name
Test status
Simulation time 3868948993 ps
CPU time 6.98 seconds
Started Jan 03 02:02:52 PM PST 24
Finished Jan 03 02:03:10 PM PST 24
Peak memory 216868 kb
Host smart-82e41102-343e-44f5-8159-0d9cdfa5f70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333380587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2333380587
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1270708146
Short name T675
Test name
Test status
Simulation time 63592937 ps
CPU time 3.73 seconds
Started Jan 03 02:02:56 PM PST 24
Finished Jan 03 02:03:12 PM PST 24
Peak memory 216860 kb
Host smart-46b30c48-3c2e-4370-9024-75cb3d264d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270708146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1270708146
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2185504162
Short name T1735
Test name
Test status
Simulation time 98061047 ps
CPU time 1.04 seconds
Started Jan 03 02:02:40 PM PST 24
Finished Jan 03 02:02:54 PM PST 24
Peak memory 208052 kb
Host smart-b6ffa9a8-070c-46fd-aa79-46db23ffc98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185504162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2185504162
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_tx_async_fifo_reset.2820241296
Short name T926
Test name
Test status
Simulation time 16772127 ps
CPU time 0.8 seconds
Started Jan 03 02:02:56 PM PST 24
Finished Jan 03 02:03:09 PM PST 24
Peak memory 208332 kb
Host smart-8686dab4-6c15-4c5d-8c56-acbde01812fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820241296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tx_async_fifo_reset.2820241296
Directory /workspace/48.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/48.spi_device_txrx.3733893795
Short name T532
Test name
Test status
Simulation time 52175281211 ps
CPU time 161.4 seconds
Started Jan 03 02:03:35 PM PST 24
Finished Jan 03 02:07:25 PM PST 24
Peak memory 254232 kb
Host smart-fc47ffb6-6b9f-4b44-8a9d-d12f56032fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733893795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_txrx.3733893795
Directory /workspace/48.spi_device_txrx/latest

Test location /workspace/coverage/default/48.spi_device_upload.197664210
Short name T1174
Test name
Test status
Simulation time 367398887 ps
CPU time 3.49 seconds
Started Jan 03 02:03:25 PM PST 24
Finished Jan 03 02:03:57 PM PST 24
Peak memory 220816 kb
Host smart-ece26ca2-d101-4055-88eb-3219896f710a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197664210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.197664210
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_abort.289346924
Short name T1718
Test name
Test status
Simulation time 23712442 ps
CPU time 0.75 seconds
Started Jan 03 02:03:33 PM PST 24
Finished Jan 03 02:04:08 PM PST 24
Peak memory 206584 kb
Host smart-86b889cd-118d-4c7e-96a6-a09d699fe757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289346924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_abort.289346924
Directory /workspace/49.spi_device_abort/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3824203841
Short name T152
Test name
Test status
Simulation time 32181677 ps
CPU time 0.75 seconds
Started Jan 03 02:02:56 PM PST 24
Finished Jan 03 02:03:09 PM PST 24
Peak memory 206496 kb
Host smart-c969e09c-0b25-45ec-bdec-0f1681d83cf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824203841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3824203841
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_bit_transfer.13548009
Short name T544
Test name
Test status
Simulation time 176420091 ps
CPU time 2.05 seconds
Started Jan 03 02:03:34 PM PST 24
Finished Jan 03 02:04:42 PM PST 24
Peak memory 216764 kb
Host smart-b64fec17-8390-4163-8bff-85ada1bd70d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13548009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_bit_transfer.13548009
Directory /workspace/49.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/49.spi_device_byte_transfer.3788230381
Short name T512
Test name
Test status
Simulation time 541490940 ps
CPU time 3.12 seconds
Started Jan 03 02:03:37 PM PST 24
Finished Jan 03 02:04:43 PM PST 24
Peak memory 216992 kb
Host smart-621e8813-cdb8-4e34-aba7-1558e6ce2107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788230381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_byte_transfer.3788230381
Directory /workspace/49.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1952066246
Short name T110
Test name
Test status
Simulation time 361423065 ps
CPU time 2.74 seconds
Started Jan 03 02:03:38 PM PST 24
Finished Jan 03 02:04:44 PM PST 24
Peak memory 241204 kb
Host smart-b64aaf80-3f9b-4563-a33c-515310b4afc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952066246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1952066246
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3419516244
Short name T1306
Test name
Test status
Simulation time 35302753 ps
CPU time 0.72 seconds
Started Jan 03 02:03:34 PM PST 24
Finished Jan 03 02:04:41 PM PST 24
Peak memory 206596 kb
Host smart-29a23bb8-92fe-4eb1-bba1-47452bf42250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419516244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3419516244
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_dummy_item_extra_dly.3219171690
Short name T1762
Test name
Test status
Simulation time 240339740884 ps
CPU time 446.12 seconds
Started Jan 03 02:03:35 PM PST 24
Finished Jan 03 02:12:08 PM PST 24
Peak memory 269996 kb
Host smart-8423294f-71c2-4ae3-9dc8-74358506a810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219171690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_dummy_item_extra_dly.3219171690
Directory /workspace/49.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/49.spi_device_extreme_fifo_size.213055070
Short name T809
Test name
Test status
Simulation time 227025824774 ps
CPU time 2738.21 seconds
Started Jan 03 02:03:33 PM PST 24
Finished Jan 03 02:49:45 PM PST 24
Peak memory 224084 kb
Host smart-3a350298-051c-4790-b553-f377428e74c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213055070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_extreme_fifo_size.213055070
Directory /workspace/49.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/49.spi_device_fifo_full.178031368
Short name T862
Test name
Test status
Simulation time 46660838498 ps
CPU time 234.67 seconds
Started Jan 03 02:03:35 PM PST 24
Finished Jan 03 02:08:36 PM PST 24
Peak memory 297772 kb
Host smart-d5c34125-5f06-4190-b51d-ac4c1fd4650d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178031368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_fifo_full.178031368
Directory /workspace/49.spi_device_fifo_full/latest

Test location /workspace/coverage/default/49.spi_device_fifo_underflow_overflow.4128488726
Short name T945
Test name
Test status
Simulation time 197444169601 ps
CPU time 703.77 seconds
Started Jan 03 02:03:26 PM PST 24
Finished Jan 03 02:15:38 PM PST 24
Peak memory 435372 kb
Host smart-f4bffe16-c826-496b-8fa5-fb8c26481ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128488726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_fifo_underflow_overf
low.4128488726
Directory /workspace/49.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3276678057
Short name T365
Test name
Test status
Simulation time 218356109322 ps
CPU time 353.32 seconds
Started Jan 03 02:03:38 PM PST 24
Finished Jan 03 02:10:33 PM PST 24
Peak memory 262704 kb
Host smart-ff7980b9-7e73-4123-a7d2-76ad373e47f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276678057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3276678057
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.413166492
Short name T244
Test name
Test status
Simulation time 47011369492 ps
CPU time 405.19 seconds
Started Jan 03 02:02:56 PM PST 24
Finished Jan 03 02:09:54 PM PST 24
Peak memory 274368 kb
Host smart-4485ffbc-ea02-4d7b-8144-efa37252f262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413166492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.413166492
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2226034025
Short name T679
Test name
Test status
Simulation time 5833948730 ps
CPU time 33.59 seconds
Started Jan 03 02:03:39 PM PST 24
Finished Jan 03 02:05:15 PM PST 24
Peak memory 250500 kb
Host smart-a1a2f98f-f064-4bde-8167-38d6902bce2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226034025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2226034025
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.4051229034
Short name T280
Test name
Test status
Simulation time 1850735317 ps
CPU time 4.47 seconds
Started Jan 03 02:03:38 PM PST 24
Finished Jan 03 02:04:44 PM PST 24
Peak memory 241424 kb
Host smart-5a11f14c-bd59-4336-be34-6dba28eed5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051229034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.4051229034
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_intr.3906554631
Short name T1382
Test name
Test status
Simulation time 9675567172 ps
CPU time 31.84 seconds
Started Jan 03 02:03:34 PM PST 24
Finished Jan 03 02:05:12 PM PST 24
Peak memory 235204 kb
Host smart-77c881cc-288c-4071-a23b-a9edd8250ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906554631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intr.3906554631
Directory /workspace/49.spi_device_intr/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3183861335
Short name T254
Test name
Test status
Simulation time 716013855 ps
CPU time 5.75 seconds
Started Jan 03 02:03:39 PM PST 24
Finished Jan 03 02:04:45 PM PST 24
Peak memory 241460 kb
Host smart-c5d39559-05b3-4c56-89d4-00f07319eeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183861335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3183861335
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2622141718
Short name T133
Test name
Test status
Simulation time 3273608104 ps
CPU time 12.93 seconds
Started Jan 03 02:03:39 PM PST 24
Finished Jan 03 02:04:55 PM PST 24
Peak memory 241428 kb
Host smart-f6a4ca14-255c-4f4f-952e-6bc0db692a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622141718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2622141718
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3838650783
Short name T1308
Test name
Test status
Simulation time 7988103869 ps
CPU time 8.46 seconds
Started Jan 03 02:03:39 PM PST 24
Finished Jan 03 02:04:50 PM PST 24
Peak memory 218580 kb
Host smart-9955db58-cf9e-44bf-af2d-e09e052d2d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838650783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3838650783
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_perf.1829823187
Short name T902
Test name
Test status
Simulation time 453684773249 ps
CPU time 918.22 seconds
Started Jan 03 02:03:32 PM PST 24
Finished Jan 03 02:19:15 PM PST 24
Peak memory 257708 kb
Host smart-60d10ab0-5184-4c87-a23b-5305e250c8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829823187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_perf.1829823187
Directory /workspace/49.spi_device_perf/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2686628401
Short name T1289
Test name
Test status
Simulation time 374503671 ps
CPU time 3.88 seconds
Started Jan 03 02:03:41 PM PST 24
Finished Jan 03 02:04:35 PM PST 24
Peak memory 220144 kb
Host smart-6e883d75-bc5b-4396-abea-ea6b231451fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2686628401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2686628401
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_rx_async_fifo_reset.694270325
Short name T951
Test name
Test status
Simulation time 29004497 ps
CPU time 0.86 seconds
Started Jan 03 02:03:38 PM PST 24
Finished Jan 03 02:04:43 PM PST 24
Peak memory 208372 kb
Host smart-7d650349-1d05-414f-a768-17f482b05d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694270325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_rx_async_fifo_reset.694270325
Directory /workspace/49.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/49.spi_device_rx_timeout.3945868257
Short name T961
Test name
Test status
Simulation time 513137080 ps
CPU time 4.81 seconds
Started Jan 03 02:03:38 PM PST 24
Finished Jan 03 02:04:44 PM PST 24
Peak memory 216908 kb
Host smart-1287bdfe-7ed7-4ca7-ba3f-f2428be80e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945868257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_rx_timeout.3945868257
Directory /workspace/49.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/49.spi_device_smoke.536540020
Short name T930
Test name
Test status
Simulation time 96355049 ps
CPU time 1.06 seconds
Started Jan 03 02:03:27 PM PST 24
Finished Jan 03 02:03:56 PM PST 24
Peak memory 208360 kb
Host smart-7e9bf6cc-2caf-4f7b-9e2b-6fc0c6aa8715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536540020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_smoke.536540020
Directory /workspace/49.spi_device_smoke/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.4186816313
Short name T1184
Test name
Test status
Simulation time 4185845836 ps
CPU time 15.63 seconds
Started Jan 03 02:03:35 PM PST 24
Finished Jan 03 02:04:56 PM PST 24
Peak memory 220816 kb
Host smart-9dd0d33c-efae-44ef-b580-88c1f5226c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186816313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4186816313
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2871618492
Short name T1550
Test name
Test status
Simulation time 1815651719 ps
CPU time 3.82 seconds
Started Jan 03 02:03:41 PM PST 24
Finished Jan 03 02:04:36 PM PST 24
Peak memory 216852 kb
Host smart-675b6ff3-b16a-4a70-bbe4-e282cd25e75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871618492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2871618492
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1533701166
Short name T570
Test name
Test status
Simulation time 58551416 ps
CPU time 0.82 seconds
Started Jan 03 02:03:38 PM PST 24
Finished Jan 03 02:04:42 PM PST 24
Peak memory 206872 kb
Host smart-4576e3ca-207d-4ac9-a937-2092f907e1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533701166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1533701166
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1017768841
Short name T1529
Test name
Test status
Simulation time 322355139 ps
CPU time 0.79 seconds
Started Jan 03 02:03:38 PM PST 24
Finished Jan 03 02:04:42 PM PST 24
Peak memory 206764 kb
Host smart-3c882bb2-e304-4fb8-a35f-4bb005a17c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017768841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1017768841
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_tx_async_fifo_reset.624122770
Short name T1357
Test name
Test status
Simulation time 126691534 ps
CPU time 0.77 seconds
Started Jan 03 02:03:38 PM PST 24
Finished Jan 03 02:04:42 PM PST 24
Peak memory 208440 kb
Host smart-aaab61cb-134d-4581-9526-2ca4554fe47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624122770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tx_async_fifo_reset.624122770
Directory /workspace/49.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/49.spi_device_txrx.73403407
Short name T109
Test name
Test status
Simulation time 26177928468 ps
CPU time 268.15 seconds
Started Jan 03 02:03:33 PM PST 24
Finished Jan 03 02:08:35 PM PST 24
Peak memory 308548 kb
Host smart-0de51e8c-80f0-4524-80e5-6bcf2d97b7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73403407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_txrx.73403407
Directory /workspace/49.spi_device_txrx/latest

Test location /workspace/coverage/default/49.spi_device_upload.1941233804
Short name T237
Test name
Test status
Simulation time 376425983 ps
CPU time 4.6 seconds
Started Jan 03 02:03:39 PM PST 24
Finished Jan 03 02:04:46 PM PST 24
Peak memory 225068 kb
Host smart-4557eea7-688d-4809-b47f-fb47a1be57a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941233804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1941233804
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_abort.4250856270
Short name T978
Test name
Test status
Simulation time 17309233 ps
CPU time 0.75 seconds
Started Jan 03 01:51:30 PM PST 24
Finished Jan 03 01:51:53 PM PST 24
Peak memory 206636 kb
Host smart-2b204cc7-9af3-4aa7-858b-b83771363398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250856270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_abort.4250856270
Directory /workspace/5.spi_device_abort/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3024833232
Short name T1393
Test name
Test status
Simulation time 11650656 ps
CPU time 0.76 seconds
Started Jan 03 01:51:31 PM PST 24
Finished Jan 03 01:51:53 PM PST 24
Peak memory 206476 kb
Host smart-e026bedf-f313-42c7-ba06-be8fc84152c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024833232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
024833232
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_bit_transfer.197067949
Short name T1126
Test name
Test status
Simulation time 498623585 ps
CPU time 2.38 seconds
Started Jan 03 01:51:21 PM PST 24
Finished Jan 03 01:51:33 PM PST 24
Peak memory 216824 kb
Host smart-4e4f4963-2ebd-42da-b712-6e4686726c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197067949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_bit_transfer.197067949
Directory /workspace/5.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/5.spi_device_byte_transfer.1448824802
Short name T1569
Test name
Test status
Simulation time 388941688 ps
CPU time 3.85 seconds
Started Jan 03 01:51:28 PM PST 24
Finished Jan 03 01:51:54 PM PST 24
Peak memory 216840 kb
Host smart-f8c2c9b9-4ec7-4bee-b74c-a8150818ca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448824802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_byte_transfer.1448824802
Directory /workspace/5.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3983135456
Short name T1384
Test name
Test status
Simulation time 10395337873 ps
CPU time 4.71 seconds
Started Jan 03 01:51:23 PM PST 24
Finished Jan 03 01:51:41 PM PST 24
Peak memory 241308 kb
Host smart-d6261637-c48d-4301-8cd5-c08d81b68b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983135456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3983135456
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3398341855
Short name T1740
Test name
Test status
Simulation time 136577554 ps
CPU time 0.75 seconds
Started Jan 03 01:51:23 PM PST 24
Finished Jan 03 01:51:37 PM PST 24
Peak memory 207552 kb
Host smart-4a9eb42d-6721-4b96-beb3-32084904e02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398341855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3398341855
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_dummy_item_extra_dly.272448018
Short name T1779
Test name
Test status
Simulation time 54684200543 ps
CPU time 1278.46 seconds
Started Jan 03 01:51:28 PM PST 24
Finished Jan 03 02:13:08 PM PST 24
Peak memory 250788 kb
Host smart-9ed06910-9c95-45b4-8227-6d5d2c5a8b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272448018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_dummy_item_extra_dly.272448018
Directory /workspace/5.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/5.spi_device_extreme_fifo_size.3507000053
Short name T826
Test name
Test status
Simulation time 2937402916 ps
CPU time 21.27 seconds
Started Jan 03 01:51:20 PM PST 24
Finished Jan 03 01:51:51 PM PST 24
Peak memory 241024 kb
Host smart-82867a44-129a-42c2-b497-e9a8220e79d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507000053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_extreme_fifo_size.3507000053
Directory /workspace/5.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/5.spi_device_fifo_full.1739502210
Short name T1207
Test name
Test status
Simulation time 44330279577 ps
CPU time 860.19 seconds
Started Jan 03 01:51:26 PM PST 24
Finished Jan 03 02:06:05 PM PST 24
Peak memory 257884 kb
Host smart-fed3b002-96f6-46c7-a832-de4be651fad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739502210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_fifo_full.1739502210
Directory /workspace/5.spi_device_fifo_full/latest

Test location /workspace/coverage/default/5.spi_device_fifo_underflow_overflow.2469144669
Short name T853
Test name
Test status
Simulation time 742813915008 ps
CPU time 1695.15 seconds
Started Jan 03 01:51:20 PM PST 24
Finished Jan 03 02:19:45 PM PST 24
Peak memory 855184 kb
Host smart-ed0a88cc-3fc4-444e-b9b6-17fa06936125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469144669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_fifo_underflow_overfl
ow.2469144669
Directory /workspace/5.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2556702658
Short name T361
Test name
Test status
Simulation time 23211678862 ps
CPU time 151.39 seconds
Started Jan 03 01:51:25 PM PST 24
Finished Jan 03 01:54:12 PM PST 24
Peak memory 266752 kb
Host smart-a4fe21ed-bb5c-480a-8de9-e539be4e6aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556702658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2556702658
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4168431642
Short name T975
Test name
Test status
Simulation time 79389845910 ps
CPU time 118.06 seconds
Started Jan 03 01:51:23 PM PST 24
Finished Jan 03 01:53:34 PM PST 24
Peak memory 239920 kb
Host smart-fc888510-9303-41ae-9899-ba67462506ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168431642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.4168431642
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3761186554
Short name T1699
Test name
Test status
Simulation time 15948068314 ps
CPU time 35.48 seconds
Started Jan 03 01:51:28 PM PST 24
Finished Jan 03 01:52:24 PM PST 24
Peak memory 256728 kb
Host smart-e533c094-3dc2-4e48-859c-10b14bee0895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761186554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3761186554
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.103775381
Short name T312
Test name
Test status
Simulation time 186073941 ps
CPU time 3.34 seconds
Started Jan 03 01:51:20 PM PST 24
Finished Jan 03 01:51:33 PM PST 24
Peak memory 240488 kb
Host smart-63f0998b-8d91-4467-948b-48ec6a72ab5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103775381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.103775381
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_intr.2304231569
Short name T795
Test name
Test status
Simulation time 15087670347 ps
CPU time 68.51 seconds
Started Jan 03 01:51:21 PM PST 24
Finished Jan 03 01:52:40 PM PST 24
Peak memory 233444 kb
Host smart-06dad584-6b7c-4d6b-aef9-ae6b91e78876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304231569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intr.2304231569
Directory /workspace/5.spi_device_intr/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.655301318
Short name T261
Test name
Test status
Simulation time 2938097122 ps
CPU time 12.04 seconds
Started Jan 03 01:51:27 PM PST 24
Finished Jan 03 01:51:59 PM PST 24
Peak memory 246968 kb
Host smart-b53ab2ee-bd67-4a78-bd8b-c8e04e8d8c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655301318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.655301318
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.4244331566
Short name T1524
Test name
Test status
Simulation time 165219113 ps
CPU time 1.11 seconds
Started Jan 03 01:51:29 PM PST 24
Finished Jan 03 01:51:51 PM PST 24
Peak memory 218888 kb
Host smart-8bc6927e-6a01-4445-a6b6-201de3bc14aa
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244331566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.4244331566
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1874274092
Short name T1075
Test name
Test status
Simulation time 82552295 ps
CPU time 3.22 seconds
Started Jan 03 01:51:22 PM PST 24
Finished Jan 03 01:51:37 PM PST 24
Peak memory 238348 kb
Host smart-79e0d4c2-cf67-45dd-9a4d-8e8a8143799c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874274092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1874274092
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2864716980
Short name T292
Test name
Test status
Simulation time 10077207910 ps
CPU time 26.04 seconds
Started Jan 03 01:51:21 PM PST 24
Finished Jan 03 01:51:57 PM PST 24
Peak memory 219472 kb
Host smart-326800f3-c21b-447d-9999-7b431e81fecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864716980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2864716980
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_perf.4215056713
Short name T825
Test name
Test status
Simulation time 7656641864 ps
CPU time 259.03 seconds
Started Jan 03 01:51:24 PM PST 24
Finished Jan 03 01:55:57 PM PST 24
Peak memory 301388 kb
Host smart-5feb91c4-4ae3-44ab-8159-79df21edb06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215056713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_perf.4215056713
Directory /workspace/5.spi_device_perf/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.2661023270
Short name T1145
Test name
Test status
Simulation time 14163936 ps
CPU time 0.72 seconds
Started Jan 03 01:51:21 PM PST 24
Finished Jan 03 01:51:32 PM PST 24
Peak memory 216708 kb
Host smart-bbfb37a0-e9fa-4c95-8722-886db049c1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661023270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.2661023270
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1226499139
Short name T683
Test name
Test status
Simulation time 6202006995 ps
CPU time 7.81 seconds
Started Jan 03 01:51:31 PM PST 24
Finished Jan 03 01:52:01 PM PST 24
Peak memory 234748 kb
Host smart-5a699523-275b-4832-9521-fe23e7aba962
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1226499139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1226499139
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_rx_async_fifo_reset.2183020474
Short name T1516
Test name
Test status
Simulation time 51092905 ps
CPU time 0.94 seconds
Started Jan 03 01:51:21 PM PST 24
Finished Jan 03 01:51:32 PM PST 24
Peak memory 208616 kb
Host smart-ab0f93da-251a-4ac5-97cb-3c36baeb6ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183020474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_rx_async_fifo_reset.2183020474
Directory /workspace/5.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/5.spi_device_rx_timeout.2957929992
Short name T564
Test name
Test status
Simulation time 1720805317 ps
CPU time 4.53 seconds
Started Jan 03 01:51:21 PM PST 24
Finished Jan 03 01:51:36 PM PST 24
Peak memory 216804 kb
Host smart-44f983bd-0858-4f4b-b51a-bcc60a856c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957929992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_rx_timeout.2957929992
Directory /workspace/5.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/5.spi_device_smoke.2176032229
Short name T735
Test name
Test status
Simulation time 94043133 ps
CPU time 1.06 seconds
Started Jan 03 01:51:24 PM PST 24
Finished Jan 03 01:51:41 PM PST 24
Peak memory 208336 kb
Host smart-9f9fcf4e-f1cf-41e5-87be-5216794fdb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176032229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_smoke.2176032229
Directory /workspace/5.spi_device_smoke/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2019981573
Short name T1710
Test name
Test status
Simulation time 10363823911 ps
CPU time 41.55 seconds
Started Jan 03 01:51:26 PM PST 24
Finished Jan 03 01:52:27 PM PST 24
Peak memory 217212 kb
Host smart-0ee51879-9701-4db2-8cd3-b04cd538f148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019981573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2019981573
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.647007978
Short name T724
Test name
Test status
Simulation time 8850782991 ps
CPU time 17.25 seconds
Started Jan 03 01:51:25 PM PST 24
Finished Jan 03 01:51:58 PM PST 24
Peak memory 216916 kb
Host smart-2023dd1b-e54b-4f88-8713-9149921104b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647007978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.647007978
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3837029584
Short name T1141
Test name
Test status
Simulation time 424758898 ps
CPU time 3.72 seconds
Started Jan 03 01:51:21 PM PST 24
Finished Jan 03 01:51:35 PM PST 24
Peak memory 216804 kb
Host smart-ee4d40d8-8406-42f1-b0c9-7acca0267d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837029584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3837029584
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1936896708
Short name T1691
Test name
Test status
Simulation time 546452089 ps
CPU time 1.11 seconds
Started Jan 03 01:51:23 PM PST 24
Finished Jan 03 01:51:37 PM PST 24
Peak memory 208076 kb
Host smart-4ab1bbac-6414-4000-810d-010b579d7386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936896708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1936896708
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_tx_async_fifo_reset.132293834
Short name T153
Test name
Test status
Simulation time 48881723 ps
CPU time 0.75 seconds
Started Jan 03 01:51:21 PM PST 24
Finished Jan 03 01:51:33 PM PST 24
Peak memory 208428 kb
Host smart-24341987-2319-4ed0-bade-462f45cfd908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132293834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tx_async_fifo_reset.132293834
Directory /workspace/5.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/5.spi_device_txrx.808235947
Short name T556
Test name
Test status
Simulation time 11832710877 ps
CPU time 41.6 seconds
Started Jan 03 01:51:06 PM PST 24
Finished Jan 03 01:51:55 PM PST 24
Peak memory 240680 kb
Host smart-1ee68c45-f8b0-41c6-8dc7-3423ae474749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808235947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_txrx.808235947
Directory /workspace/5.spi_device_txrx/latest

Test location /workspace/coverage/default/5.spi_device_upload.2190121328
Short name T1185
Test name
Test status
Simulation time 10212969548 ps
CPU time 13.41 seconds
Started Jan 03 01:51:25 PM PST 24
Finished Jan 03 01:51:56 PM PST 24
Peak memory 248056 kb
Host smart-d656afb2-0aa8-4478-a17e-ff606e4d30f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190121328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2190121328
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_abort.3186119061
Short name T1510
Test name
Test status
Simulation time 79615141 ps
CPU time 0.73 seconds
Started Jan 03 01:51:20 PM PST 24
Finished Jan 03 01:51:30 PM PST 24
Peak memory 206600 kb
Host smart-94476049-0c7c-4f1d-9a98-5c64a159aeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186119061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_abort.3186119061
Directory /workspace/6.spi_device_abort/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1820084193
Short name T93
Test name
Test status
Simulation time 41557353 ps
CPU time 0.71 seconds
Started Jan 03 01:51:52 PM PST 24
Finished Jan 03 01:52:07 PM PST 24
Peak memory 206500 kb
Host smart-c825a9a0-4ae3-4951-a94d-a0b0de7679e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820084193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
820084193
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_bit_transfer.1864577815
Short name T1632
Test name
Test status
Simulation time 124110662 ps
CPU time 1.92 seconds
Started Jan 03 01:51:20 PM PST 24
Finished Jan 03 01:51:32 PM PST 24
Peak memory 216780 kb
Host smart-ef32f8ca-5b2e-4c52-b7a6-32995a0beeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864577815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_bit_transfer.1864577815
Directory /workspace/6.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/6.spi_device_byte_transfer.3218654783
Short name T959
Test name
Test status
Simulation time 230576703 ps
CPU time 2.63 seconds
Started Jan 03 01:51:27 PM PST 24
Finished Jan 03 01:51:50 PM PST 24
Peak memory 216892 kb
Host smart-59a24007-6bcc-47f8-a68e-a7db1d7a7894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218654783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_byte_transfer.3218654783
Directory /workspace/6.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2156728121
Short name T4
Test name
Test status
Simulation time 881087721 ps
CPU time 4.71 seconds
Started Jan 03 01:51:52 PM PST 24
Finished Jan 03 01:52:10 PM PST 24
Peak memory 219248 kb
Host smart-93a12956-6ba8-41c9-95a4-7a8761f238ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156728121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2156728121
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2440553927
Short name T1561
Test name
Test status
Simulation time 23265408 ps
CPU time 0.74 seconds
Started Jan 03 01:51:24 PM PST 24
Finished Jan 03 01:51:39 PM PST 24
Peak memory 206500 kb
Host smart-dc39a51c-c3f9-44d1-a2eb-3e941e4e6130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440553927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2440553927
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_dummy_item_extra_dly.1763362402
Short name T1556
Test name
Test status
Simulation time 61789189421 ps
CPU time 589.85 seconds
Started Jan 03 01:51:20 PM PST 24
Finished Jan 03 02:01:20 PM PST 24
Peak memory 273808 kb
Host smart-3f776dca-6a8d-428e-9d78-6db730944fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763362402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_dummy_item_extra_dly.1763362402
Directory /workspace/6.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/6.spi_device_extreme_fifo_size.2308946693
Short name T1478
Test name
Test status
Simulation time 377129694954 ps
CPU time 1185.74 seconds
Started Jan 03 01:51:20 PM PST 24
Finished Jan 03 02:11:15 PM PST 24
Peak memory 223032 kb
Host smart-6527d436-dfc9-4995-8f3c-f09969a6db13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308946693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_extreme_fifo_size.2308946693
Directory /workspace/6.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/6.spi_device_fifo_full.2414716499
Short name T781
Test name
Test status
Simulation time 38114102064 ps
CPU time 381.49 seconds
Started Jan 03 01:51:28 PM PST 24
Finished Jan 03 01:58:10 PM PST 24
Peak memory 302764 kb
Host smart-89026bb5-9365-4bf7-ba9a-191c2721aa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414716499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_fifo_full.2414716499
Directory /workspace/6.spi_device_fifo_full/latest

Test location /workspace/coverage/default/6.spi_device_fifo_underflow_overflow.2015363546
Short name T732
Test name
Test status
Simulation time 147627908293 ps
CPU time 411.76 seconds
Started Jan 03 01:51:28 PM PST 24
Finished Jan 03 01:58:41 PM PST 24
Peak memory 406584 kb
Host smart-fb86cfdd-f240-43bd-a1c0-d27de78ae532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015363546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_fifo_underflow_overfl
ow.2015363546
Directory /workspace/6.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2349578101
Short name T329
Test name
Test status
Simulation time 126787144042 ps
CPU time 298.66 seconds
Started Jan 03 01:51:49 PM PST 24
Finished Jan 03 01:57:02 PM PST 24
Peak memory 255172 kb
Host smart-468e9d50-6d28-4c64-82ba-f9ad1e7c2fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349578101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2349578101
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2954442264
Short name T290
Test name
Test status
Simulation time 22114162336 ps
CPU time 141.91 seconds
Started Jan 03 01:51:49 PM PST 24
Finished Jan 03 01:54:26 PM PST 24
Peak memory 254608 kb
Host smart-d6dbb551-5afe-46a4-96dd-1cb26fc72006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954442264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2954442264
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1166583172
Short name T1582
Test name
Test status
Simulation time 29272972205 ps
CPU time 211.11 seconds
Started Jan 03 01:52:09 PM PST 24
Finished Jan 03 01:55:50 PM PST 24
Peak memory 260752 kb
Host smart-ebd4ef7d-5327-4831-bbac-05faff9e1bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166583172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1166583172
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2065517954
Short name T1657
Test name
Test status
Simulation time 2281776547 ps
CPU time 12.05 seconds
Started Jan 03 01:51:53 PM PST 24
Finished Jan 03 01:52:18 PM PST 24
Peak memory 247400 kb
Host smart-8a4905b3-eea3-4c5c-8950-be8185782c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065517954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2065517954
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1609488245
Short name T278
Test name
Test status
Simulation time 1466627473 ps
CPU time 6.16 seconds
Started Jan 03 01:51:30 PM PST 24
Finished Jan 03 01:51:58 PM PST 24
Peak memory 241208 kb
Host smart-2510de8b-743f-439d-b325-2da9859ea11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609488245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1609488245
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_intr.2006751795
Short name T1706
Test name
Test status
Simulation time 24091229566 ps
CPU time 56.98 seconds
Started Jan 03 01:51:29 PM PST 24
Finished Jan 03 01:52:48 PM PST 24
Peak memory 224168 kb
Host smart-a390661a-7085-4f31-87da-6876905f54b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006751795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intr.2006751795
Directory /workspace/6.spi_device_intr/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1884876408
Short name T1772
Test name
Test status
Simulation time 7786729790 ps
CPU time 5.69 seconds
Started Jan 03 01:51:26 PM PST 24
Finished Jan 03 01:51:50 PM PST 24
Peak memory 223108 kb
Host smart-22dfccd5-3398-4507-9229-07f290d95b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884876408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1884876408
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.633891836
Short name T1078
Test name
Test status
Simulation time 28041619 ps
CPU time 1.07 seconds
Started Jan 03 01:51:25 PM PST 24
Finished Jan 03 01:51:42 PM PST 24
Peak memory 218832 kb
Host smart-1a617992-ecba-41ea-a644-b7d00f88fe89
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633891836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.633891836
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3893153687
Short name T293
Test name
Test status
Simulation time 3207719619 ps
CPU time 5.12 seconds
Started Jan 03 01:51:21 PM PST 24
Finished Jan 03 01:51:37 PM PST 24
Peak memory 238392 kb
Host smart-96c1078d-ccf5-4490-8471-934413eac2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893153687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3893153687
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.606558937
Short name T253
Test name
Test status
Simulation time 1761657663 ps
CPU time 7.67 seconds
Started Jan 03 01:51:20 PM PST 24
Finished Jan 03 01:51:36 PM PST 24
Peak memory 233316 kb
Host smart-3408f1d5-25c0-4441-9acf-98fb1e9bd40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606558937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.606558937
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_perf.4064949519
Short name T1700
Test name
Test status
Simulation time 19405645659 ps
CPU time 1242.46 seconds
Started Jan 03 01:51:30 PM PST 24
Finished Jan 03 02:12:35 PM PST 24
Peak memory 282512 kb
Host smart-2929c7e6-5abd-4b12-8834-4c6821e8f169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064949519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_perf.4064949519
Directory /workspace/6.spi_device_perf/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.2034283335
Short name T1264
Test name
Test status
Simulation time 22274130 ps
CPU time 0.72 seconds
Started Jan 03 01:51:25 PM PST 24
Finished Jan 03 01:51:43 PM PST 24
Peak memory 216708 kb
Host smart-757010bc-3073-4500-ae59-c90c3995bb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034283335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.2034283335
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2774390842
Short name T1456
Test name
Test status
Simulation time 5351812757 ps
CPU time 6.08 seconds
Started Jan 03 01:51:50 PM PST 24
Finished Jan 03 01:52:10 PM PST 24
Peak memory 234652 kb
Host smart-f406eb98-eb22-4a1b-96a1-4d23cf31b118
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2774390842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2774390842
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_rx_async_fifo_reset.3072371344
Short name T144
Test name
Test status
Simulation time 25915229 ps
CPU time 0.89 seconds
Started Jan 03 01:51:23 PM PST 24
Finished Jan 03 01:51:38 PM PST 24
Peak memory 208532 kb
Host smart-5d9a4293-176b-4002-85c3-9c3269d45de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072371344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_rx_async_fifo_reset.3072371344
Directory /workspace/6.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/6.spi_device_rx_timeout.4183856831
Short name T1317
Test name
Test status
Simulation time 594176248 ps
CPU time 5.86 seconds
Started Jan 03 01:51:28 PM PST 24
Finished Jan 03 01:51:56 PM PST 24
Peak memory 216884 kb
Host smart-9d402030-ef65-46e6-b7c6-6ad518ea6e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183856831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_rx_timeout.4183856831
Directory /workspace/6.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/6.spi_device_smoke.1597015099
Short name T33
Test name
Test status
Simulation time 48524802 ps
CPU time 0.93 seconds
Started Jan 03 01:51:22 PM PST 24
Finished Jan 03 01:51:34 PM PST 24
Peak memory 207864 kb
Host smart-3dcc6a88-435a-40e3-a8e4-579a0b718337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597015099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_smoke.1597015099
Directory /workspace/6.spi_device_smoke/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1731666072
Short name T1066
Test name
Test status
Simulation time 9599142000 ps
CPU time 75.03 seconds
Started Jan 03 01:51:31 PM PST 24
Finished Jan 03 01:53:08 PM PST 24
Peak memory 216932 kb
Host smart-9c7b6ba6-acfb-42e0-b70d-b0ae7470e720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731666072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1731666072
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.273895648
Short name T750
Test name
Test status
Simulation time 7001534376 ps
CPU time 23.95 seconds
Started Jan 03 01:51:25 PM PST 24
Finished Jan 03 01:52:06 PM PST 24
Peak memory 216924 kb
Host smart-f0de5500-c1cb-4054-89f9-c939af19b73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273895648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.273895648
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1406366415
Short name T655
Test name
Test status
Simulation time 103337295 ps
CPU time 0.85 seconds
Started Jan 03 01:51:29 PM PST 24
Finished Jan 03 01:51:51 PM PST 24
Peak memory 206880 kb
Host smart-5a9507ce-1a48-4311-9dc8-4b3f30e5ffac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406366415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1406366415
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3339182136
Short name T1508
Test name
Test status
Simulation time 152027762 ps
CPU time 0.83 seconds
Started Jan 03 01:51:21 PM PST 24
Finished Jan 03 01:51:32 PM PST 24
Peak memory 206924 kb
Host smart-d684082d-7422-4dbb-8bfc-72de59a7d510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339182136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3339182136
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_tx_async_fifo_reset.1873428890
Short name T850
Test name
Test status
Simulation time 15973658 ps
CPU time 0.77 seconds
Started Jan 03 01:51:24 PM PST 24
Finished Jan 03 01:51:39 PM PST 24
Peak memory 208392 kb
Host smart-e973e537-6229-4e53-9d94-01b8e41545b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873428890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tx_async_fifo_reset.1873428890
Directory /workspace/6.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/6.spi_device_txrx.736926955
Short name T303
Test name
Test status
Simulation time 33509992783 ps
CPU time 357.09 seconds
Started Jan 03 01:51:26 PM PST 24
Finished Jan 03 01:57:42 PM PST 24
Peak memory 300008 kb
Host smart-0394900e-d724-48d0-95c9-560f8c76a934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736926955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_txrx.736926955
Directory /workspace/6.spi_device_txrx/latest

Test location /workspace/coverage/default/6.spi_device_upload.3610216122
Short name T347
Test name
Test status
Simulation time 1218866181 ps
CPU time 5.35 seconds
Started Jan 03 01:51:48 PM PST 24
Finished Jan 03 01:52:08 PM PST 24
Peak memory 240336 kb
Host smart-e83c80ce-fdfc-4658-ae1b-4731b4222402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610216122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3610216122
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_abort.2277022449
Short name T1621
Test name
Test status
Simulation time 15360170 ps
CPU time 0.76 seconds
Started Jan 03 01:51:49 PM PST 24
Finished Jan 03 01:52:05 PM PST 24
Peak memory 206592 kb
Host smart-80e07f29-a234-49a1-98b7-1905d8b430b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277022449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_abort.2277022449
Directory /workspace/7.spi_device_abort/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3921865442
Short name T921
Test name
Test status
Simulation time 11367067 ps
CPU time 0.73 seconds
Started Jan 03 01:51:50 PM PST 24
Finished Jan 03 01:52:05 PM PST 24
Peak memory 206524 kb
Host smart-79dc15b8-f738-4a00-989e-bcfd965b8bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921865442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
921865442
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_bit_transfer.2119997435
Short name T1267
Test name
Test status
Simulation time 1611649409 ps
CPU time 2.39 seconds
Started Jan 03 01:51:53 PM PST 24
Finished Jan 03 01:52:09 PM PST 24
Peak memory 216824 kb
Host smart-cd087fe4-9ee7-41bf-944c-58d479d32c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119997435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_bit_transfer.2119997435
Directory /workspace/7.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/7.spi_device_byte_transfer.1677000506
Short name T1728
Test name
Test status
Simulation time 97322436 ps
CPU time 2.44 seconds
Started Jan 03 01:51:48 PM PST 24
Finished Jan 03 01:52:05 PM PST 24
Peak memory 216816 kb
Host smart-4b00fcb9-9a04-4639-9678-4fa0f0214d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677000506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_byte_transfer.1677000506
Directory /workspace/7.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2550152927
Short name T1598
Test name
Test status
Simulation time 18814205583 ps
CPU time 11.14 seconds
Started Jan 03 01:52:07 PM PST 24
Finished Jan 03 01:52:28 PM PST 24
Peak memory 240944 kb
Host smart-493a8061-0156-4e3a-b2bc-a999ae2abb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550152927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2550152927
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2683826862
Short name T526
Test name
Test status
Simulation time 50339520 ps
CPU time 0.76 seconds
Started Jan 03 01:51:52 PM PST 24
Finished Jan 03 01:52:07 PM PST 24
Peak memory 207580 kb
Host smart-a7056914-5bd2-4a1e-8e61-06117624dff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683826862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2683826862
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_dummy_item_extra_dly.3312047792
Short name T1281
Test name
Test status
Simulation time 72056724125 ps
CPU time 661.16 seconds
Started Jan 03 01:51:51 PM PST 24
Finished Jan 03 02:03:07 PM PST 24
Peak memory 294368 kb
Host smart-b25fe2aa-1c31-4c98-9ed9-eac3ebed8a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312047792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_dummy_item_extra_dly.3312047792
Directory /workspace/7.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/7.spi_device_extreme_fifo_size.989014038
Short name T1531
Test name
Test status
Simulation time 2628778572 ps
CPU time 29.21 seconds
Started Jan 03 01:51:49 PM PST 24
Finished Jan 03 01:52:33 PM PST 24
Peak memory 238080 kb
Host smart-a5b79c7a-ed0e-4fff-8426-3385d69d9bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989014038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_extreme_fifo_size.989014038
Directory /workspace/7.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/7.spi_device_fifo_full.928227504
Short name T1652
Test name
Test status
Simulation time 26085545124 ps
CPU time 588.36 seconds
Started Jan 03 01:51:50 PM PST 24
Finished Jan 03 02:01:53 PM PST 24
Peak memory 273708 kb
Host smart-dabb8b6d-1c0e-445c-a383-28a529a96eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928227504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_fifo_full.928227504
Directory /workspace/7.spi_device_fifo_full/latest

Test location /workspace/coverage/default/7.spi_device_fifo_underflow_overflow.3228839714
Short name T647
Test name
Test status
Simulation time 20239922620 ps
CPU time 138.05 seconds
Started Jan 03 01:51:49 PM PST 24
Finished Jan 03 01:54:22 PM PST 24
Peak memory 347772 kb
Host smart-a7c80222-6e6f-4000-9700-e5550a1596a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228839714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_fifo_underflow_overfl
ow.3228839714
Directory /workspace/7.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.579650255
Short name T369
Test name
Test status
Simulation time 10152962075 ps
CPU time 105.15 seconds
Started Jan 03 01:51:50 PM PST 24
Finished Jan 03 01:53:49 PM PST 24
Peak memory 270432 kb
Host smart-8d3bd437-f4b1-4b25-a0a9-3af20af245a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579650255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.579650255
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1725182513
Short name T277
Test name
Test status
Simulation time 83142182356 ps
CPU time 128.05 seconds
Started Jan 03 01:51:49 PM PST 24
Finished Jan 03 01:54:12 PM PST 24
Peak memory 241632 kb
Host smart-792cd38c-ed46-40ec-beeb-12fffe16ca19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725182513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1725182513
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.728160159
Short name T690
Test name
Test status
Simulation time 93755943270 ps
CPU time 344.82 seconds
Started Jan 03 01:51:49 PM PST 24
Finished Jan 03 01:57:49 PM PST 24
Peak memory 251436 kb
Host smart-3a05612b-2a3e-450c-8f85-a8f141c771bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728160159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
728160159
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2906247003
Short name T291
Test name
Test status
Simulation time 7844270748 ps
CPU time 48.07 seconds
Started Jan 03 01:51:48 PM PST 24
Finished Jan 03 01:52:51 PM PST 24
Peak memory 237132 kb
Host smart-f76fd466-9a52-4935-b1cf-54b5ee9dc719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906247003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2906247003
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.354835864
Short name T1217
Test name
Test status
Simulation time 2385001013 ps
CPU time 8.05 seconds
Started Jan 03 01:51:49 PM PST 24
Finished Jan 03 01:52:12 PM PST 24
Peak memory 239012 kb
Host smart-a59c59fe-dceb-4c9d-8545-5d7a79079fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354835864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.354835864
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_intr.139958533
Short name T627
Test name
Test status
Simulation time 103564312655 ps
CPU time 55.59 seconds
Started Jan 03 01:51:54 PM PST 24
Finished Jan 03 01:53:02 PM PST 24
Peak memory 241308 kb
Host smart-9af4542f-a8ce-45a3-a234-e201f8338371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139958533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intr.139958533
Directory /workspace/7.spi_device_intr/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1611964527
Short name T256
Test name
Test status
Simulation time 3337949838 ps
CPU time 14.39 seconds
Started Jan 03 01:51:49 PM PST 24
Finished Jan 03 01:52:18 PM PST 24
Peak memory 225084 kb
Host smart-de5e6ad5-1436-4cc7-8ee6-05f0e49e93b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611964527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1611964527
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.186609854
Short name T789
Test name
Test status
Simulation time 91463758 ps
CPU time 1.12 seconds
Started Jan 03 01:51:56 PM PST 24
Finished Jan 03 01:52:10 PM PST 24
Peak memory 218932 kb
Host smart-9d2752ee-eb51-44a2-95ab-938d7b053d79
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186609854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.186609854
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1372041411
Short name T339
Test name
Test status
Simulation time 533423269 ps
CPU time 9.08 seconds
Started Jan 03 01:51:52 PM PST 24
Finished Jan 03 01:52:15 PM PST 24
Peak memory 246528 kb
Host smart-7401f71b-68f1-4e78-a809-23c5025193c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372041411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1372041411
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.812954830
Short name T131
Test name
Test status
Simulation time 8211923167 ps
CPU time 23.35 seconds
Started Jan 03 01:51:49 PM PST 24
Finished Jan 03 01:52:27 PM PST 24
Peak memory 249484 kb
Host smart-276fb8d5-4408-44bd-854f-de311bcddfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812954830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.812954830
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_perf.594939807
Short name T741
Test name
Test status
Simulation time 17952405299 ps
CPU time 400.76 seconds
Started Jan 03 01:51:48 PM PST 24
Finished Jan 03 01:58:44 PM PST 24
Peak memory 241472 kb
Host smart-c173bd9e-d197-4254-bbcd-20d69cffb637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594939807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_perf.594939807
Directory /workspace/7.spi_device_perf/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.2023262047
Short name T637
Test name
Test status
Simulation time 18212381 ps
CPU time 0.74 seconds
Started Jan 03 01:51:47 PM PST 24
Finished Jan 03 01:52:04 PM PST 24
Peak memory 216652 kb
Host smart-e035bcb7-0ede-4770-866c-ebb2acda93a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023262047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.2023262047
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3541069133
Short name T146
Test name
Test status
Simulation time 179482214 ps
CPU time 3.25 seconds
Started Jan 03 01:51:49 PM PST 24
Finished Jan 03 01:52:07 PM PST 24
Peak memory 219260 kb
Host smart-d9416565-ce78-4d7e-8f11-ee96b84d32bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3541069133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3541069133
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_rx_async_fifo_reset.207785094
Short name T981
Test name
Test status
Simulation time 133071653 ps
CPU time 0.91 seconds
Started Jan 03 01:51:47 PM PST 24
Finished Jan 03 01:52:04 PM PST 24
Peak memory 208500 kb
Host smart-35c217ab-1f7a-484e-ade8-c3d381c5c55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207785094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_rx_async_fifo_reset.207785094
Directory /workspace/7.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/7.spi_device_rx_timeout.410764100
Short name T1625
Test name
Test status
Simulation time 4842183730 ps
CPU time 6.44 seconds
Started Jan 03 01:51:49 PM PST 24
Finished Jan 03 01:52:10 PM PST 24
Peak memory 216748 kb
Host smart-1c611850-56bb-4b29-ba40-1a401524ac10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410764100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_rx_timeout.410764100
Directory /workspace/7.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/7.spi_device_smoke.533156232
Short name T523
Test name
Test status
Simulation time 24174158 ps
CPU time 1.12 seconds
Started Jan 03 01:51:52 PM PST 24
Finished Jan 03 01:52:07 PM PST 24
Peak memory 216816 kb
Host smart-eed7e4b2-44c5-4f92-a3fa-3aa31f156d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533156232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_smoke.533156232
Directory /workspace/7.spi_device_smoke/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1683344324
Short name T185
Test name
Test status
Simulation time 154233791204 ps
CPU time 1780.36 seconds
Started Jan 03 01:51:48 PM PST 24
Finished Jan 03 02:21:44 PM PST 24
Peak memory 284676 kb
Host smart-2eba99d8-9ee0-46ce-961b-d8e70d459005
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683344324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1683344324
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3072723101
Short name T837
Test name
Test status
Simulation time 2136471217 ps
CPU time 8.61 seconds
Started Jan 03 01:51:48 PM PST 24
Finished Jan 03 01:52:12 PM PST 24
Peak memory 218708 kb
Host smart-f9676777-3124-4c37-b2c1-4cc45dade2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072723101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3072723101
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3845599797
Short name T550
Test name
Test status
Simulation time 8361639581 ps
CPU time 8.2 seconds
Started Jan 03 01:51:51 PM PST 24
Finished Jan 03 01:52:13 PM PST 24
Peak memory 216976 kb
Host smart-c8669576-0b1d-4191-9442-05933c0930b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845599797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3845599797
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.780670021
Short name T691
Test name
Test status
Simulation time 89738857 ps
CPU time 1.25 seconds
Started Jan 03 01:51:52 PM PST 24
Finished Jan 03 01:52:07 PM PST 24
Peak memory 208580 kb
Host smart-3e2ad05a-346a-4087-8500-66da6523a4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780670021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.780670021
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4067070788
Short name T884
Test name
Test status
Simulation time 257697727 ps
CPU time 0.97 seconds
Started Jan 03 01:51:50 PM PST 24
Finished Jan 03 01:52:05 PM PST 24
Peak memory 206852 kb
Host smart-c0fa770e-7ab7-456c-96d4-28c5605888bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067070788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4067070788
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_tx_async_fifo_reset.4156985215
Short name T1481
Test name
Test status
Simulation time 17964135 ps
CPU time 0.88 seconds
Started Jan 03 01:51:48 PM PST 24
Finished Jan 03 01:52:04 PM PST 24
Peak memory 208352 kb
Host smart-ce88eb9e-67d1-4dd9-8a03-cac33a3f70b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156985215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tx_async_fifo_reset.4156985215
Directory /workspace/7.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/7.spi_device_txrx.757651899
Short name T1732
Test name
Test status
Simulation time 40715088595 ps
CPU time 425.57 seconds
Started Jan 03 01:51:50 PM PST 24
Finished Jan 03 01:59:10 PM PST 24
Peak memory 303428 kb
Host smart-2b321632-530d-4cb2-a629-a8b52f359451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757651899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_txrx.757651899
Directory /workspace/7.spi_device_txrx/latest

Test location /workspace/coverage/default/7.spi_device_upload.3599729383
Short name T1221
Test name
Test status
Simulation time 28594769804 ps
CPU time 10.27 seconds
Started Jan 03 01:52:07 PM PST 24
Finished Jan 03 01:52:28 PM PST 24
Peak memory 220412 kb
Host smart-7e11ae38-9678-450b-a8d8-7a6e32be350b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599729383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3599729383
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_abort.3926083350
Short name T1279
Test name
Test status
Simulation time 49383074 ps
CPU time 0.76 seconds
Started Jan 03 01:52:09 PM PST 24
Finished Jan 03 01:52:19 PM PST 24
Peak memory 206684 kb
Host smart-633ee340-32d5-4360-82db-1e4eaac8d2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926083350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_abort.3926083350
Directory /workspace/8.spi_device_abort/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1499077847
Short name T819
Test name
Test status
Simulation time 23772160 ps
CPU time 0.73 seconds
Started Jan 03 01:52:29 PM PST 24
Finished Jan 03 01:52:37 PM PST 24
Peak memory 206488 kb
Host smart-da4a2a63-0205-48ae-836b-c96351df32de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499077847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
499077847
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_bit_transfer.2757869538
Short name T654
Test name
Test status
Simulation time 541103537 ps
CPU time 2.7 seconds
Started Jan 03 01:52:07 PM PST 24
Finished Jan 03 01:52:20 PM PST 24
Peak memory 216724 kb
Host smart-3bb4b98f-8e0b-47bc-b948-32c7d716a046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757869538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_bit_transfer.2757869538
Directory /workspace/8.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/8.spi_device_byte_transfer.2042202644
Short name T805
Test name
Test status
Simulation time 214065174 ps
CPU time 2.65 seconds
Started Jan 03 01:52:08 PM PST 24
Finished Jan 03 01:52:20 PM PST 24
Peak memory 216832 kb
Host smart-07b8b24f-9a5a-4f7f-8468-0830f385d13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042202644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_byte_transfer.2042202644
Directory /workspace/8.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3623445648
Short name T148
Test name
Test status
Simulation time 8873401909 ps
CPU time 9.4 seconds
Started Jan 03 01:52:09 PM PST 24
Finished Jan 03 01:52:28 PM PST 24
Peak memory 225156 kb
Host smart-69983e4d-25f1-4a8b-a905-1e13de1af3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623445648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3623445648
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.90305130
Short name T893
Test name
Test status
Simulation time 42798171 ps
CPU time 0.75 seconds
Started Jan 03 01:51:48 PM PST 24
Finished Jan 03 01:52:04 PM PST 24
Peak memory 206580 kb
Host smart-b6b0e065-253d-45f0-9b24-d11c57dd5f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90305130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.90305130
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_dummy_item_extra_dly.3519007642
Short name T700
Test name
Test status
Simulation time 144522065541 ps
CPU time 239.77 seconds
Started Jan 03 01:51:49 PM PST 24
Finished Jan 03 01:56:03 PM PST 24
Peak memory 266160 kb
Host smart-516e01cf-4dc5-4e1c-bbee-adb2ce44ea8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519007642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_dummy_item_extra_dly.3519007642
Directory /workspace/8.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/8.spi_device_extreme_fifo_size.3254530344
Short name T299
Test name
Test status
Simulation time 8647956016 ps
CPU time 27.49 seconds
Started Jan 03 01:51:49 PM PST 24
Finished Jan 03 01:52:31 PM PST 24
Peak memory 235416 kb
Host smart-23594523-4076-4fe9-9613-1ea316db0f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254530344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_extreme_fifo_size.3254530344
Directory /workspace/8.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/8.spi_device_fifo_full.652046560
Short name T698
Test name
Test status
Simulation time 137611163580 ps
CPU time 321.08 seconds
Started Jan 03 01:51:49 PM PST 24
Finished Jan 03 01:57:25 PM PST 24
Peak memory 273276 kb
Host smart-5f7284ce-24bb-4f5d-896b-72f73ac2c81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652046560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_fifo_full.652046560
Directory /workspace/8.spi_device_fifo_full/latest

Test location /workspace/coverage/default/8.spi_device_fifo_underflow_overflow.4119239168
Short name T52
Test name
Test status
Simulation time 230427909894 ps
CPU time 1145.76 seconds
Started Jan 03 01:51:48 PM PST 24
Finished Jan 03 02:11:09 PM PST 24
Peak memory 533384 kb
Host smart-8e811fb0-91c4-4883-820f-816e9dbfc805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119239168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_fifo_underflow_overfl
ow.4119239168
Directory /workspace/8.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1592495076
Short name T969
Test name
Test status
Simulation time 511344267486 ps
CPU time 206.91 seconds
Started Jan 03 01:52:29 PM PST 24
Finished Jan 03 01:56:03 PM PST 24
Peak memory 252472 kb
Host smart-34228c22-fc2e-494f-8df2-0332182c3d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592495076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1592495076
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1674769402
Short name T1229
Test name
Test status
Simulation time 23089842699 ps
CPU time 33.7 seconds
Started Jan 03 01:52:10 PM PST 24
Finished Jan 03 01:52:53 PM PST 24
Peak memory 241628 kb
Host smart-1da5ed23-db66-4afa-80eb-dcb0dd940c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674769402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1674769402
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.158591701
Short name T964
Test name
Test status
Simulation time 2606557976 ps
CPU time 6.62 seconds
Started Jan 03 01:52:27 PM PST 24
Finished Jan 03 01:52:42 PM PST 24
Peak memory 220416 kb
Host smart-ce3c9459-5ed8-4ce0-a20d-f9d0787d5f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158591701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.158591701
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_intr.2124644536
Short name T803
Test name
Test status
Simulation time 3328787991 ps
CPU time 16.61 seconds
Started Jan 03 01:52:08 PM PST 24
Finished Jan 03 01:52:34 PM PST 24
Peak memory 218436 kb
Host smart-6ef90e30-ac60-4411-8730-c1a0ae9eb159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124644536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intr.2124644536
Directory /workspace/8.spi_device_intr/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1255842757
Short name T1261
Test name
Test status
Simulation time 2163202688 ps
CPU time 10.08 seconds
Started Jan 03 01:52:10 PM PST 24
Finished Jan 03 01:52:29 PM PST 24
Peak memory 244868 kb
Host smart-f1c8d754-0353-4557-b86a-48bbe334b270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255842757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1255842757
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2111667679
Short name T1355
Test name
Test status
Simulation time 26526966 ps
CPU time 1.09 seconds
Started Jan 03 01:52:05 PM PST 24
Finished Jan 03 01:52:17 PM PST 24
Peak memory 218904 kb
Host smart-dc7eac33-d31b-4543-8ec7-626ef70eb8e2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111667679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2111667679
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.525504573
Short name T367
Test name
Test status
Simulation time 444379359 ps
CPU time 2.96 seconds
Started Jan 03 01:52:10 PM PST 24
Finished Jan 03 01:52:22 PM PST 24
Peak memory 218500 kb
Host smart-36e3347e-4f90-4370-8efd-ae6bf82691ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525504573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
525504573
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2818124650
Short name T316
Test name
Test status
Simulation time 7202148417 ps
CPU time 22.36 seconds
Started Jan 03 01:52:08 PM PST 24
Finished Jan 03 01:52:40 PM PST 24
Peak memory 239204 kb
Host smart-c6a42b81-637e-4927-9fc8-6d5c7589722b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818124650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2818124650
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_perf.2983037552
Short name T522
Test name
Test status
Simulation time 556414491086 ps
CPU time 904.59 seconds
Started Jan 03 01:52:09 PM PST 24
Finished Jan 03 02:07:23 PM PST 24
Peak memory 257544 kb
Host smart-28665493-937d-43e3-98f5-b4d69672eeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983037552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_perf.2983037552
Directory /workspace/8.spi_device_perf/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.3702095971
Short name T1619
Test name
Test status
Simulation time 50019267 ps
CPU time 0.73 seconds
Started Jan 03 01:52:08 PM PST 24
Finished Jan 03 01:52:19 PM PST 24
Peak memory 216684 kb
Host smart-e5e425a6-467a-4058-a0ea-3489de1a46b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702095971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.3702095971
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2731859106
Short name T1046
Test name
Test status
Simulation time 1453887395 ps
CPU time 4.49 seconds
Started Jan 03 01:52:12 PM PST 24
Finished Jan 03 01:52:25 PM PST 24
Peak memory 221280 kb
Host smart-06610ed1-b88b-4f4b-94e6-bb154d6ef245
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2731859106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2731859106
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_rx_async_fifo_reset.3765947491
Short name T1086
Test name
Test status
Simulation time 183476559 ps
CPU time 0.84 seconds
Started Jan 03 01:52:10 PM PST 24
Finished Jan 03 01:52:20 PM PST 24
Peak memory 208488 kb
Host smart-910855c8-19d3-4f02-8f1d-cc2078bbf0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765947491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_rx_async_fifo_reset.3765947491
Directory /workspace/8.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/8.spi_device_rx_timeout.2440573514
Short name T1668
Test name
Test status
Simulation time 2707797169 ps
CPU time 6.54 seconds
Started Jan 03 01:52:08 PM PST 24
Finished Jan 03 01:52:25 PM PST 24
Peak memory 216744 kb
Host smart-cc280d22-0342-4165-a2f3-620c89b8dd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440573514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_rx_timeout.2440573514
Directory /workspace/8.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/8.spi_device_smoke.2663021449
Short name T1336
Test name
Test status
Simulation time 199653052 ps
CPU time 1.14 seconds
Started Jan 03 01:51:49 PM PST 24
Finished Jan 03 01:52:05 PM PST 24
Peak memory 216560 kb
Host smart-5e2260b0-3b83-4193-8b03-dc543c2502bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663021449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_smoke.2663021449
Directory /workspace/8.spi_device_smoke/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3253811613
Short name T149
Test name
Test status
Simulation time 42864431814 ps
CPU time 535.14 seconds
Started Jan 03 01:52:11 PM PST 24
Finished Jan 03 02:01:15 PM PST 24
Peak memory 285320 kb
Host smart-2145b125-d3f5-43fd-8a1e-7dddb1f36c3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253811613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3253811613
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.4271104354
Short name T1227
Test name
Test status
Simulation time 1804990435 ps
CPU time 18.27 seconds
Started Jan 03 01:52:06 PM PST 24
Finished Jan 03 01:52:34 PM PST 24
Peak memory 220048 kb
Host smart-33bc2864-1bb0-4565-b8c4-a36443aae646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271104354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.4271104354
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3787205637
Short name T1503
Test name
Test status
Simulation time 13630566908 ps
CPU time 12.47 seconds
Started Jan 03 01:52:08 PM PST 24
Finished Jan 03 01:52:30 PM PST 24
Peak memory 218992 kb
Host smart-efaa195e-f99d-4ccc-ad55-5680c3c1a6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787205637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3787205637
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1514587584
Short name T1337
Test name
Test status
Simulation time 369684329 ps
CPU time 1.41 seconds
Started Jan 03 01:52:09 PM PST 24
Finished Jan 03 01:52:20 PM PST 24
Peak memory 216888 kb
Host smart-5968c9af-a74e-4f6c-9e56-926b3a01a30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514587584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1514587584
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.4271779064
Short name T1716
Test name
Test status
Simulation time 50281681 ps
CPU time 0.75 seconds
Started Jan 03 01:52:10 PM PST 24
Finished Jan 03 01:52:20 PM PST 24
Peak memory 206952 kb
Host smart-dd655854-49a9-4dee-8033-d3cedf4d0908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271779064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.4271779064
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_tx_async_fifo_reset.147583798
Short name T1587
Test name
Test status
Simulation time 47994521 ps
CPU time 0.77 seconds
Started Jan 03 01:52:07 PM PST 24
Finished Jan 03 01:52:18 PM PST 24
Peak memory 208440 kb
Host smart-9b35abb0-6e39-4b9b-be99-f9ded8449719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147583798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tx_async_fifo_reset.147583798
Directory /workspace/8.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/8.spi_device_txrx.2391482555
Short name T855
Test name
Test status
Simulation time 66171452882 ps
CPU time 471.25 seconds
Started Jan 03 01:51:56 PM PST 24
Finished Jan 03 02:00:01 PM PST 24
Peak memory 284432 kb
Host smart-246b66f7-5b02-4b3a-aa6a-30b5dda4ea35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391482555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_txrx.2391482555
Directory /workspace/8.spi_device_txrx/latest

Test location /workspace/coverage/default/8.spi_device_upload.1865004831
Short name T1725
Test name
Test status
Simulation time 6748315782 ps
CPU time 15.71 seconds
Started Jan 03 01:52:09 PM PST 24
Finished Jan 03 01:52:34 PM PST 24
Peak memory 234400 kb
Host smart-03e08600-e7c9-47fa-8ef5-6588c4f292a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865004831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1865004831
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_abort.3971156964
Short name T1775
Test name
Test status
Simulation time 16537462 ps
CPU time 0.74 seconds
Started Jan 03 01:54:37 PM PST 24
Finished Jan 03 01:54:42 PM PST 24
Peak memory 206640 kb
Host smart-66dd1da0-35b1-4a0a-a9dd-8b2f30ba80e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971156964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_abort.3971156964
Directory /workspace/9.spi_device_abort/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2701864618
Short name T665
Test name
Test status
Simulation time 45234957 ps
CPU time 0.76 seconds
Started Jan 03 01:54:38 PM PST 24
Finished Jan 03 01:54:45 PM PST 24
Peak memory 206520 kb
Host smart-43b591f7-1c28-42f6-9ec5-87aeae761960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701864618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
701864618
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_bit_transfer.1452099891
Short name T221
Test name
Test status
Simulation time 183006140 ps
CPU time 2.22 seconds
Started Jan 03 01:54:36 PM PST 24
Finished Jan 03 01:54:44 PM PST 24
Peak memory 216804 kb
Host smart-12128a44-2683-4ffb-9e88-f8a388a2f44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452099891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_bit_transfer.1452099891
Directory /workspace/9.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/9.spi_device_byte_transfer.860937294
Short name T34
Test name
Test status
Simulation time 391977018 ps
CPU time 2.46 seconds
Started Jan 03 01:54:37 PM PST 24
Finished Jan 03 01:54:44 PM PST 24
Peak memory 216804 kb
Host smart-a2736c78-7435-40e7-98c3-e0b65476e7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860937294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_byte_transfer.860937294
Directory /workspace/9.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.4272698006
Short name T328
Test name
Test status
Simulation time 1494390244 ps
CPU time 4.66 seconds
Started Jan 03 01:54:36 PM PST 24
Finished Jan 03 01:54:46 PM PST 24
Peak memory 219368 kb
Host smart-4903e733-e539-4a38-a4ed-2e5347eb194c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272698006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.4272698006
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.4230362201
Short name T920
Test name
Test status
Simulation time 25501461 ps
CPU time 0.75 seconds
Started Jan 03 01:54:37 PM PST 24
Finished Jan 03 01:54:43 PM PST 24
Peak memory 206580 kb
Host smart-9d1e4d9a-a97b-4db2-a590-da4b95a20d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230362201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4230362201
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_dummy_item_extra_dly.103834242
Short name T1242
Test name
Test status
Simulation time 62804085286 ps
CPU time 1478.47 seconds
Started Jan 03 01:54:37 PM PST 24
Finished Jan 03 02:19:21 PM PST 24
Peak memory 260264 kb
Host smart-07b23812-e128-4feb-94e1-91eb264b281c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103834242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_dummy_item_extra_dly.103834242
Directory /workspace/9.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/9.spi_device_extreme_fifo_size.2162246379
Short name T525
Test name
Test status
Simulation time 59182816527 ps
CPU time 144.65 seconds
Started Jan 03 01:52:12 PM PST 24
Finished Jan 03 01:54:45 PM PST 24
Peak memory 223996 kb
Host smart-550e4b15-cbd6-41d0-a1fd-2561c0561e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162246379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_extreme_fifo_size.2162246379
Directory /workspace/9.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/9.spi_device_fifo_full.1552452925
Short name T1027
Test name
Test status
Simulation time 285186011559 ps
CPU time 2575.39 seconds
Started Jan 03 01:52:28 PM PST 24
Finished Jan 03 02:35:31 PM PST 24
Peak memory 270552 kb
Host smart-011a6ead-5125-47fe-8f5b-fa724db04d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552452925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_fifo_full.1552452925
Directory /workspace/9.spi_device_fifo_full/latest

Test location /workspace/coverage/default/9.spi_device_fifo_underflow_overflow.273988210
Short name T848
Test name
Test status
Simulation time 279387595157 ps
CPU time 314.42 seconds
Started Jan 03 01:52:29 PM PST 24
Finished Jan 03 01:57:51 PM PST 24
Peak memory 331720 kb
Host smart-18922410-689f-4144-9e2e-3e63346a877c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273988210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_fifo_underflow_overflo
w.273988210
Directory /workspace/9.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2345762863
Short name T1724
Test name
Test status
Simulation time 15925563933 ps
CPU time 128.92 seconds
Started Jan 03 01:54:37 PM PST 24
Finished Jan 03 01:56:51 PM PST 24
Peak memory 266136 kb
Host smart-83ce7324-b847-48e1-b38e-daded30d7493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345762863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2345762863
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3249924534
Short name T75
Test name
Test status
Simulation time 15216210457 ps
CPU time 162.56 seconds
Started Jan 03 01:54:35 PM PST 24
Finished Jan 03 01:57:22 PM PST 24
Peak memory 270472 kb
Host smart-0f22b41d-8128-47af-81b8-6ea05e48ab1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249924534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3249924534
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1653361765
Short name T774
Test name
Test status
Simulation time 1468230596 ps
CPU time 7.25 seconds
Started Jan 03 01:54:38 PM PST 24
Finished Jan 03 01:54:52 PM PST 24
Peak memory 249652 kb
Host smart-8c531a52-d783-4d6d-9243-317ce7824acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653361765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1653361765
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.52216754
Short name T1704
Test name
Test status
Simulation time 1078697069 ps
CPU time 6.68 seconds
Started Jan 03 01:54:34 PM PST 24
Finished Jan 03 01:54:45 PM PST 24
Peak memory 240264 kb
Host smart-92530a16-4ec1-43f8-8412-d4acb6cfde0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52216754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.52216754
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_intr.154163277
Short name T529
Test name
Test status
Simulation time 21628839673 ps
CPU time 23.4 seconds
Started Jan 03 01:54:37 PM PST 24
Finished Jan 03 01:55:06 PM PST 24
Peak memory 220724 kb
Host smart-d45a6453-733e-4947-a78a-de57fb4024eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154163277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intr.154163277
Directory /workspace/9.spi_device_intr/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3994866183
Short name T355
Test name
Test status
Simulation time 3235099558 ps
CPU time 13.12 seconds
Started Jan 03 01:54:37 PM PST 24
Finished Jan 03 01:54:55 PM PST 24
Peak memory 229840 kb
Host smart-1aff0578-6292-4152-b82e-9c16e458d345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994866183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3994866183
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2714890566
Short name T1527
Test name
Test status
Simulation time 25597965 ps
CPU time 1.07 seconds
Started Jan 03 01:54:36 PM PST 24
Finished Jan 03 01:54:42 PM PST 24
Peak memory 218824 kb
Host smart-1221f67d-84b3-4c4d-90cb-ecd5a4a5319f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714890566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2714890566
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2597157758
Short name T758
Test name
Test status
Simulation time 690999849 ps
CPU time 10.95 seconds
Started Jan 03 01:54:37 PM PST 24
Finished Jan 03 01:54:54 PM PST 24
Peak memory 240344 kb
Host smart-b350fbe9-8baf-47f9-93f4-1239a13051b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597157758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2597157758
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.652952117
Short name T61
Test name
Test status
Simulation time 595183049 ps
CPU time 4.55 seconds
Started Jan 03 01:54:38 PM PST 24
Finished Jan 03 01:54:49 PM PST 24
Peak memory 225048 kb
Host smart-a492130e-8b81-43d9-a12f-4187c15a13f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652952117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.652952117
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_perf.3116111763
Short name T857
Test name
Test status
Simulation time 8158080730 ps
CPU time 557.97 seconds
Started Jan 03 01:54:35 PM PST 24
Finished Jan 03 02:03:58 PM PST 24
Peak memory 236888 kb
Host smart-23faefa3-553e-4968-b531-65b677c9259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116111763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_perf.3116111763
Directory /workspace/9.spi_device_perf/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.3182840679
Short name T1557
Test name
Test status
Simulation time 16029457 ps
CPU time 0.79 seconds
Started Jan 03 01:54:36 PM PST 24
Finished Jan 03 01:54:42 PM PST 24
Peak memory 216716 kb
Host smart-a2fc5d26-c222-45fc-8141-5a99fce76e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182840679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.3182840679
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1568190725
Short name T37
Test name
Test status
Simulation time 674109813 ps
CPU time 3.87 seconds
Started Jan 03 01:54:34 PM PST 24
Finished Jan 03 01:54:42 PM PST 24
Peak memory 220892 kb
Host smart-89e0eaf0-c309-4c70-a456-b3aa65f216dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1568190725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1568190725
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_rx_async_fifo_reset.166649271
Short name T1558
Test name
Test status
Simulation time 64534885 ps
CPU time 0.86 seconds
Started Jan 03 01:54:36 PM PST 24
Finished Jan 03 01:54:42 PM PST 24
Peak memory 208488 kb
Host smart-79a0f170-b082-44a3-a8ba-5e524cfb3c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166649271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_rx_async_fifo_reset.166649271
Directory /workspace/9.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/9.spi_device_rx_timeout.3457674714
Short name T1655
Test name
Test status
Simulation time 4935769433 ps
CPU time 6.39 seconds
Started Jan 03 01:54:33 PM PST 24
Finished Jan 03 01:54:44 PM PST 24
Peak memory 216980 kb
Host smart-5b921d7b-3a1d-4f13-aede-bcadc19519bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457674714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_rx_timeout.3457674714
Directory /workspace/9.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/9.spi_device_smoke.1909349006
Short name T1218
Test name
Test status
Simulation time 69176308 ps
CPU time 1.11 seconds
Started Jan 03 01:52:10 PM PST 24
Finished Jan 03 01:52:21 PM PST 24
Peak memory 216596 kb
Host smart-a0223b9e-f8df-4a81-82b5-a32993100220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909349006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_smoke.1909349006
Directory /workspace/9.spi_device_smoke/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2304773680
Short name T368
Test name
Test status
Simulation time 213817521079 ps
CPU time 1471.15 seconds
Started Jan 03 01:54:38 PM PST 24
Finished Jan 03 02:19:16 PM PST 24
Peak memory 389376 kb
Host smart-33634a49-a2e9-4c06-96df-84b6149f5d8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304773680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2304773680
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3868775045
Short name T115
Test name
Test status
Simulation time 670209979 ps
CPU time 3.62 seconds
Started Jan 03 01:54:35 PM PST 24
Finished Jan 03 01:54:43 PM PST 24
Peak memory 217148 kb
Host smart-ea1eb8b2-3519-48e0-84ba-a717409ca9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868775045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3868775045
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1569886157
Short name T760
Test name
Test status
Simulation time 1282338144 ps
CPU time 9.74 seconds
Started Jan 03 01:54:34 PM PST 24
Finished Jan 03 01:54:48 PM PST 24
Peak memory 216924 kb
Host smart-9066422e-54c4-458c-bb7a-4146b44d8ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569886157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1569886157
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.538311420
Short name T1095
Test name
Test status
Simulation time 24987653 ps
CPU time 0.9 seconds
Started Jan 03 01:54:38 PM PST 24
Finished Jan 03 01:54:45 PM PST 24
Peak memory 208008 kb
Host smart-70fc3136-3c1c-4fd2-979e-75dd5660500f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538311420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.538311420
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.419059727
Short name T124
Test name
Test status
Simulation time 223725777 ps
CPU time 0.72 seconds
Started Jan 03 01:54:33 PM PST 24
Finished Jan 03 01:54:39 PM PST 24
Peak memory 206932 kb
Host smart-36737909-29c9-49a3-9e60-74680ab838ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419059727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.419059727
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_tx_async_fifo_reset.2294050543
Short name T86
Test name
Test status
Simulation time 42447357 ps
CPU time 0.78 seconds
Started Jan 03 01:54:37 PM PST 24
Finished Jan 03 01:54:43 PM PST 24
Peak memory 208464 kb
Host smart-dd1d1ba8-0122-4eef-9a7d-bcd5c98ccb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294050543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tx_async_fifo_reset.2294050543
Directory /workspace/9.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/9.spi_device_txrx.1023615438
Short name T785
Test name
Test status
Simulation time 178943289676 ps
CPU time 256.88 seconds
Started Jan 03 01:52:29 PM PST 24
Finished Jan 03 01:56:53 PM PST 24
Peak memory 249872 kb
Host smart-7f4d07e1-ad7a-4f62-849f-e2ce02862324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023615438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_txrx.1023615438
Directory /workspace/9.spi_device_txrx/latest

Test location /workspace/coverage/default/9.spi_device_upload.2585502478
Short name T311
Test name
Test status
Simulation time 9273046831 ps
CPU time 16.4 seconds
Started Jan 03 01:54:34 PM PST 24
Finished Jan 03 01:54:56 PM PST 24
Peak memory 225008 kb
Host smart-e0dfd15d-faf1-477b-8326-0632c617702a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585502478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2585502478
Directory /workspace/9.spi_device_upload/latest
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