Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 161615398 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 19410208 1 T4 11 T5 1067 T1 17



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 168641476 1 T4 25 T5 2 T1 7
values[0x0] 6192852 1 T4 1 T5 550 T1 9
values[0x1] 6191278 1 T4 10 T5 518 T1 8



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 82497290 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 98528316 1 T4 21 T5 1069 T1 19



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 681113 1 T2 15 T3 1534 T11 17
valid_sources[0x01] 697216 1 T3 2041 T11 19 T15 1
valid_sources[0x02] 711498 1 T2 17 T3 1206 T11 22
valid_sources[0x03] 684787 1 T3 1642 T11 19 T15 2
valid_sources[0x04] 699993 1 T3 1042 T11 13 T15 1
valid_sources[0x05] 692538 1 T3 1421 T11 39 T6 76
valid_sources[0x06] 716048 1 T2 15 T3 1207 T11 17
valid_sources[0x07] 731139 1 T3 1257 T11 15 T6 283
valid_sources[0x08] 673374 1 T3 1696 T11 15 T6 340
valid_sources[0x09] 696169 1 T2 15 T3 1783 T11 24
valid_sources[0x0a] 691040 1 T3 1838 T11 11 T15 4
valid_sources[0x0b] 699288 1 T3 1288 T11 24 T15 3
valid_sources[0x0c] 716004 1 T3 1446 T11 9 T8 4
valid_sources[0x0d] 715826 1 T3 1445 T11 32 T6 38
valid_sources[0x0e] 735558 1 T2 30 T3 1017 T11 29
valid_sources[0x0f] 707630 1 T3 1516 T11 12 T6 246
valid_sources[0x10] 680490 1 T3 1675 T11 15 T35 3
valid_sources[0x11] 698847 1 T2 16 T3 1443 T11 21
valid_sources[0x12] 709688 1 T3 1812 T11 22 T35 1
valid_sources[0x13] 692196 1 T2 16 T3 1304 T11 26
valid_sources[0x14] 736796 1 T2 17 T3 1723 T11 14
valid_sources[0x15] 719854 1 T3 1336 T11 21 T15 1
valid_sources[0x16] 700700 1 T3 1548 T11 18 T6 102
valid_sources[0x17] 727332 1 T3 1641 T11 19 T15 1
valid_sources[0x18] 707177 1 T3 2455 T11 10 T15 3
valid_sources[0x19] 706107 1 T3 1743 T11 17 T6 341
valid_sources[0x1a] 736939 1 T3 1958 T11 18 T6 535
valid_sources[0x1b] 742866 1 T3 1442 T11 22 T6 550
valid_sources[0x1c] 679694 1 T3 1516 T11 17 T15 1
valid_sources[0x1d] 721279 1 T3 1479 T11 15 T8 1
valid_sources[0x1e] 695982 1 T3 1545 T11 21 T6 45
valid_sources[0x1f] 671155 1 T2 15 T3 1373 T11 15
valid_sources[0x20] 726776 1 T4 1 T3 1689 T11 23
valid_sources[0x21] 699257 1 T3 1397 T11 12 T6 574
valid_sources[0x22] 683504 1 T3 1352 T11 18 T6 85
valid_sources[0x23] 713075 1 T2 32 T3 1442 T11 17
valid_sources[0x24] 712125 1 T3 1330 T11 16 T15 1
valid_sources[0x25] 657509 1 T3 1575 T11 14 T6 333
valid_sources[0x26] 713565 1 T3 1938 T11 26 T6 66
valid_sources[0x27] 698792 1 T3 1004 T11 17 T35 1
valid_sources[0x28] 671006 1 T3 1205 T11 21 T36 75
valid_sources[0x29] 708027 1 T3 1776 T11 17 T6 166
valid_sources[0x2a] 693299 1 T3 1663 T11 19 T6 915
valid_sources[0x2b] 660468 1 T3 1416 T11 19 T6 381
valid_sources[0x2c] 721836 1 T3 1469 T11 18 T6 59
valid_sources[0x2d] 686692 1 T3 2021 T11 14 T6 53
valid_sources[0x2e] 721791 1 T3 1654 T11 20 T6 655
valid_sources[0x2f] 669824 1 T3 1406 T11 21 T6 1595
valid_sources[0x30] 723114 1 T2 16 T3 1394 T11 17
valid_sources[0x31] 701597 1 T2 15 T3 1839 T11 16
valid_sources[0x32] 680260 1 T3 1581 T11 23 T15 1
valid_sources[0x33] 705538 1 T3 1671 T11 20 T6 205
valid_sources[0x34] 687748 1 T3 1703 T11 14 T6 1903
valid_sources[0x35] 688384 1 T4 1 T2 17 T3 1548
valid_sources[0x36] 674144 1 T3 1413 T11 17 T15 2
valid_sources[0x37] 747334 1 T2 16 T3 1212 T11 15
valid_sources[0x38] 726081 1 T2 31 T3 1485 T11 22
valid_sources[0x39] 682342 1 T1 13 T3 1552 T11 19
valid_sources[0x3a] 661646 1 T2 15 T3 1780 T11 18
valid_sources[0x3b] 684744 1 T3 1716 T11 22 T6 719
valid_sources[0x3c] 689982 1 T2 15 T3 1376 T11 16
valid_sources[0x3d] 734202 1 T2 31 T3 1337 T11 11
valid_sources[0x3e] 722377 1 T3 1397 T11 18 T8 1
valid_sources[0x3f] 691012 1 T3 1430 T11 17 T6 92
valid_sources[0x40] 708232 1 T3 1294 T11 23 T6 317
valid_sources[0x41] 695867 1 T3 1354 T11 25 T6 238
valid_sources[0x42] 661309 1 T3 1203 T11 21 T15 1
valid_sources[0x43] 712416 1 T2 15 T3 1242 T11 22
valid_sources[0x44] 693067 1 T3 1718 T11 15 T6 123
valid_sources[0x45] 708191 1 T3 1684 T11 10 T15 1
valid_sources[0x46] 701107 1 T2 15 T3 1433 T11 20
valid_sources[0x47] 706576 1 T2 15 T3 1548 T11 23
valid_sources[0x48] 706040 1 T4 5 T2 34 T3 1708
valid_sources[0x49] 661105 1 T3 2214 T11 14 T15 1
valid_sources[0x4a] 1394663 1 T3 1616 T11 18 T15 1
valid_sources[0x4b] 677222 1 T3 1576 T11 16 T6 5
valid_sources[0x4c] 726791 1 T3 1576 T11 16 T15 1
valid_sources[0x4d] 703540 1 T2 30 T3 1458 T11 13
valid_sources[0x4e] 728338 1 T2 16 T3 1813 T11 17
valid_sources[0x4f] 776015 1 T3 1607 T11 16 T6 44
valid_sources[0x50] 702278 1 T1 11 T3 1540 T11 23
valid_sources[0x51] 666031 1 T3 1202 T11 19 T6 45
valid_sources[0x52] 680161 1 T2 15 T3 1696 T11 22
valid_sources[0x53] 702956 1 T2 16 T3 1382 T11 29
valid_sources[0x54] 736303 1 T2 16 T3 1279 T11 22
valid_sources[0x55] 679344 1 T3 933 T11 32 T6 327
valid_sources[0x56] 691326 1 T3 1751 T11 12 T6 15
valid_sources[0x57] 670133 1 T3 1159 T11 16 T6 40
valid_sources[0x58] 723387 1 T2 15 T3 1063 T11 30
valid_sources[0x59] 709429 1 T2 15 T3 1427 T11 18
valid_sources[0x5a] 706939 1 T2 31 T3 1367 T11 15
valid_sources[0x5b] 688847 1 T2 17 T3 1857 T11 10
valid_sources[0x5c] 731399 1 T2 17 T3 1739 T11 16
valid_sources[0x5d] 704568 1 T2 15 T3 1439 T11 19
valid_sources[0x5e] 728405 1 T3 1145 T11 15 T6 41
valid_sources[0x5f] 657470 1 T2 16 T3 1526 T11 17
valid_sources[0x60] 695724 1 T3 1551 T11 24 T6 2807
valid_sources[0x61] 742620 1 T2 16 T3 1421 T11 21
valid_sources[0x62] 692637 1 T3 1537 T11 18 T6 940
valid_sources[0x63] 705607 1 T4 1 T3 1542 T11 13
valid_sources[0x64] 658617 1 T3 1325 T11 29 T35 1
valid_sources[0x65] 668203 1 T2 17 T3 1420 T11 18
valid_sources[0x66] 649794 1 T3 1623 T11 21 T6 335
valid_sources[0x67] 683978 1 T3 1555 T11 14 T6 124
valid_sources[0x68] 684218 1 T4 3 T2 18 T3 1379
valid_sources[0x69] 662543 1 T5 1070 T2 16 T3 1274
valid_sources[0x6a] 702877 1 T3 1929 T11 19 T15 1
valid_sources[0x6b] 729154 1 T2 16 T3 1781 T11 28
valid_sources[0x6c] 721926 1 T2 16 T3 1213 T11 25
valid_sources[0x6d] 685706 1 T3 1368 T11 11 T15 1
valid_sources[0x6e] 701853 1 T3 1482 T11 22 T6 198
valid_sources[0x6f] 694775 1 T2 15 T3 1410 T11 22
valid_sources[0x70] 711872 1 T3 1479 T11 17 T6 78
valid_sources[0x71] 685225 1 T2 18 T3 1570 T11 15
valid_sources[0x72] 722033 1 T3 1603 T11 13 T35 1
valid_sources[0x73] 693823 1 T2 15 T3 1887 T11 17
valid_sources[0x74] 720936 1 T4 6 T3 2016 T11 21
valid_sources[0x75] 711575 1 T3 1559 T11 19 T35 1
valid_sources[0x76] 676421 1 T2 15 T3 1271 T11 20
valid_sources[0x77] 769223 1 T3 1605 T11 21 T8 7
valid_sources[0x78] 695695 1 T3 1459 T11 19 T15 4
valid_sources[0x79] 665333 1 T3 1707 T11 15 T6 230
valid_sources[0x7a] 740911 1 T4 1 T3 1509 T11 23
valid_sources[0x7b] 706515 1 T2 15 T3 1932 T11 16
valid_sources[0x7c] 692042 1 T3 1566 T11 19 T15 1
valid_sources[0x7d] 687009 1 T3 1833 T11 27 T35 1
valid_sources[0x7e] 698518 1 T2 17 T3 1223 T11 19
valid_sources[0x7f] 719662 1 T3 1500 T11 13 T6 24
valid_sources[0x80] 701676 1 T3 1812 T11 12 T6 4



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 7380319 1 T4 1 T5 1 T1 1
values[0x0] all_enables biggest_size 6025763 1 T4 1 T5 549 T1 9
values[0x1] all_enables biggest_size 6004126 1 T4 9 T5 517 T1 7

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%