Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

161631609

1

T4

25

T5

3

T1

7

full_word

19409105

1

T4

11

T5

1067

T1

17

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	181040374	1			T4	36		T5	1070		T1	24
auto[TlIntgErrCmd]	107	1			T82	8		T116	12		T117	6
auto[TlIntgErrData]	114	1			T82	12		T116	5		T117	14
auto[TlIntgErrBoth]	119	1			T82	10		T116	13		T117	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168641341

1

T4

25

T5

2

T1

7

auto[1]

12399373

1

T4

11

T5

1068

T1

17

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	161260866	1			T4	24		T5	1		T1	6
auto[TlIntgErrNone]	partial	auto[1]	370430	1			T4	1		T5	2		T1	1
auto[TlIntgErrNone]	full_word	auto[0]	7380315	1			T4	1		T5	1		T1	1
auto[TlIntgErrNone]	full_word	auto[1]	12028763	1			T4	10		T5	1066		T1	16
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T82	7		T116	4		T117	1
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T82	1		T116	8		T117	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T196	1		T194	2		T197	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T196	1		T194	1		-	-
auto[TlIntgErrData]	partial	auto[0]	56	1			T82	6		T116	4		T117	8
auto[TlIntgErrData]	partial	auto[1]	47	1			T82	4		T116	1		T117	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T117	1		T136	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T82	2		T117	1		T134	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T82	6		T116	5		T117	4
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T82	3		T116	7		T117	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T82	1		T117	1		T137	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T116	1		T134	2		T194	1