Unified Coverage Report :: Module :: spi_p2s

Module : spi_p2s

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20	100.00	84.62			76.19	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_p2s	90.20	100.00	84.62			76.19	100.00

---

Module Instance : tb.dut.u_p2s

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20	100.00	84.62			76.19	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20	100.00	84.62			76.19	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_p2s

	Line No.	Total	Covered	Percent
TOTAL		37	37	100.00
ALWAYS	71	5	5	100.00
CONT_ASSIGN	92	1	1	100.00
ALWAYS	111	5	5	100.00
ALWAYS	123	4	4	100.00
CONT_ASSIGN	143	1	1	100.00
ALWAYS	147	5	5	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	183	6	6	100.00
CONT_ASSIGN	192	1	1	100.00
ALWAYS	196	5	5	100.00
ALWAYS	214	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
71	1	1
73	1	1
75	1	1
79	1	1
83	1	1
92	1	1
111	1	1
113	1	1
114	1	1
115	1	1
116	1	1
123	1	1
125	1	1
129	1	1
133	1	1
143	1	1
147	1	1
149	1	1
151	1	1
156	1	1
161	1	1
179	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
188	1	1
			MISSING_ELSE
192	1	1
196	1	1
198	1	1
199	1	1
200	1	1
201	1	1
214	1	1
215	1	1
217	1	1

---

Cond Coverage for Module : spi_p2s

	Total	Covered	Percent
Conditions	52	44	84.62
Logical	52	44	84.62
Non-Logical	0	0
Event	0	0

 LINE       92
 EXPRESSION (csb_i ? 4'b0 : out_enable)
             --1--

-1-	Status	Tests
0	Covered	T5,T2,T3
1	Covered	T4,T5,T1

 LINE       114
 EXPRESSION (cnt == 3'h6)
            ------1------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T11

 LINE       115
 EXPRESSION (cnt == 3'h2)
            ------1------

-1-	Status	Tests
0	Covered	T3,T11,T6
1	Covered	T3,T11,T6

 LINE       116
 EXPRESSION (cnt == 3'b0)
            ------1------

-1-	Status	Tests
0	Covered	T3,T11,T6
1	Covered	T3,T11,T6

 LINE       125
 EXPRESSION (order_i ? ({1'b0, out_shift_d[7:1]}) : ({out_shift_d[6:0], 1'b0}))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T2
1	Covered	T9,T13,T33

 LINE       129
 EXPRESSION (order_i ? ({2'b0, out_shift_d[7:2]}) : ({out_shift_d[5:0], 2'b0}))
             ---1---

-1-	Status	Tests
0	Covered	T3,T11,T6
1	Not Covered

 LINE       133
 EXPRESSION (order_i ? ({4'b0, out_shift_d[7:4]}) : ({out_shift_d[3:0], 4'b0}))
             ---1---

-1-	Status	Tests
0	Covered	T3,T11,T6
1	Not Covered

 LINE       143
 EXPRESSION (first_beat ? data_i : out_shift)
             -----1----

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T4,T5,T1

 LINE       151
 EXPRESSION (order_i ? (((!first_beat)) ? out_shift[0] : data_i[0]) : (((!first_beat)) ? out_shift[7] : data_i[7]))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T8,T34

 LINE       151
 SUB-EXPRESSION (((!first_beat)) ? out_shift[0] : data_i[0])
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T8,T34
1	Covered	T9,T13,T33

 LINE       151
 SUB-EXPRESSION (((!first_beat)) ? out_shift[7] : data_i[7])
                 -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T11

 LINE       156
 EXPRESSION (order_i ? (((!first_beat)) ? out_shift[1:0] : data_i[1:0]) : (((!first_beat)) ? out_shift[7:6] : data_i[7:6]))
             ---1---

-1-	Status	Tests
0	Covered	T3,T11,T6
1	Not Covered

 LINE       156
 SUB-EXPRESSION (((!first_beat)) ? out_shift[1:0] : data_i[1:0])
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       156
 SUB-EXPRESSION (((!first_beat)) ? out_shift[7:6] : data_i[7:6])
                 -------1-------

-1-	Status	Tests
0	Covered	T3,T11,T6
1	Covered	T3,T11,T6

 LINE       161
 EXPRESSION (order_i ? (((!first_beat)) ? out_shift[3:0] : data_i[3:0]) : (((!first_beat)) ? out_shift[7:4] : data_i[7:4]))
             ---1---

-1-	Status	Tests
0	Covered	T3,T11,T6
1	Not Covered

 LINE       161
 SUB-EXPRESSION (((!first_beat)) ? out_shift[3:0] : data_i[3:0])
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       161
 SUB-EXPRESSION (((!first_beat)) ? out_shift[7:4] : data_i[7:4])
                 -------1-------

-1-	Status	Tests
0	Covered	T3,T11,T6
1	Covered	T3,T11,T6

 LINE       187
 EXPRESSION (data_valid_i && ((tx_state != TxIdle) || (cpha_i == 1'b0)))
             ------1-----    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T3,T11
1	0	Covered	T2,T9,T10
1	1	Covered	T2,T3,T11

 LINE       187
 SUB-EXPRESSION ((tx_state != TxIdle) || (cpha_i == 1'b0))
                 ----------1---------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Covered	T5,T3,T11
1	0	Covered	T2,T9,T10

 LINE       187
 SUB-EXPRESSION (tx_state != TxIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T5,T2,T3
1	Covered	T5,T2,T3

 LINE       187
 SUB-EXPRESSION (cpha_i == 1'b0)
                --------1-------

-1-	Status	Tests
0	Covered	T2,T9,T10
1	Covered	T5,T3,T11

 LINE       192
 EXPRESSION (cnt == '0)
            -----1-----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       199
 EXPRESSION (cnt == 3'('h00000007))
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T11

 LINE       200
 EXPRESSION (cnt == 3'('h00000003))
            -----------1-----------

-1-	Status	Tests
0	Covered	T3,T11,T6
1	Covered	T3,T11,T6

 LINE       201
 EXPRESSION (cnt == 3'('b1))
            --------1-------

-1-	Status	Tests
0	Covered	T3,T11,T6
1	Covered	T3,T11,T6

---

Branch Coverage for Module : spi_p2s

	Line No.	Total	Covered	Percent
Branches		42	32	76.19
TERNARY	92	2	2	100.00
TERNARY	143	2	2	100.00
CASE	73	4	3	75.00
CASE	113	4	3	75.00
CASE	123	7	5	71.43
CASE	149	13	8	61.54
IF	183	4	4	100.00
CASE	198	4	3	75.00
IF	214	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(csb_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T5,T2,T3

	LineNo.	Expression
-1-:	143	(first_beat) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T2,T3,T11

	LineNo.	Expression
-1-:	73	case (io_mode)

Branches:

-1-	Status	Tests
SingleIO	Covered	T4,T5,T1
DualIO	Covered	T3,T11,T6
QuadIO	Covered	T3,T11,T6
default	Not Covered

	LineNo.	Expression
-1-:	113	case (io_mode)

Branches:

-1-	Status	Tests
SingleIO	Covered	T4,T5,T1
DualIO	Covered	T3,T11,T6
QuadIO	Covered	T3,T11,T6
default	Not Covered

	LineNo.	Expression
-1-:	123	case (io_mode)
-2-:	125	(order_i) ? 
-3-:	129	(order_i) ? 
-4-:	133	(order_i) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
SingleIO	1	-	-	Covered	T9,T13,T33
SingleIO	0	-	-	Covered	T4,T5,T2
DualIO	-	1	-	Not Covered
DualIO	-	0	-	Covered	T3,T11,T6
QuadIO	-	-	1	Not Covered
QuadIO	-	-	0	Covered	T3,T11,T6
default	-	-	-	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	149	case (io_mode)
-2-:	151	(order_i) ? 
-3-:	151	((!first_beat)) ? 
-4-:	151	((!first_beat)) ? 
-5-:	156	(order_i) ? 
-6-:	156	((!first_beat)) ? 
-7-:	156	((!first_beat)) ? 
-8-:	161	(order_i) ? 
-9-:	161	((!first_beat)) ? 
-10-:	161	((!first_beat)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	Status	Tests
SingleIO	1	1	-	-	-	-	-	-	-	Covered	T9,T13,T33
SingleIO	1	0	-	-	-	-	-	-	-	Covered	T1,T8,T34
SingleIO	0	-	1	-	-	-	-	-	-	Covered	T2,T3,T11
SingleIO	0	-	0	-	-	-	-	-	-	Covered	T4,T5,T1
DualIO	-	-	-	1	1	-	-	-	-	Not Covered
DualIO	-	-	-	1	0	-	-	-	-	Not Covered
DualIO	-	-	-	0	-	1	-	-	-	Covered	T3,T11,T6
DualIO	-	-	-	0	-	0	-	-	-	Covered	T3,T11,T6
QuadIO	-	-	-	-	-	-	1	1	-	Not Covered
QuadIO	-	-	-	-	-	-	1	0	-	Not Covered
QuadIO	-	-	-	-	-	-	0	-	1	Covered	T3,T11,T6
QuadIO	-	-	-	-	-	-	0	-	0	Covered	T3,T11,T6
default	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	183	if ((!rst_ni))
-2-:	185	if (last_beat)
-3-:	187	if ((data_valid_i && ((tx_state != TxIdle) || (cpha_i == 1'b0))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T11,T6
0	0	1	Covered	T2,T3,T11
0	0	0	Covered	T5,T2,T3

	LineNo.	Expression
-1-:	198	case (io_mode)

Branches:

-1-	Status	Tests
SingleIO	Covered	T4,T5,T1
DualIO	Covered	T3,T11,T6
QuadIO	Covered	T3,T11,T6
default	Not Covered

	LineNo.	Expression
-1-:	214	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T5,T2,T3

---

Assert Coverage for Module : spi_p2s

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoModeChangeValid_A	410998614	8441	0	0
IoModeDefault_A	410998614	58090	0	0

IoModeChangeValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410998614	8441	0	0
T1	1	0	0	0
T2	3297	1	0	0
T3	175606	54	0	0
T5	35201	1	0	0
T6	694999	47	0	0
T8	1	0	0	0
T11	92865	20	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	4104	0	0	0
T16	0	17	0	0
T33	0	1	0	0
T35	1	0	0	0
T36	1	0	0	0

IoModeDefault_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410998614	58090	0	0
T1	1	0	0	0
T2	3297	1	0	0
T3	175606	413	0	0
T5	35201	1	0	0
T6	694999	96	0	0
T8	1	0	0	0
T9	0	11	0	0
T10	0	278	0	0
T11	92865	5	0	0
T12	0	2	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	4104	0	0	0
T35	1	0	0	0
T36	1	0	0	0