Unified Coverage Report :: Module :: prim_fifo_async_sram_adapter

Module : prim_fifo_async_sram_adapter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_cmdfifo	93.75	100.00	75.00			100.00	100.00
tb.dut.u_upload.u_addrfifo	93.75	100.00	75.00			100.00	100.00

---

Module Instance : tb.dut.u_upload.u_cmdfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	87.18		100.00	96.30	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_rptr_gray	100.00	100.00				100.00
u_sync_wptr_gray	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_addrfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	87.18		100.00	96.30	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_rptr_gray	100.00	100.00				100.00
u_sync_wptr_gray	100.00	100.00				100.00

Line Coverage for Module : prim_fifo_async_sram_adapter ( parameter Width=8,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=896,DepthW=5,PtrVW=4,PtrW=5 )
Line Coverage for Module self-instances :

SCORE	LINE
93.75	100.00

tb.dut.u_upload.u_cmdfifo

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
ALWAYS	126	6	6	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
ALWAYS	168	6	6	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
ALWAYS	204	4	4	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
ALWAYS	270	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	324	9	9	100.00
ROUTINE	347	7	7	100.00
ROUTINE	368	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
121	1	1
123	1	1
126	1	1
127	1	1
128	1	1
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
138	1	1
149	1	1
150	1	1
151	1	1
153	1	1
163	1	1
165	1	1
168	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
			MISSING_ELSE
177	1	1
178	1	1
180	1	1
191	1	1
192	1	1
193	1	1
195	1	1
201	1	1
204	1	1
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
211	1	1
217	1	1
218	1	1
219	1	1
222	1	1
224	1	1
225	1	1
245	1	1
247	1	1
248	1	1
251	1	1
252	1	1
254	1	1
256	1	1
260	1	1
270	1	1
279	1	1
282	1	1
287	1	1
291	1	1
297	1	1
299	1	1
301	1	1
304	1	1
308	1	1
321	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
330	1	1
332	1	1
333	1	1
			MISSING_ELSE
347	1	1
349	1	1
352	1	1
353	1	1
356	1	1
357	1	1
360	1	1
368	1	1
369	1	1
370	1	1
372	1	1
373	1	1
374	1	1
376	1	1
377	1	1
379	1	1

---

Line Coverage for Module : prim_fifo_async_sram_adapter ( parameter Width=32,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=912,DepthW=5,PtrVW=4,PtrW=5 )
Line Coverage for Module self-instances :

SCORE	LINE
93.75	100.00

tb.dut.u_upload.u_addrfifo

	Line No.	Total	Covered	Percent
TOTAL		85	85	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
ALWAYS	126	6	6	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
ALWAYS	168	6	6	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
ALWAYS	204	4	4	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
ALWAYS	270	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	324	9	9	100.00
ROUTINE	347	7	7	100.00
ROUTINE	368	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
121	1	1
123	1	1
126	1	1
127	1	1
128	1	1
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
138	1	1
149	1	1
150	1	1
151	1	1
153	1	1
163	1	1
165	1	1
168	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
			MISSING_ELSE
177	1	1
178	1	1
180	1	1
191	1	1
192	1	1
193	1	1
195	1	1
201	1	1
204	1	1
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
211	1	1
217	1	1
218	1	1
219	1	1
222	1	1
224	1	1
225	1	1
245	1	1
247	1	1
248	1	1
251	1	1
252	1	1
254	1	1
256	1	1
260	1	1
270	1	1
279	1	1
282	1	1
287	1	1
291	1	1
297	1	1
299	1	1
301	1	1
304	1	1
321	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
330	1	1
332	1	1
333	1	1
			MISSING_ELSE
347	1	1
349	1	1
352	1	1
353	1	1
356	1	1
357	1	1
360	1	1
368	1	1
369	1	1
370	1	1
372	1	1
373	1	1
374	1	1
376	1	1
377	1	1
379	1	1

---

Cond Coverage for Module : prim_fifo_async_sram_adapter ( parameter Width=8,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=896,DepthW=5,PtrVW=4,PtrW=5 )
Cond Coverage for Module self-instances :

SCORE	COND
93.75	75.00

tb.dut.u_upload.u_cmdfifo

	Total	Covered	Percent
Conditions	68	51	75.00
Logical	68	51	75.00
Non-Logical	0	0
Event	0	0

 LINE       121
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       153
 EXPRESSION ((w_wptr_p == w_rptr_p) ? (5'((w_wptr_v - w_rptr_v))) : (5'(({1'b1, w_wptr_v} - {1'b0, w_rptr_v}))))
             -----------1----------

-1-	Status	Tests
0	Covered	T6,T38,T18
1	Covered	T4,T5,T1

 LINE       153
 SUB-EXPRESSION (w_wptr_p == w_rptr_p)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       195
 EXPRESSION ((r_wptr_p == r_rptr_p) ? (5'((r_wptr_v - r_rptr_v))) : (5'(({1'b1, r_wptr_v} - {1'b0, r_rptr_v}))))
             -----------1----------

-1-	Status	Tests
0	Covered	T6,T38,T18
1	Covered	T4,T5,T1

 LINE       195
 SUB-EXPRESSION (r_wptr_p == r_rptr_p)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       211
 EXPRESSION (r_wptr == r_sram_rptr)
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       217
 EXPRESSION (w_wptr_q == (w_rptr ^ XorMask))
            ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Not Covered

 LINE       218
 EXPRESSION (r_wptr == (r_rptr_q ^ XorMask))
            ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Not Covered

 LINE       219
 EXPRESSION (r_wptr == r_rptr_q)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       247
 EXPRESSION (r_sram_req_o && r_sram_gnt_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       248
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       251
 EXPRESSION (wvalid_i && ((!w_full)))
             ----1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       252
 EXPRESSION (((!w_full)) && w_sram_gnt_i)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T6,T7

 LINE       282
 EXPRESSION (((!r_sramrptr_empty)) && rfifo_ack)
             ----------1----------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Not Covered
1	1	Not Covered

 LINE       287
 EXPRESSION (((!r_sramrptr_empty)) && ( ! (r_sram_rvalid_i ^ rfifo_ack) ))
             ----------1----------    -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       287
 SUB-EXPRESSION ( ! (r_sram_rvalid_i ^ rfifo_ack) )
                    --------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       287
 SUB-EXPRESSION (r_sram_rvalid_i ^ rfifo_ack)
                 -------1-------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Not Covered

 LINE       291
 EXPRESSION (stored || r_sram_rvalid_i)
             ---1--    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       299
 EXPRESSION (r_sram_rvalid_i ? r_sram_rdata_i[0+:Width] : (8'(0)))
             -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       301
 EXPRESSION (stored ? rdata_q : rdata_d)
             ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       321
 EXPRESSION (r_sram_rvalid_i && ( ! (stored ^ rfifo_ack) ))
             -------1-------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       321
 SUB-EXPRESSION ( ! (stored ^ rfifo_ack) )
                    ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       321
 SUB-EXPRESSION (stored ^ rfifo_ack)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       330
 EXPRESSION (((!r_sram_rvalid_i)) && rfifo_ack)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T6,T7

 LINE       349
 EXPRESSION (decval[(PtrW - 1)] ? decval_sub : decval)
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T38,T18

 LINE       370
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

---

Cond Coverage for Module : prim_fifo_async_sram_adapter ( parameter Width=32,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=912,DepthW=5,PtrVW=4,PtrW=5 )
Cond Coverage for Module self-instances :

SCORE	COND
93.75	75.00

tb.dut.u_upload.u_addrfifo

	Total	Covered	Percent
Conditions	68	51	75.00
Logical	68	51	75.00
Non-Logical	0	0
Event	0	0

 LINE       121
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       153
 EXPRESSION ((w_wptr_p == w_rptr_p) ? (5'((w_wptr_v - w_rptr_v))) : (5'(({1'b1, w_wptr_v} - {1'b0, w_rptr_v}))))
             -----------1----------

-1-	Status	Tests
0	Covered	T6,T38,T18
1	Covered	T4,T5,T1

 LINE       153
 SUB-EXPRESSION (w_wptr_p == w_rptr_p)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       195
 EXPRESSION ((r_wptr_p == r_rptr_p) ? (5'((r_wptr_v - r_rptr_v))) : (5'(({1'b1, r_wptr_v} - {1'b0, r_rptr_v}))))
             -----------1----------

-1-	Status	Tests
0	Covered	T6,T38,T18
1	Covered	T4,T5,T1

 LINE       195
 SUB-EXPRESSION (r_wptr_p == r_rptr_p)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       211
 EXPRESSION (r_wptr == r_sram_rptr)
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       217
 EXPRESSION (w_wptr_q == (w_rptr ^ XorMask))
            ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Not Covered

 LINE       218
 EXPRESSION (r_wptr == (r_rptr_q ^ XorMask))
            ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Not Covered

 LINE       219
 EXPRESSION (r_wptr == r_rptr_q)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       247
 EXPRESSION (r_sram_req_o && r_sram_gnt_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       248
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       251
 EXPRESSION (wvalid_i && ((!w_full)))
             ----1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       252
 EXPRESSION (((!w_full)) && w_sram_gnt_i)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T6,T7

 LINE       282
 EXPRESSION (((!r_sramrptr_empty)) && rfifo_ack)
             ----------1----------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Not Covered
1	1	Not Covered

 LINE       287
 EXPRESSION (((!r_sramrptr_empty)) && ( ! (r_sram_rvalid_i ^ rfifo_ack) ))
             ----------1----------    -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       287
 SUB-EXPRESSION ( ! (r_sram_rvalid_i ^ rfifo_ack) )
                    --------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       287
 SUB-EXPRESSION (r_sram_rvalid_i ^ rfifo_ack)
                 -------1-------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Not Covered

 LINE       291
 EXPRESSION (stored || r_sram_rvalid_i)
             ---1--    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       299
 EXPRESSION (r_sram_rvalid_i ? r_sram_rdata_i[0+:Width] : (32'(0)))
             -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       301
 EXPRESSION (stored ? rdata_q : rdata_d)
             ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       321
 EXPRESSION (r_sram_rvalid_i && ( ! (stored ^ rfifo_ack) ))
             -------1-------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       321
 SUB-EXPRESSION ( ! (stored ^ rfifo_ack) )
                    ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       321
 SUB-EXPRESSION (stored ^ rfifo_ack)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       330
 EXPRESSION (((!r_sram_rvalid_i)) && rfifo_ack)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T6,T7

 LINE       349
 EXPRESSION (decval[(PtrW - 1)] ? decval_sub : decval)
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T38,T18

 LINE       370
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

---

Branch Coverage for Module : prim_fifo_async_sram_adapter

	Line No.	Total	Covered	Percent
Branches		27	27	100.00
TERNARY	153	2	2	100.00
TERNARY	195	2	2	100.00
TERNARY	299	2	2	100.00
TERNARY	301	2	2	100.00
IF	126	3	3	100.00
IF	168	3	3	100.00
IF	204	3	3	100.00
IF	279	2	2	100.00
IF	324	4	4	100.00
TERNARY	349	2	2	100.00
IF	373	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	153	((w_wptr_p == w_rptr_p)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T6,T38,T18

	LineNo.	Expression
-1-:	195	((r_wptr_p == r_rptr_p)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T6,T38,T18

	LineNo.	Expression
-1-:	299	(r_sram_rvalid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	301	(stored) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	126	if ((!rst_wr_ni))
-2-:	129	if (w_wptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	168	if ((!rst_rd_ni))
-2-:	171	if (r_rptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	204	if ((!rst_rd_ni))
-2-:	206	if (r_sram_rptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	279	if (stored)

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	324	if ((!rst_rd_ni))
-2-:	327	if (store_en)
-3-:	330	if (((!r_sram_rvalid_i) && rfifo_ack))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T6,T7
0	0	1	Covered	T3,T6,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	349	(decval[(PtrW - 1)]) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T38,T18
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	373	if (grayval[(PtrW - 1)])

Branches:

-1-	Status	Tests
1	Covered	T6,T38,T18
0	Covered	T4,T5,T1

---

Assert Coverage for Module : prim_fifo_async_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinDepth_A	3226	3226	0	0
NoRAckInEmpty_A	2147483647	3790	0	0
NoWAckInFull_A	821994802	3790	0	0
ParamCheckDepth_A	3226	3226	0	0
RSramRvalidOneCycle_M	2147483647	3790	0	0
RptrGrayOneBitAtATime_A	2147483647	3790	0	0
RptrIncDataValid_A	2147483647	3790	0	0
RptrIncrease_A	2147483647	3790	0	0
SramRvalid_A	2147483647	3790	0	0
WSramRvalid_A	821994802	821994780	0	0
WidthMatch_A	3226	3226	0	0
WptrGrayOneBitAtATime_A	821994802	3790	0	0
WptrIncrease_A	821994802	3790	0	0

MinDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3226	3226	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T8	2	2	0	0
T11	2	2	0	0
T15	2	2	0	0
T35	2	2	0	0
T36	2	2	0	0

NoRAckInEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3790	0	0
T3	244978	25	0	0
T6	725096	41	0	0
T7	634120	14	0	0
T8	2766	0	0	0
T11	596318	0	0	0
T12	106070	0	0	0
T15	5538	0	0	0
T18	0	39	0	0
T19	0	5	0	0
T20	0	13	0	0
T23	0	17	0	0
T26	0	112	0	0
T34	1820	0	0	0
T35	2276	0	0	0
T36	3332	0	0	0
T38	0	44	0	0
T46	0	44	0	0

NoWAckInFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821994802	3790	0	0
T3	351212	25	0	0
T6	1389996	41	0	0
T7	1377304	14	0	0
T11	185728	0	0	0
T12	96770	0	0	0
T15	8206	0	0	0
T17	146820	0	0	0
T18	0	39	0	0
T19	0	5	0	0
T20	0	13	0	0
T23	0	17	0	0
T26	0	112	0	0
T38	0	44	0	0
T46	0	44	0	0
T47	4418	0	0	0
T48	692356	0	0	0
T49	1392	0	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3226	3226	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T8	2	2	0	0
T11	2	2	0	0
T15	2	2	0	0
T35	2	2	0	0
T36	2	2	0	0

RSramRvalidOneCycle_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3790	0	0
T3	244978	25	0	0
T6	725096	41	0	0
T7	634120	14	0	0
T8	2766	0	0	0
T11	596318	0	0	0
T12	106070	0	0	0
T15	5538	0	0	0
T18	0	39	0	0
T19	0	5	0	0
T20	0	13	0	0
T23	0	17	0	0
T26	0	112	0	0
T34	1820	0	0	0
T35	2276	0	0	0
T36	3332	0	0	0
T38	0	44	0	0
T46	0	44	0	0

RptrGrayOneBitAtATime_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3790	0	0
T3	244978	25	0	0
T6	725096	41	0	0
T7	634120	14	0	0
T8	2766	0	0	0
T11	596318	0	0	0
T12	106070	0	0	0
T15	5538	0	0	0
T18	0	39	0	0
T19	0	5	0	0
T20	0	13	0	0
T23	0	17	0	0
T26	0	112	0	0
T34	1820	0	0	0
T35	2276	0	0	0
T36	3332	0	0	0
T38	0	44	0	0
T46	0	44	0	0

RptrIncDataValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3790	0	0
T3	244978	25	0	0
T6	725096	41	0	0
T7	634120	14	0	0
T8	2766	0	0	0
T11	596318	0	0	0
T12	106070	0	0	0
T15	5538	0	0	0
T18	0	39	0	0
T19	0	5	0	0
T20	0	13	0	0
T23	0	17	0	0
T26	0	112	0	0
T34	1820	0	0	0
T35	2276	0	0	0
T36	3332	0	0	0
T38	0	44	0	0
T46	0	44	0	0

RptrIncrease_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3790	0	0
T3	244978	25	0	0
T6	725096	41	0	0
T7	634120	14	0	0
T8	2766	0	0	0
T11	596318	0	0	0
T12	106070	0	0	0
T15	5538	0	0	0
T18	0	39	0	0
T19	0	5	0	0
T20	0	13	0	0
T23	0	17	0	0
T26	0	112	0	0
T34	1820	0	0	0
T35	2276	0	0	0
T36	3332	0	0	0
T38	0	44	0	0
T46	0	44	0	0

SramRvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3790	0	0
T3	244978	25	0	0
T6	725096	41	0	0
T7	634120	14	0	0
T8	2766	0	0	0
T11	596318	0	0	0
T12	106070	0	0	0
T15	5538	0	0	0
T18	0	39	0	0
T19	0	5	0	0
T20	0	13	0	0
T23	0	17	0	0
T26	0	112	0	0
T34	1820	0	0	0
T35	2276	0	0	0
T36	3332	0	0	0
T38	0	44	0	0
T46	0	44	0	0

WSramRvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821994802	821994780	0	0
T1	2	2	0	0
T2	6594	6594	0	0
T3	351212	351212	0	0
T4	720	720	0	0
T5	70400	70400	0	0
T6	1389996	1389996	0	0
T9	4820	4820	0	0
T11	185728	185728	0	0
T12	96770	96770	0	0
T15	8206	8206	0	0

WidthMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3226	3226	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T8	2	2	0	0
T11	2	2	0	0
T15	2	2	0	0
T35	2	2	0	0
T36	2	2	0	0

WptrGrayOneBitAtATime_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821994802	3790	0	0
T3	351212	25	0	0
T6	1389996	41	0	0
T7	1377304	14	0	0
T11	185728	0	0	0
T12	96770	0	0	0
T15	8206	0	0	0
T17	146820	0	0	0
T18	0	39	0	0
T19	0	5	0	0
T20	0	13	0	0
T23	0	17	0	0
T26	0	112	0	0
T38	0	44	0	0
T46	0	44	0	0
T47	4418	0	0	0
T48	692356	0	0	0
T49	1392	0	0	0

WptrIncrease_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	821994802	3790	0	0
T3	351212	25	0	0
T6	1389996	41	0	0
T7	1377304	14	0	0
T11	185728	0	0	0
T12	96770	0	0	0
T15	8206	0	0	0
T17	146820	0	0	0
T18	0	39	0	0
T19	0	5	0	0
T20	0	13	0	0
T23	0	17	0	0
T26	0	112	0	0
T38	0	44	0	0
T46	0	44	0	0
T47	4418	0	0	0
T48	692356	0	0	0
T49	1392	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_cmdfifo

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
ALWAYS	126	6	6	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
ALWAYS	168	6	6	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
ALWAYS	204	4	4	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
ALWAYS	270	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	324	9	9	100.00
ROUTINE	347	7	7	100.00
ROUTINE	368	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
121	1	1
123	1	1
126	1	1
127	1	1
128	1	1
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
138	1	1
149	1	1
150	1	1
151	1	1
153	1	1
163	1	1
165	1	1
168	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
			MISSING_ELSE
177	1	1
178	1	1
180	1	1
191	1	1
192	1	1
193	1	1
195	1	1
201	1	1
204	1	1
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
211	1	1
217	1	1
218	1	1
219	1	1
222	1	1
224	1	1
225	1	1
245	1	1
247	1	1
248	1	1
251	1	1
252	1	1
254	1	1
256	1	1
260	1	1
270	1	1
279	1	1
282	1	1
287	1	1
291	1	1
297	1	1
299	1	1
301	1	1
304	1	1
308	1	1
321	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
330	1	1
332	1	1
333	1	1
			MISSING_ELSE
347	1	1
349	1	1
352	1	1
353	1	1
356	1	1
357	1	1
360	1	1
368	1	1
369	1	1
370	1	1
372	1	1
373	1	1
374	1	1
376	1	1
377	1	1
379	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_cmdfifo

	Total	Covered	Percent
Conditions	68	51	75.00
Logical	68	51	75.00
Non-Logical	0	0
Event	0	0

 LINE       121
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       153
 EXPRESSION ((w_wptr_p == w_rptr_p) ? (5'((w_wptr_v - w_rptr_v))) : (5'(({1'b1, w_wptr_v} - {1'b0, w_rptr_v}))))
             -----------1----------

-1-	Status	Tests
0	Covered	T6,T38,T18
1	Covered	T4,T5,T1

 LINE       153
 SUB-EXPRESSION (w_wptr_p == w_rptr_p)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       195
 EXPRESSION ((r_wptr_p == r_rptr_p) ? (5'((r_wptr_v - r_rptr_v))) : (5'(({1'b1, r_wptr_v} - {1'b0, r_rptr_v}))))
             -----------1----------

-1-	Status	Tests
0	Covered	T6,T38,T18
1	Covered	T4,T5,T1

 LINE       195
 SUB-EXPRESSION (r_wptr_p == r_rptr_p)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       211
 EXPRESSION (r_wptr == r_sram_rptr)
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       217
 EXPRESSION (w_wptr_q == (w_rptr ^ XorMask))
            ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Not Covered

 LINE       218
 EXPRESSION (r_wptr == (r_rptr_q ^ XorMask))
            ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Not Covered

 LINE       219
 EXPRESSION (r_wptr == r_rptr_q)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       247
 EXPRESSION (r_sram_req_o && r_sram_gnt_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       248
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       251
 EXPRESSION (wvalid_i && ((!w_full)))
             ----1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       252
 EXPRESSION (((!w_full)) && w_sram_gnt_i)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T6,T7

 LINE       282
 EXPRESSION (((!r_sramrptr_empty)) && rfifo_ack)
             ----------1----------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Not Covered
1	1	Not Covered

 LINE       287
 EXPRESSION (((!r_sramrptr_empty)) && ( ! (r_sram_rvalid_i ^ rfifo_ack) ))
             ----------1----------    -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       287
 SUB-EXPRESSION ( ! (r_sram_rvalid_i ^ rfifo_ack) )
                    --------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       287
 SUB-EXPRESSION (r_sram_rvalid_i ^ rfifo_ack)
                 -------1-------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Not Covered

 LINE       291
 EXPRESSION (stored || r_sram_rvalid_i)
             ---1--    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       299
 EXPRESSION (r_sram_rvalid_i ? r_sram_rdata_i[0+:Width] : (8'(0)))
             -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       301
 EXPRESSION (stored ? rdata_q : rdata_d)
             ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       321
 EXPRESSION (r_sram_rvalid_i && ( ! (stored ^ rfifo_ack) ))
             -------1-------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       321
 SUB-EXPRESSION ( ! (stored ^ rfifo_ack) )
                    ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       321
 SUB-EXPRESSION (stored ^ rfifo_ack)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       330
 EXPRESSION (((!r_sram_rvalid_i)) && rfifo_ack)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T6,T7

 LINE       349
 EXPRESSION (decval[(PtrW - 1)] ? decval_sub : decval)
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T38,T18

 LINE       370
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

---

Branch Coverage for Instance : tb.dut.u_upload.u_cmdfifo

	Line No.	Total	Covered	Percent
Branches		27	27	100.00
TERNARY	153	2	2	100.00
TERNARY	195	2	2	100.00
TERNARY	299	2	2	100.00
TERNARY	301	2	2	100.00
IF	126	3	3	100.00
IF	168	3	3	100.00
IF	204	3	3	100.00
IF	279	2	2	100.00
IF	324	4	4	100.00
TERNARY	349	2	2	100.00
IF	373	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	153	((w_wptr_p == w_rptr_p)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T6,T38,T18

	LineNo.	Expression
-1-:	195	((r_wptr_p == r_rptr_p)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T6,T38,T18

	LineNo.	Expression
-1-:	299	(r_sram_rvalid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	301	(stored) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	126	if ((!rst_wr_ni))
-2-:	129	if (w_wptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	168	if ((!rst_rd_ni))
-2-:	171	if (r_rptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	204	if ((!rst_rd_ni))
-2-:	206	if (r_sram_rptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	279	if (stored)

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	324	if ((!rst_rd_ni))
-2-:	327	if (store_en)
-3-:	330	if (((!r_sram_rvalid_i) && rfifo_ack))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T6,T7
0	0	1	Covered	T3,T6,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	349	(decval[(PtrW - 1)]) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T38,T18
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	373	if (grayval[(PtrW - 1)])

Branches:

-1-	Status	Tests
1	Covered	T6,T38,T18
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_upload.u_cmdfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinDepth_A	1613	1613	0	0
NoRAckInEmpty_A	2010348469	2155	0	0
NoWAckInFull_A	410997401	2155	0	0
ParamCheckDepth_A	1613	1613	0	0
RSramRvalidOneCycle_M	2010348469	2155	0	0
RptrGrayOneBitAtATime_A	2010348469	2155	0	0
RptrIncDataValid_A	2010348469	2155	0	0
RptrIncrease_A	2010348469	2155	0	0
SramRvalid_A	2010348469	2155	0	0
WSramRvalid_A	410997401	410997390	0	0
WidthMatch_A	1613	1613	0	0
WptrGrayOneBitAtATime_A	410997401	2155	0	0
WptrIncrease_A	410997401	2155	0	0

MinDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1613	1613	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

NoRAckInEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2155	0	0
T3	122489	14	0	0
T6	362548	22	0	0
T7	317060	7	0	0
T8	1383	0	0	0
T11	298159	0	0	0
T12	53035	0	0	0
T15	2769	0	0	0
T18	0	21	0	0
T19	0	3	0	0
T20	0	8	0	0
T23	0	10	0	0
T26	0	60	0	0
T34	910	0	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	23	0	0
T46	0	23	0	0

NoWAckInFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	2155	0	0
T3	175606	14	0	0
T6	694998	22	0	0
T7	688652	7	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T15	4103	0	0	0
T17	73410	0	0	0
T18	0	21	0	0
T19	0	3	0	0
T20	0	8	0	0
T23	0	10	0	0
T26	0	60	0	0
T38	0	23	0	0
T46	0	23	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1613	1613	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

RSramRvalidOneCycle_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2155	0	0
T3	122489	14	0	0
T6	362548	22	0	0
T7	317060	7	0	0
T8	1383	0	0	0
T11	298159	0	0	0
T12	53035	0	0	0
T15	2769	0	0	0
T18	0	21	0	0
T19	0	3	0	0
T20	0	8	0	0
T23	0	10	0	0
T26	0	60	0	0
T34	910	0	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	23	0	0
T46	0	23	0	0

RptrGrayOneBitAtATime_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2155	0	0
T3	122489	14	0	0
T6	362548	22	0	0
T7	317060	7	0	0
T8	1383	0	0	0
T11	298159	0	0	0
T12	53035	0	0	0
T15	2769	0	0	0
T18	0	21	0	0
T19	0	3	0	0
T20	0	8	0	0
T23	0	10	0	0
T26	0	60	0	0
T34	910	0	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	23	0	0
T46	0	23	0	0

RptrIncDataValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2155	0	0
T3	122489	14	0	0
T6	362548	22	0	0
T7	317060	7	0	0
T8	1383	0	0	0
T11	298159	0	0	0
T12	53035	0	0	0
T15	2769	0	0	0
T18	0	21	0	0
T19	0	3	0	0
T20	0	8	0	0
T23	0	10	0	0
T26	0	60	0	0
T34	910	0	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	23	0	0
T46	0	23	0	0

RptrIncrease_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2155	0	0
T3	122489	14	0	0
T6	362548	22	0	0
T7	317060	7	0	0
T8	1383	0	0	0
T11	298159	0	0	0
T12	53035	0	0	0
T15	2769	0	0	0
T18	0	21	0	0
T19	0	3	0	0
T20	0	8	0	0
T23	0	10	0	0
T26	0	60	0	0
T34	910	0	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	23	0	0
T46	0	23	0	0

SramRvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2155	0	0
T3	122489	14	0	0
T6	362548	22	0	0
T7	317060	7	0	0
T8	1383	0	0	0
T11	298159	0	0	0
T12	53035	0	0	0
T15	2769	0	0	0
T18	0	21	0	0
T19	0	3	0	0
T20	0	8	0	0
T23	0	10	0	0
T26	0	60	0	0
T34	910	0	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	23	0	0
T46	0	23	0	0

WSramRvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	410997390	0	0
T1	1	1	0	0
T2	3297	3297	0	0
T3	175606	175606	0	0
T4	360	360	0	0
T5	35200	35200	0	0
T6	694998	694998	0	0
T9	2410	2410	0	0
T11	92864	92864	0	0
T12	48385	48385	0	0
T15	4103	4103	0	0

WidthMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1613	1613	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

WptrGrayOneBitAtATime_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	2155	0	0
T3	175606	14	0	0
T6	694998	22	0	0
T7	688652	7	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T15	4103	0	0	0
T17	73410	0	0	0
T18	0	21	0	0
T19	0	3	0	0
T20	0	8	0	0
T23	0	10	0	0
T26	0	60	0	0
T38	0	23	0	0
T46	0	23	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

WptrIncrease_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	2155	0	0
T3	175606	14	0	0
T6	694998	22	0	0
T7	688652	7	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T15	4103	0	0	0
T17	73410	0	0	0
T18	0	21	0	0
T19	0	3	0	0
T20	0	8	0	0
T23	0	10	0	0
T26	0	60	0	0
T38	0	23	0	0
T46	0	23	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_addrfifo

	Line No.	Total	Covered	Percent
TOTAL		85	85	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
ALWAYS	126	6	6	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
ALWAYS	168	6	6	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
ALWAYS	204	4	4	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
ALWAYS	270	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	324	9	9	100.00
ROUTINE	347	7	7	100.00
ROUTINE	368	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
121	1	1
123	1	1
126	1	1
127	1	1
128	1	1
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
138	1	1
149	1	1
150	1	1
151	1	1
153	1	1
163	1	1
165	1	1
168	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
			MISSING_ELSE
177	1	1
178	1	1
180	1	1
191	1	1
192	1	1
193	1	1
195	1	1
201	1	1
204	1	1
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
211	1	1
217	1	1
218	1	1
219	1	1
222	1	1
224	1	1
225	1	1
245	1	1
247	1	1
248	1	1
251	1	1
252	1	1
254	1	1
256	1	1
260	1	1
270	1	1
279	1	1
282	1	1
287	1	1
291	1	1
297	1	1
299	1	1
301	1	1
304	1	1
321	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
330	1	1
332	1	1
333	1	1
			MISSING_ELSE
347	1	1
349	1	1
352	1	1
353	1	1
356	1	1
357	1	1
360	1	1
368	1	1
369	1	1
370	1	1
372	1	1
373	1	1
374	1	1
376	1	1
377	1	1
379	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_addrfifo

	Total	Covered	Percent
Conditions	68	51	75.00
Logical	68	51	75.00
Non-Logical	0	0
Event	0	0

 LINE       121
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       153
 EXPRESSION ((w_wptr_p == w_rptr_p) ? (5'((w_wptr_v - w_rptr_v))) : (5'(({1'b1, w_wptr_v} - {1'b0, w_rptr_v}))))
             -----------1----------

-1-	Status	Tests
0	Covered	T6,T38,T18
1	Covered	T4,T5,T1

 LINE       153
 SUB-EXPRESSION (w_wptr_p == w_rptr_p)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       195
 EXPRESSION ((r_wptr_p == r_rptr_p) ? (5'((r_wptr_v - r_rptr_v))) : (5'(({1'b1, r_wptr_v} - {1'b0, r_rptr_v}))))
             -----------1----------

-1-	Status	Tests
0	Covered	T6,T38,T18
1	Covered	T4,T5,T1

 LINE       195
 SUB-EXPRESSION (r_wptr_p == r_rptr_p)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       211
 EXPRESSION (r_wptr == r_sram_rptr)
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       217
 EXPRESSION (w_wptr_q == (w_rptr ^ XorMask))
            ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Not Covered

 LINE       218
 EXPRESSION (r_wptr == (r_rptr_q ^ XorMask))
            ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Not Covered

 LINE       219
 EXPRESSION (r_wptr == r_rptr_q)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       247
 EXPRESSION (r_sram_req_o && r_sram_gnt_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       248
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       251
 EXPRESSION (wvalid_i && ((!w_full)))
             ----1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       252
 EXPRESSION (((!w_full)) && w_sram_gnt_i)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T6,T7

 LINE       282
 EXPRESSION (((!r_sramrptr_empty)) && rfifo_ack)
             ----------1----------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Not Covered
1	1	Not Covered

 LINE       287
 EXPRESSION (((!r_sramrptr_empty)) && ( ! (r_sram_rvalid_i ^ rfifo_ack) ))
             ----------1----------    -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       287
 SUB-EXPRESSION ( ! (r_sram_rvalid_i ^ rfifo_ack) )
                    --------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       287
 SUB-EXPRESSION (r_sram_rvalid_i ^ rfifo_ack)
                 -------1-------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Not Covered

 LINE       291
 EXPRESSION (stored || r_sram_rvalid_i)
             ---1--    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       299
 EXPRESSION (r_sram_rvalid_i ? r_sram_rdata_i[0+:Width] : (32'(0)))
             -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       301
 EXPRESSION (stored ? rdata_q : rdata_d)
             ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       321
 EXPRESSION (r_sram_rvalid_i && ( ! (stored ^ rfifo_ack) ))
             -------1-------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       321
 SUB-EXPRESSION ( ! (stored ^ rfifo_ack) )
                    ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       321
 SUB-EXPRESSION (stored ^ rfifo_ack)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       330
 EXPRESSION (((!r_sram_rvalid_i)) && rfifo_ack)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T6,T7

 LINE       349
 EXPRESSION (decval[(PtrW - 1)] ? decval_sub : decval)
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T38,T18

 LINE       370
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

---

Branch Coverage for Instance : tb.dut.u_upload.u_addrfifo

	Line No.	Total	Covered	Percent
Branches		27	27	100.00
TERNARY	153	2	2	100.00
TERNARY	195	2	2	100.00
TERNARY	299	2	2	100.00
TERNARY	301	2	2	100.00
IF	126	3	3	100.00
IF	168	3	3	100.00
IF	204	3	3	100.00
IF	279	2	2	100.00
IF	324	4	4	100.00
TERNARY	349	2	2	100.00
IF	373	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	153	((w_wptr_p == w_rptr_p)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T6,T38,T18

	LineNo.	Expression
-1-:	195	((r_wptr_p == r_rptr_p)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T6,T38,T18

	LineNo.	Expression
-1-:	299	(r_sram_rvalid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	301	(stored) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	126	if ((!rst_wr_ni))
-2-:	129	if (w_wptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	168	if ((!rst_rd_ni))
-2-:	171	if (r_rptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	204	if ((!rst_rd_ni))
-2-:	206	if (r_sram_rptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	279	if (stored)

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	324	if ((!rst_rd_ni))
-2-:	327	if (store_en)
-3-:	330	if (((!r_sram_rvalid_i) && rfifo_ack))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T6,T7
0	0	1	Covered	T3,T6,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	349	(decval[(PtrW - 1)]) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T38,T18
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	373	if (grayval[(PtrW - 1)])

Branches:

-1-	Status	Tests
1	Covered	T6,T38,T18
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_upload.u_addrfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinDepth_A	1613	1613	0	0
NoRAckInEmpty_A	2010348469	1635	0	0
NoWAckInFull_A	410997401	1635	0	0
ParamCheckDepth_A	1613	1613	0	0
RSramRvalidOneCycle_M	2010348469	1635	0	0
RptrGrayOneBitAtATime_A	2010348469	1635	0	0
RptrIncDataValid_A	2010348469	1635	0	0
RptrIncrease_A	2010348469	1635	0	0
SramRvalid_A	2010348469	1635	0	0
WSramRvalid_A	410997401	410997390	0	0
WidthMatch_A	1613	1613	0	0
WptrGrayOneBitAtATime_A	410997401	1635	0	0
WptrIncrease_A	410997401	1635	0	0

MinDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1613	1613	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

NoRAckInEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	1635	0	0
T3	122489	11	0	0
T6	362548	19	0	0
T7	317060	7	0	0
T8	1383	0	0	0
T11	298159	0	0	0
T12	53035	0	0	0
T15	2769	0	0	0
T18	0	18	0	0
T19	0	2	0	0
T20	0	5	0	0
T23	0	7	0	0
T26	0	52	0	0
T34	910	0	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	21	0	0
T46	0	21	0	0

NoWAckInFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	1635	0	0
T3	175606	11	0	0
T6	694998	19	0	0
T7	688652	7	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T15	4103	0	0	0
T17	73410	0	0	0
T18	0	18	0	0
T19	0	2	0	0
T20	0	5	0	0
T23	0	7	0	0
T26	0	52	0	0
T38	0	21	0	0
T46	0	21	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1613	1613	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

RSramRvalidOneCycle_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	1635	0	0
T3	122489	11	0	0
T6	362548	19	0	0
T7	317060	7	0	0
T8	1383	0	0	0
T11	298159	0	0	0
T12	53035	0	0	0
T15	2769	0	0	0
T18	0	18	0	0
T19	0	2	0	0
T20	0	5	0	0
T23	0	7	0	0
T26	0	52	0	0
T34	910	0	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	21	0	0
T46	0	21	0	0

RptrGrayOneBitAtATime_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	1635	0	0
T3	122489	11	0	0
T6	362548	19	0	0
T7	317060	7	0	0
T8	1383	0	0	0
T11	298159	0	0	0
T12	53035	0	0	0
T15	2769	0	0	0
T18	0	18	0	0
T19	0	2	0	0
T20	0	5	0	0
T23	0	7	0	0
T26	0	52	0	0
T34	910	0	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	21	0	0
T46	0	21	0	0

RptrIncDataValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	1635	0	0
T3	122489	11	0	0
T6	362548	19	0	0
T7	317060	7	0	0
T8	1383	0	0	0
T11	298159	0	0	0
T12	53035	0	0	0
T15	2769	0	0	0
T18	0	18	0	0
T19	0	2	0	0
T20	0	5	0	0
T23	0	7	0	0
T26	0	52	0	0
T34	910	0	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	21	0	0
T46	0	21	0	0

RptrIncrease_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	1635	0	0
T3	122489	11	0	0
T6	362548	19	0	0
T7	317060	7	0	0
T8	1383	0	0	0
T11	298159	0	0	0
T12	53035	0	0	0
T15	2769	0	0	0
T18	0	18	0	0
T19	0	2	0	0
T20	0	5	0	0
T23	0	7	0	0
T26	0	52	0	0
T34	910	0	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	21	0	0
T46	0	21	0	0

SramRvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	1635	0	0
T3	122489	11	0	0
T6	362548	19	0	0
T7	317060	7	0	0
T8	1383	0	0	0
T11	298159	0	0	0
T12	53035	0	0	0
T15	2769	0	0	0
T18	0	18	0	0
T19	0	2	0	0
T20	0	5	0	0
T23	0	7	0	0
T26	0	52	0	0
T34	910	0	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	21	0	0
T46	0	21	0	0

WSramRvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	410997390	0	0
T1	1	1	0	0
T2	3297	3297	0	0
T3	175606	175606	0	0
T4	360	360	0	0
T5	35200	35200	0	0
T6	694998	694998	0	0
T9	2410	2410	0	0
T11	92864	92864	0	0
T12	48385	48385	0	0
T15	4103	4103	0	0

WidthMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1613	1613	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

WptrGrayOneBitAtATime_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	1635	0	0
T3	175606	11	0	0
T6	694998	19	0	0
T7	688652	7	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T15	4103	0	0	0
T17	73410	0	0	0
T18	0	18	0	0
T19	0	2	0	0
T20	0	5	0	0
T23	0	7	0	0
T26	0	52	0	0
T38	0	21	0	0
T46	0	21	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

WptrIncrease_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	1635	0	0
T3	175606	11	0	0
T6	694998	19	0	0
T7	688652	7	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T15	4103	0	0	0
T17	73410	0	0	0
T18	0	18	0	0
T19	0	2	0	0
T20	0	5	0	0
T23	0	7	0	0
T26	0	52	0	0
T38	0	21	0	0
T46	0	21	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0