Unified Coverage Report :: Module :: spid_fifo2sram_adapter

Module : spid_fifo2sram_adapter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	77.78			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_payload_buffer	94.44	100.00	77.78			100.00	100.00

---

Module Instance : tb.dut.u_upload.u_payload_buffer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	77.78			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	77.78			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	87.18		100.00	96.30	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spid_fifo2sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		17	17	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	75	6	6	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
ALWAYS	96	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
51	1	1
55	1	1
56	1	1
61	1	1
72	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
			MISSING_ELSE
91	1	1
93	1	1
96	1	1
97	1	1
98	1	1
99	1	1
			MISSING_ELSE

---

Cond Coverage for Module : spid_fifo2sram_adapter

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       78
 EXPRESSION (fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       91
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T6,T7

 LINE       99
 EXPRESSION ((fifoptr == 8'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T3,T6,T7

 LINE       99
 SUB-EXPRESSION (fifoptr == 8'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T3,T6,T7

---

Branch Coverage for Module : spid_fifo2sram_adapter

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	96	4	4	100.00
IF	78	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if (fifoptr_inc)
-3-:	99	((fifoptr == 8'((FifoDepth - 1)))) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	1	Covered	T3,T6,T7
0	1	0	Covered	T3,T6,T7
0	0	-	Covered	T5,T2,T3

	LineNo.	Expression
-1-:	78	if ((fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Module : spid_fifo2sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A	1613	1613	0	0
g_multiple_entry_per_word.WidthDivideSramDw_A	1613	1613	0	0

g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1613	1613	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

g_multiple_entry_per_word.WidthDivideSramDw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1613	1613	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0