Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	419	1			T2	1		T3	5		T12	8
all_values[1]	419	1			T2	1		T3	5		T12	8
all_values[2]	419	1			T2	1		T3	5		T12	8
all_values[3]	419	1			T2	1		T3	5		T12	8
all_values[4]	419	1			T2	1		T3	5		T12	8
all_values[5]	419	1			T2	1		T3	5		T12	8
all_values[6]	419	1			T2	1		T3	5		T12	8
all_values[7]	419	1			T2	1		T3	5		T12	8
all_values[8]	419	1			T2	1		T3	5		T12	8
all_values[9]	419	1			T2	1		T3	5		T12	8
all_values[10]	419	1			T2	1		T3	5		T12	8
all_values[11]	419	1			T2	1		T3	5		T12	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2619

1

T2

12

T3

25

T12

41

auto[1]

2409

1

T3

35

T12

55

T13

50

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3076

1

T2

12

T3

42

T12

48

auto[1]

1952

1

T3

18

T12

48

T13

41

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	157	1			T2	1		T3	1		T12	6
all_values[0]	auto[0]	auto[1]	75	1			T13	1		T45	1		T46	2
all_values[0]	auto[1]	auto[0]	107	1			T3	1		T12	1		T13	3
all_values[0]	auto[1]	auto[1]	80	1			T3	3		T12	1		T13	3
all_values[1]	auto[0]	auto[0]	127	1			T2	1		T12	1		T45	5
all_values[1]	auto[0]	auto[1]	91	1			T3	1		T12	2		T13	1
all_values[1]	auto[1]	auto[0]	127	1			T3	3		T12	3		T13	4
all_values[1]	auto[1]	auto[1]	74	1			T3	1		T12	2		T13	3
all_values[2]	auto[0]	auto[0]	141	1			T2	1		T3	3		T12	2
all_values[2]	auto[0]	auto[1]	76	1			T3	1		T12	3		T13	1
all_values[2]	auto[1]	auto[0]	127	1			T3	1		T12	1		T13	3
all_values[2]	auto[1]	auto[1]	75	1			T12	2		T46	4		T56	1
all_values[3]	auto[0]	auto[0]	140	1			T2	1		T12	1		T13	1
all_values[3]	auto[0]	auto[1]	72	1			T3	1		T12	1		T13	3
all_values[3]	auto[1]	auto[0]	117	1			T3	4		T12	1		T13	1
all_values[3]	auto[1]	auto[1]	90	1			T12	5		T13	3		T45	3
all_values[4]	auto[0]	auto[0]	120	1			T2	1		T3	1		T13	4
all_values[4]	auto[0]	auto[1]	84	1			T12	2		T13	2		T45	6
all_values[4]	auto[1]	auto[0]	136	1			T3	4		T12	3		T13	1
all_values[4]	auto[1]	auto[1]	79	1			T12	3		T13	1		T45	1
all_values[5]	auto[0]	auto[0]	134	1			T2	1		T3	3		T12	2
all_values[5]	auto[0]	auto[1]	68	1			T12	3		T13	2		T45	2
all_values[5]	auto[1]	auto[0]	127	1			T3	1		T13	1		T44	2
all_values[5]	auto[1]	auto[1]	90	1			T3	1		T12	3		T13	2
all_values[6]	auto[0]	auto[0]	153	1			T2	1		T3	1		T12	2
all_values[6]	auto[0]	auto[1]	94	1			T3	2		T13	1		T45	1
all_values[6]	auto[1]	auto[0]	97	1			T3	2		T12	5		T13	5
all_values[6]	auto[1]	auto[1]	75	1			T12	1		T44	1		T45	5
all_values[7]	auto[0]	auto[0]	136	1			T2	1		T3	1		T13	2
all_values[7]	auto[0]	auto[1]	86	1			T3	1		T12	1		T13	5
all_values[7]	auto[1]	auto[0]	115	1			T3	3		T12	3		T44	1
all_values[7]	auto[1]	auto[1]	82	1			T12	4		T13	1		T45	2
all_values[8]	auto[0]	auto[0]	145	1			T2	1		T3	4		T13	1
all_values[8]	auto[0]	auto[1]	85	1			T12	5		T13	2		T44	2
all_values[8]	auto[1]	auto[0]	123	1			T12	1		T13	3		T44	1
all_values[8]	auto[1]	auto[1]	66	1			T3	1		T12	2		T13	2
all_values[9]	auto[0]	auto[0]	124	1			T2	1		T3	1		T12	4
all_values[9]	auto[0]	auto[1]	94	1			T3	3		T12	1		T44	1
all_values[9]	auto[1]	auto[0]	112	1			T3	1		T12	1		T13	3
all_values[9]	auto[1]	auto[1]	89	1			T12	2		T44	1		T45	3
all_values[10]	auto[0]	auto[0]	127	1			T2	1		T12	1		T13	1
all_values[10]	auto[0]	auto[1]	87	1			T3	1		T12	1		T45	3
all_values[10]	auto[1]	auto[0]	115	1			T3	4		T12	5		T13	2
all_values[10]	auto[1]	auto[1]	90	1			T12	1		T13	5		T44	1
all_values[11]	auto[0]	auto[0]	138	1			T2	1		T12	1		T13	2
all_values[11]	auto[0]	auto[1]	65	1			T12	2		T13	2		T45	1
all_values[11]	auto[1]	auto[0]	131	1			T3	3		T12	4		T13	3
all_values[11]	auto[1]	auto[1]	85	1			T3	2		T12	1		T13	1