Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
60.02	71.17	76.17	75.34	0.00	77.00	100.00	20.49

Total tests in report: 175

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
52.71	52.71	70.84	70.84	74.18	74.18	57.18	57.18	0.00	0.00	76.85	76.85	82.61	82.61	7.34	7.34	/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.719236717
58.77	6.06	70.84	0.00	74.42	0.24	83.60	26.42	0.00	0.00	76.93	0.08	98.21	15.60	7.38	0.05	/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2976874269
60.55	1.78	71.07	0.23	74.94	0.52	86.10	2.51	0.00	0.00	76.93	0.00	98.21	0.00	16.58	9.19	/workspace/coverage/cover_reg_top/7.spi_device_intr_test.478430328
61.34	0.79	71.15	0.07	76.02	1.08	87.02	0.91	0.00	0.00	76.97	0.03	100.00	1.79	18.20	1.62	/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2749721619
61.59	0.26	71.17	0.02	76.07	0.05	87.70	0.68	0.00	0.00	77.00	0.03	100.00	0.00	19.20	1.00	/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1316897517
61.70	0.11	71.17	0.00	76.07	0.00	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	19.96	0.76	/workspace/coverage/cover_reg_top/36.spi_device_intr_test.3081364322
61.75	0.05	71.17	0.00	76.07	0.00	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.30	0.33	/workspace/coverage/cover_reg_top/44.spi_device_intr_test.45669004
61.77	0.02	71.17	0.00	76.07	0.00	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.44	0.14	/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1439923664
61.78	0.01	71.17	0.00	76.15	0.08	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.44	0.00	/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.277030106
61.79	0.01	71.17	0.00	76.15	0.00	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.49	0.05	/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2891638742
61.79	0.01	71.17	0.00	76.17	0.03	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.49	0.00	/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3358791028

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1121795513
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.443119400
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1201742033
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.886568447
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.3100312051
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1139062409
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.480290015
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.959192210
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1327332469
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1360390209
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2070288727
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3166343796
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.98990855
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2588312970
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1510076258
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1737970973
/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2779095763
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1154013740
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2911735002
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2191910785
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.3645782892
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.538988619
/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1269972864
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2570566124
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.417481923
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.1687802294
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.891731670
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1818473816
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1462720368
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3388767707
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1405458266
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.3502351690
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3836472658
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1564875935
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1273776946
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2561719758
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.265221719
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.1252514431
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3441251419
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3538958404
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1790121456
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1962984918
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1133687161
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.2205305266
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1386814243
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.964981401
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2723602241
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2949624663
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.152282237
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3045790133
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1543482683
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2199720847
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3818001202
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1351990471
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.2347594618
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3653290136
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2219707078
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1114499334
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1454354393
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1593833468
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.2950826042
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3003177083
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3571784999
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2374278878
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2740356101
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.1150540991
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3151904921
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1105560427
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1824634512
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3290734998
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1687323605
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.1861774641
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1163644577
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2043288924
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3835678235
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1769413127
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1127472426
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2009618947
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2535569148
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.906569023
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.1692038570
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3364133951
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1364950166
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1216351155
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1520625515
/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3443773618
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.364343065
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.111070593
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.1192841689
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.3849251708
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.3326739721
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.1002722949
/workspace/coverage/cover_reg_top/26.spi_device_intr_test.199633481
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.4055723408
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.1433581471
/workspace/coverage/cover_reg_top/29.spi_device_intr_test.2989569116
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.311682564
/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2234213669
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1977308628
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.864421546
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1418260194
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.3242486763
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2353561508
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2117173287
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2086717319
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.461920503
/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3814083055
/workspace/coverage/cover_reg_top/30.spi_device_intr_test.1706945920
/workspace/coverage/cover_reg_top/31.spi_device_intr_test.800015204
/workspace/coverage/cover_reg_top/32.spi_device_intr_test.1766377297
/workspace/coverage/cover_reg_top/33.spi_device_intr_test.1152869936
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.3343584867
/workspace/coverage/cover_reg_top/35.spi_device_intr_test.77925346
/workspace/coverage/cover_reg_top/37.spi_device_intr_test.2023673163
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.879992613
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.2284841896
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2936864104
/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.317546857
/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4139484333
/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3630098855
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2655633340
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.3002841006
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3825304025
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3614844792
/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4268382377
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.892689842
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.4074546175
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.2318982305
/workspace/coverage/cover_reg_top/42.spi_device_intr_test.2361877991
/workspace/coverage/cover_reg_top/43.spi_device_intr_test.4097658362
/workspace/coverage/cover_reg_top/45.spi_device_intr_test.23374501
/workspace/coverage/cover_reg_top/46.spi_device_intr_test.2896453961
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.3686557806
/workspace/coverage/cover_reg_top/48.spi_device_intr_test.2357923392
/workspace/coverage/cover_reg_top/49.spi_device_intr_test.1857478122
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3461006980
/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.709921894
/workspace/coverage/cover_reg_top/5.spi_device_intr_test.1659743677
/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4195067582
/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1043134551
/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1801245830
/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2345030721
/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2258402496
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.4243369888
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.204825240
/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2174793138
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2556288090
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.908962069
/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.363652866
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3997287422
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2973935464
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1020414983
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.274739254
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2202933084
/workspace/coverage/cover_reg_top/8.spi_device_intr_test.950039051
/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.176113426
/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.761153178
/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2465448285
/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3963252877
/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1537984353
/workspace/coverage/cover_reg_top/9.spi_device_intr_test.3267823456
/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3779674843
/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.912555118
/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2723906689

Total test records in report: 175

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1510076258	Jan 10 12:29:47 PM PST 24	Jan 10 12:30:25 PM PST 24	74479283 ps
T2	/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2749721619	Jan 10 12:27:49 PM PST 24	Jan 10 12:28:08 PM PST 24	97840288 ps
T3	/workspace/coverage/cover_reg_top/20.spi_device_intr_test.364343065	Jan 10 12:29:54 PM PST 24	Jan 10 12:30:32 PM PST 24	44028645 ps
T8	/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2191910785	Jan 10 12:25:17 PM PST 24	Jan 10 12:25:20 PM PST 24	40618474 ps
T7	/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.317546857	Jan 10 12:30:26 PM PST 24	Jan 10 12:31:21 PM PST 24	702715342 ps
T14	/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2588312970	Jan 10 12:27:27 PM PST 24	Jan 10 12:27:36 PM PST 24	197887640 ps
T15	/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3825304025	Jan 10 12:30:00 PM PST 24	Jan 10 12:30:47 PM PST 24	203189516 ps
T4	/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2911735002	Jan 10 12:25:31 PM PST 24	Jan 10 12:25:33 PM PST 24	26442670 ps
T11	/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.719236717	Jan 10 12:23:39 PM PST 24	Jan 10 12:23:56 PM PST 24	258746144 ps
T12	/workspace/coverage/cover_reg_top/36.spi_device_intr_test.3081364322	Jan 10 12:26:31 PM PST 24	Jan 10 12:26:35 PM PST 24	66603467 ps
T5	/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3358791028	Jan 10 12:29:39 PM PST 24	Jan 10 12:30:11 PM PST 24	664030802 ps
T13	/workspace/coverage/cover_reg_top/45.spi_device_intr_test.23374501	Jan 10 12:26:40 PM PST 24	Jan 10 12:26:46 PM PST 24	15136045 ps
T16	/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1139062409	Jan 10 12:24:14 PM PST 24	Jan 10 12:24:19 PM PST 24	60265736 ps
T44	/workspace/coverage/cover_reg_top/5.spi_device_intr_test.1659743677	Jan 10 12:29:01 PM PST 24	Jan 10 12:29:21 PM PST 24	25199894 ps
T45	/workspace/coverage/cover_reg_top/41.spi_device_intr_test.2318982305	Jan 10 12:26:16 PM PST 24	Jan 10 12:26:20 PM PST 24	25817905 ps
T46	/workspace/coverage/cover_reg_top/46.spi_device_intr_test.2896453961	Jan 10 12:27:31 PM PST 24	Jan 10 12:27:37 PM PST 24	45849633 ps
T6	/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2374278878	Jan 10 12:28:22 PM PST 24	Jan 10 12:28:37 PM PST 24	25599911 ps
T56	/workspace/coverage/cover_reg_top/33.spi_device_intr_test.1152869936	Jan 10 12:25:42 PM PST 24	Jan 10 12:25:43 PM PST 24	12191436 ps
T57	/workspace/coverage/cover_reg_top/7.spi_device_intr_test.478430328	Jan 10 12:29:13 PM PST 24	Jan 10 12:29:36 PM PST 24	14029626 ps
T9	/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2570566124	Jan 10 12:26:50 PM PST 24	Jan 10 12:26:56 PM PST 24	34811648 ps
T10	/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2976874269	Jan 10 12:26:23 PM PST 24	Jan 10 12:26:28 PM PST 24	3251841281 ps
T17	/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2535569148	Jan 10 12:28:28 PM PST 24	Jan 10 12:28:42 PM PST 24	60985206 ps
T47	/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1439923664	Jan 10 12:30:00 PM PST 24	Jan 10 12:30:55 PM PST 24	2028774104 ps
T59	/workspace/coverage/cover_reg_top/44.spi_device_intr_test.45669004	Jan 10 12:24:57 PM PST 24	Jan 10 12:24:59 PM PST 24	15897309 ps
T19	/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3814083055	Jan 10 12:30:49 PM PST 24	Jan 10 12:31:54 PM PST 24	1021970684 ps
T60	/workspace/coverage/cover_reg_top/40.spi_device_intr_test.4074546175	Jan 10 12:28:25 PM PST 24	Jan 10 12:28:37 PM PST 24	29248641 ps
T43	/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1127472426	Jan 10 12:23:31 PM PST 24	Jan 10 12:23:46 PM PST 24	909342988 ps
T18	/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3614844792	Jan 10 12:27:03 PM PST 24	Jan 10 12:27:14 PM PST 24	301034314 ps
T31	/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3003177083	Jan 10 12:29:16 PM PST 24	Jan 10 12:29:42 PM PST 24	64710176 ps
T52	/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3461006980	Jan 10 12:29:19 PM PST 24	Jan 10 12:29:45 PM PST 24	18382626 ps
T32	/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3151904921	Jan 10 12:29:15 PM PST 24	Jan 10 12:29:42 PM PST 24	758835042 ps
T20	/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1824634512	Jan 10 12:27:03 PM PST 24	Jan 10 12:27:16 PM PST 24	470667025 ps
T69	/workspace/coverage/cover_reg_top/31.spi_device_intr_test.800015204	Jan 10 12:38:18 PM PST 24	Jan 10 12:38:54 PM PST 24	48139761 ps
T70	/workspace/coverage/cover_reg_top/0.spi_device_intr_test.3100312051	Jan 10 12:23:54 PM PST 24	Jan 10 12:23:55 PM PST 24	78986950 ps
T33	/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2353561508	Jan 10 12:27:50 PM PST 24	Jan 10 12:28:10 PM PST 24	273707773 ps
T41	/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3836472658	Jan 10 12:26:51 PM PST 24	Jan 10 12:26:58 PM PST 24	43542551 ps
T62	/workspace/coverage/cover_reg_top/43.spi_device_intr_test.4097658362	Jan 10 12:24:57 PM PST 24	Jan 10 12:24:59 PM PST 24	11198697 ps
T34	/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2949624663	Jan 10 12:27:03 PM PST 24	Jan 10 12:27:11 PM PST 24	270878242 ps
T21	/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.538988619	Jan 10 12:27:28 PM PST 24	Jan 10 12:27:37 PM PST 24	257284069 ps
T22	/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2723906689	Jan 10 12:28:36 PM PST 24	Jan 10 12:28:55 PM PST 24	768693359 ps
T35	/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2936864104	Jan 10 12:27:01 PM PST 24	Jan 10 12:27:17 PM PST 24	1835671863 ps
T42	/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3166343796	Jan 10 12:28:07 PM PST 24	Jan 10 12:28:24 PM PST 24	132734407 ps
T53	/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.443119400	Jan 10 12:27:18 PM PST 24	Jan 10 12:27:38 PM PST 24	1289293625 ps
T71	/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.864421546	Jan 10 12:30:36 PM PST 24	Jan 10 12:31:20 PM PST 24	63230059 ps
T28	/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2199720847	Jan 10 12:28:41 PM PST 24	Jan 10 12:29:05 PM PST 24	208521313 ps
T72	/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.908962069	Jan 10 12:25:42 PM PST 24	Jan 10 12:25:44 PM PST 24	64243944 ps
T54	/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3630098855	Jan 10 12:24:40 PM PST 24	Jan 10 12:24:43 PM PST 24	33566005 ps
T73	/workspace/coverage/cover_reg_top/34.spi_device_intr_test.3343584867	Jan 10 12:28:24 PM PST 24	Jan 10 12:28:36 PM PST 24	17270592 ps
T63	/workspace/coverage/cover_reg_top/24.spi_device_intr_test.3326739721	Jan 10 12:27:24 PM PST 24	Jan 10 12:27:30 PM PST 24	14703802 ps
T23	/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1316897517	Jan 10 12:23:50 PM PST 24	Jan 10 12:24:10 PM PST 24	3423992949 ps
T36	/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1405458266	Jan 10 12:26:51 PM PST 24	Jan 10 12:26:56 PM PST 24	36666556 ps
T66	/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1114499334	Jan 10 12:28:00 PM PST 24	Jan 10 12:28:23 PM PST 24	343776904 ps
T55	/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3779674843	Jan 10 12:30:29 PM PST 24	Jan 10 12:31:16 PM PST 24	225079657 ps
T74	/workspace/coverage/cover_reg_top/32.spi_device_intr_test.1766377297	Jan 10 12:23:42 PM PST 24	Jan 10 12:23:44 PM PST 24	14361981 ps
T75	/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1360390209	Jan 10 12:28:18 PM PST 24	Jan 10 12:28:56 PM PST 24	394724062 ps
T29	/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1962984918	Jan 10 12:29:18 PM PST 24	Jan 10 12:29:44 PM PST 24	153641664 ps
T37	/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1418260194	Jan 10 12:27:38 PM PST 24	Jan 10 12:27:49 PM PST 24	42710950 ps
T76	/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.891731670	Jan 10 12:26:23 PM PST 24	Jan 10 12:26:27 PM PST 24	82290195 ps
T30	/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1801245830	Jan 10 12:29:56 PM PST 24	Jan 10 12:30:46 PM PST 24	395917325 ps
T24	/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.912555118	Jan 10 12:24:27 PM PST 24	Jan 10 12:24:30 PM PST 24	63064046 ps
T77	/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.886568447	Jan 10 12:30:25 PM PST 24	Jan 10 12:31:08 PM PST 24	241640237 ps
T25	/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2043288924	Jan 10 12:28:01 PM PST 24	Jan 10 12:28:19 PM PST 24	119450031 ps
T61	/workspace/coverage/cover_reg_top/4.spi_device_intr_test.3002841006	Jan 10 12:30:00 PM PST 24	Jan 10 12:30:43 PM PST 24	15172669 ps
T49	/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2009618947	Jan 10 12:23:37 PM PST 24	Jan 10 12:23:39 PM PST 24	27617171 ps
T78	/workspace/coverage/cover_reg_top/13.spi_device_intr_test.1252514431	Jan 10 12:27:31 PM PST 24	Jan 10 12:27:37 PM PST 24	16842274 ps
T79	/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.959192210	Jan 10 12:27:58 PM PST 24	Jan 10 12:28:14 PM PST 24	65678861 ps
T80	/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2891638742	Jan 10 12:29:52 PM PST 24	Jan 10 12:30:31 PM PST 24	60489508 ps
T58	/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3388767707	Jan 10 12:29:15 PM PST 24	Jan 10 12:29:41 PM PST 24	33797316 ps
T81	/workspace/coverage/cover_reg_top/39.spi_device_intr_test.2284841896	Jan 10 12:26:33 PM PST 24	Jan 10 12:26:37 PM PST 24	69428561 ps
T82	/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1687323605	Jan 10 12:26:48 PM PST 24	Jan 10 12:26:54 PM PST 24	31506385 ps
T50	/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4139484333	Jan 10 12:29:39 PM PST 24	Jan 10 12:30:11 PM PST 24	71081426 ps
T38	/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2234213669	Jan 10 12:27:49 PM PST 24	Jan 10 12:28:28 PM PST 24	1615912764 ps
T83	/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1454354393	Jan 10 12:24:45 PM PST 24	Jan 10 12:24:49 PM PST 24	159138046 ps
T84	/workspace/coverage/cover_reg_top/19.spi_device_intr_test.1861774641	Jan 10 12:28:53 PM PST 24	Jan 10 12:29:13 PM PST 24	39377214 ps
T85	/workspace/coverage/cover_reg_top/22.spi_device_intr_test.1192841689	Jan 10 12:26:01 PM PST 24	Jan 10 12:26:12 PM PST 24	15499638 ps
T26	/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3571784999	Jan 10 12:24:17 PM PST 24	Jan 10 12:24:23 PM PST 24	62876737 ps
T39	/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3364133951	Jan 10 12:30:20 PM PST 24	Jan 10 12:31:06 PM PST 24	228917107 ps
T86	/workspace/coverage/cover_reg_top/15.spi_device_intr_test.152282237	Jan 10 12:27:51 PM PST 24	Jan 10 12:28:07 PM PST 24	25406071 ps
T87	/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2202933084	Jan 10 12:29:15 PM PST 24	Jan 10 12:29:41 PM PST 24	431001715 ps
T40	/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1537984353	Jan 10 12:28:04 PM PST 24	Jan 10 12:28:22 PM PST 24	101342831 ps
T88	/workspace/coverage/cover_reg_top/17.spi_device_intr_test.2950826042	Jan 10 12:25:21 PM PST 24	Jan 10 12:25:23 PM PST 24	10730882 ps
T27	/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2973935464	Jan 10 12:24:43 PM PST 24	Jan 10 12:24:49 PM PST 24	232602350 ps
T89	/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1020414983	Jan 10 12:28:07 PM PST 24	Jan 10 12:28:43 PM PST 24	7485637309 ps
T90	/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.964981401	Jan 10 12:30:35 PM PST 24	Jan 10 12:31:24 PM PST 24	440844487 ps
T91	/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.204825240	Jan 10 12:24:59 PM PST 24	Jan 10 12:25:03 PM PST 24	93879519 ps
T68	/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1273776946	Jan 10 12:26:59 PM PST 24	Jan 10 12:27:23 PM PST 24	580581635 ps
T92	/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3963252877	Jan 10 12:25:59 PM PST 24	Jan 10 12:26:13 PM PST 24	462144630 ps
T93	/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1351990471	Jan 10 12:27:23 PM PST 24	Jan 10 12:27:31 PM PST 24	140068395 ps
T94	/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.709921894	Jan 10 12:27:01 PM PST 24	Jan 10 12:27:09 PM PST 24	22865756 ps
T64	/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1154013740	Jan 10 12:29:16 PM PST 24	Jan 10 12:29:57 PM PST 24	614512066 ps
T95	/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2117173287	Jan 10 12:27:19 PM PST 24	Jan 10 12:27:35 PM PST 24	626593496 ps
T96	/workspace/coverage/cover_reg_top/2.spi_device_intr_test.1692038570	Jan 10 12:23:29 PM PST 24	Jan 10 12:23:31 PM PST 24	15331269 ps
T48	/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1564875935	Jan 10 12:30:24 PM PST 24	Jan 10 12:31:10 PM PST 24	243476315 ps
T97	/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2723602241	Jan 10 12:26:57 PM PST 24	Jan 10 12:27:06 PM PST 24	33183181 ps
T98	/workspace/coverage/cover_reg_top/3.spi_device_intr_test.3242486763	Jan 10 12:27:48 PM PST 24	Jan 10 12:28:01 PM PST 24	12043010 ps
T99	/workspace/coverage/cover_reg_top/42.spi_device_intr_test.2361877991	Jan 10 12:28:08 PM PST 24	Jan 10 12:28:24 PM PST 24	48314227 ps
T51	/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.277030106	Jan 10 12:26:50 PM PST 24	Jan 10 12:27:00 PM PST 24	227592494 ps
T100	/workspace/coverage/cover_reg_top/37.spi_device_intr_test.2023673163	Jan 10 12:29:41 PM PST 24	Jan 10 12:30:15 PM PST 24	14282582 ps
T101	/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1593833468	Jan 10 12:27:31 PM PST 24	Jan 10 12:27:38 PM PST 24	133427695 ps
T102	/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1163644577	Jan 10 12:27:37 PM PST 24	Jan 10 12:27:47 PM PST 24	723129324 ps
T103	/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1043134551	Jan 10 12:30:00 PM PST 24	Jan 10 12:30:50 PM PST 24	550886191 ps
T104	/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2086717319	Jan 10 12:30:41 PM PST 24	Jan 10 12:31:28 PM PST 24	406758149 ps
T105	/workspace/coverage/cover_reg_top/12.spi_device_intr_test.3502351690	Jan 10 12:26:51 PM PST 24	Jan 10 12:26:56 PM PST 24	42992431 ps
T106	/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3443773618	Jan 10 12:28:28 PM PST 24	Jan 10 12:28:47 PM PST 24	1189924798 ps
T107	/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1216351155	Jan 10 12:28:28 PM PST 24	Jan 10 12:28:43 PM PST 24	903144403 ps
T108	/workspace/coverage/cover_reg_top/27.spi_device_intr_test.4055723408	Jan 10 12:26:31 PM PST 24	Jan 10 12:26:35 PM PST 24	25583215 ps
T109	/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.906569023	Jan 10 12:28:28 PM PST 24	Jan 10 12:28:41 PM PST 24	260936127 ps
T110	/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2345030721	Jan 10 12:24:27 PM PST 24	Jan 10 12:24:29 PM PST 24	77133696 ps
T111	/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.274739254	Jan 10 12:29:48 PM PST 24	Jan 10 12:30:24 PM PST 24	126166363 ps
T112	/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.417481923	Jan 10 12:32:15 PM PST 24	Jan 10 12:32:58 PM PST 24	59079580 ps
T113	/workspace/coverage/cover_reg_top/38.spi_device_intr_test.879992613	Jan 10 12:30:01 PM PST 24	Jan 10 12:30:43 PM PST 24	27345371 ps
T114	/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3538958404	Jan 10 12:24:59 PM PST 24	Jan 10 12:25:03 PM PST 24	40889454 ps
T115	/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1364950166	Jan 10 12:31:41 PM PST 24	Jan 10 12:32:40 PM PST 24	266975533 ps
T116	/workspace/coverage/cover_reg_top/35.spi_device_intr_test.77925346	Jan 10 12:28:28 PM PST 24	Jan 10 12:28:39 PM PST 24	50760833 ps
T117	/workspace/coverage/cover_reg_top/48.spi_device_intr_test.2357923392	Jan 10 12:25:13 PM PST 24	Jan 10 12:25:14 PM PST 24	27842856 ps
T118	/workspace/coverage/cover_reg_top/25.spi_device_intr_test.1002722949	Jan 10 12:26:33 PM PST 24	Jan 10 12:26:37 PM PST 24	28384154 ps
T119	/workspace/coverage/cover_reg_top/1.spi_device_intr_test.98990855	Jan 10 12:29:53 PM PST 24	Jan 10 12:30:35 PM PST 24	28329116 ps
T65	/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2465448285	Jan 10 12:30:26 PM PST 24	Jan 10 12:31:20 PM PST 24	1281815114 ps
T120	/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2655633340	Jan 10 12:25:39 PM PST 24	Jan 10 12:25:41 PM PST 24	98471465 ps
T121	/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2740356101	Jan 10 12:23:55 PM PST 24	Jan 10 12:23:58 PM PST 24	95973230 ps
T122	/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1105560427	Jan 10 12:29:06 PM PST 24	Jan 10 12:29:32 PM PST 24	714624565 ps
T123	/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1790121456	Jan 10 12:26:51 PM PST 24	Jan 10 12:27:14 PM PST 24	1306913483 ps
T67	/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.892689842	Jan 10 12:27:49 PM PST 24	Jan 10 12:28:15 PM PST 24	1236721942 ps
T124	/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.311682564	Jan 10 12:29:54 PM PST 24	Jan 10 12:30:49 PM PST 24	4890028409 ps
T125	/workspace/coverage/cover_reg_top/6.spi_device_intr_test.4243369888	Jan 10 12:26:34 PM PST 24	Jan 10 12:26:38 PM PST 24	82918742 ps
T126	/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2561719758	Jan 10 12:29:02 PM PST 24	Jan 10 12:29:23 PM PST 24	58094969 ps
T127	/workspace/coverage/cover_reg_top/30.spi_device_intr_test.1706945920	Jan 10 12:27:32 PM PST 24	Jan 10 12:27:38 PM PST 24	11393039 ps
T128	/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2556288090	Jan 10 12:25:04 PM PST 24	Jan 10 12:25:22 PM PST 24	2976038473 ps
T129	/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.265221719	Jan 10 12:29:04 PM PST 24	Jan 10 12:29:27 PM PST 24	91235467 ps
T130	/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1327332469	Jan 10 12:29:45 PM PST 24	Jan 10 12:30:21 PM PST 24	71093280 ps
T131	/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3290734998	Jan 10 12:29:56 PM PST 24	Jan 10 12:30:36 PM PST 24	20242970 ps
T132	/workspace/coverage/cover_reg_top/47.spi_device_intr_test.3686557806	Jan 10 12:27:07 PM PST 24	Jan 10 12:27:14 PM PST 24	40708023 ps
T133	/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1818473816	Jan 10 12:31:28 PM PST 24	Jan 10 12:32:22 PM PST 24	1305386798 ps
T134	/workspace/coverage/cover_reg_top/26.spi_device_intr_test.199633481	Jan 10 12:27:24 PM PST 24	Jan 10 12:27:30 PM PST 24	22327404 ps
T135	/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.176113426	Jan 10 12:27:31 PM PST 24	Jan 10 12:27:38 PM PST 24	134013892 ps
T136	/workspace/coverage/cover_reg_top/49.spi_device_intr_test.1857478122	Jan 10 12:27:07 PM PST 24	Jan 10 12:27:14 PM PST 24	63297525 ps
T137	/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3818001202	Jan 10 12:27:24 PM PST 24	Jan 10 12:27:30 PM PST 24	16714007 ps
T138	/workspace/coverage/cover_reg_top/9.spi_device_intr_test.3267823456	Jan 10 12:30:55 PM PST 24	Jan 10 12:31:42 PM PST 24	15480634 ps
T139	/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.363652866	Jan 10 12:23:51 PM PST 24	Jan 10 12:23:53 PM PST 24	152422567 ps
T140	/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1386814243	Jan 10 12:29:18 PM PST 24	Jan 10 12:29:46 PM PST 24	965728071 ps
T141	/workspace/coverage/cover_reg_top/21.spi_device_intr_test.111070593	Jan 10 12:30:26 PM PST 24	Jan 10 12:31:08 PM PST 24	15028994 ps
T142	/workspace/coverage/cover_reg_top/28.spi_device_intr_test.1433581471	Jan 10 12:30:26 PM PST 24	Jan 10 12:31:07 PM PST 24	34979055 ps
T143	/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1121795513	Jan 10 12:29:17 PM PST 24	Jan 10 12:29:57 PM PST 24	3666716574 ps
T144	/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1543482683	Jan 10 12:28:22 PM PST 24	Jan 10 12:28:37 PM PST 24	292642194 ps
T145	/workspace/coverage/cover_reg_top/16.spi_device_intr_test.2347594618	Jan 10 12:28:06 PM PST 24	Jan 10 12:28:22 PM PST 24	14964839 ps
T146	/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1201742033	Jan 10 12:27:59 PM PST 24	Jan 10 12:28:14 PM PST 24	20822858 ps
T147	/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4268382377	Jan 10 12:29:17 PM PST 24	Jan 10 12:29:44 PM PST 24	1272213929 ps
T148	/workspace/coverage/cover_reg_top/14.spi_device_intr_test.2205305266	Jan 10 12:28:38 PM PST 24	Jan 10 12:28:51 PM PST 24	50978758 ps
T149	/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4195067582	Jan 10 12:29:16 PM PST 24	Jan 10 12:29:41 PM PST 24	83386644 ps
T150	/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3997287422	Jan 10 12:29:16 PM PST 24	Jan 10 12:29:48 PM PST 24	564528853 ps
T151	/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1769413127	Jan 10 12:28:28 PM PST 24	Jan 10 12:28:48 PM PST 24	535154993 ps
T152	/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3045790133	Jan 10 12:29:18 PM PST 24	Jan 10 12:29:46 PM PST 24	263467791 ps
T153	/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3835678235	Jan 10 12:25:29 PM PST 24	Jan 10 12:25:43 PM PST 24	212285364 ps
T154	/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.761153178	Jan 10 12:30:26 PM PST 24	Jan 10 12:31:10 PM PST 24	454189990 ps
T155	/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1269972864	Jan 10 12:23:50 PM PST 24	Jan 10 12:24:08 PM PST 24	1233371021 ps
T156	/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1133687161	Jan 10 12:25:40 PM PST 24	Jan 10 12:25:44 PM PST 24	120853539 ps
T157	/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.480290015	Jan 10 12:29:30 PM PST 24	Jan 10 12:30:01 PM PST 24	3176071626 ps
T158	/workspace/coverage/cover_reg_top/11.spi_device_intr_test.1687802294	Jan 10 12:28:37 PM PST 24	Jan 10 12:28:50 PM PST 24	14179506 ps
T159	/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2219707078	Jan 10 12:24:17 PM PST 24	Jan 10 12:24:20 PM PST 24	29521672 ps
T160	/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3653290136	Jan 10 12:29:07 PM PST 24	Jan 10 12:29:30 PM PST 24	454663939 ps
T161	/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2174793138	Jan 10 12:29:16 PM PST 24	Jan 10 12:29:42 PM PST 24	24596208 ps
T162	/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2779095763	Jan 10 12:29:17 PM PST 24	Jan 10 12:29:45 PM PST 24	47830758 ps
T163	/workspace/coverage/cover_reg_top/18.spi_device_intr_test.1150540991	Jan 10 12:25:59 PM PST 24	Jan 10 12:26:11 PM PST 24	48342861 ps
T164	/workspace/coverage/cover_reg_top/23.spi_device_intr_test.3849251708	Jan 10 12:27:39 PM PST 24	Jan 10 12:27:48 PM PST 24	47845092 ps
T165	/workspace/coverage/cover_reg_top/8.spi_device_intr_test.950039051	Jan 10 12:29:18 PM PST 24	Jan 10 12:29:43 PM PST 24	17468745 ps
T166	/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1977308628	Jan 10 12:23:30 PM PST 24	Jan 10 12:23:32 PM PST 24	131969992 ps
T167	/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1520625515	Jan 10 12:28:29 PM PST 24	Jan 10 12:28:41 PM PST 24	124846299 ps
T168	/workspace/coverage/cover_reg_top/29.spi_device_intr_test.2989569116	Jan 10 12:31:34 PM PST 24	Jan 10 12:32:25 PM PST 24	50654527 ps
T169	/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.461920503	Jan 10 12:27:44 PM PST 24	Jan 10 12:28:00 PM PST 24	60012950 ps
T170	/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3441251419	Jan 10 12:27:30 PM PST 24	Jan 10 12:27:39 PM PST 24	123102713 ps
T171	/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2070288727	Jan 10 12:28:09 PM PST 24	Jan 10 12:28:27 PM PST 24	21775620 ps
T172	/workspace/coverage/cover_reg_top/10.spi_device_intr_test.3645782892	Jan 10 12:29:16 PM PST 24	Jan 10 12:29:41 PM PST 24	36199612 ps
T173	/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1737970973	Jan 10 12:29:15 PM PST 24	Jan 10 12:29:40 PM PST 24	174185565 ps
T174	/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1462720368	Jan 10 12:28:04 PM PST 24	Jan 10 12:28:32 PM PST 24	865572390 ps
T175	/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2258402496	Jan 10 12:30:34 PM PST 24	Jan 10 12:31:18 PM PST 24	353834705 ps

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.719236717
Short name	T11
Test name
Test status
Simulation time	258746144 ps
CPU time	16.74 seconds
Started	Jan 10 12:23:39 PM PST 24
Finished	Jan 10 12:23:56 PM PST 24
Peak memory	217012 kb
Host	smart-3ddfb1e7-2982-4490-8a6b-a2ec847842ed
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719236717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr _aliasing.719236717
Directory	/workspace/1.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2976874269
Short name	T10
Test name
Test status
Simulation time	3251841281 ps
CPU time	4.08 seconds
Started	Jan 10 12:26:23 PM PST 24
Finished	Jan 10 12:26:28 PM PST 24
Peak memory	215032 kb
Host	smart-8fded707-0e3e-440b-8082-03ba6272abb0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976874269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. spi_device_same_csr_outstanding.2976874269
Directory	/workspace/10.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_intr_test.478430328
Short name	T57
Test name
Test status
Simulation time	14029626 ps
CPU time	0.73 seconds
Started	Jan 10 12:29:13 PM PST 24
Finished	Jan 10 12:29:36 PM PST 24
Peak memory	204740 kb
Host	smart-4a99729b-9e16-4a67-a1c3-20d0146cc2d3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478430328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.478430328
Directory	/workspace/7.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2749721619
Short name	T2
Test name
Test status
Simulation time	97840288 ps
CPU time	3.64 seconds
Started	Jan 10 12:27:49 PM PST 24
Finished	Jan 10 12:28:08 PM PST 24
Peak memory	215808 kb
Host	smart-e5d59ba3-4d31-423f-9535-98b76c6cd984
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749721619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2 749721619
Directory	/workspace/4.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1316897517
Short name	T23
Test name
Test status
Simulation time	3423992949 ps
CPU time	19.32 seconds
Started	Jan 10 12:23:50 PM PST 24
Finished	Jan 10 12:24:10 PM PST 24
Peak memory	215004 kb
Host	smart-11354e3e-7ee2-4310-9dd3-760ad7de6398
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316897517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic e_tl_intg_err.1316897517
Directory	/workspace/17.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/36.spi_device_intr_test.3081364322
Short name	T12
Test name
Test status
Simulation time	66603467 ps
CPU time	0.8 seconds
Started	Jan 10 12:26:31 PM PST 24
Finished	Jan 10 12:26:35 PM PST 24
Peak memory	203488 kb
Host	smart-c1ca3288-9fc8-4325-98a2-748315c9dd7c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081364322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test. 3081364322
Directory	/workspace/36.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.spi_device_intr_test.45669004
Short name	T59
Test name
Test status
Simulation time	15897309 ps
CPU time	0.76 seconds
Started	Jan 10 12:24:57 PM PST 24
Finished	Jan 10 12:24:59 PM PST 24
Peak memory	204768 kb
Host	smart-e678ee3d-8a46-4d2e-9385-e445903dc955
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45669004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.45669004
Directory	/workspace/44.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1439923664
Short name	T47
Test name
Test status
Simulation time	2028774104 ps
CPU time	12.02 seconds
Started	Jan 10 12:30:00 PM PST 24
Finished	Jan 10 12:30:55 PM PST 24
Peak memory	215360 kb
Host	smart-6c7210ed-7bb1-498e-9f06-7943952c80d4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439923664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device _tl_intg_err.1439923664
Directory	/workspace/0.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.277030106
Short name	T51
Test name
Test status
Simulation time	227592494 ps
CPU time	5.02 seconds
Started	Jan 10 12:26:50 PM PST 24
Finished	Jan 10 12:27:00 PM PST 24
Peak memory	215968 kb
Host	smart-a206261e-c33a-4d88-9b96-c5fb74bd46c6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277030106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.277030106
Directory	/workspace/14.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2891638742
Short name	T80
Test name
Test status
Simulation time	60489508 ps
CPU time	2.89 seconds
Started	Jan 10 12:29:52 PM PST 24
Finished	Jan 10 12:30:31 PM PST 24
Peak memory	219180 kb
Host	smart-139f4db5-9d72-47ee-bd58-24485120fe1f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891638742 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2891638742
Directory	/workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3358791028
Short name	T5
Test name
Test status
Simulation time	664030802 ps
CPU time	1.53 seconds
Started	Jan 10 12:29:39 PM PST 24
Finished	Jan 10 12:30:11 PM PST 24
Peak memory	206968 kb
Host	smart-22e55ebe-7646-489b-84a4-e7698d779ba2
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358791028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_hw_reset.3358791028
Directory	/workspace/0.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1121795513
Short name	T143
Test name
Test status
Simulation time	3666716574 ps
CPU time	16.49 seconds
Started	Jan 10 12:29:17 PM PST 24
Finished	Jan 10 12:29:57 PM PST 24
Peak memory	215856 kb
Host	smart-6525ac44-3c95-4648-b4a5-1147862d7a81
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121795513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_aliasing.1121795513
Directory	/workspace/0.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.443119400
Short name	T53
Test name
Test status
Simulation time	1289293625 ps
CPU time	15.07 seconds
Started	Jan 10 12:27:18 PM PST 24
Finished	Jan 10 12:27:38 PM PST 24
Peak memory	207552 kb
Host	smart-1648db7b-33bc-4125-ba55-c3268972d955
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443119400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr _bit_bash.443119400
Directory	/workspace/0.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1201742033
Short name	T146
Test name
Test status
Simulation time	20822858 ps
CPU time	1.45 seconds
Started	Jan 10 12:27:59 PM PST 24
Finished	Jan 10 12:28:14 PM PST 24
Peak memory	217104 kb
Host	smart-e9c24873-62f9-494c-bb2b-10e0f2017c06
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201742033 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1201742033
Directory	/workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.886568447
Short name	T77
Test name
Test status
Simulation time	241640237 ps
CPU time	1.63 seconds
Started	Jan 10 12:30:25 PM PST 24
Finished	Jan 10 12:31:08 PM PST 24
Peak memory	215584 kb
Host	smart-a0bc8947-d5e9-4f0b-bed9-e3dcffa950de
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886568447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.886568447
Directory	/workspace/0.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_intr_test.3100312051
Short name	T70
Test name
Test status
Simulation time	78986950 ps
CPU time	0.7 seconds
Started	Jan 10 12:23:54 PM PST 24
Finished	Jan 10 12:23:55 PM PST 24
Peak memory	204824 kb
Host	smart-137c0f11-3d71-40b3-9b42-33529234f0e9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100312051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3 100312051
Directory	/workspace/0.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1139062409
Short name	T16
Test name
Test status
Simulation time	60265736 ps
CPU time	4.15 seconds
Started	Jan 10 12:24:14 PM PST 24
Finished	Jan 10 12:24:19 PM PST 24
Peak memory	215836 kb
Host	smart-663dbd3b-8bdb-4b29-baa2-36ec369aa594
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139062409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi _device_mem_partial_access.1139062409
Directory	/workspace/0.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.480290015
Short name	T157
Test name
Test status
Simulation time	3176071626 ps
CPU time	4.93 seconds
Started	Jan 10 12:29:30 PM PST 24
Finished	Jan 10 12:30:01 PM PST 24
Peak memory	215300 kb
Host	smart-f7b3ec56-8c62-448d-8b77-796a1eaf5da9
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480290015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem _walk.480290015
Directory	/workspace/0.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.959192210
Short name	T79
Test name
Test status
Simulation time	65678861 ps
CPU time	3.88 seconds
Started	Jan 10 12:27:58 PM PST 24
Finished	Jan 10 12:28:14 PM PST 24
Peak memory	215828 kb
Host	smart-e2531a1d-ecea-4ce1-81dd-52be81d4b530
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959192210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp i_device_same_csr_outstanding.959192210
Directory	/workspace/0.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1327332469
Short name	T130
Test name
Test status
Simulation time	71093280 ps
CPU time	1.94 seconds
Started	Jan 10 12:29:45 PM PST 24
Finished	Jan 10 12:30:21 PM PST 24
Peak memory	214732 kb
Host	smart-c17e0fa0-ac8b-4e3a-8c96-98191f8a222b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327332469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1 327332469
Directory	/workspace/0.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1360390209
Short name	T75
Test name
Test status
Simulation time	394724062 ps
CPU time	24.29 seconds
Started	Jan 10 12:28:18 PM PST 24
Finished	Jan 10 12:28:56 PM PST 24
Peak memory	207612 kb
Host	smart-249a6b38-9a72-419e-a0b3-598a395685d4
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360390209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_bit_bash.1360390209
Directory	/workspace/1.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2070288727
Short name	T171
Test name
Test status
Simulation time	21775620 ps
CPU time	1.3 seconds
Started	Jan 10 12:28:09 PM PST 24
Finished	Jan 10 12:28:27 PM PST 24
Peak memory	207628 kb
Host	smart-83b9cf0a-d35a-4347-9521-ea92b2492b50
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070288727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_hw_reset.2070288727
Directory	/workspace/1.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3166343796
Short name	T42
Test name
Test status
Simulation time	132734407 ps
CPU time	1.85 seconds
Started	Jan 10 12:28:07 PM PST 24
Finished	Jan 10 12:28:24 PM PST 24
Peak memory	215756 kb
Host	smart-8d4be1ff-4277-4d22-b09d-c94346b0c3da
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166343796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3 166343796
Directory	/workspace/1.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_intr_test.98990855
Short name	T119
Test name
Test status
Simulation time	28329116 ps
CPU time	0.72 seconds
Started	Jan 10 12:29:53 PM PST 24
Finished	Jan 10 12:30:35 PM PST 24
Peak memory	204600 kb
Host	smart-904ad7a1-e107-4df0-b5d6-d676d1e3fd2f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98990855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.98990855
Directory	/workspace/1.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2588312970
Short name	T14
Test name
Test status
Simulation time	197887640 ps
CPU time	4.19 seconds
Started	Jan 10 12:27:27 PM PST 24
Finished	Jan 10 12:27:36 PM PST 24
Peak memory	215720 kb
Host	smart-d8b55cd5-f5b7-4acd-b6c3-28c51ae1d958
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588312970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi _device_mem_partial_access.2588312970
Directory	/workspace/1.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1510076258
Short name	T1
Test name
Test status
Simulation time	74479283 ps
CPU time	4.69 seconds
Started	Jan 10 12:29:47 PM PST 24
Finished	Jan 10 12:30:25 PM PST 24
Peak memory	215548 kb
Host	smart-5c0a16eb-def2-45b2-be03-366f73eb60be
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510076258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me m_walk.1510076258
Directory	/workspace/1.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1737970973
Short name	T173
Test name
Test status
Simulation time	174185565 ps
CPU time	2.6 seconds
Started	Jan 10 12:29:15 PM PST 24
Finished	Jan 10 12:29:40 PM PST 24
Peak memory	215752 kb
Host	smart-381306f3-26ed-44d6-848c-372eb7fcab23
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737970973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s pi_device_same_csr_outstanding.1737970973
Directory	/workspace/1.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2779095763
Short name	T162
Test name
Test status
Simulation time	47830758 ps
CPU time	3.04 seconds
Started	Jan 10 12:29:17 PM PST 24
Finished	Jan 10 12:29:45 PM PST 24
Peak memory	215696 kb
Host	smart-b3ada5ec-b493-4d5e-9942-e1c6be77fef1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779095763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2 779095763
Directory	/workspace/1.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1154013740
Short name	T64
Test name
Test status
Simulation time	614512066 ps
CPU time	16.79 seconds
Started	Jan 10 12:29:16 PM PST 24
Finished	Jan 10 12:29:57 PM PST 24
Peak memory	215540 kb
Host	smart-f0a50e24-b03b-469e-bd7c-54d4ce690d83
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154013740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device _tl_intg_err.1154013740
Directory	/workspace/1.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2911735002
Short name	T4
Test name
Test status
Simulation time	26442670 ps
CPU time	1.44 seconds
Started	Jan 10 12:25:31 PM PST 24
Finished	Jan 10 12:25:33 PM PST 24
Peak memory	219068 kb
Host	smart-ad309f36-2074-43aa-8813-230c3902a112
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911735002 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2911735002
Directory	/workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2191910785
Short name	T8
Test name
Test status
Simulation time	40618474 ps
CPU time	2.48 seconds
Started	Jan 10 12:25:17 PM PST 24
Finished	Jan 10 12:25:20 PM PST 24
Peak memory	215872 kb
Host	smart-18c33f91-2dfe-4b0c-a1a6-c446ff8ee086
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191910785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw. 2191910785
Directory	/workspace/10.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_intr_test.3645782892
Short name	T172
Test name
Test status
Simulation time	36199612 ps
CPU time	0.66 seconds
Started	Jan 10 12:29:16 PM PST 24
Finished	Jan 10 12:29:41 PM PST 24
Peak memory	204624 kb
Host	smart-477486a3-5c56-4bda-b83b-403b3f350d48
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645782892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test. 3645782892
Directory	/workspace/10.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.538988619
Short name	T21
Test name
Test status
Simulation time	257284069 ps
CPU time	4.55 seconds
Started	Jan 10 12:27:28 PM PST 24
Finished	Jan 10 12:27:37 PM PST 24
Peak memory	215960 kb
Host	smart-7b91bbb1-bc52-4918-a5bd-cc11b86b0ba0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538988619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.538988619
Directory	/workspace/10.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1269972864
Short name	T155
Test name
Test status
Simulation time	1233371021 ps
CPU time	17.16 seconds
Started	Jan 10 12:23:50 PM PST 24
Finished	Jan 10 12:24:08 PM PST 24
Peak memory	214960 kb
Host	smart-1c1d3560-7678-4210-bce1-09e368ea7f04
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269972864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic e_tl_intg_err.1269972864
Directory	/workspace/10.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2570566124
Short name	T9
Test name
Test status
Simulation time	34811648 ps
CPU time	2.39 seconds
Started	Jan 10 12:26:50 PM PST 24
Finished	Jan 10 12:26:56 PM PST 24
Peak memory	217600 kb
Host	smart-9280f2b4-ee0c-4079-86c9-40cd387ea03d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570566124 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2570566124
Directory	/workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.417481923
Short name	T112
Test name
Test status
Simulation time	59079580 ps
CPU time	1.78 seconds
Started	Jan 10 12:32:15 PM PST 24
Finished	Jan 10 12:32:58 PM PST 24
Peak memory	215748 kb
Host	smart-3cfe0b4f-485b-4639-9e87-82b4076479c1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417481923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.417481923
Directory	/workspace/11.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_intr_test.1687802294
Short name	T158
Test name
Test status
Simulation time	14179506 ps
CPU time	0.73 seconds
Started	Jan 10 12:28:37 PM PST 24
Finished	Jan 10 12:28:50 PM PST 24
Peak memory	204564 kb
Host	smart-3b1d4711-b059-4a7a-907a-2366b483893c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687802294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test. 1687802294
Directory	/workspace/11.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.891731670
Short name	T76
Test name
Test status
Simulation time	82290195 ps
CPU time	2.73 seconds
Started	Jan 10 12:26:23 PM PST 24
Finished	Jan 10 12:26:27 PM PST 24
Peak memory	214620 kb
Host	smart-568d080e-e02a-45ef-9c39-03e60dc6a7ca
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891731670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s pi_device_same_csr_outstanding.891731670
Directory	/workspace/11.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1818473816
Short name	T133
Test name
Test status
Simulation time	1305386798 ps
CPU time	5.2 seconds
Started	Jan 10 12:31:28 PM PST 24
Finished	Jan 10 12:32:22 PM PST 24
Peak memory	215144 kb
Host	smart-31bfea2f-c19d-440b-9fb1-7bb8917e8918
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818473816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors. 1818473816
Directory	/workspace/11.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1462720368
Short name	T174
Test name
Test status
Simulation time	865572390 ps
CPU time	12.86 seconds
Started	Jan 10 12:28:04 PM PST 24
Finished	Jan 10 12:28:32 PM PST 24
Peak memory	215768 kb
Host	smart-e3a43fa8-9ce4-42f1-a216-0d338fdb4bca
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462720368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic e_tl_intg_err.1462720368
Directory	/workspace/11.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3388767707
Short name	T58
Test name
Test status
Simulation time	33797316 ps
CPU time	1.79 seconds
Started	Jan 10 12:29:15 PM PST 24
Finished	Jan 10 12:29:41 PM PST 24
Peak memory	219160 kb
Host	smart-4ae018c9-e62b-42f9-8b28-89c860876d17
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388767707 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3388767707
Directory	/workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1405458266
Short name	T36
Test name
Test status
Simulation time	36666556 ps
CPU time	1.25 seconds
Started	Jan 10 12:26:51 PM PST 24
Finished	Jan 10 12:26:56 PM PST 24
Peak memory	215728 kb
Host	smart-618bfaf2-ea54-4729-924c-d45c2bcd7524
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405458266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw. 1405458266
Directory	/workspace/12.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_intr_test.3502351690
Short name	T105
Test name
Test status
Simulation time	42992431 ps
CPU time	0.68 seconds
Started	Jan 10 12:26:51 PM PST 24
Finished	Jan 10 12:26:56 PM PST 24
Peak memory	204808 kb
Host	smart-970bd2c5-1195-4509-95cc-c2b02af46abc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502351690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test. 3502351690
Directory	/workspace/12.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3836472658
Short name	T41
Test name
Test status
Simulation time	43542551 ps
CPU time	2.68 seconds
Started	Jan 10 12:26:51 PM PST 24
Finished	Jan 10 12:26:58 PM PST 24
Peak memory	215788 kb
Host	smart-63fc2259-b5fe-4777-9c30-2d3daef7767d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836472658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. spi_device_same_csr_outstanding.3836472658
Directory	/workspace/12.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1564875935
Short name	T48
Test name
Test status
Simulation time	243476315 ps
CPU time	4.2 seconds
Started	Jan 10 12:30:24 PM PST 24
Finished	Jan 10 12:31:10 PM PST 24
Peak memory	215844 kb
Host	smart-4f197f3a-6af3-48bf-9177-899d8a201847
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564875935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors. 1564875935
Directory	/workspace/12.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1273776946
Short name	T68
Test name
Test status
Simulation time	580581635 ps
CPU time	17.5 seconds
Started	Jan 10 12:26:59 PM PST 24
Finished	Jan 10 12:27:23 PM PST 24
Peak memory	215696 kb
Host	smart-8b30c8b3-7fc4-4733-81b9-6ac66580d47d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273776946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic e_tl_intg_err.1273776946
Directory	/workspace/12.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2561719758
Short name	T126
Test name
Test status
Simulation time	58094969 ps
CPU time	2.27 seconds
Started	Jan 10 12:29:02 PM PST 24
Finished	Jan 10 12:29:23 PM PST 24
Peak memory	216976 kb
Host	smart-1fad9b5a-b602-4e62-b726-ac8867f7d539
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561719758 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2561719758
Directory	/workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.265221719
Short name	T129
Test name
Test status
Simulation time	91235467 ps
CPU time	2.41 seconds
Started	Jan 10 12:29:04 PM PST 24
Finished	Jan 10 12:29:27 PM PST 24
Peak memory	215056 kb
Host	smart-e90e8446-9dcb-46ef-894c-bd7b48c32463
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265221719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.265221719
Directory	/workspace/13.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_intr_test.1252514431
Short name	T78
Test name
Test status
Simulation time	16842274 ps
CPU time	0.65 seconds
Started	Jan 10 12:27:31 PM PST 24
Finished	Jan 10 12:27:37 PM PST 24
Peak memory	204832 kb
Host	smart-25728225-b42d-4a59-87c0-670efb1c0fb9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252514431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test. 1252514431
Directory	/workspace/13.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3441251419
Short name	T170
Test name
Test status
Simulation time	123102713 ps
CPU time	2.96 seconds
Started	Jan 10 12:27:30 PM PST 24
Finished	Jan 10 12:27:39 PM PST 24
Peak memory	215792 kb
Host	smart-2f2a1438-dd23-4846-b5c7-723c6e1978c9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441251419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. spi_device_same_csr_outstanding.3441251419
Directory	/workspace/13.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3538958404
Short name	T114
Test name
Test status
Simulation time	40889454 ps
CPU time	2.6 seconds
Started	Jan 10 12:24:59 PM PST 24
Finished	Jan 10 12:25:03 PM PST 24
Peak memory	216020 kb
Host	smart-c8e70cca-917a-4e08-a4cf-83bcdb944a0c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538958404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors. 3538958404
Directory	/workspace/13.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1790121456
Short name	T123
Test name
Test status
Simulation time	1306913483 ps
CPU time	19.03 seconds
Started	Jan 10 12:26:51 PM PST 24
Finished	Jan 10 12:27:14 PM PST 24
Peak memory	215784 kb
Host	smart-f3d04187-ec1c-4bd1-9070-786d4d4de484
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790121456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic e_tl_intg_err.1790121456
Directory	/workspace/13.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1962984918
Short name	T29
Test name
Test status
Simulation time	153641664 ps
CPU time	2.46 seconds
Started	Jan 10 12:29:18 PM PST 24
Finished	Jan 10 12:29:44 PM PST 24
Peak memory	218820 kb
Host	smart-aa00aeca-fbc5-4d26-bffb-6006ab6c5d39
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962984918 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1962984918
Directory	/workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1133687161
Short name	T156
Test name
Test status
Simulation time	120853539 ps
CPU time	2.63 seconds
Started	Jan 10 12:25:40 PM PST 24
Finished	Jan 10 12:25:44 PM PST 24
Peak memory	207984 kb
Host	smart-f77a7ab6-48fe-4bde-87cd-42f371d302ed
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133687161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw. 1133687161
Directory	/workspace/14.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_intr_test.2205305266
Short name	T148
Test name
Test status
Simulation time	50978758 ps
CPU time	0.74 seconds
Started	Jan 10 12:28:38 PM PST 24
Finished	Jan 10 12:28:51 PM PST 24
Peak memory	204652 kb
Host	smart-327fa772-9129-4012-a031-5ea3d5084a57
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205305266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test. 2205305266
Directory	/workspace/14.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1386814243
Short name	T140
Test name
Test status
Simulation time	965728071 ps
CPU time	3.57 seconds
Started	Jan 10 12:29:18 PM PST 24
Finished	Jan 10 12:29:46 PM PST 24
Peak memory	215524 kb
Host	smart-b5f7d0b0-0619-4050-8d05-466785e58f33
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386814243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. spi_device_same_csr_outstanding.1386814243
Directory	/workspace/14.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.964981401
Short name	T90
Test name
Test status
Simulation time	440844487 ps
CPU time	6.66 seconds
Started	Jan 10 12:30:35 PM PST 24
Finished	Jan 10 12:31:24 PM PST 24
Peak memory	215644 kb
Host	smart-01ef6859-69fe-4863-a62a-2ef98d0bcbe4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964981401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device _tl_intg_err.964981401
Directory	/workspace/14.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2723602241
Short name	T97
Test name
Test status
Simulation time	33183181 ps
CPU time	1.93 seconds
Started	Jan 10 12:26:57 PM PST 24
Finished	Jan 10 12:27:06 PM PST 24
Peak memory	218916 kb
Host	smart-cf40269f-b711-412e-84da-d44816b3b862
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723602241 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2723602241
Directory	/workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2949624663
Short name	T34
Test name
Test status
Simulation time	270878242 ps
CPU time	2.37 seconds
Started	Jan 10 12:27:03 PM PST 24
Finished	Jan 10 12:27:11 PM PST 24
Peak memory	214968 kb
Host	smart-d86c41b3-4cb9-46d7-8624-f6da4941cad3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949624663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw. 2949624663
Directory	/workspace/15.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_intr_test.152282237
Short name	T86
Test name
Test status
Simulation time	25406071 ps
CPU time	0.75 seconds
Started	Jan 10 12:27:51 PM PST 24
Finished	Jan 10 12:28:07 PM PST 24
Peak memory	204840 kb
Host	smart-32dc5cd9-ad34-4d87-b4dd-90bae31ac43f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152282237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.152282237
Directory	/workspace/15.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3045790133
Short name	T152
Test name
Test status
Simulation time	263467791 ps
CPU time	3.81 seconds
Started	Jan 10 12:29:18 PM PST 24
Finished	Jan 10 12:29:46 PM PST 24
Peak memory	215600 kb
Host	smart-965a7958-1311-4a35-9fcc-3aa0508a03a4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045790133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. spi_device_same_csr_outstanding.3045790133
Directory	/workspace/15.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1543482683
Short name	T144
Test name
Test status
Simulation time	292642194 ps
CPU time	2.71 seconds
Started	Jan 10 12:28:22 PM PST 24
Finished	Jan 10 12:28:37 PM PST 24
Peak memory	215672 kb
Host	smart-071fd279-d977-4b9b-bd44-1fca8145d73d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543482683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors. 1543482683
Directory	/workspace/15.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2199720847
Short name	T28
Test name
Test status
Simulation time	208521313 ps
CPU time	11.21 seconds
Started	Jan 10 12:28:41 PM PST 24
Finished	Jan 10 12:29:05 PM PST 24
Peak memory	216136 kb
Host	smart-7d8c6ba2-ba52-4e73-b60b-b66e9a52f9ed
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199720847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic e_tl_intg_err.2199720847
Directory	/workspace/15.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3818001202
Short name	T137
Test name
Test status
Simulation time	16714007 ps
CPU time	1.28 seconds
Started	Jan 10 12:27:24 PM PST 24
Finished	Jan 10 12:27:30 PM PST 24
Peak memory	217444 kb
Host	smart-c89d707e-c02e-49d5-be86-2d5c927d5e42
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818001202 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3818001202
Directory	/workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1351990471
Short name	T93
Test name
Test status
Simulation time	140068395 ps
CPU time	2.37 seconds
Started	Jan 10 12:27:23 PM PST 24
Finished	Jan 10 12:27:31 PM PST 24
Peak memory	215732 kb
Host	smart-23112306-d9c9-471b-a94f-06221edbe994
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351990471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw. 1351990471
Directory	/workspace/16.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_intr_test.2347594618
Short name	T145
Test name
Test status
Simulation time	14964839 ps
CPU time	0.71 seconds
Started	Jan 10 12:28:06 PM PST 24
Finished	Jan 10 12:28:22 PM PST 24
Peak memory	204864 kb
Host	smart-613a9002-0f9a-4931-a802-63e83c2fd4ba
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347594618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test. 2347594618
Directory	/workspace/16.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3653290136
Short name	T160
Test name
Test status
Simulation time	454663939 ps
CPU time	1.94 seconds
Started	Jan 10 12:29:07 PM PST 24
Finished	Jan 10 12:29:30 PM PST 24
Peak memory	214924 kb
Host	smart-269d6b44-bdf3-44cc-b740-91cee41c5a47
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653290136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. spi_device_same_csr_outstanding.3653290136
Directory	/workspace/16.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2219707078
Short name	T159
Test name
Test status
Simulation time	29521672 ps
CPU time	1.83 seconds
Started	Jan 10 12:24:17 PM PST 24
Finished	Jan 10 12:24:20 PM PST 24
Peak memory	215840 kb
Host	smart-328ec4f0-7b60-44b4-9bdb-fe8e0267eec3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219707078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors. 2219707078
Directory	/workspace/16.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1114499334
Short name	T66
Test name
Test status
Simulation time	343776904 ps
CPU time	7.51 seconds
Started	Jan 10 12:28:00 PM PST 24
Finished	Jan 10 12:28:23 PM PST 24
Peak memory	215992 kb
Host	smart-510d33a6-a800-4446-9c5c-2434ff736f9b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114499334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic e_tl_intg_err.1114499334
Directory	/workspace/16.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1454354393
Short name	T83
Test name
Test status
Simulation time	159138046 ps
CPU time	2.69 seconds
Started	Jan 10 12:24:45 PM PST 24
Finished	Jan 10 12:24:49 PM PST 24
Peak memory	219640 kb
Host	smart-529a112f-3e0a-4973-a07d-ab50e61c7476
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454354393 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1454354393
Directory	/workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1593833468
Short name	T101
Test name
Test status
Simulation time	133427695 ps
CPU time	2.19 seconds
Started	Jan 10 12:27:31 PM PST 24
Finished	Jan 10 12:27:38 PM PST 24
Peak memory	215828 kb
Host	smart-e7599a66-dc96-4f8f-8f40-7074640e920d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593833468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw. 1593833468
Directory	/workspace/17.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_intr_test.2950826042
Short name	T88
Test name
Test status
Simulation time	10730882 ps
CPU time	0.76 seconds
Started	Jan 10 12:25:21 PM PST 24
Finished	Jan 10 12:25:23 PM PST 24
Peak memory	204876 kb
Host	smart-87aef078-4c9e-4c6b-9d62-dc4994fffb53
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950826042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test. 2950826042
Directory	/workspace/17.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3003177083
Short name	T31
Test name
Test status
Simulation time	64710176 ps
CPU time	1.93 seconds
Started	Jan 10 12:29:16 PM PST 24
Finished	Jan 10 12:29:42 PM PST 24
Peak memory	215736 kb
Host	smart-7bfeb2f9-8ab5-4708-af3c-041d2a2320b3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003177083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. spi_device_same_csr_outstanding.3003177083
Directory	/workspace/17.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3571784999
Short name	T26
Test name
Test status
Simulation time	62876737 ps
CPU time	4.45 seconds
Started	Jan 10 12:24:17 PM PST 24
Finished	Jan 10 12:24:23 PM PST 24
Peak memory	215916 kb
Host	smart-7f94cb09-8a64-419f-b8c5-aff6c55e27d3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571784999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors. 3571784999
Directory	/workspace/17.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2374278878
Short name	T6
Test name
Test status
Simulation time	25599911 ps
CPU time	2.1 seconds
Started	Jan 10 12:28:22 PM PST 24
Finished	Jan 10 12:28:37 PM PST 24
Peak memory	217520 kb
Host	smart-bbe97711-02fa-4a6c-bda4-f7fdeae6e13a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374278878 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2374278878
Directory	/workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2740356101
Short name	T121
Test name
Test status
Simulation time	95973230 ps
CPU time	2.42 seconds
Started	Jan 10 12:23:55 PM PST 24
Finished	Jan 10 12:23:58 PM PST 24
Peak memory	215832 kb
Host	smart-52da26d2-ad6b-46c5-9da9-4fe452854543
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740356101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw. 2740356101
Directory	/workspace/18.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_intr_test.1150540991
Short name	T163
Test name
Test status
Simulation time	48342861 ps
CPU time	0.71 seconds
Started	Jan 10 12:25:59 PM PST 24
Finished	Jan 10 12:26:11 PM PST 24
Peak memory	204868 kb
Host	smart-bb9950c4-43c9-4dd5-b0e3-3b608370ee3d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150540991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test. 1150540991
Directory	/workspace/18.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3151904921
Short name	T32
Test name
Test status
Simulation time	758835042 ps
CPU time	3.93 seconds
Started	Jan 10 12:29:15 PM PST 24
Finished	Jan 10 12:29:42 PM PST 24
Peak memory	215720 kb
Host	smart-9907ae46-65dd-4e6e-973d-e98a213ba154
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151904921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. spi_device_same_csr_outstanding.3151904921
Directory	/workspace/18.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1105560427
Short name	T122
Test name
Test status
Simulation time	714624565 ps
CPU time	4.67 seconds
Started	Jan 10 12:29:06 PM PST 24
Finished	Jan 10 12:29:32 PM PST 24
Peak memory	216828 kb
Host	smart-675acd7d-d0e1-4726-92f3-b9d3cd126f0e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105560427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors. 1105560427
Directory	/workspace/18.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1824634512
Short name	T20
Test name
Test status
Simulation time	470667025 ps
CPU time	5.84 seconds
Started	Jan 10 12:27:03 PM PST 24
Finished	Jan 10 12:27:16 PM PST 24
Peak memory	215856 kb
Host	smart-aa6a6e24-6a5f-4ac9-91f5-91ffaf031ab3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824634512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic e_tl_intg_err.1824634512
Directory	/workspace/18.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3290734998
Short name	T131
Test name
Test status
Simulation time	20242970 ps
CPU time	1.45 seconds
Started	Jan 10 12:29:56 PM PST 24
Finished	Jan 10 12:30:36 PM PST 24
Peak memory	216260 kb
Host	smart-a0900430-1b9f-4894-b11e-fb65661ee1ff
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290734998 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3290734998
Directory	/workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1687323605
Short name	T82
Test name
Test status
Simulation time	31506385 ps
CPU time	1.18 seconds
Started	Jan 10 12:26:48 PM PST 24
Finished	Jan 10 12:26:54 PM PST 24
Peak memory	215888 kb
Host	smart-33d514d4-e6f8-4f58-b7fd-c5e1f5efda60
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687323605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw. 1687323605
Directory	/workspace/19.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_intr_test.1861774641
Short name	T84
Test name
Test status
Simulation time	39377214 ps
CPU time	0.74 seconds
Started	Jan 10 12:28:53 PM PST 24
Finished	Jan 10 12:29:13 PM PST 24
Peak memory	204824 kb
Host	smart-81b36913-c062-46e8-b908-d14060df8cf7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861774641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test. 1861774641
Directory	/workspace/19.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1163644577
Short name	T102
Test name
Test status
Simulation time	723129324 ps
CPU time	3.14 seconds
Started	Jan 10 12:27:37 PM PST 24
Finished	Jan 10 12:27:47 PM PST 24
Peak memory	216200 kb
Host	smart-0f24c969-c761-4b14-b7b3-c20e816eec6f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163644577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. spi_device_same_csr_outstanding.1163644577
Directory	/workspace/19.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2043288924
Short name	T25
Test name
Test status
Simulation time	119450031 ps
CPU time	2.77 seconds
Started	Jan 10 12:28:01 PM PST 24
Finished	Jan 10 12:28:19 PM PST 24
Peak memory	215700 kb
Host	smart-1146e764-92d0-450b-bbd9-60da586c5708
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043288924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors. 2043288924
Directory	/workspace/19.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3835678235
Short name	T153
Test name
Test status
Simulation time	212285364 ps
CPU time	13.11 seconds
Started	Jan 10 12:25:29 PM PST 24
Finished	Jan 10 12:25:43 PM PST 24
Peak memory	215868 kb
Host	smart-81964928-86cc-40fe-a169-43d215448b78
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835678235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic e_tl_intg_err.3835678235
Directory	/workspace/19.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1769413127
Short name	T151
Test name
Test status
Simulation time	535154993 ps
CPU time	9.42 seconds
Started	Jan 10 12:28:28 PM PST 24
Finished	Jan 10 12:28:48 PM PST 24
Peak memory	215732 kb
Host	smart-a619741e-0ea6-4e32-8267-dd8ca5e06efb
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769413127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_aliasing.1769413127
Directory	/workspace/2.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1127472426
Short name	T43
Test name
Test status
Simulation time	909342988 ps
CPU time	13.78 seconds
Started	Jan 10 12:23:31 PM PST 24
Finished	Jan 10 12:23:46 PM PST 24
Peak memory	207924 kb
Host	smart-4aa776e7-4335-44c0-90aa-c1ed42a25317
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127472426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_bit_bash.1127472426
Directory	/workspace/2.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2009618947
Short name	T49
Test name
Test status
Simulation time	27617171 ps
CPU time	1.01 seconds
Started	Jan 10 12:23:37 PM PST 24
Finished	Jan 10 12:23:39 PM PST 24
Peak memory	207448 kb
Host	smart-df019f33-ce88-421e-a91d-d0863b00dcfc
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009618947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_hw_reset.2009618947
Directory	/workspace/2.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2535569148
Short name	T17
Test name
Test status
Simulation time	60985206 ps
CPU time	2.82 seconds
Started	Jan 10 12:28:28 PM PST 24
Finished	Jan 10 12:28:42 PM PST 24
Peak memory	218168 kb
Host	smart-b7772e0a-264e-4409-a16a-fb9141aa4401
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535569148 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2535569148
Directory	/workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.906569023
Short name	T109
Test name
Test status
Simulation time	260936127 ps
CPU time	1.97 seconds
Started	Jan 10 12:28:28 PM PST 24
Finished	Jan 10 12:28:41 PM PST 24
Peak memory	215468 kb
Host	smart-1317893e-f083-4c0e-a464-d639dcef7f63
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906569023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.906569023
Directory	/workspace/2.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_intr_test.1692038570
Short name	T96
Test name
Test status
Simulation time	15331269 ps
CPU time	0.83 seconds
Started	Jan 10 12:23:29 PM PST 24
Finished	Jan 10 12:23:31 PM PST 24
Peak memory	204132 kb
Host	smart-caa549b0-0066-4912-9224-00e88c870c5d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692038570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1 692038570
Directory	/workspace/2.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3364133951
Short name	T39
Test name
Test status
Simulation time	228917107 ps
CPU time	5.81 seconds
Started	Jan 10 12:30:20 PM PST 24
Finished	Jan 10 12:31:06 PM PST 24
Peak memory	215580 kb
Host	smart-b5f1168e-9bbb-4700-bea5-f32f2520c611
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364133951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi _device_mem_partial_access.3364133951
Directory	/workspace/2.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1364950166
Short name	T115
Test name
Test status
Simulation time	266975533 ps
CPU time	8.62 seconds
Started	Jan 10 12:31:41 PM PST 24
Finished	Jan 10 12:32:40 PM PST 24
Peak memory	215480 kb
Host	smart-2bbbff41-9297-4eb7-8956-a6d5de3a8266
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364950166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me m_walk.1364950166
Directory	/workspace/2.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1216351155
Short name	T107
Test name
Test status
Simulation time	903144403 ps
CPU time	4.48 seconds
Started	Jan 10 12:28:28 PM PST 24
Finished	Jan 10 12:28:43 PM PST 24
Peak memory	215236 kb
Host	smart-c9238ce2-f9cb-47bc-b905-9e9b706f1379
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216351155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s pi_device_same_csr_outstanding.1216351155
Directory	/workspace/2.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1520625515
Short name	T167
Test name
Test status
Simulation time	124846299 ps
CPU time	1.86 seconds
Started	Jan 10 12:28:29 PM PST 24
Finished	Jan 10 12:28:41 PM PST 24
Peak memory	215540 kb
Host	smart-fcda4fad-30c3-430f-b670-b2497414deef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520625515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1 520625515
Directory	/workspace/2.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3443773618
Short name	T106
Test name
Test status
Simulation time	1189924798 ps
CPU time	7.94 seconds
Started	Jan 10 12:28:28 PM PST 24
Finished	Jan 10 12:28:47 PM PST 24
Peak memory	216380 kb
Host	smart-63b5d802-0888-4189-b6e4-40b83a6522dd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443773618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device _tl_intg_err.3443773618
Directory	/workspace/2.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.spi_device_intr_test.364343065
Short name	T3
Test name
Test status
Simulation time	44028645 ps
CPU time	0.66 seconds
Started	Jan 10 12:29:54 PM PST 24
Finished	Jan 10 12:30:32 PM PST 24
Peak memory	204628 kb
Host	smart-7e459c72-2033-407d-9c18-4d498ca3ad2b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364343065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.364343065
Directory	/workspace/20.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.spi_device_intr_test.111070593
Short name	T141
Test name
Test status
Simulation time	15028994 ps
CPU time	0.7 seconds
Started	Jan 10 12:30:26 PM PST 24
Finished	Jan 10 12:31:08 PM PST 24
Peak memory	204620 kb
Host	smart-e7c513a1-e07b-41a5-a08b-0d53da46f266
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111070593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.111070593
Directory	/workspace/21.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.spi_device_intr_test.1192841689
Short name	T85
Test name
Test status
Simulation time	15499638 ps
CPU time	0.74 seconds
Started	Jan 10 12:26:01 PM PST 24
Finished	Jan 10 12:26:12 PM PST 24
Peak memory	205268 kb
Host	smart-6f867aec-2066-4f12-b53d-75607168c1bf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192841689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test. 1192841689
Directory	/workspace/22.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.spi_device_intr_test.3849251708
Short name	T164
Test name
Test status
Simulation time	47845092 ps
CPU time	0.74 seconds
Started	Jan 10 12:27:39 PM PST 24
Finished	Jan 10 12:27:48 PM PST 24
Peak memory	204760 kb
Host	smart-e41c43b3-fb35-4edd-bab6-fb302358f9aa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849251708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test. 3849251708
Directory	/workspace/23.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.spi_device_intr_test.3326739721
Short name	T63
Test name
Test status
Simulation time	14703802 ps
CPU time	0.7 seconds
Started	Jan 10 12:27:24 PM PST 24
Finished	Jan 10 12:27:30 PM PST 24
Peak memory	204632 kb
Host	smart-f1aa8073-0c58-4c12-aded-b77f43a29721
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326739721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test. 3326739721
Directory	/workspace/24.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.spi_device_intr_test.1002722949
Short name	T118
Test name
Test status
Simulation time	28384154 ps
CPU time	0.66 seconds
Started	Jan 10 12:26:33 PM PST 24
Finished	Jan 10 12:26:37 PM PST 24
Peak memory	204620 kb
Host	smart-39809066-c7e3-4868-8629-f4503ed5bcb1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002722949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test. 1002722949
Directory	/workspace/25.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.spi_device_intr_test.199633481
Short name	T134
Test name
Test status
Simulation time	22327404 ps
CPU time	0.76 seconds
Started	Jan 10 12:27:24 PM PST 24
Finished	Jan 10 12:27:30 PM PST 24
Peak memory	204764 kb
Host	smart-8337975d-7a29-4741-bdfa-36a5fc0d8cf9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199633481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.199633481
Directory	/workspace/26.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.spi_device_intr_test.4055723408
Short name	T108
Test name
Test status
Simulation time	25583215 ps
CPU time	0.73 seconds
Started	Jan 10 12:26:31 PM PST 24
Finished	Jan 10 12:26:35 PM PST 24
Peak memory	203956 kb
Host	smart-229a100e-589d-4d80-8c40-d7ec914a5692
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055723408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test. 4055723408
Directory	/workspace/27.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.spi_device_intr_test.1433581471
Short name	T142
Test name
Test status
Simulation time	34979055 ps
CPU time	0.73 seconds
Started	Jan 10 12:30:26 PM PST 24
Finished	Jan 10 12:31:07 PM PST 24
Peak memory	204628 kb
Host	smart-c2f5fa8d-cfaa-40d0-8e8d-26d1be84042a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433581471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test. 1433581471
Directory	/workspace/28.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.spi_device_intr_test.2989569116
Short name	T168
Test name
Test status
Simulation time	50654527 ps
CPU time	0.73 seconds
Started	Jan 10 12:31:34 PM PST 24
Finished	Jan 10 12:32:25 PM PST 24
Peak memory	204664 kb
Host	smart-d7aed682-73b7-4255-9bab-3965693f27f7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989569116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test. 2989569116
Directory	/workspace/29.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.311682564
Short name	T124
Test name
Test status
Simulation time	4890028409 ps
CPU time	16.06 seconds
Started	Jan 10 12:29:54 PM PST 24
Finished	Jan 10 12:30:49 PM PST 24
Peak memory	216392 kb
Host	smart-afbb2bcb-78d0-4728-96d7-92ef81d3aea0
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311682564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr _aliasing.311682564
Directory	/workspace/3.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2234213669
Short name	T38
Test name
Test status
Simulation time	1615912764 ps
CPU time	24.12 seconds
Started	Jan 10 12:27:49 PM PST 24
Finished	Jan 10 12:28:28 PM PST 24
Peak memory	207500 kb
Host	smart-b4d93926-8fe9-488f-b16e-014be31f38d5
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234213669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_bit_bash.2234213669
Directory	/workspace/3.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1977308628
Short name	T166
Test name
Test status
Simulation time	131969992 ps
CPU time	1.32 seconds
Started	Jan 10 12:23:30 PM PST 24
Finished	Jan 10 12:23:32 PM PST 24
Peak memory	207528 kb
Host	smart-7a259a6b-8fb1-48cd-b10a-f0c03d47efc9
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977308628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_hw_reset.1977308628
Directory	/workspace/3.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.864421546
Short name	T71
Test name
Test status
Simulation time	63230059 ps
CPU time	1.53 seconds
Started	Jan 10 12:30:36 PM PST 24
Finished	Jan 10 12:31:20 PM PST 24
Peak memory	217292 kb
Host	smart-185985d2-a0e2-460f-aee5-f89251dc571d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864421546 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.864421546
Directory	/workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1418260194
Short name	T37
Test name
Test status
Simulation time	42710950 ps
CPU time	1.32 seconds
Started	Jan 10 12:27:38 PM PST 24
Finished	Jan 10 12:27:49 PM PST 24
Peak memory	207616 kb
Host	smart-e6f95643-72a2-4ca6-b386-10bab092752b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418260194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1 418260194
Directory	/workspace/3.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_intr_test.3242486763
Short name	T98
Test name
Test status
Simulation time	12043010 ps
CPU time	0.67 seconds
Started	Jan 10 12:27:48 PM PST 24
Finished	Jan 10 12:28:01 PM PST 24
Peak memory	204808 kb
Host	smart-7e38be89-21b2-4d47-9082-fb2812fb3fde
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242486763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3 242486763
Directory	/workspace/3.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2353561508
Short name	T33
Test name
Test status
Simulation time	273707773 ps
CPU time	4.83 seconds
Started	Jan 10 12:27:50 PM PST 24
Finished	Jan 10 12:28:10 PM PST 24
Peak memory	215764 kb
Host	smart-3bf3edb7-0f1d-42ed-823f-a46b10c284db
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353561508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi _device_mem_partial_access.2353561508
Directory	/workspace/3.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2117173287
Short name	T95
Test name
Test status
Simulation time	626593496 ps
CPU time	8.98 seconds
Started	Jan 10 12:27:19 PM PST 24
Finished	Jan 10 12:27:35 PM PST 24
Peak memory	215096 kb
Host	smart-099a0a22-257c-41cf-bb35-1b34743f0978
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117173287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me m_walk.2117173287
Directory	/workspace/3.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2086717319
Short name	T104
Test name
Test status
Simulation time	406758149 ps
CPU time	3.87 seconds
Started	Jan 10 12:30:41 PM PST 24
Finished	Jan 10 12:31:28 PM PST 24
Peak memory	214528 kb
Host	smart-74189931-6d11-4f90-9221-da94217ad276
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086717319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s pi_device_same_csr_outstanding.2086717319
Directory	/workspace/3.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.461920503
Short name	T169
Test name
Test status
Simulation time	60012950 ps
CPU time	2.05 seconds
Started	Jan 10 12:27:44 PM PST 24
Finished	Jan 10 12:28:00 PM PST 24
Peak memory	215868 kb
Host	smart-6f31c2be-5a64-4adb-90c7-fc93fca39a3d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461920503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.461920503
Directory	/workspace/3.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3814083055
Short name	T19
Test name
Test status
Simulation time	1021970684 ps
CPU time	20.48 seconds
Started	Jan 10 12:30:49 PM PST 24
Finished	Jan 10 12:31:54 PM PST 24
Peak memory	215580 kb
Host	smart-2ef4343d-7ab2-434e-aa61-0cdaffe07249
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814083055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device _tl_intg_err.3814083055
Directory	/workspace/3.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.spi_device_intr_test.1706945920
Short name	T127
Test name
Test status
Simulation time	11393039 ps
CPU time	0.76 seconds
Started	Jan 10 12:27:32 PM PST 24
Finished	Jan 10 12:27:38 PM PST 24
Peak memory	204768 kb
Host	smart-69c3db44-fbc5-481e-ad9c-9478b01d21ab
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706945920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test. 1706945920
Directory	/workspace/30.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.spi_device_intr_test.800015204
Short name	T69
Test name
Test status
Simulation time	48139761 ps
CPU time	0.75 seconds
Started	Jan 10 12:38:18 PM PST 24
Finished	Jan 10 12:38:54 PM PST 24
Peak memory	204888 kb
Host	smart-4d1c2712-dca0-49ca-b724-67f3658c3011
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800015204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.800015204
Directory	/workspace/31.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.spi_device_intr_test.1766377297
Short name	T74
Test name
Test status
Simulation time	14361981 ps
CPU time	0.73 seconds
Started	Jan 10 12:23:42 PM PST 24
Finished	Jan 10 12:23:44 PM PST 24
Peak memory	205268 kb
Host	smart-b8d0bd2f-1a6c-4bae-b53e-ec80f8c20874
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766377297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test. 1766377297
Directory	/workspace/32.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.spi_device_intr_test.1152869936
Short name	T56
Test name
Test status
Simulation time	12191436 ps
CPU time	0.73 seconds
Started	Jan 10 12:25:42 PM PST 24
Finished	Jan 10 12:25:43 PM PST 24
Peak memory	205028 kb
Host	smart-d349f9ba-a79a-419e-bea4-c9b8198edf9b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152869936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test. 1152869936
Directory	/workspace/33.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.spi_device_intr_test.3343584867
Short name	T73
Test name
Test status
Simulation time	17270592 ps
CPU time	0.68 seconds
Started	Jan 10 12:28:24 PM PST 24
Finished	Jan 10 12:28:36 PM PST 24
Peak memory	204636 kb
Host	smart-b989acbf-2be8-47d8-ba26-da1e51041085
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343584867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test. 3343584867
Directory	/workspace/34.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.spi_device_intr_test.77925346
Short name	T116
Test name
Test status
Simulation time	50760833 ps
CPU time	0.76 seconds
Started	Jan 10 12:28:28 PM PST 24
Finished	Jan 10 12:28:39 PM PST 24
Peak memory	204768 kb
Host	smart-5e2fb4d7-f909-49e9-9708-748faecef859
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77925346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.77925346
Directory	/workspace/35.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.spi_device_intr_test.2023673163
Short name	T100
Test name
Test status
Simulation time	14282582 ps
CPU time	0.79 seconds
Started	Jan 10 12:29:41 PM PST 24
Finished	Jan 10 12:30:15 PM PST 24
Peak memory	204116 kb
Host	smart-93c8f8bd-aff0-4dbf-a872-e2120c0efcb5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023673163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test. 2023673163
Directory	/workspace/37.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.spi_device_intr_test.879992613
Short name	T113
Test name
Test status
Simulation time	27345371 ps
CPU time	0.69 seconds
Started	Jan 10 12:30:01 PM PST 24
Finished	Jan 10 12:30:43 PM PST 24
Peak memory	204576 kb
Host	smart-6a641e95-5294-4f6e-8d9e-e194e06372d7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879992613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.879992613
Directory	/workspace/38.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.spi_device_intr_test.2284841896
Short name	T81
Test name
Test status
Simulation time	69428561 ps
CPU time	0.72 seconds
Started	Jan 10 12:26:33 PM PST 24
Finished	Jan 10 12:26:37 PM PST 24
Peak memory	204600 kb
Host	smart-2576a479-d1aa-41ae-8bbd-47a8cab33d8e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284841896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test. 2284841896
Directory	/workspace/39.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2936864104
Short name	T35
Test name
Test status
Simulation time	1835671863 ps
CPU time	9.33 seconds
Started	Jan 10 12:27:01 PM PST 24
Finished	Jan 10 12:27:17 PM PST 24
Peak memory	216724 kb
Host	smart-fa3f6eef-342e-462c-8895-342b5e1e210f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936864104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs r_aliasing.2936864104
Directory	/workspace/4.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.317546857
Short name	T7
Test name
Test status
Simulation time	702715342 ps
CPU time	13.96 seconds
Started	Jan 10 12:30:26 PM PST 24
Finished	Jan 10 12:31:21 PM PST 24
Peak memory	214264 kb
Host	smart-95419698-24d9-4ee6-ac17-71a810e7fa14
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317546857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr _bit_bash.317546857
Directory	/workspace/4.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4139484333
Short name	T50
Test name
Test status
Simulation time	71081426 ps
CPU time	1.16 seconds
Started	Jan 10 12:29:39 PM PST 24
Finished	Jan 10 12:30:11 PM PST 24
Peak memory	206956 kb
Host	smart-ade1df8f-cbed-4c80-9aeb-b988d2c7e104
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139484333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs r_hw_reset.4139484333
Directory	/workspace/4.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3630098855
Short name	T54
Test name
Test status
Simulation time	33566005 ps
CPU time	1.81 seconds
Started	Jan 10 12:24:40 PM PST 24
Finished	Jan 10 12:24:43 PM PST 24
Peak memory	218340 kb
Host	smart-62af712d-10cb-44a3-b1ba-d95fa5a2b173
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630098855 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3630098855
Directory	/workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2655633340
Short name	T120
Test name
Test status
Simulation time	98471465 ps
CPU time	1.8 seconds
Started	Jan 10 12:25:39 PM PST 24
Finished	Jan 10 12:25:41 PM PST 24
Peak memory	208080 kb
Host	smart-6daf962c-28fe-4df5-b95d-adb295ce3288
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655633340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2 655633340
Directory	/workspace/4.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_intr_test.3002841006
Short name	T61
Test name
Test status
Simulation time	15172669 ps
CPU time	0.72 seconds
Started	Jan 10 12:30:00 PM PST 24
Finished	Jan 10 12:30:43 PM PST 24
Peak memory	203936 kb
Host	smart-4e6c5118-69c0-4240-a435-2fd6a8598816
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002841006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3 002841006
Directory	/workspace/4.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3825304025
Short name	T15
Test name
Test status
Simulation time	203189516 ps
CPU time	4.11 seconds
Started	Jan 10 12:30:00 PM PST 24
Finished	Jan 10 12:30:47 PM PST 24
Peak memory	214848 kb
Host	smart-128e3110-4a7d-4457-b005-e00a4b939b88
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825304025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi _device_mem_partial_access.3825304025
Directory	/workspace/4.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3614844792
Short name	T18
Test name
Test status
Simulation time	301034314 ps
CPU time	4.93 seconds
Started	Jan 10 12:27:03 PM PST 24
Finished	Jan 10 12:27:14 PM PST 24
Peak memory	215700 kb
Host	smart-0905498a-869a-497b-8859-eb205f9c69db
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614844792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me m_walk.3614844792
Directory	/workspace/4.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4268382377
Short name	T147
Test name
Test status
Simulation time	1272213929 ps
CPU time	2.83 seconds
Started	Jan 10 12:29:17 PM PST 24
Finished	Jan 10 12:29:44 PM PST 24
Peak memory	214916 kb
Host	smart-76dbac4e-568d-474e-8430-31a7882a01b0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268382377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s pi_device_same_csr_outstanding.4268382377
Directory	/workspace/4.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.892689842
Short name	T67
Test name
Test status
Simulation time	1236721942 ps
CPU time	12.09 seconds
Started	Jan 10 12:27:49 PM PST 24
Finished	Jan 10 12:28:15 PM PST 24
Peak memory	223876 kb
Host	smart-4af99528-8eab-4435-8fa1-1a1ea06e0f30
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892689842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_ tl_intg_err.892689842
Directory	/workspace/4.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.spi_device_intr_test.4074546175
Short name	T60
Test name
Test status
Simulation time	29248641 ps
CPU time	0.71 seconds
Started	Jan 10 12:28:25 PM PST 24
Finished	Jan 10 12:28:37 PM PST 24
Peak memory	204644 kb
Host	smart-0a92ad86-9dbe-4d7f-8ba4-127fd7dd3e75
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074546175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test. 4074546175
Directory	/workspace/40.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.spi_device_intr_test.2318982305
Short name	T45
Test name
Test status
Simulation time	25817905 ps
CPU time	0.84 seconds
Started	Jan 10 12:26:16 PM PST 24
Finished	Jan 10 12:26:20 PM PST 24
Peak memory	204100 kb
Host	smart-75b45088-0ced-49b8-bbe2-f77d29de2f6e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318982305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test. 2318982305
Directory	/workspace/41.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.spi_device_intr_test.2361877991
Short name	T99
Test name
Test status
Simulation time	48314227 ps
CPU time	0.75 seconds
Started	Jan 10 12:28:08 PM PST 24
Finished	Jan 10 12:28:24 PM PST 24
Peak memory	204156 kb
Host	smart-076ca034-fc3a-47ba-b47b-2880cf0af846
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361877991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test. 2361877991
Directory	/workspace/42.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.spi_device_intr_test.4097658362
Short name	T62
Test name
Test status
Simulation time	11198697 ps
CPU time	0.75 seconds
Started	Jan 10 12:24:57 PM PST 24
Finished	Jan 10 12:24:59 PM PST 24
Peak memory	204752 kb
Host	smart-b9f94edf-0d00-4ca4-99ab-9413ae0ccd82
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097658362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test. 4097658362
Directory	/workspace/43.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.spi_device_intr_test.23374501
Short name	T13
Test name
Test status
Simulation time	15136045 ps
CPU time	0.75 seconds
Started	Jan 10 12:26:40 PM PST 24
Finished	Jan 10 12:26:46 PM PST 24
Peak memory	204096 kb
Host	smart-59a334a1-f950-45ab-bcea-f50b8cdafb4b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23374501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.23374501
Directory	/workspace/45.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.spi_device_intr_test.2896453961
Short name	T46
Test name
Test status
Simulation time	45849633 ps
CPU time	0.74 seconds
Started	Jan 10 12:27:31 PM PST 24
Finished	Jan 10 12:27:37 PM PST 24
Peak memory	204908 kb
Host	smart-36d604bc-135e-4c4b-956e-55604b072fdd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896453961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test. 2896453961
Directory	/workspace/46.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.spi_device_intr_test.3686557806
Short name	T132
Test name
Test status
Simulation time	40708023 ps
CPU time	0.71 seconds
Started	Jan 10 12:27:07 PM PST 24
Finished	Jan 10 12:27:14 PM PST 24
Peak memory	204844 kb
Host	smart-527a8807-589b-470b-9501-389280aaa3d3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686557806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test. 3686557806
Directory	/workspace/47.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.spi_device_intr_test.2357923392
Short name	T117
Test name
Test status
Simulation time	27842856 ps
CPU time	0.92 seconds
Started	Jan 10 12:25:13 PM PST 24
Finished	Jan 10 12:25:14 PM PST 24
Peak memory	204824 kb
Host	smart-17e847b2-032a-4af9-a5ac-85b6bf8b7e89
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357923392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test. 2357923392
Directory	/workspace/48.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.spi_device_intr_test.1857478122
Short name	T136
Test name
Test status
Simulation time	63297525 ps
CPU time	0.77 seconds
Started	Jan 10 12:27:07 PM PST 24
Finished	Jan 10 12:27:14 PM PST 24
Peak memory	204812 kb
Host	smart-28a16a2b-adce-43d9-b6be-70d15aad910e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857478122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test. 1857478122
Directory	/workspace/49.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3461006980
Short name	T52
Test name
Test status
Simulation time	18382626 ps
CPU time	1.21 seconds
Started	Jan 10 12:29:19 PM PST 24
Finished	Jan 10 12:29:45 PM PST 24
Peak memory	216844 kb
Host	smart-84a642a9-a8d9-4087-b42a-82e283429986
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461006980 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3461006980
Directory	/workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.709921894
Short name	T94
Test name
Test status
Simulation time	22865756 ps
CPU time	1.38 seconds
Started	Jan 10 12:27:01 PM PST 24
Finished	Jan 10 12:27:09 PM PST 24
Peak memory	207560 kb
Host	smart-fe06253f-9246-4dc1-8bdc-224c00290b15
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709921894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.709921894
Directory	/workspace/5.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_intr_test.1659743677
Short name	T44
Test name
Test status
Simulation time	25199894 ps
CPU time	0.73 seconds
Started	Jan 10 12:29:01 PM PST 24
Finished	Jan 10 12:29:21 PM PST 24
Peak memory	204100 kb
Host	smart-b3edeef5-784a-47ad-ba87-096f8ca7a02d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659743677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1 659743677
Directory	/workspace/5.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4195067582
Short name	T149
Test name
Test status
Simulation time	83386644 ps
CPU time	1.81 seconds
Started	Jan 10 12:29:16 PM PST 24
Finished	Jan 10 12:29:41 PM PST 24
Peak memory	215472 kb
Host	smart-f2410fe5-a526-4659-9db6-f7a652df4fc9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195067582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s pi_device_same_csr_outstanding.4195067582
Directory	/workspace/5.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1043134551
Short name	T103
Test name
Test status
Simulation time	550886191 ps
CPU time	3.55 seconds
Started	Jan 10 12:30:00 PM PST 24
Finished	Jan 10 12:30:50 PM PST 24
Peak memory	220368 kb
Host	smart-779352ec-2d2b-4baa-9427-ff0439df0227
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043134551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1 043134551
Directory	/workspace/5.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1801245830
Short name	T30
Test name
Test status
Simulation time	395917325 ps
CPU time	11.52 seconds
Started	Jan 10 12:29:56 PM PST 24
Finished	Jan 10 12:30:46 PM PST 24
Peak memory	215872 kb
Host	smart-e04c1faf-4f00-4130-8389-24a51367ac85
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801245830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device _tl_intg_err.1801245830
Directory	/workspace/5.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2345030721
Short name	T110
Test name
Test status
Simulation time	77133696 ps
CPU time	1.64 seconds
Started	Jan 10 12:24:27 PM PST 24
Finished	Jan 10 12:24:29 PM PST 24
Peak memory	217208 kb
Host	smart-e69c2183-888d-4436-82a1-04257b1774df
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345030721 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2345030721
Directory	/workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2258402496
Short name	T175
Test name
Test status
Simulation time	353834705 ps
CPU time	2.31 seconds
Started	Jan 10 12:30:34 PM PST 24
Finished	Jan 10 12:31:18 PM PST 24
Peak memory	207452 kb
Host	smart-e91d906b-808f-4e58-b9da-cdc09d1bff96
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258402496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2 258402496
Directory	/workspace/6.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_intr_test.4243369888
Short name	T125
Test name
Test status
Simulation time	82918742 ps
CPU time	0.77 seconds
Started	Jan 10 12:26:34 PM PST 24
Finished	Jan 10 12:26:38 PM PST 24
Peak memory	205028 kb
Host	smart-f39bdb07-fcdc-451a-a78c-dad28cd1c7f1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243369888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4 243369888
Directory	/workspace/6.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.204825240
Short name	T91
Test name
Test status
Simulation time	93879519 ps
CPU time	3.29 seconds
Started	Jan 10 12:24:59 PM PST 24
Finished	Jan 10 12:25:03 PM PST 24
Peak memory	216232 kb
Host	smart-db20199f-085f-4c79-8bdb-98f9c1028a64
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204825240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp i_device_same_csr_outstanding.204825240
Directory	/workspace/6.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2174793138
Short name	T161
Test name
Test status
Simulation time	24596208 ps
CPU time	1.73 seconds
Started	Jan 10 12:29:16 PM PST 24
Finished	Jan 10 12:29:42 PM PST 24
Peak memory	215664 kb
Host	smart-b59f52f4-5d27-484e-8b2b-610870df6fe5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174793138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2 174793138
Directory	/workspace/6.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2556288090
Short name	T128
Test name
Test status
Simulation time	2976038473 ps
CPU time	16.96 seconds
Started	Jan 10 12:25:04 PM PST 24
Finished	Jan 10 12:25:22 PM PST 24
Peak memory	216316 kb
Host	smart-ab4f760f-2697-431d-b6a4-dbd0fa31e61f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556288090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device _tl_intg_err.2556288090
Directory	/workspace/6.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.908962069
Short name	T72
Test name
Test status
Simulation time	64243944 ps
CPU time	1.71 seconds
Started	Jan 10 12:25:42 PM PST 24
Finished	Jan 10 12:25:44 PM PST 24
Peak memory	217488 kb
Host	smart-6579be72-8ffa-41a7-9c44-03bf1f2c9798
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908962069 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.908962069
Directory	/workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.363652866
Short name	T139
Test name
Test status
Simulation time	152422567 ps
CPU time	1.34 seconds
Started	Jan 10 12:23:51 PM PST 24
Finished	Jan 10 12:23:53 PM PST 24
Peak memory	207272 kb
Host	smart-673ca463-c2c3-4c15-a8fa-6971ee6adf65
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363652866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.363652866
Directory	/workspace/7.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3997287422
Short name	T150
Test name
Test status
Simulation time	564528853 ps
CPU time	2.88 seconds
Started	Jan 10 12:29:16 PM PST 24
Finished	Jan 10 12:29:48 PM PST 24
Peak memory	216944 kb
Host	smart-676f86f5-b4a6-4782-b419-0c74401aec37
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997287422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s pi_device_same_csr_outstanding.3997287422
Directory	/workspace/7.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2973935464
Short name	T27
Test name
Test status
Simulation time	232602350 ps
CPU time	5.2 seconds
Started	Jan 10 12:24:43 PM PST 24
Finished	Jan 10 12:24:49 PM PST 24
Peak memory	215936 kb
Host	smart-4f6d10f9-b19e-438c-a21f-43d34044006d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973935464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2 973935464
Directory	/workspace/7.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1020414983
Short name	T89
Test name
Test status
Simulation time	7485637309 ps
CPU time	19.92 seconds
Started	Jan 10 12:28:07 PM PST 24
Finished	Jan 10 12:28:43 PM PST 24
Peak memory	215976 kb
Host	smart-af284f56-6431-42ba-bbeb-b8a4a115e8a9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020414983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device _tl_intg_err.1020414983
Directory	/workspace/7.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.274739254
Short name	T111
Test name
Test status
Simulation time	126166363 ps
CPU time	2.13 seconds
Started	Jan 10 12:29:48 PM PST 24
Finished	Jan 10 12:30:24 PM PST 24
Peak memory	218288 kb
Host	smart-1f431ede-9a93-40ef-8f26-c2e1a7f843ef
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274739254 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.274739254
Directory	/workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2202933084
Short name	T87
Test name
Test status
Simulation time	431001715 ps
CPU time	2.23 seconds
Started	Jan 10 12:29:15 PM PST 24
Finished	Jan 10 12:29:41 PM PST 24
Peak memory	215744 kb
Host	smart-9a693144-3943-4704-bbad-f96e8198bb64
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202933084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2 202933084
Directory	/workspace/8.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_intr_test.950039051
Short name	T165
Test name
Test status
Simulation time	17468745 ps
CPU time	0.71 seconds
Started	Jan 10 12:29:18 PM PST 24
Finished	Jan 10 12:29:43 PM PST 24
Peak memory	204656 kb
Host	smart-58d19e7a-9d65-48a2-992d-2372efe2d677
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950039051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.950039051
Directory	/workspace/8.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.176113426
Short name	T135
Test name
Test status
Simulation time	134013892 ps
CPU time	1.9 seconds
Started	Jan 10 12:27:31 PM PST 24
Finished	Jan 10 12:27:38 PM PST 24
Peak memory	215776 kb
Host	smart-7c086b48-715a-4a4b-ac03-255068374a36
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176113426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp i_device_same_csr_outstanding.176113426
Directory	/workspace/8.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.761153178
Short name	T154
Test name
Test status
Simulation time	454189990 ps
CPU time	3.26 seconds
Started	Jan 10 12:30:26 PM PST 24
Finished	Jan 10 12:31:10 PM PST 24
Peak memory	214524 kb
Host	smart-abf6abb2-1956-4855-a3fa-93dfebc32230
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761153178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.761153178
Directory	/workspace/8.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2465448285
Short name	T65
Test name
Test status
Simulation time	1281815114 ps
CPU time	13.16 seconds
Started	Jan 10 12:30:26 PM PST 24
Finished	Jan 10 12:31:20 PM PST 24
Peak memory	216232 kb
Host	smart-17225688-350e-4383-ad28-b406ac848f17
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465448285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device _tl_intg_err.2465448285
Directory	/workspace/8.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3963252877
Short name	T92
Test name
Test status
Simulation time	462144630 ps
CPU time	2.75 seconds
Started	Jan 10 12:25:59 PM PST 24
Finished	Jan 10 12:26:13 PM PST 24
Peak memory	218224 kb
Host	smart-f45950c1-1f51-4929-a91c-99c4955a3c66
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963252877 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3963252877
Directory	/workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1537984353
Short name	T40
Test name
Test status
Simulation time	101342831 ps
CPU time	2.42 seconds
Started	Jan 10 12:28:04 PM PST 24
Finished	Jan 10 12:28:22 PM PST 24
Peak memory	215784 kb
Host	smart-53190ca0-3aaf-4fa6-a2bb-0509f8ec4d07
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537984353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1 537984353
Directory	/workspace/9.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_intr_test.3267823456
Short name	T138
Test name
Test status
Simulation time	15480634 ps
CPU time	0.76 seconds
Started	Jan 10 12:30:55 PM PST 24
Finished	Jan 10 12:31:42 PM PST 24
Peak memory	203928 kb
Host	smart-a1ae01f6-a68e-4054-8969-42b5049fb4c0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267823456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3 267823456
Directory	/workspace/9.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3779674843
Short name	T55
Test name
Test status
Simulation time	225079657 ps
CPU time	4.24 seconds
Started	Jan 10 12:30:29 PM PST 24
Finished	Jan 10 12:31:16 PM PST 24
Peak memory	215708 kb
Host	smart-a219dfbf-16eb-4264-8a9f-b37ecf65458b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779674843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s pi_device_same_csr_outstanding.3779674843
Directory	/workspace/9.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.912555118
Short name	T24
Test name
Test status
Simulation time	63064046 ps
CPU time	1.84 seconds
Started	Jan 10 12:24:27 PM PST 24
Finished	Jan 10 12:24:30 PM PST 24
Peak memory	215884 kb
Host	smart-375483c7-2aba-4c66-bd83-b4162ce8df04
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912555118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.912555118
Directory	/workspace/9.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2723906689
Short name	T22
Test name
Test status
Simulation time	768693359 ps
CPU time	6.39 seconds
Started	Jan 10 12:28:36 PM PST 24
Finished	Jan 10 12:28:55 PM PST 24
Peak memory	214936 kb
Host	smart-46e4ebe3-8fcf-4640-a5c0-9affe09c4e2e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723906689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device _tl_intg_err.2723906689
Directory	/workspace/9.spi_device_tl_intg_err/latest