Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	12	0	12	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	419	1			T2	1		T3	5		T12	8
all_pins[1]	419	1			T2	1		T3	5		T12	8
all_pins[2]	419	1			T2	1		T3	5		T12	8
all_pins[3]	419	1			T2	1		T3	5		T12	8
all_pins[4]	419	1			T2	1		T3	5		T12	8
all_pins[5]	419	1			T2	1		T3	5		T12	8
all_pins[6]	419	1			T2	1		T3	5		T12	8
all_pins[7]	419	1			T2	1		T3	5		T12	8
all_pins[8]	419	1			T2	1		T3	5		T12	8
all_pins[9]	419	1			T2	1		T3	5		T12	8
all_pins[10]	419	1			T2	1		T3	5		T12	8
all_pins[11]	419	1			T2	1		T3	5		T12	8

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	4053	1			T2	12		T3	52		T12	69
values[0x1]	975	1			T3	8		T12	27		T13	21
transitions[0x0=>0x1]	727	1			T3	7		T12	17		T13	17
transitions[0x1=>0x0]	744	1			T3	8		T12	17		T13	17

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	339	1			T2	1		T3	2		T12	7
all_pins[0]	values[0x1]	80	1			T3	3		T12	1		T13	3
all_pins[0]	transitions[0x0=>0x1]	61	1			T3	3		T12	1		T13	1
all_pins[0]	transitions[0x1=>0x0]	55	1			T3	1		T12	2		T13	1
all_pins[1]	values[0x0]	345	1			T2	1		T3	4		T12	6
all_pins[1]	values[0x1]	74	1			T3	1		T12	2		T13	3
all_pins[1]	transitions[0x0=>0x1]	58	1			T3	1		T13	3		T44	2
all_pins[1]	transitions[0x1=>0x0]	59	1			T59	3		T60	3		T63	1
all_pins[2]	values[0x0]	344	1			T2	1		T3	5		T12	6
all_pins[2]	values[0x1]	75	1			T12	2		T46	4		T56	1
all_pins[2]	transitions[0x0=>0x1]	51	1			T46	4		T59	2		T60	2
all_pins[2]	transitions[0x1=>0x0]	66	1			T12	3		T13	3		T45	3
all_pins[3]	values[0x0]	329	1			T2	1		T3	5		T12	3
all_pins[3]	values[0x1]	90	1			T12	5		T13	3		T45	3
all_pins[3]	transitions[0x0=>0x1]	64	1			T12	3		T13	2		T45	3
all_pins[3]	transitions[0x1=>0x0]	53	1			T12	1		T45	1		T46	1
all_pins[4]	values[0x0]	340	1			T2	1		T3	5		T12	5
all_pins[4]	values[0x1]	79	1			T12	3		T13	1		T45	1
all_pins[4]	transitions[0x0=>0x1]	56	1			T12	2		T13	1		T45	1
all_pins[4]	transitions[0x1=>0x0]	67	1			T3	1		T12	2		T13	2
all_pins[5]	values[0x0]	329	1			T2	1		T3	4		T12	5
all_pins[5]	values[0x1]	90	1			T3	1		T12	3		T13	2
all_pins[5]	transitions[0x0=>0x1]	69	1			T3	1		T12	2		T13	2
all_pins[5]	transitions[0x1=>0x0]	54	1			T44	1		T45	5		T46	2
all_pins[6]	values[0x0]	344	1			T2	1		T3	5		T12	7
all_pins[6]	values[0x1]	75	1			T12	1		T44	1		T45	5
all_pins[6]	transitions[0x0=>0x1]	59	1			T44	1		T45	4		T46	1
all_pins[6]	transitions[0x1=>0x0]	66	1			T12	3		T13	1		T45	1
all_pins[7]	values[0x0]	337	1			T2	1		T3	5		T12	4
all_pins[7]	values[0x1]	82	1			T12	4		T13	1		T45	2
all_pins[7]	transitions[0x0=>0x1]	70	1			T12	4		T13	1		T45	1
all_pins[7]	transitions[0x1=>0x0]	54	1			T3	1		T12	2		T13	2
all_pins[8]	values[0x0]	353	1			T2	1		T3	4		T12	6
all_pins[8]	values[0x1]	66	1			T3	1		T12	2		T13	2
all_pins[8]	transitions[0x0=>0x1]	51	1			T3	1		T12	2		T13	2
all_pins[8]	transitions[0x1=>0x0]	74	1			T12	2		T44	1		T45	2
all_pins[9]	values[0x0]	330	1			T2	1		T3	5		T12	6
all_pins[9]	values[0x1]	89	1			T12	2		T44	1		T45	3
all_pins[9]	transitions[0x0=>0x1]	64	1			T12	2		T45	2		T56	1
all_pins[9]	transitions[0x1=>0x0]	65	1			T12	1		T13	5		T45	3
all_pins[10]	values[0x0]	329	1			T2	1		T3	5		T12	7
all_pins[10]	values[0x1]	90	1			T12	1		T13	5		T44	1
all_pins[10]	transitions[0x0=>0x1]	69	1			T12	1		T13	4		T44	1
all_pins[10]	transitions[0x1=>0x0]	64	1			T3	2		T12	1		T44	1
all_pins[11]	values[0x0]	334	1			T2	1		T3	3		T12	7
all_pins[11]	values[0x1]	85	1			T3	2		T12	1		T13	1
all_pins[11]	transitions[0x0=>0x1]	55	1			T3	1		T13	1		T46	2
all_pins[11]	transitions[0x1=>0x0]	67	1			T3	3		T13	3		T56	4