Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	72	2	70	97.22

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	72	2	70	97.22	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	350	1			T3	4		T12	7		T13	7
all_values[1]	350	1			T3	4		T12	7		T13	7
all_values[2]	350	1			T3	4		T12	7		T13	7
all_values[3]	350	1			T3	4		T12	7		T13	7
all_values[4]	350	1			T3	4		T12	7		T13	7
all_values[5]	350	1			T3	4		T12	7		T13	7
all_values[6]	350	1			T3	4		T12	7		T13	7
all_values[7]	350	1			T3	4		T12	7		T13	7
all_values[8]	350	1			T3	4		T12	7		T13	7
all_values[9]	350	1			T3	4		T12	7		T13	7
all_values[10]	350	1			T3	4		T12	7		T13	7
all_values[11]	350	1			T3	4		T12	7		T13	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2261

1

T3

20

T12

41

T13

41

auto[1]

1939

1

T3

28

T12

43

T13

43

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1645

1

T3

30

T12

31

T13

37

auto[1]

2555

1

T3

18

T12

53

T13

47

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2354

1

T3

33

T12

47

T13

49

auto[1]

1846

1

T3

15

T12

37

T13

35

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	2	70	97.22	2
Automatically Generated Cross Bins	72	2	70	97.22	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[11]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	76	1			T3	1		T12	4		T13	2
all_values[0]	auto[0]	auto[0]	auto[1]	33	1			T57	3		T59	1		T60	1
all_values[0]	auto[0]	auto[1]	auto[0]	58	1			T12	1		T44	1		T45	3
all_values[0]	auto[0]	auto[1]	auto[1]	30	1			T3	1		T13	1		T56	2
all_values[0]	auto[1]	auto[0]	auto[1]	83	1			T12	1		T13	1		T45	1
all_values[0]	auto[1]	auto[1]	auto[1]	70	1			T3	2		T12	1		T13	3
all_values[1]	auto[0]	auto[0]	auto[0]	69	1			T3	1		T12	1		T45	3
all_values[1]	auto[0]	auto[0]	auto[1]	28	1			T13	1		T57	1		T61	1
all_values[1]	auto[0]	auto[1]	auto[0]	68	1			T3	1		T12	1		T13	3
all_values[1]	auto[0]	auto[1]	auto[1]	32	1			T12	2		T13	2		T44	1
all_values[1]	auto[1]	auto[0]	auto[1]	93	1			T3	1		T12	3		T13	1
all_values[1]	auto[1]	auto[1]	auto[1]	60	1			T3	1		T44	1		T46	3
all_values[2]	auto[0]	auto[0]	auto[0]	84	1			T3	1		T12	2		T13	4
all_values[2]	auto[0]	auto[0]	auto[1]	30	1			T12	1		T44	1		T45	2
all_values[2]	auto[0]	auto[1]	auto[0]	64	1			T3	2		T13	2		T45	1
all_values[2]	auto[0]	auto[1]	auto[1]	29	1			T46	1		T59	1		T60	1
all_values[2]	auto[1]	auto[0]	auto[1]	77	1			T3	1		T12	3		T13	1
all_values[2]	auto[1]	auto[1]	auto[1]	66	1			T12	1		T46	2		T56	2
all_values[3]	auto[0]	auto[0]	auto[0]	72	1			T12	1		T44	2		T45	2
all_values[3]	auto[0]	auto[0]	auto[1]	22	1			T45	2		T59	1		T60	1
all_values[3]	auto[0]	auto[1]	auto[0]	63	1			T3	3		T44	1		T46	2
all_values[3]	auto[0]	auto[1]	auto[1]	39	1			T12	2		T13	1		T45	1
all_values[3]	auto[1]	auto[0]	auto[1]	95	1			T3	1		T12	3		T13	3
all_values[3]	auto[1]	auto[1]	auto[1]	59	1			T12	1		T13	3		T44	1
all_values[4]	auto[0]	auto[0]	auto[0]	70	1			T3	2		T13	2		T44	1
all_values[4]	auto[0]	auto[0]	auto[1]	31	1			T12	1		T45	3		T57	1
all_values[4]	auto[0]	auto[1]	auto[0]	65	1			T3	2		T12	1		T13	1
all_values[4]	auto[0]	auto[1]	auto[1]	36	1			T12	1		T13	2		T46	3
all_values[4]	auto[1]	auto[0]	auto[1]	81	1			T12	1		T13	1		T44	1
all_values[4]	auto[1]	auto[1]	auto[1]	67	1			T12	3		T13	1		T45	2
all_values[5]	auto[0]	auto[0]	auto[0]	62	1			T3	1		T12	1		T13	2
all_values[5]	auto[0]	auto[0]	auto[1]	25	1			T12	2		T13	1		T45	1
all_values[5]	auto[0]	auto[1]	auto[0]	66	1			T3	2		T13	1		T44	3
all_values[5]	auto[0]	auto[1]	auto[1]	36	1			T12	2		T46	2		T60	2
all_values[5]	auto[1]	auto[0]	auto[1]	91	1			T12	1		T13	3		T45	2
all_values[5]	auto[1]	auto[1]	auto[1]	70	1			T3	1		T12	1		T45	1
all_values[6]	auto[0]	auto[0]	auto[0]	79	1			T12	2		T13	2		T44	2
all_values[6]	auto[0]	auto[0]	auto[1]	44	1			T3	1		T46	1		T57	1
all_values[6]	auto[0]	auto[1]	auto[0]	48	1			T3	2		T12	3		T13	3
all_values[6]	auto[0]	auto[1]	auto[1]	28	1			T44	1		T45	2		T46	1
all_values[6]	auto[1]	auto[0]	auto[1]	77	1			T13	1		T45	4		T46	1
all_values[6]	auto[1]	auto[1]	auto[1]	74	1			T3	1		T12	2		T13	1
all_values[7]	auto[0]	auto[0]	auto[0]	76	1			T3	2		T13	1		T44	3
all_values[7]	auto[0]	auto[0]	auto[1]	35	1			T13	1		T46	1		T56	1
all_values[7]	auto[0]	auto[1]	auto[0]	56	1			T3	1		T12	1		T44	1
all_values[7]	auto[0]	auto[1]	auto[1]	28	1			T12	2		T45	2		T62	1
all_values[7]	auto[1]	auto[0]	auto[1]	91	1			T3	1		T13	5		T45	1
all_values[7]	auto[1]	auto[1]	auto[1]	64	1			T12	4		T45	1		T46	3
all_values[8]	auto[0]	auto[0]	auto[0]	79	1			T3	3		T13	1		T45	4
all_values[8]	auto[0]	auto[0]	auto[1]	29	1			T12	1		T44	1		T45	1
all_values[8]	auto[0]	auto[1]	auto[0]	66	1			T13	2		T44	2		T45	1
all_values[8]	auto[0]	auto[1]	auto[1]	31	1			T12	2		T13	1		T45	1
all_values[8]	auto[1]	auto[0]	auto[1]	94	1			T12	4		T13	1		T44	1
all_values[8]	auto[1]	auto[1]	auto[1]	51	1			T3	1		T13	2		T45	2
all_values[9]	auto[0]	auto[0]	auto[0]	54	1			T12	3		T13	3		T45	1
all_values[9]	auto[0]	auto[0]	auto[1]	38	1			T3	1		T44	1		T46	1
all_values[9]	auto[0]	auto[1]	auto[0]	53	1			T3	1		T12	1		T13	3
all_values[9]	auto[0]	auto[1]	auto[1]	32	1			T44	1		T56	1		T57	1
all_values[9]	auto[1]	auto[0]	auto[1]	97	1			T3	2		T12	3		T45	2
all_values[9]	auto[1]	auto[1]	auto[1]	76	1			T13	1		T44	1		T45	2
all_values[10]	auto[0]	auto[0]	auto[0]	62	1			T12	1		T44	2		T45	1
all_values[10]	auto[0]	auto[0]	auto[1]	32	1			T45	1		T57	2		T60	1
all_values[10]	auto[0]	auto[1]	auto[0]	55	1			T3	3		T12	4		T13	1
all_values[10]	auto[0]	auto[1]	auto[1]	41	1			T13	2		T44	1		T46	3
all_values[10]	auto[1]	auto[0]	auto[1]	80	1			T3	1		T45	1		T46	3
all_values[10]	auto[1]	auto[1]	auto[1]	80	1			T12	2		T13	4		T44	1
all_values[11]	auto[0]	auto[0]	auto[0]	94	1			T12	1		T13	2		T44	1
all_values[11]	auto[0]	auto[1]	auto[0]	106	1			T3	2		T12	3		T13	2
all_values[11]	auto[1]	auto[0]	auto[1]	78	1			T12	1		T13	2		T44	1
all_values[11]	auto[1]	auto[1]	auto[1]	72	1			T3	2		T12	2		T13	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal