Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	410	1			T3	1		T7	8		T13	5
all_values[1]	410	1			T3	1		T7	8		T13	5
all_values[2]	410	1			T3	1		T7	8		T13	5
all_values[3]	410	1			T3	1		T7	8		T13	5
all_values[4]	410	1			T3	1		T7	8		T13	5
all_values[5]	410	1			T3	1		T7	8		T13	5
all_values[6]	410	1			T3	1		T7	8		T13	5
all_values[7]	410	1			T3	1		T7	8		T13	5
all_values[8]	410	1			T3	1		T7	8		T13	5
all_values[9]	410	1			T3	1		T7	8		T13	5
all_values[10]	410	1			T3	1		T7	8		T13	5
all_values[11]	410	1			T3	1		T7	8		T13	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2587

1

T3

12

T7

59

T13

27

auto[1]

2333

1

T7

37

T13

33

T11

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2983

1

T3

12

T7

73

T13

44

auto[1]

1937

1

T7

23

T13

16

T11

14

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	135	1			T3	1		T7	1		T13	3
all_values[0]	auto[0]	auto[1]	85	1			T7	3		T11	1		T14	5
all_values[0]	auto[1]	auto[0]	98	1			T7	1		T13	2		T11	3
all_values[0]	auto[1]	auto[1]	92	1			T7	3		T11	1		T12	1
all_values[1]	auto[0]	auto[0]	122	1			T3	1		T7	4		T13	1
all_values[1]	auto[0]	auto[1]	95	1			T13	3		T12	1		T14	3
all_values[1]	auto[1]	auto[0]	114	1			T7	4		T11	1		T12	1
all_values[1]	auto[1]	auto[1]	79	1			T13	1		T11	1		T12	3
all_values[2]	auto[0]	auto[0]	142	1			T3	1		T7	5		T13	4
all_values[2]	auto[0]	auto[1]	81	1			T12	1		T15	1		T16	4
all_values[2]	auto[1]	auto[0]	111	1			T7	2		T13	1		T11	4
all_values[2]	auto[1]	auto[1]	76	1			T7	1		T11	1		T12	1
all_values[3]	auto[0]	auto[0]	144	1			T3	1		T7	6		T13	3
all_values[3]	auto[0]	auto[1]	60	1			T12	3		T14	1		T16	3
all_values[3]	auto[1]	auto[0]	124	1			T7	2		T11	3		T14	4
all_values[3]	auto[1]	auto[1]	82	1			T13	2		T11	2		T14	2
all_values[4]	auto[0]	auto[0]	149	1			T3	1		T7	5		T13	1
all_values[4]	auto[0]	auto[1]	66	1			T12	2		T14	3		T15	2
all_values[4]	auto[1]	auto[0]	108	1			T7	3		T13	2		T11	1
all_values[4]	auto[1]	auto[1]	87	1			T13	2		T14	4		T15	2
all_values[5]	auto[0]	auto[0]	128	1			T3	1		T7	6		T13	1
all_values[5]	auto[0]	auto[1]	81	1			T14	3		T15	1		T16	3
all_values[5]	auto[1]	auto[0]	120	1			T7	1		T13	4		T11	1
all_values[5]	auto[1]	auto[1]	81	1			T7	1		T15	1		T16	2
all_values[6]	auto[0]	auto[0]	127	1			T3	1		T7	6		T13	1
all_values[6]	auto[0]	auto[1]	87	1			T13	2		T14	5		T50	1
all_values[6]	auto[1]	auto[0]	104	1			T11	5		T12	3		T15	1
all_values[6]	auto[1]	auto[1]	92	1			T7	2		T13	2		T14	2
all_values[7]	auto[0]	auto[0]	124	1			T3	1		T7	4		T13	1
all_values[7]	auto[0]	auto[1]	91	1			T7	1		T11	1		T12	1
all_values[7]	auto[1]	auto[0]	111	1			T7	1		T13	1		T11	4
all_values[7]	auto[1]	auto[1]	84	1			T7	2		T13	3		T12	2
all_values[8]	auto[0]	auto[0]	145	1			T3	1		T7	6		T13	5
all_values[8]	auto[0]	auto[1]	86	1			T7	1		T14	1		T15	1
all_values[8]	auto[1]	auto[0]	106	1			T11	2		T12	3		T14	3
all_values[8]	auto[1]	auto[1]	73	1			T7	1		T11	3		T14	1
all_values[9]	auto[0]	auto[0]	130	1			T3	1		T7	3		T11	2
all_values[9]	auto[0]	auto[1]	92	1			T7	3		T14	2		T16	2
all_values[9]	auto[1]	auto[0]	111	1			T7	1		T13	4		T11	1
all_values[9]	auto[1]	auto[1]	77	1			T7	1		T13	1		T11	2
all_values[10]	auto[0]	auto[0]	128	1			T3	1		T7	3		T11	4
all_values[10]	auto[0]	auto[1]	70	1			T11	1		T12	2		T14	2
all_values[10]	auto[1]	auto[0]	128	1			T7	2		T13	5		T12	1
all_values[10]	auto[1]	auto[1]	84	1			T7	3		T14	3		T15	1
all_values[11]	auto[0]	auto[0]	162	1			T3	1		T7	2		T13	2
all_values[11]	auto[0]	auto[1]	57	1			T12	1		T14	1		T15	1
all_values[11]	auto[1]	auto[0]	112	1			T7	5		T13	3		T12	2
all_values[11]	auto[1]	auto[1]	79	1			T7	1		T11	1		T12	1