Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
60.02	71.17	76.17	75.34	0.00	77.00	100.00	20.49

Total tests in report: 175

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
58.66	58.66	70.81	70.81	74.45	74.45	83.37	83.37	0.00	0.00	76.93	76.93	97.70	97.70	7.34	7.34	/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3732408064
60.44	1.79	71.04	0.23	74.92	0.47	85.65	2.28	0.00	0.00	76.93	0.00	97.70	0.00	16.87	9.53	/workspace/coverage/cover_reg_top/27.spi_device_intr_test.1945206392
61.27	0.82	71.06	0.02	75.15	0.23	87.70	2.05	0.00	0.00	76.97	0.03	98.98	1.28	19.01	2.14	/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4209140259
61.51	0.25	71.14	0.07	75.88	0.74	87.70	0.00	0.00	0.00	77.00	0.03	99.49	0.51	19.39	0.38	/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2114970422
61.60	0.09	71.14	0.00	75.88	0.00	87.70	0.00	0.00	0.00	77.00	0.00	99.49	0.00	20.01	0.62	/workspace/coverage/cover_reg_top/2.spi_device_intr_test.3088049777
61.68	0.07	71.15	0.01	75.88	0.00	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.51	20.01	0.00	/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3487995159
61.71	0.04	71.15	0.00	76.14	0.25	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.01	0.00	/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1736995475
61.73	0.02	71.15	0.00	76.14	0.00	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.15	0.14	/workspace/coverage/cover_reg_top/32.spi_device_intr_test.1911766288
61.75	0.01	71.15	0.00	76.14	0.00	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.25	0.10	/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2340181932
61.76	0.01	71.15	0.00	76.14	0.00	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.34	0.10	/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.322183070
61.77	0.01	71.17	0.02	76.15	0.01	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.39	0.05	/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3880006081
61.78	0.01	71.17	0.00	76.15	0.00	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.44	0.05	/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3436529751
61.79	0.01	71.17	0.00	76.15	0.00	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.49	0.05	/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.837301295
61.79	0.01	71.17	0.00	76.17	0.03	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.49	0.00	/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.212979090

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3546857748
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1262559173
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3960009545
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3535012898
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.2361278874
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3683891344
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1051164721
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3382173317
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2722331939
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.277209178
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3065130563
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3387588298
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.247867025
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.517274665
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.1084364429
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2528649821
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2387129290
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2120099037
/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3279251455
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1191085877
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2714025312
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.3590269511
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1600210947
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.803426394
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.430206055
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1110939193
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.1229393015
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2913118005
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.942860062
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4211261793
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1912480178
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2100745803
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.3993251438
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1452942199
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1687233832
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4068997432
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.120719487
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.2175212965
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1430656316
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1103814006
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4124606441
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.73622464
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3438396011
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.3279925979
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3954275158
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.888374537
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3398023356
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.3194180691
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1293396339
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1338430014
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1995220649
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3548955819
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.1201192540
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1808446351
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2234110967
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2633172550
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.707003983
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.477041327
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.2574919256
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3364904536
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.850431173
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3698597894
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.47723095
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3156630146
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.4023033319
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4242789317
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1440214939
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2109594267
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3912302233
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.644028545
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.3875694115
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2696786271
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1308739782
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2605829583
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3845402103
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1015563149
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.863849200
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3046874753
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1437798326
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2195690663
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.463430678
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3713924459
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2328111249
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.590990462
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.1925392342
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.1672409610
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.729100931
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.447194177
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.387033735
/workspace/coverage/cover_reg_top/26.spi_device_intr_test.986359943
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.1935648834
/workspace/coverage/cover_reg_top/29.spi_device_intr_test.1779026605
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4212895105
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1670304529
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.753289707
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1541384469
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.844640522
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.248898506
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3494758287
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3939060951
/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2808439932
/workspace/coverage/cover_reg_top/30.spi_device_intr_test.1372882690
/workspace/coverage/cover_reg_top/31.spi_device_intr_test.4238365509
/workspace/coverage/cover_reg_top/33.spi_device_intr_test.2078597174
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.1432729345
/workspace/coverage/cover_reg_top/35.spi_device_intr_test.942108432
/workspace/coverage/cover_reg_top/36.spi_device_intr_test.10305780
/workspace/coverage/cover_reg_top/37.spi_device_intr_test.766282699
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.1165469272
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.970904387
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.811243416
/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4078911261
/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1140466257
/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2196503268
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2163120841
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.1154993820
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3964623146
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2079300786
/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.845881246
/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1768199145
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3348599128
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.3291027541
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.3810122583
/workspace/coverage/cover_reg_top/42.spi_device_intr_test.3993311357
/workspace/coverage/cover_reg_top/43.spi_device_intr_test.1787639090
/workspace/coverage/cover_reg_top/44.spi_device_intr_test.1313293099
/workspace/coverage/cover_reg_top/45.spi_device_intr_test.3299859765
/workspace/coverage/cover_reg_top/46.spi_device_intr_test.2373552263
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.2739337756
/workspace/coverage/cover_reg_top/48.spi_device_intr_test.472393599
/workspace/coverage/cover_reg_top/49.spi_device_intr_test.559800011
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.544413335
/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3523723588
/workspace/coverage/cover_reg_top/5.spi_device_intr_test.3954933385
/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2170477738
/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2738179235
/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2884563437
/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1546453849
/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.994907294
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.3851100592
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.733352030
/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3725867017
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1965761536
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.172953976
/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.805843074
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.713576888
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3271625146
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2197815317
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2440943939
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3907472400
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3873876819
/workspace/coverage/cover_reg_top/8.spi_device_intr_test.4152827626
/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3263734309
/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1559388654
/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4268271964
/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1878636237
/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3265688767
/workspace/coverage/cover_reg_top/9.spi_device_intr_test.392055400
/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3978891201
/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3819287607
/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3780292478

Total test records in report: 175

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3487995159	Jan 14 12:25:32 PM PST 24	Jan 14 12:25:40 PM PST 24	487864270 ps
T2	/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2528649821	Jan 14 12:25:10 PM PST 24	Jan 14 12:25:18 PM PST 24	772433763 ps
T3	/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1103814006	Jan 14 12:25:15 PM PST 24	Jan 14 12:25:18 PM PST 24	21208733 ps
T7	/workspace/coverage/cover_reg_top/14.spi_device_intr_test.3279925979	Jan 14 12:25:19 PM PST 24	Jan 14 12:25:21 PM PST 24	101241735 ps
T13	/workspace/coverage/cover_reg_top/5.spi_device_intr_test.3954933385	Jan 14 12:25:05 PM PST 24	Jan 14 12:25:09 PM PST 24	50796979 ps
T11	/workspace/coverage/cover_reg_top/21.spi_device_intr_test.1925392342	Jan 14 12:25:13 PM PST 24	Jan 14 12:25:15 PM PST 24	34972234 ps
T8	/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3732408064	Jan 14 12:25:08 PM PST 24	Jan 14 12:25:46 PM PST 24	2614350003 ps
T12	/workspace/coverage/cover_reg_top/23.spi_device_intr_test.729100931	Jan 14 12:25:17 PM PST 24	Jan 14 12:25:19 PM PST 24	16620144 ps
T9	/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2197815317	Jan 14 12:25:23 PM PST 24	Jan 14 12:25:31 PM PST 24	139885040 ps
T10	/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3873876819	Jan 14 12:25:01 PM PST 24	Jan 14 12:25:07 PM PST 24	90958820 ps
T4	/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3907472400	Jan 14 12:25:40 PM PST 24	Jan 14 12:25:47 PM PST 24	205189529 ps
T14	/workspace/coverage/cover_reg_top/0.spi_device_intr_test.2361278874	Jan 14 12:25:08 PM PST 24	Jan 14 12:25:11 PM PST 24	51040598 ps
T15	/workspace/coverage/cover_reg_top/33.spi_device_intr_test.2078597174	Jan 14 12:25:45 PM PST 24	Jan 14 12:25:49 PM PST 24	42175108 ps
T5	/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3780292478	Jan 14 12:25:48 PM PST 24	Jan 14 12:26:01 PM PST 24	211601268 ps
T16	/workspace/coverage/cover_reg_top/32.spi_device_intr_test.1911766288	Jan 14 12:25:15 PM PST 24	Jan 14 12:25:17 PM PST 24	49368147 ps
T6	/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2808439932	Jan 14 12:25:05 PM PST 24	Jan 14 12:25:24 PM PST 24	5368065470 ps
T31	/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3535012898	Jan 14 12:24:44 PM PST 24	Jan 14 12:24:46 PM PST 24	412410986 ps
T50	/workspace/coverage/cover_reg_top/27.spi_device_intr_test.1945206392	Jan 14 12:25:49 PM PST 24	Jan 14 12:25:51 PM PST 24	81847616 ps
T51	/workspace/coverage/cover_reg_top/11.spi_device_intr_test.1229393015	Jan 14 12:25:14 PM PST 24	Jan 14 12:25:16 PM PST 24	13704545 ps
T23	/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4209140259	Jan 14 12:25:15 PM PST 24	Jan 14 12:25:38 PM PST 24	1030697473 ps
T24	/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2633172550	Jan 14 12:25:17 PM PST 24	Jan 14 12:25:41 PM PST 24	1077477099 ps
T62	/workspace/coverage/cover_reg_top/9.spi_device_intr_test.392055400	Jan 14 12:25:16 PM PST 24	Jan 14 12:25:18 PM PST 24	39843121 ps
T17	/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2195690663	Jan 14 12:25:10 PM PST 24	Jan 14 12:25:14 PM PST 24	149957521 ps
T32	/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1015563149	Jan 14 12:25:22 PM PST 24	Jan 14 12:25:58 PM PST 24	664390461 ps
T52	/workspace/coverage/cover_reg_top/2.spi_device_intr_test.3088049777	Jan 14 12:25:05 PM PST 24	Jan 14 12:25:09 PM PST 24	84395067 ps
T42	/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3713924459	Jan 14 12:25:03 PM PST 24	Jan 14 12:25:12 PM PST 24	184020801 ps
T25	/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3698597894	Jan 14 12:25:16 PM PST 24	Jan 14 12:25:32 PM PST 24	691731244 ps
T53	/workspace/coverage/cover_reg_top/30.spi_device_intr_test.1372882690	Jan 14 12:25:21 PM PST 24	Jan 14 12:25:24 PM PST 24	35271656 ps
T48	/workspace/coverage/cover_reg_top/16.spi_device_intr_test.1201192540	Jan 14 12:25:19 PM PST 24	Jan 14 12:25:21 PM PST 24	46549687 ps
T18	/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2114970422	Jan 14 12:25:25 PM PST 24	Jan 14 12:25:34 PM PST 24	133541852 ps
T63	/workspace/coverage/cover_reg_top/37.spi_device_intr_test.766282699	Jan 14 12:25:19 PM PST 24	Jan 14 12:25:21 PM PST 24	20704021 ps
T26	/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1965761536	Jan 14 12:25:09 PM PST 24	Jan 14 12:25:32 PM PST 24	1023693161 ps
T33	/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1140466257	Jan 14 12:25:16 PM PST 24	Jan 14 12:25:19 PM PST 24	175211708 ps
T19	/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1995220649	Jan 14 12:25:38 PM PST 24	Jan 14 12:25:46 PM PST 24	44967137 ps
T20	/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2387129290	Jan 14 12:24:53 PM PST 24	Jan 14 12:25:05 PM PST 24	274213411 ps
T21	/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3880006081	Jan 14 12:25:04 PM PST 24	Jan 14 12:25:11 PM PST 24	43625828 ps
T22	/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1546453849	Jan 14 12:25:06 PM PST 24	Jan 14 12:25:11 PM PST 24	110245677 ps
T34	/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2170477738	Jan 14 12:25:28 PM PST 24	Jan 14 12:25:32 PM PST 24	73824484 ps
T64	/workspace/coverage/cover_reg_top/48.spi_device_intr_test.472393599	Jan 14 12:25:32 PM PST 24	Jan 14 12:25:37 PM PST 24	41615771 ps
T27	/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2234110967	Jan 14 12:25:44 PM PST 24	Jan 14 12:25:51 PM PST 24	2429384527 ps
T43	/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.845881246	Jan 14 12:25:09 PM PST 24	Jan 14 12:25:14 PM PST 24	117310465 ps
T35	/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3271625146	Jan 14 12:25:07 PM PST 24	Jan 14 12:25:13 PM PST 24	203776430 ps
T28	/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3279251455	Jan 14 12:25:39 PM PST 24	Jan 14 12:25:46 PM PST 24	130110800 ps
T58	/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4268271964	Jan 14 12:25:08 PM PST 24	Jan 14 12:25:22 PM PST 24	211166323 ps
T65	/workspace/coverage/cover_reg_top/36.spi_device_intr_test.10305780	Jan 14 12:25:54 PM PST 24	Jan 14 12:25:55 PM PST 24	35336040 ps
T29	/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3725867017	Jan 14 12:25:10 PM PST 24	Jan 14 12:25:14 PM PST 24	287028169 ps
T44	/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1452942199	Jan 14 12:25:22 PM PST 24	Jan 14 12:25:26 PM PST 24	84743677 ps
T45	/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1600210947	Jan 14 12:25:31 PM PST 24	Jan 14 12:25:40 PM PST 24	128553885 ps
T30	/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2722331939	Jan 14 12:25:18 PM PST 24	Jan 14 12:25:22 PM PST 24	256420500 ps
T47	/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1736995475	Jan 14 12:25:08 PM PST 24	Jan 14 12:25:16 PM PST 24	977422882 ps
T66	/workspace/coverage/cover_reg_top/18.spi_device_intr_test.4023033319	Jan 14 12:25:05 PM PST 24	Jan 14 12:25:09 PM PST 24	43301553 ps
T36	/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.212979090	Jan 14 12:24:51 PM PST 24	Jan 14 12:24:52 PM PST 24	64422508 ps
T67	/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1191085877	Jan 14 12:25:38 PM PST 24	Jan 14 12:25:44 PM PST 24	31715950 ps
T46	/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3265688767	Jan 14 12:25:17 PM PST 24	Jan 14 12:25:20 PM PST 24	78405553 ps
T68	/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3939060951	Jan 14 12:25:09 PM PST 24	Jan 14 12:25:13 PM PST 24	249180450 ps
T37	/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3156630146	Jan 14 12:25:22 PM PST 24	Jan 14 12:25:30 PM PST 24	402078104 ps
T49	/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2913118005	Jan 14 12:25:03 PM PST 24	Jan 14 12:25:09 PM PST 24	292294490 ps
T69	/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3494758287	Jan 14 12:25:07 PM PST 24	Jan 14 12:25:21 PM PST 24	799240153 ps
T70	/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3263734309	Jan 14 12:25:32 PM PST 24	Jan 14 12:25:41 PM PST 24	867091358 ps
T57	/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3436529751	Jan 14 12:25:29 PM PST 24	Jan 14 12:25:56 PM PST 24	849798128 ps
T71	/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.463430678	Jan 14 12:24:53 PM PST 24	Jan 14 12:24:58 PM PST 24	122011037 ps
T72	/workspace/coverage/cover_reg_top/41.spi_device_intr_test.3810122583	Jan 14 12:25:30 PM PST 24	Jan 14 12:25:36 PM PST 24	277130437 ps
T73	/workspace/coverage/cover_reg_top/42.spi_device_intr_test.3993311357	Jan 14 12:25:17 PM PST 24	Jan 14 12:25:19 PM PST 24	140305472 ps
T74	/workspace/coverage/cover_reg_top/1.spi_device_intr_test.1084364429	Jan 14 12:25:13 PM PST 24	Jan 14 12:25:15 PM PST 24	10849635 ps
T38	/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3845402103	Jan 14 12:25:09 PM PST 24	Jan 14 12:25:40 PM PST 24	2940903528 ps
T75	/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1687233832	Jan 14 12:25:17 PM PST 24	Jan 14 12:25:21 PM PST 24	151269690 ps
T76	/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4124606441	Jan 14 12:25:17 PM PST 24	Jan 14 12:25:32 PM PST 24	642683430 ps
T77	/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2120099037	Jan 14 12:25:20 PM PST 24	Jan 14 12:25:24 PM PST 24	516940985 ps
T54	/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4211261793	Jan 14 12:25:14 PM PST 24	Jan 14 12:25:27 PM PST 24	206892341 ps
T39	/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3438396011	Jan 14 12:25:28 PM PST 24	Jan 14 12:25:33 PM PST 24	85324720 ps
T78	/workspace/coverage/cover_reg_top/38.spi_device_intr_test.1165469272	Jan 14 12:25:15 PM PST 24	Jan 14 12:25:16 PM PST 24	19474378 ps
T79	/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1110939193	Jan 14 12:25:25 PM PST 24	Jan 14 12:25:32 PM PST 24	99933438 ps
T80	/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.942860062	Jan 14 12:25:15 PM PST 24	Jan 14 12:25:18 PM PST 24	69766395 ps
T81	/workspace/coverage/cover_reg_top/4.spi_device_intr_test.1154993820	Jan 14 12:25:05 PM PST 24	Jan 14 12:25:09 PM PST 24	12970287 ps
T61	/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.837301295	Jan 14 12:25:02 PM PST 24	Jan 14 12:25:21 PM PST 24	3639204420 ps
T82	/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.172953976	Jan 14 12:25:02 PM PST 24	Jan 14 12:25:09 PM PST 24	28670935 ps
T83	/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1808446351	Jan 14 12:25:32 PM PST 24	Jan 14 12:25:38 PM PST 24	125463738 ps
T84	/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1308739782	Jan 14 12:25:24 PM PST 24	Jan 14 12:25:34 PM PST 24	255965501 ps
T55	/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.322183070	Jan 14 12:24:48 PM PST 24	Jan 14 12:25:07 PM PST 24	393296978 ps
T85	/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3978891201	Jan 14 12:25:13 PM PST 24	Jan 14 12:25:18 PM PST 24	165718218 ps
T86	/workspace/coverage/cover_reg_top/25.spi_device_intr_test.387033735	Jan 14 12:25:29 PM PST 24	Jan 14 12:25:36 PM PST 24	61038251 ps
T87	/workspace/coverage/cover_reg_top/24.spi_device_intr_test.447194177	Jan 14 12:25:07 PM PST 24	Jan 14 12:25:10 PM PST 24	46778596 ps
T88	/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3046874753	Jan 14 12:24:55 PM PST 24	Jan 14 12:24:58 PM PST 24	78040504 ps
T89	/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4078911261	Jan 14 12:25:18 PM PST 24	Jan 14 12:25:35 PM PST 24	3133722891 ps
T90	/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1768199145	Jan 14 12:25:14 PM PST 24	Jan 14 12:25:18 PM PST 24	680693296 ps
T91	/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.247867025	Jan 14 12:24:57 PM PST 24	Jan 14 12:25:04 PM PST 24	38290883 ps
T92	/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.544413335	Jan 14 12:25:01 PM PST 24	Jan 14 12:25:06 PM PST 24	69358416 ps
T93	/workspace/coverage/cover_reg_top/22.spi_device_intr_test.1672409610	Jan 14 12:25:04 PM PST 24	Jan 14 12:25:09 PM PST 24	15002103 ps
T94	/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.888374537	Jan 14 12:25:33 PM PST 24	Jan 14 12:25:39 PM PST 24	88845137 ps
T95	/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4068997432	Jan 14 12:25:15 PM PST 24	Jan 14 12:25:18 PM PST 24	38086468 ps
T96	/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1437798326	Jan 14 12:25:23 PM PST 24	Jan 14 12:25:29 PM PST 24	78519642 ps
T97	/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.430206055	Jan 14 12:25:11 PM PST 24	Jan 14 12:25:13 PM PST 24	76152888 ps
T98	/workspace/coverage/cover_reg_top/3.spi_device_intr_test.844640522	Jan 14 12:25:22 PM PST 24	Jan 14 12:25:24 PM PST 24	16880815 ps
T99	/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1430656316	Jan 14 12:25:22 PM PST 24	Jan 14 12:25:28 PM PST 24	245888652 ps
T40	/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3387588298	Jan 14 12:25:12 PM PST 24	Jan 14 12:25:15 PM PST 24	186260264 ps
T100	/workspace/coverage/cover_reg_top/34.spi_device_intr_test.1432729345	Jan 14 12:25:24 PM PST 24	Jan 14 12:25:30 PM PST 24	42249928 ps
T101	/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2884563437	Jan 14 12:24:56 PM PST 24	Jan 14 12:25:04 PM PST 24	428558449 ps
T102	/workspace/coverage/cover_reg_top/20.spi_device_intr_test.590990462	Jan 14 12:25:45 PM PST 24	Jan 14 12:25:49 PM PST 24	13519791 ps
T103	/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4242789317	Jan 14 12:25:18 PM PST 24	Jan 14 12:25:22 PM PST 24	61928653 ps
T104	/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1541384469	Jan 14 12:25:15 PM PST 24	Jan 14 12:25:18 PM PST 24	93590453 ps
T41	/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2163120841	Jan 14 12:25:13 PM PST 24	Jan 14 12:25:16 PM PST 24	80384264 ps
T105	/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2100745803	Jan 14 12:25:25 PM PST 24	Jan 14 12:25:32 PM PST 24	64701331 ps
T106	/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3954275158	Jan 14 12:25:25 PM PST 24	Jan 14 12:25:34 PM PST 24	647369352 ps
T107	/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.850431173	Jan 14 12:25:16 PM PST 24	Jan 14 12:25:21 PM PST 24	116094713 ps
T108	/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.47723095	Jan 14 12:25:29 PM PST 24	Jan 14 12:25:36 PM PST 24	131327002 ps
T109	/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1670304529	Jan 14 12:25:27 PM PST 24	Jan 14 12:25:32 PM PST 24	46215281 ps
T110	/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3523723588	Jan 14 12:25:18 PM PST 24	Jan 14 12:25:22 PM PST 24	585421597 ps
T111	/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1878636237	Jan 14 12:25:08 PM PST 24	Jan 14 12:25:11 PM PST 24	67423785 ps
T112	/workspace/coverage/cover_reg_top/28.spi_device_intr_test.1935648834	Jan 14 12:25:14 PM PST 24	Jan 14 12:25:16 PM PST 24	31418412 ps
T113	/workspace/coverage/cover_reg_top/45.spi_device_intr_test.3299859765	Jan 14 12:25:15 PM PST 24	Jan 14 12:25:17 PM PST 24	21181634 ps
T114	/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2605829583	Jan 14 12:25:07 PM PST 24	Jan 14 12:25:16 PM PST 24	221434125 ps
T115	/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3382173317	Jan 14 12:25:12 PM PST 24	Jan 14 12:25:17 PM PST 24	2970959175 ps
T59	/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2340181932	Jan 14 12:25:08 PM PST 24	Jan 14 12:25:25 PM PST 24	567610511 ps
T116	/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.644028545	Jan 14 12:25:08 PM PST 24	Jan 14 12:25:12 PM PST 24	20243530 ps
T117	/workspace/coverage/cover_reg_top/8.spi_device_intr_test.4152827626	Jan 14 12:25:08 PM PST 24	Jan 14 12:25:11 PM PST 24	25083342 ps
T118	/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2196503268	Jan 14 12:25:33 PM PST 24	Jan 14 12:25:40 PM PST 24	201739538 ps
T119	/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.277209178	Jan 14 12:24:59 PM PST 24	Jan 14 12:25:23 PM PST 24	3948404113 ps
T120	/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.803426394	Jan 14 12:25:23 PM PST 24	Jan 14 12:25:32 PM PST 24	630680988 ps
T121	/workspace/coverage/cover_reg_top/13.spi_device_intr_test.2175212965	Jan 14 12:25:10 PM PST 24	Jan 14 12:25:11 PM PST 24	10897611 ps
T122	/workspace/coverage/cover_reg_top/29.spi_device_intr_test.1779026605	Jan 14 12:25:58 PM PST 24	Jan 14 12:25:59 PM PST 24	15052766 ps
T123	/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1293396339	Jan 14 12:25:24 PM PST 24	Jan 14 12:25:33 PM PST 24	1729512184 ps
T124	/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3683891344	Jan 14 12:25:03 PM PST 24	Jan 14 12:25:12 PM PST 24	105971660 ps
T125	/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.994907294	Jan 14 12:25:27 PM PST 24	Jan 14 12:25:32 PM PST 24	22499735 ps
T56	/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2109594267	Jan 14 12:25:30 PM PST 24	Jan 14 12:25:57 PM PST 24	900311351 ps
T126	/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3960009545	Jan 14 12:25:24 PM PST 24	Jan 14 12:25:32 PM PST 24	38910411 ps
T127	/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3065130563	Jan 14 12:24:54 PM PST 24	Jan 14 12:25:21 PM PST 24	1413371941 ps
T128	/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1051164721	Jan 14 12:25:20 PM PST 24	Jan 14 12:25:30 PM PST 24	524993198 ps
T129	/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.120719487	Jan 14 12:25:24 PM PST 24	Jan 14 12:25:31 PM PST 24	294974663 ps
T130	/workspace/coverage/cover_reg_top/7.spi_device_intr_test.713576888	Jan 14 12:25:14 PM PST 24	Jan 14 12:25:16 PM PST 24	33824904 ps
T131	/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1440214939	Jan 14 12:25:18 PM PST 24	Jan 14 12:25:24 PM PST 24	180414879 ps
T132	/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2079300786	Jan 14 12:25:21 PM PST 24	Jan 14 12:25:36 PM PST 24	2642678807 ps
T133	/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1338430014	Jan 14 12:25:29 PM PST 24	Jan 14 12:25:46 PM PST 24	553572143 ps
T134	/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3364904536	Jan 14 12:25:29 PM PST 24	Jan 14 12:25:36 PM PST 24	126070088 ps
T135	/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3548955819	Jan 14 12:25:08 PM PST 24	Jan 14 12:25:12 PM PST 24	301309558 ps
T136	/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2714025312	Jan 14 12:25:08 PM PST 24	Jan 14 12:25:11 PM PST 24	69653863 ps
T137	/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.863849200	Jan 14 12:25:06 PM PST 24	Jan 14 12:25:10 PM PST 24	36139321 ps
T138	/workspace/coverage/cover_reg_top/31.spi_device_intr_test.4238365509	Jan 14 12:25:16 PM PST 24	Jan 14 12:25:18 PM PST 24	14129257 ps
T139	/workspace/coverage/cover_reg_top/10.spi_device_intr_test.3590269511	Jan 14 12:25:17 PM PST 24	Jan 14 12:25:19 PM PST 24	12151806 ps
T140	/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2738179235	Jan 14 12:25:05 PM PST 24	Jan 14 12:25:13 PM PST 24	96484881 ps
T141	/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3819287607	Jan 14 12:25:22 PM PST 24	Jan 14 12:25:31 PM PST 24	232128370 ps
T142	/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.517274665	Jan 14 12:25:20 PM PST 24	Jan 14 12:25:23 PM PST 24	24147751 ps
T143	/workspace/coverage/cover_reg_top/44.spi_device_intr_test.1313293099	Jan 14 12:25:21 PM PST 24	Jan 14 12:25:24 PM PST 24	34310335 ps
T144	/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.477041327	Jan 14 12:25:19 PM PST 24	Jan 14 12:25:23 PM PST 24	198593835 ps
T145	/workspace/coverage/cover_reg_top/6.spi_device_intr_test.3851100592	Jan 14 12:25:10 PM PST 24	Jan 14 12:25:12 PM PST 24	24562722 ps
T146	/workspace/coverage/cover_reg_top/19.spi_device_intr_test.3875694115	Jan 14 12:25:15 PM PST 24	Jan 14 12:25:17 PM PST 24	12840403 ps
T147	/workspace/coverage/cover_reg_top/43.spi_device_intr_test.1787639090	Jan 14 12:25:32 PM PST 24	Jan 14 12:25:38 PM PST 24	49014111 ps
T148	/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3348599128	Jan 14 12:25:02 PM PST 24	Jan 14 12:25:19 PM PST 24	582499400 ps
T149	/workspace/coverage/cover_reg_top/26.spi_device_intr_test.986359943	Jan 14 12:25:30 PM PST 24	Jan 14 12:25:36 PM PST 24	12181236 ps
T150	/workspace/coverage/cover_reg_top/39.spi_device_intr_test.970904387	Jan 14 12:25:35 PM PST 24	Jan 14 12:25:39 PM PST 24	13976082 ps
T151	/workspace/coverage/cover_reg_top/12.spi_device_intr_test.3993251438	Jan 14 12:25:14 PM PST 24	Jan 14 12:25:15 PM PST 24	13164021 ps
T152	/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3964623146	Jan 14 12:25:14 PM PST 24	Jan 14 12:25:18 PM PST 24	72352543 ps
T153	/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3546857748	Jan 14 12:25:11 PM PST 24	Jan 14 12:25:36 PM PST 24	1428638863 ps
T154	/workspace/coverage/cover_reg_top/17.spi_device_intr_test.2574919256	Jan 14 12:25:25 PM PST 24	Jan 14 12:25:31 PM PST 24	52967734 ps
T155	/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.753289707	Jan 14 12:24:55 PM PST 24	Jan 14 12:24:58 PM PST 24	25653876 ps
T156	/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1559388654	Jan 14 12:25:20 PM PST 24	Jan 14 12:25:27 PM PST 24	214583320 ps
T60	/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3398023356	Jan 14 12:25:19 PM PST 24	Jan 14 12:25:33 PM PST 24	2358118937 ps
T157	/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2440943939	Jan 14 12:25:04 PM PST 24	Jan 14 12:25:31 PM PST 24	22664309691 ps
T158	/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.248898506	Jan 14 12:25:05 PM PST 24	Jan 14 12:25:15 PM PST 24	814081889 ps
T159	/workspace/coverage/cover_reg_top/40.spi_device_intr_test.3291027541	Jan 14 12:25:25 PM PST 24	Jan 14 12:25:31 PM PST 24	63488840 ps
T160	/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4212895105	Jan 14 12:25:09 PM PST 24	Jan 14 12:25:39 PM PST 24	5953286639 ps
T161	/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.811243416	Jan 14 12:25:04 PM PST 24	Jan 14 12:25:25 PM PST 24	258444475 ps
T162	/workspace/coverage/cover_reg_top/46.spi_device_intr_test.2373552263	Jan 14 12:25:22 PM PST 24	Jan 14 12:25:25 PM PST 24	35144436 ps
T163	/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2696786271	Jan 14 12:25:08 PM PST 24	Jan 14 12:25:14 PM PST 24	185450339 ps
T164	/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.733352030	Jan 14 12:25:25 PM PST 24	Jan 14 12:25:32 PM PST 24	64511421 ps
T165	/workspace/coverage/cover_reg_top/15.spi_device_intr_test.3194180691	Jan 14 12:25:09 PM PST 24	Jan 14 12:25:11 PM PST 24	22856158 ps
T166	/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.73622464	Jan 14 12:25:19 PM PST 24	Jan 14 12:25:22 PM PST 24	34181876 ps
T167	/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1912480178	Jan 14 12:25:14 PM PST 24	Jan 14 12:25:17 PM PST 24	43725696 ps
T168	/workspace/coverage/cover_reg_top/35.spi_device_intr_test.942108432	Jan 14 12:26:01 PM PST 24	Jan 14 12:26:03 PM PST 24	42844064 ps
T169	/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.805843074	Jan 14 12:25:16 PM PST 24	Jan 14 12:25:20 PM PST 24	70185490 ps
T170	/workspace/coverage/cover_reg_top/49.spi_device_intr_test.559800011	Jan 14 12:25:21 PM PST 24	Jan 14 12:25:24 PM PST 24	16208757 ps
T171	/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1262559173	Jan 14 12:25:33 PM PST 24	Jan 14 12:26:04 PM PST 24	1335496127 ps
T172	/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2328111249	Jan 14 12:25:14 PM PST 24	Jan 14 12:25:19 PM PST 24	349268016 ps
T173	/workspace/coverage/cover_reg_top/47.spi_device_intr_test.2739337756	Jan 14 12:25:18 PM PST 24	Jan 14 12:25:21 PM PST 24	11004965 ps
T174	/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.707003983	Jan 14 12:25:20 PM PST 24	Jan 14 12:25:24 PM PST 24	24211945 ps
T175	/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3912302233	Jan 14 12:25:13 PM PST 24	Jan 14 12:25:16 PM PST 24	27291609 ps

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3732408064
Short name	T8
Test name
Test status
Simulation time	2614350003 ps
CPU time	36.48 seconds
Started	Jan 14 12:25:08 PM PST 24
Finished	Jan 14 12:25:46 PM PST 24
Peak memory	207664 kb
Host	smart-66676edd-9cf5-45da-8515-89427b904d53
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732408064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_bit_bash.3732408064
Directory	/workspace/3.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/27.spi_device_intr_test.1945206392
Short name	T50
Test name
Test status
Simulation time	81847616 ps
CPU time	0.75 seconds
Started	Jan 14 12:25:49 PM PST 24
Finished	Jan 14 12:25:51 PM PST 24
Peak memory	204848 kb
Host	smart-59dbe0a4-73cf-4ab1-b8b3-e700b90c15d3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945206392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test. 1945206392
Directory	/workspace/27.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4209140259
Short name	T23
Test name
Test status
Simulation time	1030697473 ps
CPU time	21.43 seconds
Started	Jan 14 12:25:15 PM PST 24
Finished	Jan 14 12:25:38 PM PST 24
Peak memory	215908 kb
Host	smart-01f23b42-8b8e-48f6-9171-9ce0a77ca30c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209140259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device _tl_intg_err.4209140259
Directory	/workspace/0.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2114970422
Short name	T18
Test name
Test status
Simulation time	133541852 ps
CPU time	3.59 seconds
Started	Jan 14 12:25:25 PM PST 24
Finished	Jan 14 12:25:34 PM PST 24
Peak memory	215856 kb
Host	smart-f6264e4c-feae-4b36-95a7-da61a1629860
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114970422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors. 2114970422
Directory	/workspace/15.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_intr_test.3088049777
Short name	T52
Test name
Test status
Simulation time	84395067 ps
CPU time	0.73 seconds
Started	Jan 14 12:25:05 PM PST 24
Finished	Jan 14 12:25:09 PM PST 24
Peak memory	204856 kb
Host	smart-5cd5b524-34df-4a4c-a770-0295753f11f1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088049777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3 088049777
Directory	/workspace/2.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3487995159
Short name	T1
Test name
Test status
Simulation time	487864270 ps
CPU time	3.16 seconds
Started	Jan 14 12:25:32 PM PST 24
Finished	Jan 14 12:25:40 PM PST 24
Peak memory	215908 kb
Host	smart-71a91ce7-2b1d-41a2-b8a4-04b5256e239d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487995159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw. 3487995159
Directory	/workspace/15.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1736995475
Short name	T47
Test name
Test status
Simulation time	977422882 ps
CPU time	5.44 seconds
Started	Jan 14 12:25:08 PM PST 24
Finished	Jan 14 12:25:16 PM PST 24
Peak memory	215888 kb
Host	smart-1c604855-289f-4c10-8bfa-6f65e82fb529
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736995475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1 736995475
Directory	/workspace/3.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/32.spi_device_intr_test.1911766288
Short name	T16
Test name
Test status
Simulation time	49368147 ps
CPU time	0.74 seconds
Started	Jan 14 12:25:15 PM PST 24
Finished	Jan 14 12:25:17 PM PST 24
Peak memory	204872 kb
Host	smart-95d927f4-8443-4bce-8d64-f6764d04e71d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911766288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test. 1911766288
Directory	/workspace/32.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2340181932
Short name	T59
Test name
Test status
Simulation time	567610511 ps
CPU time	14.46 seconds
Started	Jan 14 12:25:08 PM PST 24
Finished	Jan 14 12:25:25 PM PST 24
Peak memory	215884 kb
Host	smart-9794abec-36d3-49a4-a804-8af5f2ee0e04
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340181932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic e_tl_intg_err.2340181932
Directory	/workspace/10.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.322183070
Short name	T55
Test name
Test status
Simulation time	393296978 ps
CPU time	12.57 seconds
Started	Jan 14 12:24:48 PM PST 24
Finished	Jan 14 12:25:07 PM PST 24
Peak memory	215864 kb
Host	smart-a53680ed-c73b-440d-a4ba-b4c058393092
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322183070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_ tl_intg_err.322183070
Directory	/workspace/2.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3880006081
Short name	T21
Test name
Test status
Simulation time	43625828 ps
CPU time	3.27 seconds
Started	Jan 14 12:25:04 PM PST 24
Finished	Jan 14 12:25:11 PM PST 24
Peak memory	218636 kb
Host	smart-355e7bbd-f7e8-4533-8441-2e7b487acf70
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880006081 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3880006081
Directory	/workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3436529751
Short name	T57
Test name
Test status
Simulation time	849798128 ps
CPU time	20.96 seconds
Started	Jan 14 12:25:29 PM PST 24
Finished	Jan 14 12:25:56 PM PST 24
Peak memory	215852 kb
Host	smart-4aba2614-57e3-4ba5-a9fd-323c2f60207e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436529751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device _tl_intg_err.3436529751
Directory	/workspace/1.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.837301295
Short name	T61
Test name
Test status
Simulation time	3639204420 ps
CPU time	15.47 seconds
Started	Jan 14 12:25:02 PM PST 24
Finished	Jan 14 12:25:21 PM PST 24
Peak memory	215960 kb
Host	smart-d4deb57e-6efb-4794-aaa3-ce386f13b2bb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837301295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device _tl_intg_err.837301295
Directory	/workspace/12.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.212979090
Short name	T36
Test name
Test status
Simulation time	64422508 ps
CPU time	0.94 seconds
Started	Jan 14 12:24:51 PM PST 24
Finished	Jan 14 12:24:52 PM PST 24
Peak memory	207480 kb
Host	smart-8bda275e-ffdf-4115-9d37-757b3a7825ed
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212979090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr _hw_reset.212979090
Directory	/workspace/0.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3546857748
Short name	T153
Test name
Test status
Simulation time	1428638863 ps
CPU time	24.07 seconds
Started	Jan 14 12:25:11 PM PST 24
Finished	Jan 14 12:25:36 PM PST 24
Peak memory	217196 kb
Host	smart-9ce57ddc-abe6-44a4-b96e-f49c8c4e402f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546857748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_aliasing.3546857748
Directory	/workspace/0.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1262559173
Short name	T171
Test name
Test status
Simulation time	1335496127 ps
CPU time	26.36 seconds
Started	Jan 14 12:25:33 PM PST 24
Finished	Jan 14 12:26:04 PM PST 24
Peak memory	207604 kb
Host	smart-8fef3eb8-3b6e-4fc7-a2b4-0695f2d3532a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262559173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_bit_bash.1262559173
Directory	/workspace/0.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3960009545
Short name	T126
Test name
Test status
Simulation time	38910411 ps
CPU time	2.45 seconds
Started	Jan 14 12:25:24 PM PST 24
Finished	Jan 14 12:25:32 PM PST 24
Peak memory	218300 kb
Host	smart-d97598e0-81ad-4eb7-bcc5-87ac8577646a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960009545 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3960009545
Directory	/workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3535012898
Short name	T31
Test name
Test status
Simulation time	412410986 ps
CPU time	2.12 seconds
Started	Jan 14 12:24:44 PM PST 24
Finished	Jan 14 12:24:46 PM PST 24
Peak memory	215844 kb
Host	smart-66a35a7e-f9ec-4b71-b7d8-262cfae010c1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535012898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3 535012898
Directory	/workspace/0.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_intr_test.2361278874
Short name	T14
Test name
Test status
Simulation time	51040598 ps
CPU time	0.74 seconds
Started	Jan 14 12:25:08 PM PST 24
Finished	Jan 14 12:25:11 PM PST 24
Peak memory	204820 kb
Host	smart-b64adf53-e923-4923-80a0-1cb416d40122
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361278874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2 361278874
Directory	/workspace/0.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3683891344
Short name	T124
Test name
Test status
Simulation time	105971660 ps
CPU time	4.31 seconds
Started	Jan 14 12:25:03 PM PST 24
Finished	Jan 14 12:25:12 PM PST 24
Peak memory	215776 kb
Host	smart-3aaaed34-418f-4ada-87a2-737952f530d3
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683891344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi _device_mem_partial_access.3683891344
Directory	/workspace/0.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1051164721
Short name	T128
Test name
Test status
Simulation time	524993198 ps
CPU time	8.18 seconds
Started	Jan 14 12:25:20 PM PST 24
Finished	Jan 14 12:25:30 PM PST 24
Peak memory	215800 kb
Host	smart-1e63c629-41bb-4139-8150-86f2204d74d5
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051164721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me m_walk.1051164721
Directory	/workspace/0.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3382173317
Short name	T115
Test name
Test status
Simulation time	2970959175 ps
CPU time	4.28 seconds
Started	Jan 14 12:25:12 PM PST 24
Finished	Jan 14 12:25:17 PM PST 24
Peak memory	217516 kb
Host	smart-308b83bc-1d2d-4fee-a4bb-5567ff36ac40
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382173317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s pi_device_same_csr_outstanding.3382173317
Directory	/workspace/0.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2722331939
Short name	T30
Test name
Test status
Simulation time	256420500 ps
CPU time	2.07 seconds
Started	Jan 14 12:25:18 PM PST 24
Finished	Jan 14 12:25:22 PM PST 24
Peak memory	215892 kb
Host	smart-9653cedd-d3e8-4d0d-8003-f106fbc18738
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722331939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2 722331939
Directory	/workspace/0.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.277209178
Short name	T119
Test name
Test status
Simulation time	3948404113 ps
CPU time	18.5 seconds
Started	Jan 14 12:24:59 PM PST 24
Finished	Jan 14 12:25:23 PM PST 24
Peak memory	207656 kb
Host	smart-e59fae23-0782-4b9c-9abc-703a3004db46
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277209178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr _aliasing.277209178
Directory	/workspace/1.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3065130563
Short name	T127
Test name
Test status
Simulation time	1413371941 ps
CPU time	26.21 seconds
Started	Jan 14 12:24:54 PM PST 24
Finished	Jan 14 12:25:21 PM PST 24
Peak memory	207568 kb
Host	smart-35583ba8-0c69-4753-915b-3cf221612471
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065130563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_bit_bash.3065130563
Directory	/workspace/1.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3387588298
Short name	T40
Test name
Test status
Simulation time	186260264 ps
CPU time	1.41 seconds
Started	Jan 14 12:25:12 PM PST 24
Finished	Jan 14 12:25:15 PM PST 24
Peak memory	215780 kb
Host	smart-9d2f25e6-8b79-424b-b1a4-9dc392937f28
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387588298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_hw_reset.3387588298
Directory	/workspace/1.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.247867025
Short name	T91
Test name
Test status
Simulation time	38290883 ps
CPU time	2.46 seconds
Started	Jan 14 12:24:57 PM PST 24
Finished	Jan 14 12:25:04 PM PST 24
Peak memory	219144 kb
Host	smart-db8561c5-e20d-4535-8ce0-64fb43a9d79a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247867025 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.247867025
Directory	/workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.517274665
Short name	T142
Test name
Test status
Simulation time	24147751 ps
CPU time	1.33 seconds
Started	Jan 14 12:25:20 PM PST 24
Finished	Jan 14 12:25:23 PM PST 24
Peak memory	215728 kb
Host	smart-c62c72d7-861a-49a0-b341-518ed447d739
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517274665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.517274665
Directory	/workspace/1.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_intr_test.1084364429
Short name	T74
Test name
Test status
Simulation time	10849635 ps
CPU time	0.7 seconds
Started	Jan 14 12:25:13 PM PST 24
Finished	Jan 14 12:25:15 PM PST 24
Peak memory	204860 kb
Host	smart-90ad0872-3169-4b84-9188-b6f87082eedf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084364429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1 084364429
Directory	/workspace/1.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2528649821
Short name	T2
Test name
Test status
Simulation time	772433763 ps
CPU time	6.62 seconds
Started	Jan 14 12:25:10 PM PST 24
Finished	Jan 14 12:25:18 PM PST 24
Peak memory	215788 kb
Host	smart-583c5d72-7de0-43df-b12d-788f19c8a7a7
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528649821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi _device_mem_partial_access.2528649821
Directory	/workspace/1.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2387129290
Short name	T20
Test name
Test status
Simulation time	274213411 ps
CPU time	12.01 seconds
Started	Jan 14 12:24:53 PM PST 24
Finished	Jan 14 12:25:05 PM PST 24
Peak memory	215796 kb
Host	smart-2059d6ec-8a4c-41c2-a4db-f24438ff5ba7
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387129290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me m_walk.2387129290
Directory	/workspace/1.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2120099037
Short name	T77
Test name
Test status
Simulation time	516940985 ps
CPU time	1.85 seconds
Started	Jan 14 12:25:20 PM PST 24
Finished	Jan 14 12:25:24 PM PST 24
Peak memory	215736 kb
Host	smart-ad93f3f6-03ba-4262-a8d7-270aa9aed89b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120099037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s pi_device_same_csr_outstanding.2120099037
Directory	/workspace/1.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3279251455
Short name	T28
Test name
Test status
Simulation time	130110800 ps
CPU time	2.45 seconds
Started	Jan 14 12:25:39 PM PST 24
Finished	Jan 14 12:25:46 PM PST 24
Peak memory	215924 kb
Host	smart-74a5e9e0-fc15-46e6-b853-30f486ab34a4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279251455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3 279251455
Directory	/workspace/1.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1191085877
Short name	T67
Test name
Test status
Simulation time	31715950 ps
CPU time	1.24 seconds
Started	Jan 14 12:25:38 PM PST 24
Finished	Jan 14 12:25:44 PM PST 24
Peak memory	217032 kb
Host	smart-fe7f3f0b-eadd-4d84-84b6-a51c1863f3c8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191085877 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1191085877
Directory	/workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2714025312
Short name	T136
Test name
Test status
Simulation time	69653863 ps
CPU time	1.3 seconds
Started	Jan 14 12:25:08 PM PST 24
Finished	Jan 14 12:25:11 PM PST 24
Peak memory	215788 kb
Host	smart-2e92acce-ced4-46ea-8aeb-f86d31644a15
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714025312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw. 2714025312
Directory	/workspace/10.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_intr_test.3590269511
Short name	T139
Test name
Test status
Simulation time	12151806 ps
CPU time	0.71 seconds
Started	Jan 14 12:25:17 PM PST 24
Finished	Jan 14 12:25:19 PM PST 24
Peak memory	204888 kb
Host	smart-0e0f019d-c7bd-4281-ae11-c0a7265cf0ed
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590269511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test. 3590269511
Directory	/workspace/10.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1600210947
Short name	T45
Test name
Test status
Simulation time	128553885 ps
CPU time	4.06 seconds
Started	Jan 14 12:25:31 PM PST 24
Finished	Jan 14 12:25:40 PM PST 24
Peak memory	215708 kb
Host	smart-2c34106c-07cd-4d2d-96f8-e487c9030a90
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600210947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. spi_device_same_csr_outstanding.1600210947
Directory	/workspace/10.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.803426394
Short name	T120
Test name
Test status
Simulation time	630680988 ps
CPU time	4.5 seconds
Started	Jan 14 12:25:23 PM PST 24
Finished	Jan 14 12:25:32 PM PST 24
Peak memory	215984 kb
Host	smart-5fd6ea83-8efe-47b5-b54f-31db1b3ecf85
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803426394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.803426394
Directory	/workspace/10.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.430206055
Short name	T97
Test name
Test status
Simulation time	76152888 ps
CPU time	1.79 seconds
Started	Jan 14 12:25:11 PM PST 24
Finished	Jan 14 12:25:13 PM PST 24
Peak memory	217140 kb
Host	smart-3277af35-ad5c-44b4-ad57-43462da65bf4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430206055 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.430206055
Directory	/workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1110939193
Short name	T79
Test name
Test status
Simulation time	99933438 ps
CPU time	1.34 seconds
Started	Jan 14 12:25:25 PM PST 24
Finished	Jan 14 12:25:32 PM PST 24
Peak memory	215784 kb
Host	smart-74d291f8-cb31-468a-ab5f-f698f9d9c242
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110939193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw. 1110939193
Directory	/workspace/11.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_intr_test.1229393015
Short name	T51
Test name
Test status
Simulation time	13704545 ps
CPU time	0.74 seconds
Started	Jan 14 12:25:14 PM PST 24
Finished	Jan 14 12:25:16 PM PST 24
Peak memory	204872 kb
Host	smart-93e82df5-0482-4d97-86cd-c673482d361f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229393015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test. 1229393015
Directory	/workspace/11.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2913118005
Short name	T49
Test name
Test status
Simulation time	292294490 ps
CPU time	1.86 seconds
Started	Jan 14 12:25:03 PM PST 24
Finished	Jan 14 12:25:09 PM PST 24
Peak memory	215808 kb
Host	smart-9e55c850-b661-431f-84fb-133438d38b1b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913118005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. spi_device_same_csr_outstanding.2913118005
Directory	/workspace/11.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.942860062
Short name	T80
Test name
Test status
Simulation time	69766395 ps
CPU time	1.93 seconds
Started	Jan 14 12:25:15 PM PST 24
Finished	Jan 14 12:25:18 PM PST 24
Peak memory	215916 kb
Host	smart-1433cbe5-266d-4eae-a99d-0d721ea89bd7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942860062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.942860062
Directory	/workspace/11.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4211261793
Short name	T54
Test name
Test status
Simulation time	206892341 ps
CPU time	12.3 seconds
Started	Jan 14 12:25:14 PM PST 24
Finished	Jan 14 12:25:27 PM PST 24
Peak memory	215792 kb
Host	smart-b3724d4f-d9e1-4c95-80e2-a9422116a966
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211261793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic e_tl_intg_err.4211261793
Directory	/workspace/11.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1912480178
Short name	T167
Test name
Test status
Simulation time	43725696 ps
CPU time	2.22 seconds
Started	Jan 14 12:25:14 PM PST 24
Finished	Jan 14 12:25:17 PM PST 24
Peak memory	219080 kb
Host	smart-4a30acab-e09d-42b9-831c-81b4c15a4b79
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912480178 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1912480178
Directory	/workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2100745803
Short name	T105
Test name
Test status
Simulation time	64701331 ps
CPU time	1.19 seconds
Started	Jan 14 12:25:25 PM PST 24
Finished	Jan 14 12:25:32 PM PST 24
Peak memory	207516 kb
Host	smart-8f268002-3457-4497-b5da-7a01046d45ef
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100745803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw. 2100745803
Directory	/workspace/12.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_intr_test.3993251438
Short name	T151
Test name
Test status
Simulation time	13164021 ps
CPU time	0.72 seconds
Started	Jan 14 12:25:14 PM PST 24
Finished	Jan 14 12:25:15 PM PST 24
Peak memory	204888 kb
Host	smart-66c7e55e-2753-4763-9141-4c9da0a9c764
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993251438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test. 3993251438
Directory	/workspace/12.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1452942199
Short name	T44
Test name
Test status
Simulation time	84743677 ps
CPU time	2.84 seconds
Started	Jan 14 12:25:22 PM PST 24
Finished	Jan 14 12:25:26 PM PST 24
Peak memory	215796 kb
Host	smart-b31ef16e-db1f-4be9-9051-8626439d5aec
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452942199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. spi_device_same_csr_outstanding.1452942199
Directory	/workspace/12.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1687233832
Short name	T75
Test name
Test status
Simulation time	151269690 ps
CPU time	3.65 seconds
Started	Jan 14 12:25:17 PM PST 24
Finished	Jan 14 12:25:21 PM PST 24
Peak memory	215944 kb
Host	smart-0c651158-4371-4b7e-a6dd-e7317b86def6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687233832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors. 1687233832
Directory	/workspace/12.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4068997432
Short name	T95
Test name
Test status
Simulation time	38086468 ps
CPU time	1.31 seconds
Started	Jan 14 12:25:15 PM PST 24
Finished	Jan 14 12:25:18 PM PST 24
Peak memory	217164 kb
Host	smart-c5fd5e2f-b121-4472-93fe-a7eb54502f47
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068997432 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.4068997432
Directory	/workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.120719487
Short name	T129
Test name
Test status
Simulation time	294974663 ps
CPU time	1.88 seconds
Started	Jan 14 12:25:24 PM PST 24
Finished	Jan 14 12:25:31 PM PST 24
Peak memory	215772 kb
Host	smart-8374823e-81fb-454f-a6a1-f5090c98581e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120719487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.120719487
Directory	/workspace/13.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_intr_test.2175212965
Short name	T121
Test name
Test status
Simulation time	10897611 ps
CPU time	0.78 seconds
Started	Jan 14 12:25:10 PM PST 24
Finished	Jan 14 12:25:11 PM PST 24
Peak memory	204880 kb
Host	smart-c9947f44-6aa0-45e8-9586-da05cb82461a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175212965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test. 2175212965
Directory	/workspace/13.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1430656316
Short name	T99
Test name
Test status
Simulation time	245888652 ps
CPU time	3.87 seconds
Started	Jan 14 12:25:22 PM PST 24
Finished	Jan 14 12:25:28 PM PST 24
Peak memory	215716 kb
Host	smart-fa425077-87f8-4acb-b3f8-0798438d07ac
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430656316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. spi_device_same_csr_outstanding.1430656316
Directory	/workspace/13.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1103814006
Short name	T3
Test name
Test status
Simulation time	21208733 ps
CPU time	1.61 seconds
Started	Jan 14 12:25:15 PM PST 24
Finished	Jan 14 12:25:18 PM PST 24
Peak memory	216924 kb
Host	smart-8fc692ed-e568-4cba-b9cd-ce3b4b6b666e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103814006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors. 1103814006
Directory	/workspace/13.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4124606441
Short name	T76
Test name
Test status
Simulation time	642683430 ps
CPU time	14.31 seconds
Started	Jan 14 12:25:17 PM PST 24
Finished	Jan 14 12:25:32 PM PST 24
Peak memory	215792 kb
Host	smart-e30dbabe-91fe-4dd8-9ce8-eee43d762e45
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124606441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic e_tl_intg_err.4124606441
Directory	/workspace/13.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.73622464
Short name	T166
Test name
Test status
Simulation time	34181876 ps
CPU time	1.85 seconds
Started	Jan 14 12:25:19 PM PST 24
Finished	Jan 14 12:25:22 PM PST 24
Peak memory	218432 kb
Host	smart-acac3ef9-8458-4a75-8c35-79d0bf4b85f2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73622464 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.73622464
Directory	/workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3438396011
Short name	T39
Test name
Test status
Simulation time	85324720 ps
CPU time	2.73 seconds
Started	Jan 14 12:25:28 PM PST 24
Finished	Jan 14 12:25:33 PM PST 24
Peak memory	215840 kb
Host	smart-51f63fdd-6c6a-4ee2-bbfb-3915b7abf6c6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438396011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw. 3438396011
Directory	/workspace/14.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_intr_test.3279925979
Short name	T7
Test name
Test status
Simulation time	101241735 ps
CPU time	0.72 seconds
Started	Jan 14 12:25:19 PM PST 24
Finished	Jan 14 12:25:21 PM PST 24
Peak memory	204880 kb
Host	smart-d44bd6f5-ad7a-44a3-85f9-980bce05e171
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279925979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test. 3279925979
Directory	/workspace/14.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3954275158
Short name	T106
Test name
Test status
Simulation time	647369352 ps
CPU time	3.46 seconds
Started	Jan 14 12:25:25 PM PST 24
Finished	Jan 14 12:25:34 PM PST 24
Peak memory	215800 kb
Host	smart-5572092c-0f0a-4db5-8a42-3e1f6bb0ef27
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954275158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. spi_device_same_csr_outstanding.3954275158
Directory	/workspace/14.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.888374537
Short name	T94
Test name
Test status
Simulation time	88845137 ps
CPU time	2.29 seconds
Started	Jan 14 12:25:33 PM PST 24
Finished	Jan 14 12:25:39 PM PST 24
Peak memory	215980 kb
Host	smart-f6f9e063-53fa-4dff-af20-d4b3bd627c55
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888374537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.888374537
Directory	/workspace/14.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3398023356
Short name	T60
Test name
Test status
Simulation time	2358118937 ps
CPU time	12.91 seconds
Started	Jan 14 12:25:19 PM PST 24
Finished	Jan 14 12:25:33 PM PST 24
Peak memory	215928 kb
Host	smart-698b6909-6e1a-4257-8084-5a589f48ffb8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398023356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic e_tl_intg_err.3398023356
Directory	/workspace/14.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_intr_test.3194180691
Short name	T165
Test name
Test status
Simulation time	22856158 ps
CPU time	0.69 seconds
Started	Jan 14 12:25:09 PM PST 24
Finished	Jan 14 12:25:11 PM PST 24
Peak memory	204796 kb
Host	smart-e3e21cf5-09dc-4ad6-8697-059c41640bc8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194180691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test. 3194180691
Directory	/workspace/15.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1293396339
Short name	T123
Test name
Test status
Simulation time	1729512184 ps
CPU time	2.9 seconds
Started	Jan 14 12:25:24 PM PST 24
Finished	Jan 14 12:25:33 PM PST 24
Peak memory	215688 kb
Host	smart-c652969e-73fe-480c-bfe2-f7815f8b4bab
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293396339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. spi_device_same_csr_outstanding.1293396339
Directory	/workspace/15.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1338430014
Short name	T133
Test name
Test status
Simulation time	553572143 ps
CPU time	14.08 seconds
Started	Jan 14 12:25:29 PM PST 24
Finished	Jan 14 12:25:46 PM PST 24
Peak memory	215944 kb
Host	smart-c946cade-2b49-421c-8d0c-58f84f3df83a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338430014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic e_tl_intg_err.1338430014
Directory	/workspace/15.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1995220649
Short name	T19
Test name
Test status
Simulation time	44967137 ps
CPU time	2.65 seconds
Started	Jan 14 12:25:38 PM PST 24
Finished	Jan 14 12:25:46 PM PST 24
Peak memory	218288 kb
Host	smart-09dccff0-745e-4f17-b8c0-ca68996cc76d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995220649 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1995220649
Directory	/workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3548955819
Short name	T135
Test name
Test status
Simulation time	301309558 ps
CPU time	2.53 seconds
Started	Jan 14 12:25:08 PM PST 24
Finished	Jan 14 12:25:12 PM PST 24
Peak memory	215816 kb
Host	smart-c343c360-f175-4d8a-9449-ed2997ff5436
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548955819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw. 3548955819
Directory	/workspace/16.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_intr_test.1201192540
Short name	T48
Test name
Test status
Simulation time	46549687 ps
CPU time	0.73 seconds
Started	Jan 14 12:25:19 PM PST 24
Finished	Jan 14 12:25:21 PM PST 24
Peak memory	204868 kb
Host	smart-58d248cb-d7d9-4435-be32-b93acc57bebd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201192540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test. 1201192540
Directory	/workspace/16.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1808446351
Short name	T83
Test name
Test status
Simulation time	125463738 ps
CPU time	1.96 seconds
Started	Jan 14 12:25:32 PM PST 24
Finished	Jan 14 12:25:38 PM PST 24
Peak memory	215724 kb
Host	smart-99653aff-36f5-4a43-84d7-0048225ef9bc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808446351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. spi_device_same_csr_outstanding.1808446351
Directory	/workspace/16.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2234110967
Short name	T27
Test name
Test status
Simulation time	2429384527 ps
CPU time	4.14 seconds
Started	Jan 14 12:25:44 PM PST 24
Finished	Jan 14 12:25:51 PM PST 24
Peak memory	215980 kb
Host	smart-c9ac7bb4-de19-4eb8-8192-89e7ba0f1650
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234110967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors. 2234110967
Directory	/workspace/16.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2633172550
Short name	T24
Test name
Test status
Simulation time	1077477099 ps
CPU time	22.44 seconds
Started	Jan 14 12:25:17 PM PST 24
Finished	Jan 14 12:25:41 PM PST 24
Peak memory	215740 kb
Host	smart-49d49419-db10-4683-891d-db7bae082699
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633172550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic e_tl_intg_err.2633172550
Directory	/workspace/16.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.707003983
Short name	T174
Test name
Test status
Simulation time	24211945 ps
CPU time	2.1 seconds
Started	Jan 14 12:25:20 PM PST 24
Finished	Jan 14 12:25:24 PM PST 24
Peak memory	218652 kb
Host	smart-e4716d66-fe51-4ca3-82d2-fc3a9d9a8bf7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707003983 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.707003983
Directory	/workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.477041327
Short name	T144
Test name
Test status
Simulation time	198593835 ps
CPU time	2.7 seconds
Started	Jan 14 12:25:19 PM PST 24
Finished	Jan 14 12:25:23 PM PST 24
Peak memory	215756 kb
Host	smart-48614a00-baf6-4fe3-97d3-9427e34703ca
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477041327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.477041327
Directory	/workspace/17.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_intr_test.2574919256
Short name	T154
Test name
Test status
Simulation time	52967734 ps
CPU time	0.67 seconds
Started	Jan 14 12:25:25 PM PST 24
Finished	Jan 14 12:25:31 PM PST 24
Peak memory	204756 kb
Host	smart-6017fdce-1cc0-414b-8f6f-e3a1160c0ea0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574919256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test. 2574919256
Directory	/workspace/17.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3364904536
Short name	T134
Test name
Test status
Simulation time	126070088 ps
CPU time	1.9 seconds
Started	Jan 14 12:25:29 PM PST 24
Finished	Jan 14 12:25:36 PM PST 24
Peak memory	215684 kb
Host	smart-285d6c0e-6285-4175-ad05-3354eb56cacb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364904536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. spi_device_same_csr_outstanding.3364904536
Directory	/workspace/17.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.850431173
Short name	T107
Test name
Test status
Simulation time	116094713 ps
CPU time	3.52 seconds
Started	Jan 14 12:25:16 PM PST 24
Finished	Jan 14 12:25:21 PM PST 24
Peak memory	215976 kb
Host	smart-d29882ef-7f08-43f0-8f84-fb88b066e6cf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850431173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.850431173
Directory	/workspace/17.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3698597894
Short name	T25
Test name
Test status
Simulation time	691731244 ps
CPU time	14.77 seconds
Started	Jan 14 12:25:16 PM PST 24
Finished	Jan 14 12:25:32 PM PST 24
Peak memory	215900 kb
Host	smart-d5d2cc32-28e2-470e-b408-6581573277d4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698597894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic e_tl_intg_err.3698597894
Directory	/workspace/17.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.47723095
Short name	T108
Test name
Test status
Simulation time	131327002 ps
CPU time	1.97 seconds
Started	Jan 14 12:25:29 PM PST 24
Finished	Jan 14 12:25:36 PM PST 24
Peak memory	218136 kb
Host	smart-288d48c5-6c62-4fba-b076-141cee73b16d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47723095 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.47723095
Directory	/workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3156630146
Short name	T37
Test name
Test status
Simulation time	402078104 ps
CPU time	2.8 seconds
Started	Jan 14 12:25:22 PM PST 24
Finished	Jan 14 12:25:30 PM PST 24
Peak memory	215772 kb
Host	smart-2c6bcdd0-31b7-4443-94ee-c6150c4fc206
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156630146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw. 3156630146
Directory	/workspace/18.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_intr_test.4023033319
Short name	T66
Test name
Test status
Simulation time	43301553 ps
CPU time	0.75 seconds
Started	Jan 14 12:25:05 PM PST 24
Finished	Jan 14 12:25:09 PM PST 24
Peak memory	204932 kb
Host	smart-51156452-3fdd-4b2b-a26b-57b89dc3bd34
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023033319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test. 4023033319
Directory	/workspace/18.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4242789317
Short name	T103
Test name
Test status
Simulation time	61928653 ps
CPU time	1.85 seconds
Started	Jan 14 12:25:18 PM PST 24
Finished	Jan 14 12:25:22 PM PST 24
Peak memory	215928 kb
Host	smart-434988df-c7d3-4658-92e8-bf86dc7071d1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242789317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. spi_device_same_csr_outstanding.4242789317
Directory	/workspace/18.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1440214939
Short name	T131
Test name
Test status
Simulation time	180414879 ps
CPU time	4.21 seconds
Started	Jan 14 12:25:18 PM PST 24
Finished	Jan 14 12:25:24 PM PST 24
Peak memory	216024 kb
Host	smart-bb1a1c5b-fd96-4b3a-bb16-66dd18a9eedc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440214939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors. 1440214939
Directory	/workspace/18.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2109594267
Short name	T56
Test name
Test status
Simulation time	900311351 ps
CPU time	21.95 seconds
Started	Jan 14 12:25:30 PM PST 24
Finished	Jan 14 12:25:57 PM PST 24
Peak memory	215908 kb
Host	smart-a6ba53ad-8b98-478d-aa4a-769587b28ced
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109594267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic e_tl_intg_err.2109594267
Directory	/workspace/18.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3912302233
Short name	T175
Test name
Test status
Simulation time	27291609 ps
CPU time	1.41 seconds
Started	Jan 14 12:25:13 PM PST 24
Finished	Jan 14 12:25:16 PM PST 24
Peak memory	217232 kb
Host	smart-b086992d-3d83-4d36-a826-93a84c8c1b9a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912302233 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3912302233
Directory	/workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.644028545
Short name	T116
Test name
Test status
Simulation time	20243530 ps
CPU time	1.34 seconds
Started	Jan 14 12:25:08 PM PST 24
Finished	Jan 14 12:25:12 PM PST 24
Peak memory	215836 kb
Host	smart-cc2e3785-21d5-473d-aa66-aac973f0064a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644028545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.644028545
Directory	/workspace/19.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_intr_test.3875694115
Short name	T146
Test name
Test status
Simulation time	12840403 ps
CPU time	0.68 seconds
Started	Jan 14 12:25:15 PM PST 24
Finished	Jan 14 12:25:17 PM PST 24
Peak memory	204876 kb
Host	smart-6957bf70-d577-4ded-9d00-6d09403a190c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875694115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test. 3875694115
Directory	/workspace/19.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2696786271
Short name	T163
Test name
Test status
Simulation time	185450339 ps
CPU time	3.96 seconds
Started	Jan 14 12:25:08 PM PST 24
Finished	Jan 14 12:25:14 PM PST 24
Peak memory	215748 kb
Host	smart-5d0c7e11-21de-4691-b08f-d773d0b81efb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696786271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. spi_device_same_csr_outstanding.2696786271
Directory	/workspace/19.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1308739782
Short name	T84
Test name
Test status
Simulation time	255965501 ps
CPU time	3.85 seconds
Started	Jan 14 12:25:24 PM PST 24
Finished	Jan 14 12:25:34 PM PST 24
Peak memory	215968 kb
Host	smart-08e8ee7b-d80d-4602-88d8-a834448cffb7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308739782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors. 1308739782
Directory	/workspace/19.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2605829583
Short name	T114
Test name
Test status
Simulation time	221434125 ps
CPU time	7.02 seconds
Started	Jan 14 12:25:07 PM PST 24
Finished	Jan 14 12:25:16 PM PST 24
Peak memory	215832 kb
Host	smart-b5c126dd-fe88-4b7d-a8fb-ff4ceca525e2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605829583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic e_tl_intg_err.2605829583
Directory	/workspace/19.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3845402103
Short name	T38
Test name
Test status
Simulation time	2940903528 ps
CPU time	30.12 seconds
Started	Jan 14 12:25:09 PM PST 24
Finished	Jan 14 12:25:40 PM PST 24
Peak memory	217064 kb
Host	smart-94011b38-826f-4e99-b17d-1b173183a4cb
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845402103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_aliasing.3845402103
Directory	/workspace/2.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1015563149
Short name	T32
Test name
Test status
Simulation time	664390461 ps
CPU time	34.49 seconds
Started	Jan 14 12:25:22 PM PST 24
Finished	Jan 14 12:25:58 PM PST 24
Peak memory	215768 kb
Host	smart-fc3a2152-ff98-44d6-ab85-cd0d5daf0fbc
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015563149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_bit_bash.1015563149
Directory	/workspace/2.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.863849200
Short name	T137
Test name
Test status
Simulation time	36139321 ps
CPU time	1.25 seconds
Started	Jan 14 12:25:06 PM PST 24
Finished	Jan 14 12:25:10 PM PST 24
Peak memory	215756 kb
Host	smart-a96d3353-4d17-4947-83f8-96cfd15cf1e5
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863849200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr _hw_reset.863849200
Directory	/workspace/2.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3046874753
Short name	T88
Test name
Test status
Simulation time	78040504 ps
CPU time	1.78 seconds
Started	Jan 14 12:24:55 PM PST 24
Finished	Jan 14 12:24:58 PM PST 24
Peak memory	217136 kb
Host	smart-209138e9-ad4f-4198-abcf-2a6d0863e7c0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046874753 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3046874753
Directory	/workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1437798326
Short name	T96
Test name
Test status
Simulation time	78519642 ps
CPU time	1.21 seconds
Started	Jan 14 12:25:23 PM PST 24
Finished	Jan 14 12:25:29 PM PST 24
Peak memory	215844 kb
Host	smart-2ac4e026-6ff3-4a2d-a12a-90e75183e32b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437798326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1 437798326
Directory	/workspace/2.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2195690663
Short name	T17
Test name
Test status
Simulation time	149957521 ps
CPU time	2.6 seconds
Started	Jan 14 12:25:10 PM PST 24
Finished	Jan 14 12:25:14 PM PST 24
Peak memory	215828 kb
Host	smart-4e7660d6-17d8-4652-9baf-63ed99f74405
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195690663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi _device_mem_partial_access.2195690663
Directory	/workspace/2.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.463430678
Short name	T71
Test name
Test status
Simulation time	122011037 ps
CPU time	4.43 seconds
Started	Jan 14 12:24:53 PM PST 24
Finished	Jan 14 12:24:58 PM PST 24
Peak memory	215784 kb
Host	smart-16087c4b-370c-41a9-b1df-2b9840130853
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463430678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem _walk.463430678
Directory	/workspace/2.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3713924459
Short name	T42
Test name
Test status
Simulation time	184020801 ps
CPU time	4.34 seconds
Started	Jan 14 12:25:03 PM PST 24
Finished	Jan 14 12:25:12 PM PST 24
Peak memory	215740 kb
Host	smart-dfa61ea8-5475-415d-9e1a-d72b09385122
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713924459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s pi_device_same_csr_outstanding.3713924459
Directory	/workspace/2.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2328111249
Short name	T172
Test name
Test status
Simulation time	349268016 ps
CPU time	3.74 seconds
Started	Jan 14 12:25:14 PM PST 24
Finished	Jan 14 12:25:19 PM PST 24
Peak memory	215932 kb
Host	smart-d793b788-b77e-433a-9652-d0cadaea792a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328111249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2 328111249
Directory	/workspace/2.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.spi_device_intr_test.590990462
Short name	T102
Test name
Test status
Simulation time	13519791 ps
CPU time	0.73 seconds
Started	Jan 14 12:25:45 PM PST 24
Finished	Jan 14 12:25:49 PM PST 24
Peak memory	204900 kb
Host	smart-7528c6c9-f53f-4f27-ac96-b93c3ab6cfbd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590990462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.590990462
Directory	/workspace/20.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.spi_device_intr_test.1925392342
Short name	T11
Test name
Test status
Simulation time	34972234 ps
CPU time	0.7 seconds
Started	Jan 14 12:25:13 PM PST 24
Finished	Jan 14 12:25:15 PM PST 24
Peak memory	204868 kb
Host	smart-f2f94b66-f4a7-4cdb-8db3-56c1a5681fd3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925392342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test. 1925392342
Directory	/workspace/21.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.spi_device_intr_test.1672409610
Short name	T93
Test name
Test status
Simulation time	15002103 ps
CPU time	0.76 seconds
Started	Jan 14 12:25:04 PM PST 24
Finished	Jan 14 12:25:09 PM PST 24
Peak memory	204820 kb
Host	smart-559c8c6e-aff2-4551-a3ad-788ef6541fc1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672409610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test. 1672409610
Directory	/workspace/22.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.spi_device_intr_test.729100931
Short name	T12
Test name
Test status
Simulation time	16620144 ps
CPU time	0.72 seconds
Started	Jan 14 12:25:17 PM PST 24
Finished	Jan 14 12:25:19 PM PST 24
Peak memory	204832 kb
Host	smart-a6baf8a2-7b71-40b7-95d3-dc69aa18fd39
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729100931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.729100931
Directory	/workspace/23.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.spi_device_intr_test.447194177
Short name	T87
Test name
Test status
Simulation time	46778596 ps
CPU time	0.71 seconds
Started	Jan 14 12:25:07 PM PST 24
Finished	Jan 14 12:25:10 PM PST 24
Peak memory	204820 kb
Host	smart-3d656b9a-18c6-4004-8c3a-cf5710107174
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447194177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.447194177
Directory	/workspace/24.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.spi_device_intr_test.387033735
Short name	T86
Test name
Test status
Simulation time	61038251 ps
CPU time	0.71 seconds
Started	Jan 14 12:25:29 PM PST 24
Finished	Jan 14 12:25:36 PM PST 24
Peak memory	204796 kb
Host	smart-fcfd716f-bf4d-41df-85b5-dd692b7aa1d1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387033735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.387033735
Directory	/workspace/25.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.spi_device_intr_test.986359943
Short name	T149
Test name
Test status
Simulation time	12181236 ps
CPU time	0.68 seconds
Started	Jan 14 12:25:30 PM PST 24
Finished	Jan 14 12:25:36 PM PST 24
Peak memory	204844 kb
Host	smart-312cf9da-0774-4c19-9811-fd4bf84eb251
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986359943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.986359943
Directory	/workspace/26.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.spi_device_intr_test.1935648834
Short name	T112
Test name
Test status
Simulation time	31418412 ps
CPU time	0.76 seconds
Started	Jan 14 12:25:14 PM PST 24
Finished	Jan 14 12:25:16 PM PST 24
Peak memory	204888 kb
Host	smart-226f4adc-9704-46fe-9013-d44ba83dee18
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935648834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test. 1935648834
Directory	/workspace/28.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.spi_device_intr_test.1779026605
Short name	T122
Test name
Test status
Simulation time	15052766 ps
CPU time	0.73 seconds
Started	Jan 14 12:25:58 PM PST 24
Finished	Jan 14 12:25:59 PM PST 24
Peak memory	204852 kb
Host	smart-da4beb4c-2583-4c17-8390-b939bb7070fd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779026605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test. 1779026605
Directory	/workspace/29.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4212895105
Short name	T160
Test name
Test status
Simulation time	5953286639 ps
CPU time	28.88 seconds
Started	Jan 14 12:25:09 PM PST 24
Finished	Jan 14 12:25:39 PM PST 24
Peak memory	216976 kb
Host	smart-c7816675-5ca8-4201-a9cc-234d9811fcbb
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212895105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_aliasing.4212895105
Directory	/workspace/3.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1670304529
Short name	T109
Test name
Test status
Simulation time	46215281 ps
CPU time	1.49 seconds
Started	Jan 14 12:25:27 PM PST 24
Finished	Jan 14 12:25:32 PM PST 24
Peak memory	215704 kb
Host	smart-2d4d3483-cfda-411b-b2ae-662fa6394e38
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670304529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_hw_reset.1670304529
Directory	/workspace/3.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.753289707
Short name	T155
Test name
Test status
Simulation time	25653876 ps
CPU time	1.36 seconds
Started	Jan 14 12:24:55 PM PST 24
Finished	Jan 14 12:24:58 PM PST 24
Peak memory	217484 kb
Host	smart-d1a76030-d061-465d-9719-c09a5e9ed060
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753289707 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.753289707
Directory	/workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1541384469
Short name	T104
Test name
Test status
Simulation time	93590453 ps
CPU time	2.6 seconds
Started	Jan 14 12:25:15 PM PST 24
Finished	Jan 14 12:25:18 PM PST 24
Peak memory	215792 kb
Host	smart-b16bdffb-902a-4a03-8939-00f5c9454aec
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541384469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1 541384469
Directory	/workspace/3.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_intr_test.844640522
Short name	T98
Test name
Test status
Simulation time	16880815 ps
CPU time	0.75 seconds
Started	Jan 14 12:25:22 PM PST 24
Finished	Jan 14 12:25:24 PM PST 24
Peak memory	204860 kb
Host	smart-97f67458-b1de-412c-88bd-9171d434a193
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844640522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.844640522
Directory	/workspace/3.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.248898506
Short name	T158
Test name
Test status
Simulation time	814081889 ps
CPU time	6.45 seconds
Started	Jan 14 12:25:05 PM PST 24
Finished	Jan 14 12:25:15 PM PST 24
Peak memory	215832 kb
Host	smart-56c3637f-9466-4180-a0c3-746b57355518
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248898506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_ device_mem_partial_access.248898506
Directory	/workspace/3.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3494758287
Short name	T69
Test name
Test status
Simulation time	799240153 ps
CPU time	12.34 seconds
Started	Jan 14 12:25:07 PM PST 24
Finished	Jan 14 12:25:21 PM PST 24
Peak memory	215756 kb
Host	smart-3a7fc6d8-668c-4102-bdba-3c8b3b2c199d
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494758287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me m_walk.3494758287
Directory	/workspace/3.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3939060951
Short name	T68
Test name
Test status
Simulation time	249180450 ps
CPU time	3 seconds
Started	Jan 14 12:25:09 PM PST 24
Finished	Jan 14 12:25:13 PM PST 24
Peak memory	215848 kb
Host	smart-6b9a3eb5-956c-497c-8489-a70021c0128c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939060951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s pi_device_same_csr_outstanding.3939060951
Directory	/workspace/3.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2808439932
Short name	T6
Test name
Test status
Simulation time	5368065470 ps
CPU time	15.7 seconds
Started	Jan 14 12:25:05 PM PST 24
Finished	Jan 14 12:25:24 PM PST 24
Peak memory	215868 kb
Host	smart-ffefb5e9-2f38-49c0-ab61-37e92e659a65
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808439932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device _tl_intg_err.2808439932
Directory	/workspace/3.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.spi_device_intr_test.1372882690
Short name	T53
Test name
Test status
Simulation time	35271656 ps
CPU time	0.71 seconds
Started	Jan 14 12:25:21 PM PST 24
Finished	Jan 14 12:25:24 PM PST 24
Peak memory	204856 kb
Host	smart-9e0e03d6-efbe-4cbe-9d3f-d36f63104931
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372882690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test. 1372882690
Directory	/workspace/30.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.spi_device_intr_test.4238365509
Short name	T138
Test name
Test status
Simulation time	14129257 ps
CPU time	0.75 seconds
Started	Jan 14 12:25:16 PM PST 24
Finished	Jan 14 12:25:18 PM PST 24
Peak memory	204876 kb
Host	smart-347d05cc-35bf-4408-af11-5b75fb33b333
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238365509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test. 4238365509
Directory	/workspace/31.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.spi_device_intr_test.2078597174
Short name	T15
Test name
Test status
Simulation time	42175108 ps
CPU time	0.73 seconds
Started	Jan 14 12:25:45 PM PST 24
Finished	Jan 14 12:25:49 PM PST 24
Peak memory	204832 kb
Host	smart-9be48f02-82e2-43ed-b5a9-1b2e7f566dcb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078597174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test. 2078597174
Directory	/workspace/33.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.spi_device_intr_test.1432729345
Short name	T100
Test name
Test status
Simulation time	42249928 ps
CPU time	0.68 seconds
Started	Jan 14 12:25:24 PM PST 24
Finished	Jan 14 12:25:30 PM PST 24
Peak memory	204856 kb
Host	smart-04d31c50-5024-4ab3-9a81-abcffc1f4d11
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432729345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test. 1432729345
Directory	/workspace/34.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.spi_device_intr_test.942108432
Short name	T168
Test name
Test status
Simulation time	42844064 ps
CPU time	0.75 seconds
Started	Jan 14 12:26:01 PM PST 24
Finished	Jan 14 12:26:03 PM PST 24
Peak memory	204864 kb
Host	smart-6cc3604a-ef32-4082-94ab-3079f49b6b36
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942108432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.942108432
Directory	/workspace/35.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.spi_device_intr_test.10305780
Short name	T65
Test name
Test status
Simulation time	35336040 ps
CPU time	0.7 seconds
Started	Jan 14 12:25:54 PM PST 24
Finished	Jan 14 12:25:55 PM PST 24
Peak memory	204844 kb
Host	smart-8deb7d10-84da-4e60-a6c2-96c9f2f00b42
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10305780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.10305780
Directory	/workspace/36.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.spi_device_intr_test.766282699
Short name	T63
Test name
Test status
Simulation time	20704021 ps
CPU time	0.7 seconds
Started	Jan 14 12:25:19 PM PST 24
Finished	Jan 14 12:25:21 PM PST 24
Peak memory	204820 kb
Host	smart-1d958dd3-3a64-458e-b9de-8fe9702147b7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766282699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.766282699
Directory	/workspace/37.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.spi_device_intr_test.1165469272
Short name	T78
Test name
Test status
Simulation time	19474378 ps
CPU time	0.79 seconds
Started	Jan 14 12:25:15 PM PST 24
Finished	Jan 14 12:25:16 PM PST 24
Peak memory	205024 kb
Host	smart-95fb8ec1-e46d-42b7-a6c8-59146031a58a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165469272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test. 1165469272
Directory	/workspace/38.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.spi_device_intr_test.970904387
Short name	T150
Test name
Test status
Simulation time	13976082 ps
CPU time	0.74 seconds
Started	Jan 14 12:25:35 PM PST 24
Finished	Jan 14 12:25:39 PM PST 24
Peak memory	204940 kb
Host	smart-6f432328-e706-49b0-a62b-37d19466f81f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970904387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.970904387
Directory	/workspace/39.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.811243416
Short name	T161
Test name
Test status
Simulation time	258444475 ps
CPU time	16.79 seconds
Started	Jan 14 12:25:04 PM PST 24
Finished	Jan 14 12:25:25 PM PST 24
Peak memory	216868 kb
Host	smart-50707eb6-98af-44ce-84b7-524eedf3b5df
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811243416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr _aliasing.811243416
Directory	/workspace/4.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4078911261
Short name	T89
Test name
Test status
Simulation time	3133722891 ps
CPU time	14.74 seconds
Started	Jan 14 12:25:18 PM PST 24
Finished	Jan 14 12:25:35 PM PST 24
Peak memory	207668 kb
Host	smart-83000634-0a51-4d09-8da6-69f65037ed68
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078911261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs r_bit_bash.4078911261
Directory	/workspace/4.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1140466257
Short name	T33
Test name
Test status
Simulation time	175211708 ps
CPU time	1.29 seconds
Started	Jan 14 12:25:16 PM PST 24
Finished	Jan 14 12:25:19 PM PST 24
Peak memory	207660 kb
Host	smart-03875110-1155-4e51-8b6c-7f771f501f5f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140466257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs r_hw_reset.1140466257
Directory	/workspace/4.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2196503268
Short name	T118
Test name
Test status
Simulation time	201739538 ps
CPU time	2.81 seconds
Started	Jan 14 12:25:33 PM PST 24
Finished	Jan 14 12:25:40 PM PST 24
Peak memory	219916 kb
Host	smart-bf107b54-1ec9-444a-8623-0db5357e8917
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196503268 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2196503268
Directory	/workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2163120841
Short name	T41
Test name
Test status
Simulation time	80384264 ps
CPU time	2.05 seconds
Started	Jan 14 12:25:13 PM PST 24
Finished	Jan 14 12:25:16 PM PST 24
Peak memory	215812 kb
Host	smart-64cd7b0e-e44e-4226-9a36-d5ee7258d8e3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163120841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2 163120841
Directory	/workspace/4.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_intr_test.1154993820
Short name	T81
Test name
Test status
Simulation time	12970287 ps
CPU time	0.74 seconds
Started	Jan 14 12:25:05 PM PST 24
Finished	Jan 14 12:25:09 PM PST 24
Peak memory	203816 kb
Host	smart-6f7cf356-c67e-422b-93bc-07bffce2995b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154993820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1 154993820
Directory	/workspace/4.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3964623146
Short name	T152
Test name
Test status
Simulation time	72352543 ps
CPU time	2.6 seconds
Started	Jan 14 12:25:14 PM PST 24
Finished	Jan 14 12:25:18 PM PST 24
Peak memory	215792 kb
Host	smart-95301b28-da6a-4360-83c4-3f19b3e585a7
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964623146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi _device_mem_partial_access.3964623146
Directory	/workspace/4.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2079300786
Short name	T132
Test name
Test status
Simulation time	2642678807 ps
CPU time	12.49 seconds
Started	Jan 14 12:25:21 PM PST 24
Finished	Jan 14 12:25:36 PM PST 24
Peak memory	215828 kb
Host	smart-5faa6d21-58f4-4eab-9d9a-d8d731afa716
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079300786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me m_walk.2079300786
Directory	/workspace/4.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.845881246
Short name	T43
Test name
Test status
Simulation time	117310465 ps
CPU time	3.73 seconds
Started	Jan 14 12:25:09 PM PST 24
Finished	Jan 14 12:25:14 PM PST 24
Peak memory	215788 kb
Host	smart-dcc1ac3b-515d-4409-840a-5e2ca5205d53
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845881246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp i_device_same_csr_outstanding.845881246
Directory	/workspace/4.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1768199145
Short name	T90
Test name
Test status
Simulation time	680693296 ps
CPU time	3.17 seconds
Started	Jan 14 12:25:14 PM PST 24
Finished	Jan 14 12:25:18 PM PST 24
Peak memory	215952 kb
Host	smart-784160ff-9bac-4cad-9c05-082b30f73f79
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768199145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1 768199145
Directory	/workspace/4.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3348599128
Short name	T148
Test name
Test status
Simulation time	582499400 ps
CPU time	13.83 seconds
Started	Jan 14 12:25:02 PM PST 24
Finished	Jan 14 12:25:19 PM PST 24
Peak memory	215872 kb
Host	smart-c3c0b8b0-5e02-49a8-b301-164b6cad5438
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348599128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device _tl_intg_err.3348599128
Directory	/workspace/4.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.spi_device_intr_test.3291027541
Short name	T159
Test name
Test status
Simulation time	63488840 ps
CPU time	0.72 seconds
Started	Jan 14 12:25:25 PM PST 24
Finished	Jan 14 12:25:31 PM PST 24
Peak memory	204844 kb
Host	smart-af2c95fc-ac7f-40df-beb5-e132912548e5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291027541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test. 3291027541
Directory	/workspace/40.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.spi_device_intr_test.3810122583
Short name	T72
Test name
Test status
Simulation time	277130437 ps
CPU time	0.75 seconds
Started	Jan 14 12:25:30 PM PST 24
Finished	Jan 14 12:25:36 PM PST 24
Peak memory	204800 kb
Host	smart-78713f7c-708e-4d5d-9195-f4341bb55382
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810122583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test. 3810122583
Directory	/workspace/41.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.spi_device_intr_test.3993311357
Short name	T73
Test name
Test status
Simulation time	140305472 ps
CPU time	0.76 seconds
Started	Jan 14 12:25:17 PM PST 24
Finished	Jan 14 12:25:19 PM PST 24
Peak memory	204836 kb
Host	smart-e09723b6-da2a-4cd9-a4b8-fd86092b80c6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993311357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test. 3993311357
Directory	/workspace/42.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.spi_device_intr_test.1787639090
Short name	T147
Test name
Test status
Simulation time	49014111 ps
CPU time	0.81 seconds
Started	Jan 14 12:25:32 PM PST 24
Finished	Jan 14 12:25:38 PM PST 24
Peak memory	204828 kb
Host	smart-79292bed-b803-472c-9f3f-d23f4a9ee491
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787639090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test. 1787639090
Directory	/workspace/43.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.spi_device_intr_test.1313293099
Short name	T143
Test name
Test status
Simulation time	34310335 ps
CPU time	0.72 seconds
Started	Jan 14 12:25:21 PM PST 24
Finished	Jan 14 12:25:24 PM PST 24
Peak memory	204884 kb
Host	smart-e5a18458-3e24-4ee3-9e48-92374f93e539
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313293099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test. 1313293099
Directory	/workspace/44.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.spi_device_intr_test.3299859765
Short name	T113
Test name
Test status
Simulation time	21181634 ps
CPU time	0.7 seconds
Started	Jan 14 12:25:15 PM PST 24
Finished	Jan 14 12:25:17 PM PST 24
Peak memory	204892 kb
Host	smart-c705af51-afd1-4c8e-a085-90582f134ce9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299859765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test. 3299859765
Directory	/workspace/45.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.spi_device_intr_test.2373552263
Short name	T162
Test name
Test status
Simulation time	35144436 ps
CPU time	0.74 seconds
Started	Jan 14 12:25:22 PM PST 24
Finished	Jan 14 12:25:25 PM PST 24
Peak memory	204884 kb
Host	smart-bbd9440a-c89d-4195-9a69-d7f931fcd665
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373552263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test. 2373552263
Directory	/workspace/46.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.spi_device_intr_test.2739337756
Short name	T173
Test name
Test status
Simulation time	11004965 ps
CPU time	0.7 seconds
Started	Jan 14 12:25:18 PM PST 24
Finished	Jan 14 12:25:21 PM PST 24
Peak memory	204820 kb
Host	smart-1aaca181-2edc-430b-8863-f3fb18ac4934
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739337756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test. 2739337756
Directory	/workspace/47.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.spi_device_intr_test.472393599
Short name	T64
Test name
Test status
Simulation time	41615771 ps
CPU time	0.72 seconds
Started	Jan 14 12:25:32 PM PST 24
Finished	Jan 14 12:25:37 PM PST 24
Peak memory	204952 kb
Host	smart-3fdc0c75-9f25-45ba-86cd-15b8f9baf890
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472393599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.472393599
Directory	/workspace/48.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.spi_device_intr_test.559800011
Short name	T170
Test name
Test status
Simulation time	16208757 ps
CPU time	0.73 seconds
Started	Jan 14 12:25:21 PM PST 24
Finished	Jan 14 12:25:24 PM PST 24
Peak memory	204880 kb
Host	smart-d8e3e30d-5e7c-4991-97ea-516abc930fbf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559800011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.559800011
Directory	/workspace/49.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.544413335
Short name	T92
Test name
Test status
Simulation time	69358416 ps
CPU time	1.87 seconds
Started	Jan 14 12:25:01 PM PST 24
Finished	Jan 14 12:25:06 PM PST 24
Peak memory	217880 kb
Host	smart-8fc4054f-9473-491b-82c0-ea7de012a4e8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544413335 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.544413335
Directory	/workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3523723588
Short name	T110
Test name
Test status
Simulation time	585421597 ps
CPU time	2.62 seconds
Started	Jan 14 12:25:18 PM PST 24
Finished	Jan 14 12:25:22 PM PST 24
Peak memory	215808 kb
Host	smart-a090248a-fa6e-498f-b0d0-4be9be2ba4ef
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523723588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3 523723588
Directory	/workspace/5.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_intr_test.3954933385
Short name	T13
Test name
Test status
Simulation time	50796979 ps
CPU time	0.73 seconds
Started	Jan 14 12:25:05 PM PST 24
Finished	Jan 14 12:25:09 PM PST 24
Peak memory	204892 kb
Host	smart-6de094e5-16cf-4b7b-8c95-4e25464ebacb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954933385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3 954933385
Directory	/workspace/5.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2170477738
Short name	T34
Test name
Test status
Simulation time	73824484 ps
CPU time	1.77 seconds
Started	Jan 14 12:25:28 PM PST 24
Finished	Jan 14 12:25:32 PM PST 24
Peak memory	215820 kb
Host	smart-b6c6f559-a039-4768-a5ea-ea631147dd22
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170477738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s pi_device_same_csr_outstanding.2170477738
Directory	/workspace/5.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2738179235
Short name	T140
Test name
Test status
Simulation time	96484881 ps
CPU time	5.16 seconds
Started	Jan 14 12:25:05 PM PST 24
Finished	Jan 14 12:25:13 PM PST 24
Peak memory	215864 kb
Host	smart-1563ab02-8ad4-4ea9-8503-35da3a4f2eda
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738179235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2 738179235
Directory	/workspace/5.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2884563437
Short name	T101
Test name
Test status
Simulation time	428558449 ps
CPU time	6.55 seconds
Started	Jan 14 12:24:56 PM PST 24
Finished	Jan 14 12:25:04 PM PST 24
Peak memory	215768 kb
Host	smart-e4e21256-989a-4b27-970a-6678a5f17959
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884563437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device _tl_intg_err.2884563437
Directory	/workspace/5.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1546453849
Short name	T22
Test name
Test status
Simulation time	110245677 ps
CPU time	2.19 seconds
Started	Jan 14 12:25:06 PM PST 24
Finished	Jan 14 12:25:11 PM PST 24
Peak memory	219348 kb
Host	smart-db6c328c-5732-4719-bdca-9ea758cf6516
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546453849 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1546453849
Directory	/workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.994907294
Short name	T125
Test name
Test status
Simulation time	22499735 ps
CPU time	1.3 seconds
Started	Jan 14 12:25:27 PM PST 24
Finished	Jan 14 12:25:32 PM PST 24
Peak memory	215852 kb
Host	smart-c7817d82-3939-4364-8839-f1b3626e15a5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994907294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.994907294
Directory	/workspace/6.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_intr_test.3851100592
Short name	T145
Test name
Test status
Simulation time	24562722 ps
CPU time	0.71 seconds
Started	Jan 14 12:25:10 PM PST 24
Finished	Jan 14 12:25:12 PM PST 24
Peak memory	205020 kb
Host	smart-0e5c0297-31bc-4f61-ac6d-1c5b59a690dd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851100592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3 851100592
Directory	/workspace/6.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.733352030
Short name	T164
Test name
Test status
Simulation time	64511421 ps
CPU time	1.88 seconds
Started	Jan 14 12:25:25 PM PST 24
Finished	Jan 14 12:25:32 PM PST 24
Peak memory	207668 kb
Host	smart-39839028-0200-4ac7-a11a-0c3e3aea946d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733352030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp i_device_same_csr_outstanding.733352030
Directory	/workspace/6.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3725867017
Short name	T29
Test name
Test status
Simulation time	287028169 ps
CPU time	3.36 seconds
Started	Jan 14 12:25:10 PM PST 24
Finished	Jan 14 12:25:14 PM PST 24
Peak memory	215992 kb
Host	smart-e5c29147-b4c0-4692-9cad-4234652fd35f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725867017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3 725867017
Directory	/workspace/6.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1965761536
Short name	T26
Test name
Test status
Simulation time	1023693161 ps
CPU time	21.49 seconds
Started	Jan 14 12:25:09 PM PST 24
Finished	Jan 14 12:25:32 PM PST 24
Peak memory	215588 kb
Host	smart-c0be3f78-f213-44a6-b75f-119ffc23878f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965761536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device _tl_intg_err.1965761536
Directory	/workspace/6.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.172953976
Short name	T82
Test name
Test status
Simulation time	28670935 ps
CPU time	1.64 seconds
Started	Jan 14 12:25:02 PM PST 24
Finished	Jan 14 12:25:09 PM PST 24
Peak memory	219380 kb
Host	smart-02b79e8d-eb47-40b2-a641-dd1565f98829
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172953976 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.172953976
Directory	/workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.805843074
Short name	T169
Test name
Test status
Simulation time	70185490 ps
CPU time	1.97 seconds
Started	Jan 14 12:25:16 PM PST 24
Finished	Jan 14 12:25:20 PM PST 24
Peak memory	215864 kb
Host	smart-a7c85f27-36f3-456d-a321-80cb123f4324
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805843074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.805843074
Directory	/workspace/7.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_intr_test.713576888
Short name	T130
Test name
Test status
Simulation time	33824904 ps
CPU time	0.71 seconds
Started	Jan 14 12:25:14 PM PST 24
Finished	Jan 14 12:25:16 PM PST 24
Peak memory	204864 kb
Host	smart-88628aea-725b-4522-be8d-14e3245a6cae
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713576888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.713576888
Directory	/workspace/7.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3271625146
Short name	T35
Test name
Test status
Simulation time	203776430 ps
CPU time	4.18 seconds
Started	Jan 14 12:25:07 PM PST 24
Finished	Jan 14 12:25:13 PM PST 24
Peak memory	215748 kb
Host	smart-d00f215d-ff61-4b2d-ac65-3bab4fa3aabc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271625146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s pi_device_same_csr_outstanding.3271625146
Directory	/workspace/7.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2197815317
Short name	T9
Test name
Test status
Simulation time	139885040 ps
CPU time	2.62 seconds
Started	Jan 14 12:25:23 PM PST 24
Finished	Jan 14 12:25:31 PM PST 24
Peak memory	217128 kb
Host	smart-f5cbf176-e0d8-41b3-9072-f7b0efc5d5a2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197815317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2 197815317
Directory	/workspace/7.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2440943939
Short name	T157
Test name
Test status
Simulation time	22664309691 ps
CPU time	23.25 seconds
Started	Jan 14 12:25:04 PM PST 24
Finished	Jan 14 12:25:31 PM PST 24
Peak memory	215864 kb
Host	smart-62b2bbe3-b7e1-4726-9469-91d25d3c0834
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440943939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device _tl_intg_err.2440943939
Directory	/workspace/7.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3907472400
Short name	T4
Test name
Test status
Simulation time	205189529 ps
CPU time	2.76 seconds
Started	Jan 14 12:25:40 PM PST 24
Finished	Jan 14 12:25:47 PM PST 24
Peak memory	219776 kb
Host	smart-fc5ee17a-487b-4af2-bf7d-fbb75d5b1651
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907472400 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3907472400
Directory	/workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3873876819
Short name	T10
Test name
Test status
Simulation time	90958820 ps
CPU time	2.6 seconds
Started	Jan 14 12:25:01 PM PST 24
Finished	Jan 14 12:25:07 PM PST 24
Peak memory	215736 kb
Host	smart-4125fae8-bf53-4bd8-a808-a936256d4b04
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873876819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3 873876819
Directory	/workspace/8.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_intr_test.4152827626
Short name	T117
Test name
Test status
Simulation time	25083342 ps
CPU time	0.7 seconds
Started	Jan 14 12:25:08 PM PST 24
Finished	Jan 14 12:25:11 PM PST 24
Peak memory	204364 kb
Host	smart-aec061d2-292c-48f9-aa59-6831e4bf3c3a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152827626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.4 152827626
Directory	/workspace/8.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3263734309
Short name	T70
Test name
Test status
Simulation time	867091358 ps
CPU time	4 seconds
Started	Jan 14 12:25:32 PM PST 24
Finished	Jan 14 12:25:41 PM PST 24
Peak memory	215864 kb
Host	smart-b6bd20b4-34cc-4986-94f4-81648a4f1f4e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263734309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s pi_device_same_csr_outstanding.3263734309
Directory	/workspace/8.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1559388654
Short name	T156
Test name
Test status
Simulation time	214583320 ps
CPU time	5.36 seconds
Started	Jan 14 12:25:20 PM PST 24
Finished	Jan 14 12:25:27 PM PST 24
Peak memory	215984 kb
Host	smart-e0c61a6a-e9b2-401b-9dea-82df7f03d1c0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559388654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1 559388654
Directory	/workspace/8.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4268271964
Short name	T58
Test name
Test status
Simulation time	211166323 ps
CPU time	12.27 seconds
Started	Jan 14 12:25:08 PM PST 24
Finished	Jan 14 12:25:22 PM PST 24
Peak memory	215512 kb
Host	smart-17fdf322-78e0-497e-9907-028f983a9459
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268271964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device _tl_intg_err.4268271964
Directory	/workspace/8.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1878636237
Short name	T111
Test name
Test status
Simulation time	67423785 ps
CPU time	1.19 seconds
Started	Jan 14 12:25:08 PM PST 24
Finished	Jan 14 12:25:11 PM PST 24
Peak memory	217164 kb
Host	smart-a283a97f-ddae-4806-889b-1376fc8607c8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878636237 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1878636237
Directory	/workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3265688767
Short name	T46
Test name
Test status
Simulation time	78405553 ps
CPU time	1.3 seconds
Started	Jan 14 12:25:17 PM PST 24
Finished	Jan 14 12:25:20 PM PST 24
Peak memory	215668 kb
Host	smart-82a95eef-eec7-4eb8-9fd5-c5f20b28417e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265688767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3 265688767
Directory	/workspace/9.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_intr_test.392055400
Short name	T62
Test name
Test status
Simulation time	39843121 ps
CPU time	0.79 seconds
Started	Jan 14 12:25:16 PM PST 24
Finished	Jan 14 12:25:18 PM PST 24
Peak memory	204832 kb
Host	smart-f646d00f-c184-43e0-a4aa-1bab9dc69097
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392055400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.392055400
Directory	/workspace/9.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3978891201
Short name	T85
Test name
Test status
Simulation time	165718218 ps
CPU time	4.19 seconds
Started	Jan 14 12:25:13 PM PST 24
Finished	Jan 14 12:25:18 PM PST 24
Peak memory	215724 kb
Host	smart-761a2d7d-1874-414a-95de-4c148739adc3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978891201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s pi_device_same_csr_outstanding.3978891201
Directory	/workspace/9.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3819287607
Short name	T141
Test name
Test status
Simulation time	232128370 ps
CPU time	3.38 seconds
Started	Jan 14 12:25:22 PM PST 24
Finished	Jan 14 12:25:31 PM PST 24
Peak memory	215896 kb
Host	smart-036621db-74d2-4166-bc22-2222f21f2279
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819287607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3 819287607
Directory	/workspace/9.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3780292478
Short name	T5
Test name
Test status
Simulation time	211601268 ps
CPU time	12.42 seconds
Started	Jan 14 12:25:48 PM PST 24
Finished	Jan 14 12:26:01 PM PST 24
Peak memory	215828 kb
Host	smart-7fb7e732-e2a3-4488-8d2a-276a4e6e8fcc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780292478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device _tl_intg_err.3780292478
Directory	/workspace/9.spi_device_tl_intg_err/latest