Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	12	0	12	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	410	1			T3	1		T7	8		T13	5
all_pins[1]	410	1			T3	1		T7	8		T13	5
all_pins[2]	410	1			T3	1		T7	8		T13	5
all_pins[3]	410	1			T3	1		T7	8		T13	5
all_pins[4]	410	1			T3	1		T7	8		T13	5
all_pins[5]	410	1			T3	1		T7	8		T13	5
all_pins[6]	410	1			T3	1		T7	8		T13	5
all_pins[7]	410	1			T3	1		T7	8		T13	5
all_pins[8]	410	1			T3	1		T7	8		T13	5
all_pins[9]	410	1			T3	1		T7	8		T13	5
all_pins[10]	410	1			T3	1		T7	8		T13	5
all_pins[11]	410	1			T3	1		T7	8		T13	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	3934	1			T3	12		T7	81		T13	49
values[0x1]	986	1			T7	15		T13	11		T11	11
transitions[0x0=>0x1]	731	1			T7	9		T13	10		T11	7
transitions[0x1=>0x0]	743	1			T7	10		T13	10		T11	7

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	318	1			T3	1		T7	5		T13	5
all_pins[0]	values[0x1]	92	1			T7	3		T11	1		T12	1
all_pins[0]	transitions[0x0=>0x1]	70	1			T7	3		T11	1		T12	1
all_pins[0]	transitions[0x1=>0x0]	57	1			T13	1		T11	1		T12	3
all_pins[1]	values[0x0]	331	1			T3	1		T7	8		T13	4
all_pins[1]	values[0x1]	79	1			T13	1		T11	1		T12	3
all_pins[1]	transitions[0x0=>0x1]	59	1			T13	1		T12	3		T15	1
all_pins[1]	transitions[0x1=>0x0]	56	1			T7	1		T12	1		T14	3
all_pins[2]	values[0x0]	334	1			T3	1		T7	7		T13	5
all_pins[2]	values[0x1]	76	1			T7	1		T11	1		T12	1
all_pins[2]	transitions[0x0=>0x1]	55	1			T7	1		T11	1		T12	1
all_pins[2]	transitions[0x1=>0x0]	61	1			T13	2		T11	2		T14	2
all_pins[3]	values[0x0]	328	1			T3	1		T7	8		T13	3
all_pins[3]	values[0x1]	82	1			T13	2		T11	2		T14	2
all_pins[3]	transitions[0x0=>0x1]	57	1			T13	2		T11	2		T14	2
all_pins[3]	transitions[0x1=>0x0]	62	1			T13	2		T14	4		T15	2
all_pins[4]	values[0x0]	323	1			T3	1		T7	8		T13	3
all_pins[4]	values[0x1]	87	1			T13	2		T14	4		T15	2
all_pins[4]	transitions[0x0=>0x1]	72	1			T13	2		T14	4		T15	2
all_pins[4]	transitions[0x1=>0x0]	66	1			T7	1		T15	1		T16	2
all_pins[5]	values[0x0]	329	1			T3	1		T7	7		T13	5
all_pins[5]	values[0x1]	81	1			T7	1		T15	1		T16	2
all_pins[5]	transitions[0x0=>0x1]	57	1			T16	2		T50	2		T51	1
all_pins[5]	transitions[0x1=>0x0]	68	1			T7	1		T13	2		T14	2
all_pins[6]	values[0x0]	318	1			T3	1		T7	6		T13	3
all_pins[6]	values[0x1]	92	1			T7	2		T13	2		T14	2
all_pins[6]	transitions[0x0=>0x1]	66	1			T7	1		T13	1		T14	1
all_pins[6]	transitions[0x1=>0x0]	58	1			T7	1		T13	2		T12	2
all_pins[7]	values[0x0]	326	1			T3	1		T7	6		T13	2
all_pins[7]	values[0x1]	84	1			T7	2		T13	3		T12	2
all_pins[7]	transitions[0x0=>0x1]	68	1			T7	1		T13	3		T12	2
all_pins[7]	transitions[0x1=>0x0]	57	1			T11	3		T14	1		T16	2
all_pins[8]	values[0x0]	337	1			T3	1		T7	7		T13	5
all_pins[8]	values[0x1]	73	1			T7	1		T11	3		T14	1
all_pins[8]	transitions[0x0=>0x1]	57	1			T7	1		T11	1		T50	2
all_pins[8]	transitions[0x1=>0x0]	61	1			T7	1		T13	1		T14	3
all_pins[9]	values[0x0]	333	1			T3	1		T7	7		T13	4
all_pins[9]	values[0x1]	77	1			T7	1		T13	1		T11	2
all_pins[9]	transitions[0x0=>0x1]	57	1			T13	1		T11	2		T14	3
all_pins[9]	transitions[0x1=>0x0]	64	1			T7	2		T14	2		T15	1
all_pins[10]	values[0x0]	326	1			T3	1		T7	5		T13	5
all_pins[10]	values[0x1]	84	1			T7	3		T14	3		T15	1
all_pins[10]	transitions[0x0=>0x1]	70	1			T7	2		T14	2		T50	1
all_pins[10]	transitions[0x1=>0x0]	65	1			T11	1		T12	1		T14	3
all_pins[11]	values[0x0]	331	1			T3	1		T7	7		T13	5
all_pins[11]	values[0x1]	79	1			T7	1		T11	1		T12	1
all_pins[11]	transitions[0x0=>0x1]	43	1			T14	2		T16	2		T50	1
all_pins[11]	transitions[0x1=>0x0]	68	1			T7	3		T15	1		T16	2