Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	72	2	70	97.22

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	72	2	70	97.22	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	341	1			T7	7		T13	4		T11	4
all_values[1]	341	1			T7	7		T13	4		T11	4
all_values[2]	341	1			T7	7		T13	4		T11	4
all_values[3]	341	1			T7	7		T13	4		T11	4
all_values[4]	341	1			T7	7		T13	4		T11	4
all_values[5]	341	1			T7	7		T13	4		T11	4
all_values[6]	341	1			T7	7		T13	4		T11	4
all_values[7]	341	1			T7	7		T13	4		T11	4
all_values[8]	341	1			T7	7		T13	4		T11	4
all_values[9]	341	1			T7	7		T13	4		T11	4
all_values[10]	341	1			T7	7		T13	4		T11	4
all_values[11]	341	1			T7	7		T13	4		T11	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2134

1

T7

46

T13

20

T11

22

auto[1]

1958

1

T7

38

T13

28

T11

26

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1616

1

T7

37

T13

29

T11

29

auto[1]

2476

1

T7

47

T13

19

T11

19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2357

1

T7

48

T13

35

T11

34

auto[1]

1735

1

T7

36

T13

13

T11

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	2	70	97.22	2
Automatically Generated Cross Bins	72	2	70	97.22	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[11]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	69	1			T13	2		T12	1		T16	1
all_values[0]	auto[0]	auto[0]	auto[1]	34	1			T7	1		T12	1		T14	4
all_values[0]	auto[0]	auto[1]	auto[0]	52	1			T13	2		T11	2		T16	1
all_values[0]	auto[0]	auto[1]	auto[1]	43	1			T7	2		T11	1		T14	1
all_values[0]	auto[1]	auto[0]	auto[1]	74	1			T7	2		T12	1		T16	2
all_values[0]	auto[1]	auto[1]	auto[1]	69	1			T7	2		T11	1		T12	1
all_values[1]	auto[0]	auto[0]	auto[0]	59	1			T7	1		T11	2		T14	4
all_values[1]	auto[0]	auto[0]	auto[1]	39	1			T13	1		T12	1		T14	1
all_values[1]	auto[0]	auto[1]	auto[0]	64	1			T7	3		T11	1		T15	2
all_values[1]	auto[0]	auto[1]	auto[1]	32	1			T12	1		T16	1		T50	3
all_values[1]	auto[1]	auto[0]	auto[1]	76	1			T7	2		T13	1		T12	1
all_values[1]	auto[1]	auto[1]	auto[1]	71	1			T7	1		T13	2		T11	1
all_values[2]	auto[0]	auto[0]	auto[0]	74	1			T7	2		T13	4		T12	1
all_values[2]	auto[0]	auto[0]	auto[1]	37	1			T12	1		T16	1		T50	1
all_values[2]	auto[0]	auto[1]	auto[0]	60	1			T7	1		T11	3		T15	1
all_values[2]	auto[0]	auto[1]	auto[1]	26	1			T7	1		T14	1		T16	2
all_values[2]	auto[1]	auto[0]	auto[1]	73	1			T7	1		T12	1		T14	1
all_values[2]	auto[1]	auto[1]	auto[1]	71	1			T7	2		T11	1		T12	1
all_values[3]	auto[0]	auto[0]	auto[0]	85	1			T7	4		T13	2		T12	1
all_values[3]	auto[0]	auto[0]	auto[1]	21	1			T12	2		T16	1		T50	1
all_values[3]	auto[0]	auto[1]	auto[0]	63	1			T7	1		T11	2		T14	2
all_values[3]	auto[0]	auto[1]	auto[1]	35	1			T13	1		T11	1		T14	1
all_values[3]	auto[1]	auto[0]	auto[1]	68	1			T7	2		T12	1		T14	1
all_values[3]	auto[1]	auto[1]	auto[1]	69	1			T13	1		T11	1		T14	1
all_values[4]	auto[0]	auto[0]	auto[0]	77	1			T7	4		T11	3		T16	2
all_values[4]	auto[0]	auto[0]	auto[1]	24	1			T12	1		T14	1		T15	1
all_values[4]	auto[0]	auto[1]	auto[0]	58	1			T7	2		T13	2		T12	1
all_values[4]	auto[0]	auto[1]	auto[1]	41	1			T13	1		T14	3		T15	1
all_values[4]	auto[1]	auto[0]	auto[1]	75	1			T11	1		T12	2		T14	2
all_values[4]	auto[1]	auto[1]	auto[1]	66	1			T7	1		T13	1		T14	1
all_values[5]	auto[0]	auto[0]	auto[0]	57	1			T7	3		T13	1		T11	3
all_values[5]	auto[0]	auto[0]	auto[1]	28	1			T16	1		T50	2		T51	1
all_values[5]	auto[0]	auto[1]	auto[0]	67	1			T13	2		T12	2		T14	2
all_values[5]	auto[0]	auto[1]	auto[1]	39	1			T15	1		T16	2		T52	1
all_values[5]	auto[1]	auto[0]	auto[1]	82	1			T7	1		T13	1		T11	1
all_values[5]	auto[1]	auto[1]	auto[1]	68	1			T7	3		T50	2		T51	1
all_values[6]	auto[0]	auto[0]	auto[0]	57	1			T7	2		T12	2		T16	2
all_values[6]	auto[0]	auto[0]	auto[1]	39	1			T7	1		T13	2		T14	3
all_values[6]	auto[0]	auto[1]	auto[0]	55	1			T11	3		T12	2		T16	4
all_values[6]	auto[0]	auto[1]	auto[1]	36	1			T14	1		T15	2		T50	1
all_values[6]	auto[1]	auto[0]	auto[1]	80	1			T7	2		T14	2		T16	1
all_values[6]	auto[1]	auto[1]	auto[1]	74	1			T7	2		T13	2		T11	1
all_values[7]	auto[0]	auto[0]	auto[0]	65	1			T7	2		T12	1		T15	1
all_values[7]	auto[0]	auto[0]	auto[1]	32	1			T11	1		T14	1		T15	1
all_values[7]	auto[0]	auto[1]	auto[0]	56	1			T7	1		T11	2		T14	2
all_values[7]	auto[0]	auto[1]	auto[1]	39	1			T7	1		T13	1		T12	1
all_values[7]	auto[1]	auto[0]	auto[1]	89	1			T7	3		T11	1		T12	1
all_values[7]	auto[1]	auto[1]	auto[1]	60	1			T13	3		T12	1		T14	2
all_values[8]	auto[0]	auto[0]	auto[0]	78	1			T7	2		T13	3		T12	1
all_values[8]	auto[0]	auto[0]	auto[1]	42	1			T7	1		T14	1		T16	1
all_values[8]	auto[0]	auto[1]	auto[0]	56	1			T12	2		T14	2		T16	4
all_values[8]	auto[0]	auto[1]	auto[1]	25	1			T7	1		T11	1		T16	1
all_values[8]	auto[1]	auto[0]	auto[1]	72	1			T7	3		T13	1		T12	1
all_values[8]	auto[1]	auto[1]	auto[1]	68	1			T11	3		T16	1		T50	4
all_values[9]	auto[0]	auto[0]	auto[0]	59	1			T7	1		T11	2		T12	3
all_values[9]	auto[0]	auto[0]	auto[1]	38	1			T14	1		T16	1		T50	2
all_values[9]	auto[0]	auto[1]	auto[0]	66	1			T13	3		T15	2		T16	1
all_values[9]	auto[0]	auto[1]	auto[1]	27	1			T7	1		T11	1		T14	1
all_values[9]	auto[1]	auto[0]	auto[1]	81	1			T7	3		T12	1		T14	1
all_values[9]	auto[1]	auto[1]	auto[1]	70	1			T7	2		T13	1		T11	1
all_values[10]	auto[0]	auto[0]	auto[0]	72	1			T7	1		T11	3		T12	2
all_values[10]	auto[0]	auto[0]	auto[1]	21	1			T12	1		T16	2		T53	2
all_values[10]	auto[0]	auto[1]	auto[0]	62	1			T7	1		T13	4		T14	2
all_values[10]	auto[0]	auto[1]	auto[1]	43	1			T7	2		T14	3		T15	1
all_values[10]	auto[1]	auto[0]	auto[1]	81	1			T7	1		T11	1		T12	1
all_values[10]	auto[1]	auto[1]	auto[1]	62	1			T7	2		T14	2		T15	1
all_values[11]	auto[0]	auto[0]	auto[0]	106	1			T7	1		T13	2		T11	3
all_values[11]	auto[0]	auto[1]	auto[0]	99	1			T7	5		T13	2		T12	1
all_values[11]	auto[1]	auto[0]	auto[1]	70	1			T11	1		T12	1		T14	1
all_values[11]	auto[1]	auto[1]	auto[1]	66	1			T7	1		T12	1		T14	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal