Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::all_modes_cg

Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	5	0	0.00
Crosses	5	5	0	0.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	3	0	0.00	100	1	1	0
cp_tpm_enabled	2	2	0	0.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	5	5	0	0.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	3	0	0.00

Automatically Generated Bins for cp_mode

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[GenericMode]	0	1	1
auto[FlashMode]	0	1	1
auto[PassthroughMode]	0	1	1

---

Summary for Variable cp_tpm_enabled

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_tpm_enabled

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Cross cr_all

Samples crossed: cp_mode cp_tpm_enabled

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	5	5	0	0.00	5
Automatically Generated Cross Bins	5	5	0	0.00	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Element holes

cp_mode	cp_tpm_enabled	COUNT	AT LEAST	NUMBER	STATUS
[auto[FlashMode] , auto[PassthroughMode]]	*	--	--	4

Uncovered bins

cp_mode	cp_tpm_enabled	COUNT	AT LEAST	NUMBER	STATUS
[auto[GenericMode]]	[auto[0]]	0	1	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded