Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6666855	1			T4	135		T6	1138		T12	1
all_values[1]	6666855	1			T4	135		T6	1138		T12	1
all_values[2]	6666855	1			T4	135		T6	1138		T12	1
all_values[3]	6666855	1			T4	135		T6	1138		T12	1
all_values[4]	6666855	1			T4	135		T6	1138		T12	1
all_values[5]	6666855	1			T4	135		T6	1138		T12	1
all_values[6]	6666855	1			T4	135		T6	1138		T12	1
all_values[7]	6666855	1			T4	135		T6	1138		T12	1
all_values[8]	6666855	1			T4	135		T6	1138		T12	1
all_values[9]	6666855	1			T4	135		T6	1138		T12	1
all_values[10]	6666855	1			T4	135		T6	1138		T12	1
all_values[11]	6666855	1			T4	135		T6	1138		T12	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78779999

1

T4

1620

T6

13656

T12

12

auto[1]

1222261

1

T2

16

T3

14

T10

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79937565

1

T4

1605

T6

13653

T12

12

auto[1]

64695

1

T4

15

T6

3

T1

423

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	6549133	1			T4	135		T6	1138		T12	1
all_values[0]	auto[0]	auto[1]	105	1			T68	2		T69	3		T70	2
all_values[0]	auto[1]	auto[0]	117503	1			T2	2		T3	2		T14	2
all_values[0]	auto[1]	auto[1]	114	1			T68	5		T70	2		T190	3
all_values[1]	auto[0]	auto[0]	6549281	1			T4	135		T6	1138		T12	1
all_values[1]	auto[0]	auto[1]	142	1			T68	4		T69	2		T70	2
all_values[1]	auto[1]	auto[0]	117313	1			T11	2		T14	2		T46	2
all_values[1]	auto[1]	auto[1]	119	1			T68	1		T69	1		T70	4
all_values[2]	auto[0]	auto[0]	6574229	1			T4	135		T6	1138		T12	1
all_values[2]	auto[0]	auto[1]	92	1			T68	3		T69	1		T70	1
all_values[2]	auto[1]	auto[0]	92404	1			T2	2		T11	2		T14	2
all_values[2]	auto[1]	auto[1]	130	1			T69	3		T191	1		T192	1
all_values[3]	auto[0]	auto[0]	6635973	1			T4	135		T6	1138		T12	1
all_values[3]	auto[0]	auto[1]	112	1			T68	1		T69	3		T190	2
all_values[3]	auto[1]	auto[0]	30658	1			T2	2		T32	2		T68	3
all_values[3]	auto[1]	auto[1]	112	1			T68	3		T69	1		T70	1
all_values[4]	auto[0]	auto[0]	6484235	1			T4	135		T6	1138		T12	1
all_values[4]	auto[0]	auto[1]	120	1			T68	2		T69	3		T70	3
all_values[4]	auto[1]	auto[0]	182382	1			T2	2		T3	2		T11	2
all_values[4]	auto[1]	auto[1]	118	1			T68	2		T69	3		T70	2
all_values[5]	auto[0]	auto[0]	6584093	1			T4	135		T6	1138		T12	1
all_values[5]	auto[0]	auto[1]	116	1			T68	2		T69	2		T70	4
all_values[5]	auto[1]	auto[0]	82520	1			T2	2		T3	2		T10	2
all_values[5]	auto[1]	auto[1]	126	1			T68	4		T69	3		T70	1
all_values[6]	auto[0]	auto[0]	6473031	1			T4	135		T6	1138		T12	1
all_values[6]	auto[0]	auto[1]	36895	1			T1	256		T8	298		T68	2
all_values[6]	auto[1]	auto[0]	156159	1			T3	2		T11	2		T14	2
all_values[6]	auto[1]	auto[1]	770	1			T68	1		T69	2		T70	2
all_values[7]	auto[0]	auto[0]	6500630	1			T4	135		T6	1138		T12	1
all_values[7]	auto[0]	auto[1]	17346	1			T1	111		T8	99		T68	1
all_values[7]	auto[1]	auto[0]	148507	1			T2	2		T3	2		T11	2
all_values[7]	auto[1]	auto[1]	372	1			T68	4		T69	1		T70	1
all_values[8]	auto[0]	auto[0]	6597873	1			T4	135		T6	1138		T12	1
all_values[8]	auto[0]	auto[1]	6750	1			T1	56		T8	55		T68	1
all_values[8]	auto[1]	auto[0]	61995	1			T11	2		T14	2		T69	1
all_values[8]	auto[1]	auto[1]	237	1			T68	1		T69	1		T70	4
all_values[9]	auto[0]	auto[0]	6555311	1			T4	135		T6	1138		T12	1
all_values[9]	auto[0]	auto[1]	115	1			T68	2		T69	2		T70	1
all_values[9]	auto[1]	auto[0]	111315	1			T2	2		T3	2		T10	2
all_values[9]	auto[1]	auto[1]	114	1			T69	4		T70	2		T190	3
all_values[10]	auto[0]	auto[0]	6589598	1			T4	135		T6	1138		T12	1
all_values[10]	auto[0]	auto[1]	137	1			T69	2		T70	2		T190	1
all_values[10]	auto[1]	auto[0]	77023	1			T2	2		T10	2		T15	2
all_values[10]	auto[1]	auto[1]	97	1			T68	2		T69	1		T70	3
all_values[11]	auto[0]	auto[0]	6624324	1			T4	120		T6	1135		T12	1
all_values[11]	auto[0]	auto[1]	358	1			T4	15		T6	3		T68	3
all_values[11]	auto[1]	auto[0]	42075	1			T3	2		T11	2		T14	2
all_values[11]	auto[1]	auto[1]	98	1			T68	1		T69	2		T70	2