Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.10 99.01 96.32 98.63 92.06 98.05 95.86 99.76


Total tests in report: 1776
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
76.67 76.67 96.41 96.41 87.22 87.22 68.00 68.00 68.85 68.85 94.73 94.73 82.57 82.57 38.88 38.88 /workspace/coverage/default/13.spi_device_flash_and_tpm.1216650962
83.99 7.32 98.04 1.63 92.26 5.04 89.53 21.53 86.89 18.03 96.95 2.22 83.90 1.33 40.35 1.48 /workspace/coverage/default/12.spi_device_dummy_item_extra_dly.1861409017
87.62 3.63 98.33 0.29 92.91 0.65 89.63 0.10 91.80 4.92 97.39 0.44 84.49 0.59 58.79 18.44 /workspace/coverage/default/40.spi_device_stress_all.2974499035
89.70 2.08 98.38 0.05 93.12 0.22 92.17 2.54 91.80 0.00 97.43 0.03 94.09 9.60 60.89 2.10 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.116911791
91.11 1.42 98.43 0.05 93.21 0.09 92.17 0.00 91.80 0.00 97.53 0.10 94.09 0.00 70.56 9.67 /workspace/coverage/default/12.spi_device_flash_and_tpm.3215758690
92.27 1.16 98.66 0.23 93.53 0.32 94.13 1.96 91.80 0.00 97.53 0.00 94.09 0.00 76.18 5.62 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2815301020
93.22 0.94 98.74 0.08 94.06 0.53 94.13 0.00 93.44 1.64 97.63 0.10 94.24 0.15 80.28 4.10 /workspace/coverage/default/18.spi_device_stress_all.3462819359
93.78 0.56 98.75 0.01 94.06 0.00 98.04 3.91 93.44 0.00 97.63 0.00 94.24 0.00 80.28 0.00 /workspace/coverage/default/0.spi_device_ram_cfg.2351760890
94.32 0.54 98.75 0.00 94.13 0.06 98.04 0.00 93.44 0.00 97.65 0.02 94.24 0.00 83.99 3.72 /workspace/coverage/default/16.spi_device_flash_and_tpm.1987671463
94.68 0.36 98.75 0.00 94.13 0.00 98.04 0.00 93.44 0.00 97.65 0.00 94.24 0.00 86.52 2.53 /workspace/coverage/default/7.spi_device_flash_and_tpm.3858217904
94.95 0.27 98.75 0.00 94.13 0.00 98.04 0.00 93.44 0.00 97.65 0.00 94.24 0.00 88.38 1.86 /workspace/coverage/default/23.spi_device_flash_and_tpm.2000316104
95.21 0.26 98.79 0.04 94.18 0.05 98.04 0.00 95.08 1.64 97.71 0.07 94.24 0.00 88.42 0.05 /workspace/coverage/default/44.spi_device_rx_timeout.2573176638
95.47 0.26 98.89 0.10 94.60 0.42 98.04 0.00 95.08 0.00 97.85 0.14 94.83 0.59 88.99 0.57 /workspace/coverage/default/23.spi_device_flash_mode.3778074682
95.68 0.21 98.90 0.01 94.60 0.00 98.04 0.00 95.08 0.00 97.87 0.02 94.83 0.00 90.42 1.43 /workspace/coverage/default/11.spi_device_stress_all.588058837
95.86 0.18 98.90 0.00 95.48 0.89 98.04 0.00 95.08 0.00 97.88 0.02 94.83 0.00 90.81 0.38 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1153593915
96.02 0.16 98.90 0.00 95.48 0.00 98.04 0.00 95.08 0.00 97.88 0.00 94.83 0.00 91.90 1.10 /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2839804301
96.17 0.15 98.92 0.02 96.04 0.56 98.24 0.20 95.08 0.00 97.90 0.02 94.83 0.00 92.19 0.29 /workspace/coverage/default/29.spi_device_stress_all.857589212
96.32 0.15 98.92 0.00 96.04 0.00 98.24 0.00 95.08 0.00 97.90 0.00 94.83 0.00 93.23 1.05 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1063878875
96.45 0.13 98.92 0.00 96.04 0.00 98.24 0.00 95.08 0.00 97.90 0.00 95.72 0.89 93.23 0.00 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2378981164
96.57 0.12 98.92 0.00 96.04 0.00 98.24 0.00 95.08 0.00 97.90 0.00 95.72 0.00 94.09 0.86 /workspace/coverage/default/26.spi_device_flash_and_tpm.4018688563
96.68 0.11 98.92 0.00 96.04 0.00 98.24 0.00 95.08 0.00 97.90 0.00 95.72 0.00 94.85 0.76 /workspace/coverage/default/7.spi_device_stress_all.2398529921
96.77 0.09 98.92 0.00 96.04 0.00 98.24 0.00 95.08 0.00 97.90 0.00 95.72 0.00 95.47 0.62 /workspace/coverage/default/6.spi_device_flash_and_tpm.3738499195
96.84 0.07 98.92 0.00 96.04 0.00 98.24 0.00 95.08 0.00 97.90 0.00 95.72 0.00 96.00 0.52 /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.140073495
96.91 0.07 98.92 0.00 96.07 0.03 98.43 0.20 95.08 0.00 97.90 0.00 95.86 0.15 96.09 0.10 /workspace/coverage/default/0.spi_device_sec_cm.3418321659
96.96 0.05 98.92 0.00 96.07 0.00 98.43 0.00 95.08 0.00 97.90 0.00 95.86 0.00 96.47 0.38 /workspace/coverage/default/24.spi_device_flash_all.1851540248
97.01 0.05 98.92 0.00 96.07 0.00 98.43 0.00 95.08 0.00 97.90 0.00 95.86 0.00 96.81 0.33 /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1845181264
97.06 0.04 99.09 0.17 96.07 0.00 98.43 0.00 95.08 0.00 97.90 0.00 95.86 0.00 96.95 0.14 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4057714128
97.10 0.04 99.09 0.00 96.07 0.00 98.43 0.00 95.08 0.00 97.90 0.00 95.86 0.00 97.24 0.29 /workspace/coverage/default/19.spi_device_flash_all.2835772497
97.13 0.03 99.09 0.00 96.07 0.00 98.43 0.00 95.08 0.00 97.90 0.00 95.86 0.00 97.47 0.24 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.525434735
97.16 0.03 99.09 0.00 96.07 0.00 98.43 0.00 95.08 0.00 97.90 0.00 95.86 0.00 97.71 0.24 /workspace/coverage/default/23.spi_device_bit_transfer.1555704707
97.20 0.03 99.15 0.06 96.16 0.09 98.43 0.00 95.08 0.00 97.98 0.08 95.86 0.00 97.71 0.00 /workspace/coverage/default/10.spi_device_mem_parity.3092559753
97.23 0.03 99.15 0.00 96.18 0.03 98.63 0.20 95.08 0.00 97.98 0.00 95.86 0.00 97.71 0.00 /workspace/coverage/default/10.spi_device_alert_test.1469369610
97.26 0.03 99.15 0.00 96.18 0.00 98.63 0.00 95.08 0.00 97.98 0.00 95.86 0.00 97.90 0.19 /workspace/coverage/default/12.spi_device_stress_all.2988348012
97.28 0.03 99.15 0.00 96.18 0.00 98.63 0.00 95.08 0.00 97.98 0.00 95.86 0.00 98.09 0.19 /workspace/coverage/default/37.spi_device_stress_all.3230730419
97.30 0.02 99.15 0.00 96.18 0.00 98.63 0.00 95.08 0.00 97.98 0.00 95.86 0.00 98.24 0.14 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.997997445
97.32 0.02 99.15 0.00 96.18 0.00 98.63 0.00 95.08 0.00 97.98 0.00 95.86 0.00 98.38 0.14 /workspace/coverage/default/1.spi_device_stress_all.697177214
97.34 0.02 99.15 0.00 96.21 0.03 98.63 0.00 95.08 0.00 98.00 0.02 95.86 0.00 98.48 0.10 /workspace/coverage/default/17.spi_device_fifo_underflow_overflow.2584691156
97.36 0.01 99.15 0.00 96.21 0.00 98.63 0.00 95.08 0.00 98.00 0.00 95.86 0.00 98.57 0.10 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3571134222
97.37 0.01 99.15 0.00 96.21 0.00 98.63 0.00 95.08 0.00 98.00 0.00 95.86 0.00 98.67 0.10 /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1754417007
97.38 0.01 99.15 0.00 96.21 0.00 98.63 0.00 95.08 0.00 98.00 0.00 95.86 0.00 98.76 0.10 /workspace/coverage/default/17.spi_device_stress_all.1019134157
97.40 0.01 99.15 0.00 96.21 0.00 98.63 0.00 95.08 0.00 98.00 0.00 95.86 0.00 98.86 0.10 /workspace/coverage/default/2.spi_device_stress_all.1637261232
97.41 0.01 99.15 0.00 96.21 0.00 98.63 0.00 95.08 0.00 98.00 0.00 95.86 0.00 98.95 0.10 /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3566220440
97.43 0.01 99.15 0.00 96.21 0.00 98.63 0.00 95.08 0.00 98.00 0.00 95.86 0.00 99.05 0.10 /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2531458821
97.44 0.01 99.16 0.01 96.22 0.01 98.63 0.00 95.08 0.00 98.02 0.02 95.86 0.00 99.09 0.05 /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3975745813
97.45 0.01 99.17 0.01 96.22 0.00 98.63 0.00 95.08 0.00 98.04 0.02 95.86 0.00 99.14 0.05 /workspace/coverage/default/15.spi_device_flash_mode.1304555557
97.46 0.01 99.17 0.00 96.28 0.06 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.14 0.00 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3868892625
97.46 0.01 99.17 0.00 96.28 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.19 0.05 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4086111369
97.47 0.01 99.17 0.00 96.28 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.24 0.05 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3541586670
97.48 0.01 99.17 0.00 96.28 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.29 0.05 /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.18535458
97.48 0.01 99.17 0.00 96.28 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.33 0.05 /workspace/coverage/default/11.spi_device_extreme_fifo_size.606705012
97.49 0.01 99.17 0.00 96.28 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.38 0.05 /workspace/coverage/default/15.spi_device_flash_all.1647358245
97.50 0.01 99.17 0.00 96.28 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.43 0.05 /workspace/coverage/default/17.spi_device_dummy_item_extra_dly.125315732
97.51 0.01 99.17 0.00 96.28 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.48 0.05 /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.716995094
97.51 0.01 99.17 0.00 96.28 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.52 0.05 /workspace/coverage/default/2.spi_device_intr.1380279969
97.52 0.01 99.17 0.00 96.28 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.57 0.05 /workspace/coverage/default/28.spi_device_flash_all.2011988359
97.53 0.01 99.17 0.00 96.28 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.62 0.05 /workspace/coverage/default/29.spi_device_flash_all.2789730382
97.53 0.01 99.17 0.00 96.28 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.67 0.05 /workspace/coverage/default/33.spi_device_flash_all.23906276
97.54 0.01 99.17 0.00 96.28 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.71 0.05 /workspace/coverage/default/38.spi_device_flash_all.1862898278
97.55 0.01 99.17 0.00 96.28 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.76 0.05 /workspace/coverage/default/4.spi_device_extreme_fifo_size.2907094752
97.55 0.01 99.18 0.01 96.30 0.01 98.63 0.00 95.08 0.00 98.05 0.02 95.86 0.00 99.76 0.00 /workspace/coverage/default/17.spi_device_abort.1336462287
97.55 0.01 99.18 0.00 96.31 0.01 98.63 0.00 95.08 0.00 98.05 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/1.spi_device_rx_async_fifo_reset.3313754858
97.56 0.01 99.18 0.00 96.32 0.01 98.63 0.00 95.08 0.00 98.05 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/13.spi_device_tx_async_fifo_reset.332952580

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.594377960
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3908808777
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.637344679
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.3584415210
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1983295752
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.583309469
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2493010425
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2796827571
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2183276118
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1743069689
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3788563712
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4118229889
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3776517960
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.1580735610
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.644391281
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3891701766
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.813058287
/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2584707731
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.556612485
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3759990931
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.1542467046
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.456496003
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1971734872
/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3694615741
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.812253915
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3931444916
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.187315921
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2601211189
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1173114841
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3783574569
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2127530749
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.3576472181
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2813801116
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1362632300
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3550696274
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.769881783
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.320035256
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.1857643216
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3651997187
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.208221983
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.486729424
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.276196216
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1712185258
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.613198912
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.736701552
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3218039100
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1472961987
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1456516588
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.719790982
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3741241882
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2405545797
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1524013893
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2085818459
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.2026627604
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1900360817
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1105755383
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.464049136
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.956445721
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.138639575
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.406409252
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2758383154
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.215967540
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2168828608
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4125120662
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3721190736
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.1348156963
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2920604504
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2467114701
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4037972140
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.327632250
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.173397053
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.1828159311
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2678189284
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3662428653
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2384039322
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3414030357
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2188233915
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1777117720
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1870971707
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.3558478246
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2849610998
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1496636751
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2982822183
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1598954697
/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2780404857
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.2536393379
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.2040663536
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.1387625066
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.3100530053
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.956882046
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.2276278640
/workspace/coverage/cover_reg_top/26.spi_device_intr_test.4292272487
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.1565643372
/workspace/coverage/cover_reg_top/29.spi_device_intr_test.3606187846
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3616861185
/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3577338638
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3034921066
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2300825960
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.861060194
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.2637562443
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1821387069
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.888176076
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1318797908
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2522010164
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/workspace/coverage/default/7.spi_device_fifo_underflow_overflow.3318877290
/workspace/coverage/default/7.spi_device_flash_all.3362286709
/workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2887689551
/workspace/coverage/default/7.spi_device_flash_mode.816740808
/workspace/coverage/default/7.spi_device_intercept.2701461752
/workspace/coverage/default/7.spi_device_intr.2753451174
/workspace/coverage/default/7.spi_device_mailbox.1381636813
/workspace/coverage/default/7.spi_device_mem_parity.2047101467
/workspace/coverage/default/7.spi_device_pass_addr_payload_swap.546259542
/workspace/coverage/default/7.spi_device_pass_cmd_filtering.532966925
/workspace/coverage/default/7.spi_device_perf.2551861891
/workspace/coverage/default/7.spi_device_ram_cfg.2697532473
/workspace/coverage/default/7.spi_device_read_buffer_direct.4244636012
/workspace/coverage/default/7.spi_device_rx_async_fifo_reset.2117064152
/workspace/coverage/default/7.spi_device_rx_timeout.3309485482
/workspace/coverage/default/7.spi_device_smoke.2205763136
/workspace/coverage/default/7.spi_device_tpm_all.4142016978
/workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3150514219
/workspace/coverage/default/7.spi_device_tpm_rw.2011718873
/workspace/coverage/default/7.spi_device_tpm_sts_read.2574956808
/workspace/coverage/default/7.spi_device_tx_async_fifo_reset.1807346902
/workspace/coverage/default/7.spi_device_txrx.4141654401
/workspace/coverage/default/7.spi_device_upload.3532060250
/workspace/coverage/default/8.spi_device_abort.846621046
/workspace/coverage/default/8.spi_device_alert_test.2844384939
/workspace/coverage/default/8.spi_device_bit_transfer.957562887
/workspace/coverage/default/8.spi_device_byte_transfer.940027105
/workspace/coverage/default/8.spi_device_cfg_cmd.3461129883
/workspace/coverage/default/8.spi_device_csb_read.1507212768
/workspace/coverage/default/8.spi_device_dummy_item_extra_dly.4245792259
/workspace/coverage/default/8.spi_device_extreme_fifo_size.621660027
/workspace/coverage/default/8.spi_device_fifo_full.4274757594
/workspace/coverage/default/8.spi_device_fifo_underflow_overflow.4095234822
/workspace/coverage/default/8.spi_device_flash_all.2814830860
/workspace/coverage/default/8.spi_device_flash_mode.2251303850
/workspace/coverage/default/8.spi_device_intercept.1881880607
/workspace/coverage/default/8.spi_device_intr.1949479645
/workspace/coverage/default/8.spi_device_mailbox.3179731331
/workspace/coverage/default/8.spi_device_mem_parity.1431320988
/workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1837540329
/workspace/coverage/default/8.spi_device_pass_cmd_filtering.492797528
/workspace/coverage/default/8.spi_device_perf.3938747797
/workspace/coverage/default/8.spi_device_ram_cfg.3623293726
/workspace/coverage/default/8.spi_device_read_buffer_direct.202597478
/workspace/coverage/default/8.spi_device_rx_async_fifo_reset.1369105146
/workspace/coverage/default/8.spi_device_rx_timeout.2833060462
/workspace/coverage/default/8.spi_device_smoke.1937376110
/workspace/coverage/default/8.spi_device_stress_all.3986775783
/workspace/coverage/default/8.spi_device_tpm_all.1570991979
/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3969670821
/workspace/coverage/default/8.spi_device_tpm_rw.1029474936
/workspace/coverage/default/8.spi_device_tpm_sts_read.2554945105
/workspace/coverage/default/8.spi_device_tx_async_fifo_reset.3961774107
/workspace/coverage/default/8.spi_device_txrx.3504729493
/workspace/coverage/default/8.spi_device_upload.503692987
/workspace/coverage/default/9.spi_device_abort.1807707438
/workspace/coverage/default/9.spi_device_alert_test.4033216511
/workspace/coverage/default/9.spi_device_bit_transfer.621558695
/workspace/coverage/default/9.spi_device_byte_transfer.2962748668
/workspace/coverage/default/9.spi_device_cfg_cmd.563527234
/workspace/coverage/default/9.spi_device_csb_read.531608733
/workspace/coverage/default/9.spi_device_dummy_item_extra_dly.4235158792
/workspace/coverage/default/9.spi_device_extreme_fifo_size.3275350983
/workspace/coverage/default/9.spi_device_fifo_full.2112983021
/workspace/coverage/default/9.spi_device_fifo_underflow_overflow.892849840
/workspace/coverage/default/9.spi_device_flash_all.2759514242
/workspace/coverage/default/9.spi_device_flash_and_tpm.3854949721
/workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.143940832
/workspace/coverage/default/9.spi_device_flash_mode.1992462412
/workspace/coverage/default/9.spi_device_intercept.4217701010
/workspace/coverage/default/9.spi_device_intr.2142556048
/workspace/coverage/default/9.spi_device_mailbox.2964297952
/workspace/coverage/default/9.spi_device_mem_parity.2490872427
/workspace/coverage/default/9.spi_device_pass_addr_payload_swap.248027493
/workspace/coverage/default/9.spi_device_pass_cmd_filtering.4271121231
/workspace/coverage/default/9.spi_device_perf.3774276797
/workspace/coverage/default/9.spi_device_ram_cfg.2353116156
/workspace/coverage/default/9.spi_device_rx_async_fifo_reset.1110481614
/workspace/coverage/default/9.spi_device_rx_timeout.1352075742
/workspace/coverage/default/9.spi_device_smoke.2627281439
/workspace/coverage/default/9.spi_device_stress_all.1349990564
/workspace/coverage/default/9.spi_device_tpm_all.3571086035
/workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2654898274
/workspace/coverage/default/9.spi_device_tpm_rw.2533122705
/workspace/coverage/default/9.spi_device_tpm_sts_read.3188089649
/workspace/coverage/default/9.spi_device_tx_async_fifo_reset.2367639539
/workspace/coverage/default/9.spi_device_txrx.515857094



Total test records in report: 1776
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspace/coverage/default/32.spi_device_tpm_rw.3821011555 Jan 17 03:34:36 PM PST 24 Jan 17 03:34:41 PM PST 24 64754362 ps
T5 /workspace/coverage/default/10.spi_device_alert_test.1469369610 Jan 17 03:30:39 PM PST 24 Jan 17 03:30:41 PM PST 24 127785831 ps
T6 /workspace/coverage/default/2.spi_device_tpm_rw.2729522095 Jan 17 03:28:57 PM PST 24 Jan 17 03:29:09 PM PST 24 1251135887 ps
T7 /workspace/coverage/default/35.spi_device_read_buffer_direct.1609894020 Jan 17 03:35:25 PM PST 24 Jan 17 03:35:29 PM PST 24 666576530 ps
T12 /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1555133852 Jan 17 03:31:14 PM PST 24 Jan 17 03:31:23 PM PST 24 2362653211 ps
T1 /workspace/coverage/default/13.spi_device_flash_and_tpm.1216650962 Jan 17 03:31:01 PM PST 24 Jan 17 03:34:34 PM PST 24 112651594716 ps
T2 /workspace/coverage/default/12.spi_device_fifo_full.2900700737 Jan 17 03:30:50 PM PST 24 Jan 17 04:05:50 PM PST 24 67017976471 ps
T3 /workspace/coverage/default/3.spi_device_abort.2574259880 Jan 17 03:29:04 PM PST 24 Jan 17 03:29:06 PM PST 24 24959557 ps
T8 /workspace/coverage/default/37.spi_device_flash_and_tpm.311383002 Jan 17 03:35:53 PM PST 24 Jan 17 03:40:54 PM PST 24 54467264085 ps
T10 /workspace/coverage/default/7.spi_device_rx_async_fifo_reset.2117064152 Jan 17 03:29:58 PM PST 24 Jan 17 03:30:01 PM PST 24 35634320 ps
T37 /workspace/coverage/default/22.spi_device_alert_test.2691390480 Jan 17 03:32:48 PM PST 24 Jan 17 03:32:49 PM PST 24 14745098 ps
T11 /workspace/coverage/default/5.spi_device_extreme_fifo_size.3070138416 Jan 17 03:29:26 PM PST 24 Jan 17 03:30:46 PM PST 24 14132648308 ps
T13 /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3947080602 Jan 17 03:28:58 PM PST 24 Jan 17 03:29:20 PM PST 24 15862952597 ps
T14 /workspace/coverage/default/16.spi_device_perf.901992689 Jan 17 03:31:28 PM PST 24 Jan 17 03:40:08 PM PST 24 17552846288 ps
T31 /workspace/coverage/default/29.spi_device_tpm_all.210918667 Jan 17 03:33:59 PM PST 24 Jan 17 03:34:24 PM PST 24 4407748758 ps
T15 /workspace/coverage/default/31.spi_device_rx_async_fifo_reset.2928361632 Jan 17 03:34:25 PM PST 24 Jan 17 03:34:27 PM PST 24 54515606 ps
T81 /workspace/coverage/default/49.spi_device_csb_read.1385895871 Jan 17 03:38:17 PM PST 24 Jan 17 03:38:19 PM PST 24 73714503 ps
T36 /workspace/coverage/default/38.spi_device_mailbox.4061443829 Jan 17 03:36:04 PM PST 24 Jan 17 03:36:29 PM PST 24 132650722409 ps
T103 /workspace/coverage/default/31.spi_device_tpm_sts_read.259523005 Jan 17 03:34:24 PM PST 24 Jan 17 03:34:26 PM PST 24 46645339 ps
T46 /workspace/coverage/default/21.spi_device_tx_async_fifo_reset.2108214924 Jan 17 03:32:22 PM PST 24 Jan 17 03:32:25 PM PST 24 49007521 ps
T32 /workspace/coverage/default/12.spi_device_dummy_item_extra_dly.1861409017 Jan 17 03:30:52 PM PST 24 Jan 17 03:38:28 PM PST 24 67547903169 ps
T142 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1983295752 Jan 17 12:58:15 PM PST 24 Jan 17 12:58:24 PM PST 24 360740623 ps
T86 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1153593915 Jan 17 12:58:37 PM PST 24 Jan 17 12:58:44 PM PST 24 776449390 ps
T364 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.888176076 Jan 17 12:58:32 PM PST 24 Jan 17 12:58:50 PM PST 24 3908119637 ps
T71 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.861060194 Jan 17 12:58:31 PM PST 24 Jan 17 12:58:33 PM PST 24 136109539 ps
T67 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2378981164 Jan 17 12:58:15 PM PST 24 Jan 17 12:58:18 PM PST 24 44861677 ps
T365 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3577338638 Jan 17 12:58:30 PM PST 24 Jan 17 12:58:57 PM PST 24 732013500 ps
T68 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1569789975 Jan 17 12:58:32 PM PST 24 Jan 17 12:58:34 PM PST 24 14250701 ps
T84 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1210875550 Jan 17 12:58:41 PM PST 24 Jan 17 12:59:01 PM PST 24 1077132659 ps
T69 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1828159311 Jan 17 12:59:15 PM PST 24 Jan 17 12:59:18 PM PST 24 17040837 ps
T85 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1173114841 Jan 17 12:58:44 PM PST 24 Jan 17 12:59:07 PM PST 24 5745963355 ps
T70 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2815301020 Jan 17 12:59:25 PM PST 24 Jan 17 12:59:29 PM PST 24 27642242 ps
T190 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1214200201 Jan 17 12:59:30 PM PST 24 Jan 17 12:59:32 PM PST 24 14427013 ps
T143 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2601211189 Jan 17 12:59:04 PM PST 24 Jan 17 12:59:09 PM PST 24 63360617 ps
T189 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1348156963 Jan 17 12:59:17 PM PST 24 Jan 17 12:59:19 PM PST 24 15849520 ps
T191 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.613198912 Jan 17 12:59:02 PM PST 24 Jan 17 12:59:03 PM PST 24 24090019 ps
T117 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.116911791 Jan 17 12:59:14 PM PST 24 Jan 17 12:59:33 PM PST 24 1437889560 ps
T192 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3292969272 Jan 17 12:59:22 PM PST 24 Jan 17 12:59:27 PM PST 24 14681173 ps
T144 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1712185258 Jan 17 12:59:00 PM PST 24 Jan 17 12:59:03 PM PST 24 113389874 ps
T162 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.719790982 Jan 17 12:59:20 PM PST 24 Jan 17 12:59:28 PM PST 24 91029176 ps
T163 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.138639575 Jan 17 12:59:05 PM PST 24 Jan 17 12:59:08 PM PST 24 272265314 ps
T173 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2723639926 Jan 17 12:58:46 PM PST 24 Jan 17 12:58:48 PM PST 24 48457422 ps
T174 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3891701766 Jan 17 12:58:18 PM PST 24 Jan 17 12:58:25 PM PST 24 295948109 ps
T115 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2467114701 Jan 17 12:59:15 PM PST 24 Jan 17 12:59:20 PM PST 24 105135682 ps
T134 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4057714128 Jan 17 12:59:37 PM PST 24 Jan 17 12:59:39 PM PST 24 15835012 ps
T135 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1002860660 Jan 17 12:59:33 PM PST 24 Jan 17 12:59:35 PM PST 24 54786469 ps
T136 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.187315921 Jan 17 12:58:44 PM PST 24 Jan 17 12:58:47 PM PST 24 16226840 ps
T137 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2678189284 Jan 17 12:59:15 PM PST 24 Jan 17 12:59:19 PM PST 24 283040507 ps
T116 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3218039100 Jan 17 12:59:18 PM PST 24 Jan 17 12:59:28 PM PST 24 29981609 ps
T138 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1496636751 Jan 17 12:58:27 PM PST 24 Jan 17 12:58:38 PM PST 24 545027595 ps
T133 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.276196216 Jan 17 12:59:07 PM PST 24 Jan 17 12:59:10 PM PST 24 61676359 ps
T145 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.173397053 Jan 17 12:59:22 PM PST 24 Jan 17 12:59:28 PM PST 24 21173789 ps
T146 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3571134222 Jan 17 12:59:07 PM PST 24 Jan 17 12:59:08 PM PST 24 17882492 ps
T147 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2255078932 Jan 17 12:58:31 PM PST 24 Jan 17 12:58:34 PM PST 24 306477771 ps
T148 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3931444916 Jan 17 12:58:42 PM PST 24 Jan 17 12:58:48 PM PST 24 21644469 ps
T149 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2920604504 Jan 17 12:59:13 PM PST 24 Jan 17 12:59:17 PM PST 24 113763944 ps
T150 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2300825960 Jan 17 12:58:33 PM PST 24 Jan 17 12:58:37 PM PST 24 144696687 ps
T151 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.769881783 Jan 17 12:59:01 PM PST 24 Jan 17 12:59:05 PM PST 24 43834447 ps
T158 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1063878875 Jan 17 12:59:23 PM PST 24 Jan 17 12:59:27 PM PST 24 15616202 ps
T120 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3662428653 Jan 17 12:59:18 PM PST 24 Jan 17 12:59:31 PM PST 24 269410585 ps
T366 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.583309469 Jan 17 12:58:15 PM PST 24 Jan 17 12:58:32 PM PST 24 6146309178 ps
T367 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3584415210 Jan 17 12:58:21 PM PST 24 Jan 17 12:58:22 PM PST 24 64283737 ps
T176 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3100530053 Jan 17 12:59:21 PM PST 24 Jan 17 12:59:27 PM PST 24 24768992 ps
T368 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2982822183 Jan 17 12:58:29 PM PST 24 Jan 17 12:58:32 PM PST 24 50573243 ps
T152 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3377676575 Jan 17 12:58:36 PM PST 24 Jan 17 12:58:41 PM PST 24 168713337 ps
T369 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1580735610 Jan 17 12:58:18 PM PST 24 Jan 17 12:58:21 PM PST 24 69885489 ps
T370 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3718381223 Jan 17 12:58:38 PM PST 24 Jan 17 12:58:41 PM PST 24 97158978 ps
T371 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2638958669 Jan 17 12:58:37 PM PST 24 Jan 17 12:58:40 PM PST 24 14269757 ps
T372 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1900360817 Jan 17 12:59:14 PM PST 24 Jan 17 12:59:20 PM PST 24 442912162 ps
T373 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1524013893 Jan 17 12:59:11 PM PST 24 Jan 17 12:59:16 PM PST 24 73975273 ps
T374 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.813058287 Jan 17 12:58:21 PM PST 24 Jan 17 12:58:23 PM PST 24 32113137 ps
T375 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1870971707 Jan 17 12:58:33 PM PST 24 Jan 17 12:58:38 PM PST 24 92747369 ps
T153 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3759990931 Jan 17 12:58:48 PM PST 24 Jan 17 12:58:51 PM PST 24 81419619 ps
T121 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3340451894 Jan 17 12:58:37 PM PST 24 Jan 17 12:58:43 PM PST 24 385311838 ps
T376 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2276278640 Jan 17 12:59:22 PM PST 24 Jan 17 12:59:27 PM PST 24 14290771 ps
T377 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.456496003 Jan 17 12:58:43 PM PST 24 Jan 17 12:58:51 PM PST 24 359881084 ps
T378 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.812253915 Jan 17 12:59:05 PM PST 24 Jan 17 12:59:08 PM PST 24 39345129 ps
T171 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4118229889 Jan 17 12:58:30 PM PST 24 Jan 17 12:58:32 PM PST 24 26706415 ps
T139 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2994017370 Jan 17 12:58:27 PM PST 24 Jan 17 12:58:36 PM PST 24 1234701063 ps
T118 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2796827571 Jan 17 12:58:12 PM PST 24 Jan 17 12:58:16 PM PST 24 270384916 ps
T379 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2040663536 Jan 17 12:59:24 PM PST 24 Jan 17 12:59:27 PM PST 24 16212378 ps
T154 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3776517960 Jan 17 12:58:23 PM PST 24 Jan 17 12:58:26 PM PST 24 83046055 ps
T119 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3868892625 Jan 17 12:58:44 PM PST 24 Jan 17 12:58:52 PM PST 24 979210153 ps
T157 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1950719910 Jan 17 12:58:37 PM PST 24 Jan 17 12:59:08 PM PST 24 2002447235 ps
T380 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3889923437 Jan 17 12:58:37 PM PST 24 Jan 17 12:58:41 PM PST 24 126130141 ps
T381 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3576472181 Jan 17 12:59:02 PM PST 24 Jan 17 12:59:03 PM PST 24 42597065 ps
T155 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3414030357 Jan 17 12:58:24 PM PST 24 Jan 17 12:58:53 PM PST 24 2072599336 ps
T382 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2457369499 Jan 17 12:58:36 PM PST 24 Jan 17 12:58:40 PM PST 24 74290709 ps
T140 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3105862186 Jan 17 12:58:29 PM PST 24 Jan 17 12:58:32 PM PST 24 66137012 ps
T141 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.525434735 Jan 17 12:59:09 PM PST 24 Jan 17 12:59:24 PM PST 24 563856467 ps
T156 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.644391281 Jan 17 12:58:21 PM PST 24 Jan 17 12:58:24 PM PST 24 32417469 ps
T383 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2522010164 Jan 17 12:58:27 PM PST 24 Jan 17 12:58:31 PM PST 24 52058413 ps
T384 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2584707731 Jan 17 12:58:15 PM PST 24 Jan 17 12:58:19 PM PST 24 89333776 ps
T159 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2849610998 Jan 17 12:58:28 PM PST 24 Jan 17 12:58:37 PM PST 24 74464120 ps
T385 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1766226705 Jan 17 12:58:41 PM PST 24 Jan 17 12:58:49 PM PST 24 164516028 ps
T386 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3908808777 Jan 17 12:58:14 PM PST 24 Jan 17 12:58:40 PM PST 24 4286705401 ps
T387 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4236050446 Jan 17 12:59:30 PM PST 24 Jan 17 12:59:32 PM PST 24 95410982 ps
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T432 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.449305588 Jan 17 12:59:29 PM PST 24 Jan 17 12:59:31 PM PST 24 51189431 ps
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T464 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1521813577 Jan 17 12:58:35 PM PST 24 Jan 17 12:58:41 PM PST 24 382974377 ps
T465 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3051867505 Jan 17 12:58:54 PM PST 24 Jan 17 12:59:00 PM PST 24 70814145 ps
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T467 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3788563712 Jan 17 12:58:20 PM PST 24 Jan 17 12:58:23 PM PST 24 49713612 ps
T468 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.736701552 Jan 17 12:59:08 PM PST 24 Jan 17 12:59:12 PM PST 24 144658027 ps
T469 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2780404857 Jan 17 12:58:33 PM PST 24 Jan 17 12:58:51 PM PST 24 773892986 ps
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T472 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2183276118 Jan 17 12:58:20 PM PST 24 Jan 17 12:58:31 PM PST 24 540304325 ps
T473 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2536393379 Jan 17 12:59:22 PM PST 24 Jan 17 12:59:27 PM PST 24 20321597 ps
T33 /workspace/coverage/default/17.spi_device_fifo_underflow_overflow.2584691156 Jan 17 03:31:35 PM PST 24 Jan 17 03:35:08 PM PST 24 349464543060 ps
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T35 /workspace/coverage/default/24.spi_device_dummy_item_extra_dly.30502453 Jan 17 03:32:54 PM PST 24 Jan 17 03:39:53 PM PST 24 177154025665 ps
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T62 /workspace/coverage/default/45.spi_device_tpm_all.1552682896 Jan 17 03:37:30 PM PST 24 Jan 17 03:38:02 PM PST 24 14820424523 ps
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T232 /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3759119913 Jan 17 03:31:30 PM PST 24 Jan 17 03:31:41 PM PST 24 1325180475 ps
T475 /workspace/coverage/default/33.spi_device_csb_read.3927626335 Jan 17 03:34:46 PM PST 24 Jan 17 03:34:48 PM PST 24 46952646 ps
T104 /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3398301782 Jan 17 03:30:45 PM PST 24 Jan 17 03:30:54 PM PST 24 5037922074 ps
T179 /workspace/coverage/default/2.spi_device_extreme_fifo_size.106104774 Jan 17 03:28:47 PM PST 24 Jan 17 04:12:21 PM PST 24 56389447895 ps
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T42 /workspace/coverage/default/18.spi_device_mem_parity.216050531 Jan 17 03:31:47 PM PST 24 Jan 17 03:31:49 PM PST 24 53786030 ps
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T206 /workspace/coverage/default/48.spi_device_fifo_full.510914212 Jan 17 03:37:59 PM PST 24 Jan 17 03:42:55 PM PST 24 64493328971 ps
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