Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

Group : spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	16	0	16	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_bit_order	2	0	2	100.00	100	1	1	2
cp_cpha	2	0	2	100.00	100	1	1	2
cp_cpol	2	0	2	100.00	100	1	1	2
cp_rx_order	2	0	2	100.00	100	1	1	2
rx_order	2	0	2	100.00	100	1	1	2
tx_order	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_bit_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bit_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3348148

1

T2

11802

T11

1441

T14

17659

auto[1]

3270498

1

T10

12

T11

1724

T15

12

---

Summary for Variable cp_cpha

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cpha

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3307939

1

T2

11802

T10

12

T11

3165

auto[1]

3310707

1

T32

9498

T34

6940

T35

6040

---

Summary for Variable cp_cpol

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cpol

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3404090

1

T2

5612

T11

1441

T14

9229

auto[1]

3214556

1

T2

6190

T10

12

T11

1724

---

Summary for Variable cp_rx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3156277

1

T10

12

T11

3165

T14

17659

auto[1]

3462369

1

T2

11802

T32

9498

T33

35994

---

Summary for Variable rx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3156277

1

T10

12

T11

3165

T14

17659

auto[1]

3462369

1

T2

11802

T32

9498

T33

35994

---

Summary for Variable tx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for tx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3348148

1

T2

11802

T11

1441

T14

17659

auto[1]

3270498

1

T10

12

T11

1724

T15

12

---

Summary for Cross cr_all

Samples crossed: tx_order rx_order cp_cpol cp_cpha

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

tx_order

rx_order

cp_cpol

cp_cpha

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

319238

1

T11

1441

T14

9229

T32

6470

auto[0]

auto[0]

auto[0]

auto[1]

638047

1

T34

6940

T9

12466

T60

16401

auto[0]

auto[0]

auto[1]

auto[0]

341098

1

T14

8430

T46

1

T35

2720

auto[0]

auto[0]

auto[1]

auto[1]

317918

1

T57

9383

T39

3969

T206

5565

auto[0]

auto[1]

auto[0]

auto[0]

553129

1

T2

5612

T33

21079

T59

4

auto[0]

auto[1]

auto[0]

auto[1]

415118

1

T32

9498

T45

2

T9

5983

auto[0]

auto[1]

auto[1]

auto[0]

448844

1

T2

6190

T9

11175

T39

4226

auto[0]

auto[1]

auto[1]

auto[1]

314756

1

T48

6270

T58

146

T59

2

auto[1]

auto[0]

auto[0]

auto[0]

349542

1

T9

6695

T59

2

T207

1985

auto[1]

auto[0]

auto[0]

auto[1]

282680

1

T35

6040

T9

1061

T39

1165

auto[1]

auto[0]

auto[1]

auto[0]

378826

1

T10

12

T11

1724

T15

12

auto[1]

auto[0]

auto[1]

auto[1]

528928

1

T39

1273

T48

6152

T59

1

auto[1]

auto[1]

auto[0]

auto[0]

453047

1

T34

5542

T39

3358

T59

1

auto[1]

auto[1]

auto[0]

auto[1]

393289

1

T59

6

T208

7

T209

36163

auto[1]

auto[1]

auto[1]

auto[0]

464215

1

T33

14915

T9

14579

T59

16

auto[1]

auto[1]

auto[1]

auto[1]

419971

1

T77

65

T59

5

T207

1594