Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35082	1			T12	4		T1	377		T8	431
auto[SpiFlashAddrCfg]	8197	1			T1	60		T8	66		T13	4
auto[SpiFlashAddr3b]	9570	1			T1	53		T8	79		T13	4
auto[SpiFlashAddr4b]	7914	1			T12	14		T1	60		T8	68

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34851

1

T1

186

T8

416

T36

22

auto[1]

25912

1

T12

18

T1

364

T8

228

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32775

1

T12

8

T1

230

T8

429

auto[1]

27988

1

T12

10

T1

320

T8

215

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39905	1			T12	10		T1	409		T8	473
values[1]	1197	1			T1	8		T8	8		T16	8
values[2]	1559	1			T1	8		T8	12		T9	10
values[3]	1611	1			T1	10		T8	18		T13	2
values[4]	1632	1			T1	13		T8	12		T41	4
values[5]	1522	1			T1	7		T8	14		T9	5
values[6]	1602	1			T12	4		T1	14		T8	16
values[7]	1462	1			T1	11		T8	11		T16	4
values[8]	10273	1			T12	4		T1	70		T8	80

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32611

1

T12

18

T1

550

T13

18

auto[1]

28152

1

T8

644

T41

9

T39

80

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58620

1

T12

18

T1

535

T8

624

write

2143

1

T1

15

T8

20

T16

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20644

1

T12

14

T1

140

T8

189

valids[0x1]

40119

1

T12

4

T1

410

T8

455

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1647	1			T1	8		T8	21		T36	6
internal_process_ops[0x5a]	1679	1			T1	6		T8	10		T9	6
internal_process_ops[0x05]	20831	1			T1	281		T8	259		T36	4
internal_process_ops[0x35]	1644	1			T12	2		T1	14		T8	28
internal_process_ops[0x15]	1681	1			T1	8		T8	15		T13	2
internal_process_ops[0x03]	1248	1			T1	9		T8	8		T41	5
internal_process_ops[0x0b]	1232	1			T12	2		T1	8		T8	5
internal_process_ops[0x3b]	1229	1			T1	11		T8	8		T41	4
internal_process_ops[0x6b]	1218	1			T1	7		T8	6		T13	2
internal_process_ops[0xbb]	1238	1			T12	4		T1	5		T8	7
internal_process_ops[0xeb]	1227	1			T1	10		T8	5		T13	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59788

1

T12

18

T1

543

T8

630

auto[1]

975

1

T1

7

T8

14

T17

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58663

1

T12

18

T1

532

T8

614

auto[1]

2100

1

T1

18

T8

30

T9

11

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10844

1

T1

103

T36

22

T16

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6619

1

T12

4

T1

266

T13

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2403

1

T1

22

T9

14

T21

20

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2100

1

T1

37

T13

4

T9

21

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2676

1

T1

25

T16

4

T9

24

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2375

1

T1

25

T13

4

T9

21

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2332

1

T1

28

T16

12

T9

27

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2154

1

T12

14

T1

29

T13

8

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

103

1

T1

1

T9

1

T24

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

41

1

T1

2

T9

1

T25

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

88

1

T1

3

T24

2

T26

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

69

1

T1

2

T9

3

T24

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

69

1

T193

2

T194

2

T27

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

54

1

T9

1

T26

1

T27

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

51

1

T9

1

T24

1

T26

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

81

1

T1

1

T9

1

T24

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

109

1

T1

1

T16

4

T19

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

64

1

T1

1

T25

2

T27

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

62

1

T1

1

T19

2

T24

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

64

1

T17

2

T26

1

T27

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

77

1

T1

2

T24

2

T25

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

54

1

T1

1

T24

2

T195

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

60

1

T26

1

T30

2

T196

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

62

1

T9

6

T24

1

T25

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10105

1

T8

297

T39

37

T40

42

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6972

1

T8

125

T39

6

T40

33

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1698

1

T8

29

T39

3

T40

14

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1445

1

T8

33

T39

5

T40

10

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2132

1

T8

40

T41

5

T39

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1832

1

T8

36

T39

8

T40

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1580

1

T8

36

T41

4

T39

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1353

1

T8

28

T39

12

T40

9

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

52

1

T8

2

T40

2

T47

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

61

1

T8

3

T66

1

T110

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

61

1

T47

1

T110

1

T54

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

67

1

T8

4

T127

1

T130

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

71

1

T40

3

T66

2

T110

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

74

1

T8

3

T47

2

T66

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

76

1

T8

1

T40

1

T110

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

75

1

T66

1

T110

2

T123

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

82

1

T8

2

T40

2

T110

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

55

1

T40

1

T66

1

T110

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

61

1

T8

1

T114

1

T197

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

58

1

T47

1

T54

1

T197

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

67

1

T47

4

T66

4

T123

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

48

1

T8

4

T66

2

T123

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

79

1

T40

1

T47

8

T66

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

48

1

T66

2

T197

1

T198

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4421	1			T12	6		T1	60		T16	6
auto[0]	values[0]	valids[0x1]	16036	1			T12	4		T1	349		T13	2
auto[0]	values[1]	valids[0x1]	686	1			T1	8		T16	8		T9	7
auto[0]	values[2]	valids[0x0]	561	1			T1	5		T9	8		T21	10
auto[0]	values[2]	valids[0x1]	375	1			T1	3		T9	2		T19	2
auto[0]	values[3]	valids[0x0]	599	1			T1	7		T13	2		T9	7
auto[0]	values[3]	valids[0x1]	376	1			T1	3		T9	8		T19	3
auto[0]	values[4]	valids[0x0]	607	1			T1	6		T9	7		T18	4
auto[0]	values[4]	valids[0x1]	327	1			T1	7		T9	6		T18	2
auto[0]	values[5]	valids[0x0]	579	1			T1	7		T9	5		T24	13
auto[0]	values[5]	valids[0x1]	325	1			T24	9		T25	4		T27	6
auto[0]	values[6]	valids[0x0]	581	1			T12	4		T1	10		T13	4
auto[0]	values[6]	valids[0x1]	298	1			T1	4		T9	3		T24	8
auto[0]	values[7]	valids[0x0]	511	1			T1	5		T17	8		T9	5
auto[0]	values[7]	valids[0x1]	304	1			T1	6		T16	4		T9	1
auto[0]	values[8]	valids[0x0]	3806	1			T12	4		T1	40		T13	8
auto[0]	values[8]	valids[0x1]	2219	1			T1	30		T13	2		T16	4
auto[1]	values[0]	valids[0x0]	4046	1			T8	97		T39	14		T40	36
auto[1]	values[0]	valids[0x1]	15402	1			T8	376		T39	30		T40	66
auto[1]	values[1]	valids[0x1]	511	1			T8	8		T41	5		T39	3
auto[1]	values[2]	valids[0x0]	373	1			T8	9		T40	8		T47	7
auto[1]	values[2]	valids[0x1]	250	1			T8	3		T39	1		T47	6
auto[1]	values[3]	valids[0x0]	401	1			T8	16		T40	8		T47	4
auto[1]	values[3]	valids[0x1]	235	1			T8	2		T47	4		T66	3
auto[1]	values[4]	valids[0x0]	411	1			T8	6		T41	4		T47	4
auto[1]	values[4]	valids[0x1]	287	1			T8	6		T40	7		T47	7
auto[1]	values[5]	valids[0x0]	375	1			T8	6		T40	2		T47	7
auto[1]	values[5]	valids[0x1]	243	1			T8	8		T39	2		T40	2
auto[1]	values[6]	valids[0x0]	455	1			T8	9		T39	3		T40	2
auto[1]	values[6]	valids[0x1]	268	1			T8	7		T39	1		T40	11
auto[1]	values[7]	valids[0x0]	389	1			T8	7		T39	3		T40	5
auto[1]	values[7]	valids[0x1]	258	1			T8	4		T39	2		T47	5
auto[1]	values[8]	valids[0x0]	2529	1			T8	39		T39	16		T40	15
auto[1]	values[8]	valids[0x1]	1719	1			T8	41		T39	5		T40	12