Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18745

1

T12

1

T1

123

T8

202

auto[1]

19189

1

T1

270

T8

244

T9

61

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14186

1

T12

1

T1

90

T8

144

auto[1]

23748

1

T1

303

T8

302

T36

16

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	6631	1			T12	1		T1	92		T8	20
auto[524288:1048575]	4445	1			T1	25		T8	51		T41	2
auto[1048576:1572863]	4636	1			T1	40		T8	76		T36	3
auto[1572864:2097151]	4491	1			T1	45		T8	54		T36	1
auto[2097152:2621439]	4332	1			T1	110		T8	81		T36	3
auto[2621440:3145727]	4918	1			T1	3		T8	69		T36	7
auto[3145728:3670015]	4323	1			T1	70		T8	35		T36	11
auto[3670016:4194303]	4158	1			T1	8		T8	60		T36	5

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37394

1

T12

1

T1

387

T8

418

auto[1]

540

1

T1

6

T8

28

T24

7

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19772

1

T12

1

T1

292

T8

275

auto[1]

18162

1

T1

101

T8

171

T36

19

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1308	1			T12	1		T1	10		T8	4
auto[0]	auto[0]	auto[0:524287]	auto[1]	733	1			T1	6		T8	7		T36	1
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	688	1			T1	9		T8	4		T41	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	400	1			T1	6		T8	6		T9	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	690	1			T1	5		T8	13		T39	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	385	1			T1	4		T8	5		T36	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	705	1			T1	9		T8	11		T9	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	375	1			T1	5		T8	8		T9	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	768	1			T1	13		T8	13		T36	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	399	1			T1	8		T8	11		T36	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	728	1			T8	3		T36	3		T39	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	407	1			T8	8		T40	5		T24	4
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	761	1			T1	2		T8	10		T36	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	430	1			T1	2		T8	4		T36	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	736	1			T1	2		T8	8		T9	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	398	1			T1	1		T8	4		T36	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	744	1			T1	2		T9	2		T21	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	417	1			T1	2		T9	2		T24	5
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	709	1			T8	9		T9	12		T19	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	387	1			T1	1		T8	9		T9	10
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	739	1			T1	3		T8	13		T36	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	397	1			T1	5		T8	9		T36	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	753	1			T1	4		T8	6		T9	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	417	1			T1	3		T8	4		T36	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	675	1			T1	2		T8	10		T20	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	345	1			T1	3		T8	6		T24	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	727	1			T1	3		T8	6		T36	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	422	1			T8	3		T36	2		T40	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	667	1			T1	4		T8	2		T36	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	366	1			T1	4		T8	4		T36	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	688	1			T1	4		T8	2		T36	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	381	1			T1	1		T36	3		T9	4
auto[1]	auto[0]	auto[0:524287]	auto[0]	210	1			T1	3		T8	2		T40	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	1781	1			T1	69		T8	7		T40	5
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	141	1			T1	2		T8	1		T9	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1217	1			T1	7		T8	6		T9	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	121	1			T1	2		T8	2		T47	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	892	1			T1	21		T8	22		T47	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	113	1			T1	3		T8	1		T24	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	774	1			T1	19		T8	1		T24	7
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	129	1			T1	5		T8	7		T47	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1010	1			T1	79		T8	34		T47	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	140	1			T8	2		T40	3		T24	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1210	1			T8	15		T40	5		T24	16
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	137	1			T8	2		T9	3		T19	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	930	1			T8	8		T9	10		T19	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	117	1			T8	3		T25	1		T26	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	939	1			T8	43		T25	2		T26	11
auto[1]	auto[1]	auto[0:524287]	auto[0]	147	1			T24	1		T47	4		T66	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	1291	1			T24	13		T47	11		T66	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	115	1			T8	2		T9	3		T25	4
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	788	1			T8	14		T9	20		T25	16
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	128	1			T8	3		T47	3		T25	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1284	1			T8	9		T47	6		T25	71
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	139	1			T1	1		T8	1		T24	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1215	1			T1	1		T8	22		T24	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	109	1			T24	4		T27	1		T123	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	897	1			T24	39		T27	17		T123	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	136	1			T8	3		T40	1		T24	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1148	1			T8	29		T40	1		T24	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	106	1			T1	2		T8	1		T9	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	926	1			T1	56		T8	4		T9	12
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	112	1			T9	2		T47	2		T25	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	787	1			T9	7		T47	3		T25	7

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	9829	1			T12	1		T1	80		T8	114
auto[0]	auto[0]	auto[1]	82	1			T1	2		T8	5		T25	1
auto[0]	auto[1]	auto[0]	8758	1			T1	41		T8	81		T36	19
auto[0]	auto[1]	auto[1]	76	1			T8	2		T24	2		T26	5
auto[1]	auto[0]	auto[0]	9673	1			T1	208		T8	143		T9	15
auto[1]	auto[0]	auto[1]	188	1			T1	2		T8	13		T24	1
auto[1]	auto[1]	auto[0]	9134	1			T1	58		T8	80		T9	46
auto[1]	auto[1]	auto[1]	194	1			T1	2		T8	8		T24	4