Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.50	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50

Variables for Group spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_rx_size	8	1	7	87.50	100	1	1	0

Summary for Variable cp_rx_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	1	7	87.50

User Defined Bins for cp_rx_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
specific_sizes[4092]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
specific_sizes[4]	52960	1			T9	2410		T179	2259		T122	3
specific_sizes[2048]	2	1			T180	1		T181	1		-	-
sizes[0]	74148	1			T10	3		T15	3		T34	2
sizes[1]	5377	1			T48	22		T49	290		T182	2
sizes[2]	2211	1			T9	225		T183	86		T55	133
sizes[3]	366	1			T33	37		T184	112		T185	48
sizes[4]	128	1			T186	52		T187	19		T188	25