Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18826

1

T1

186

T36

22

T16

28

auto[1]

13785

1

T12

18

T1

364

T13

18

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4203	1			T1	219		T9	43		T24	34
values[1]	4469	1			T1	120		T24	80		T232	30
values[2]	4275	1			T1	41		T16	28		T9	60
values[3]	4323	1			T9	110		T273	12		T22	4
values[4]	3690	1			T1	42		T36	22		T9	20
values[5]	3895	1			T12	18		T1	42		T13	18
values[6]	3380	1			T1	22		T17	20		T9	26
values[7]	4376	1			T1	64		T9	22		T24	44

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4031	1			T9	44		T21	24		T24	71
values[1]	4731	1			T1	64		T13	18		T9	22
values[2]	5075	1			T1	98		T9	72		T20	22
values[3]	3352	1			T1	41		T9	40		T19	20
values[4]	3950	1			T1	86		T36	22		T17	20
values[5]	3848	1			T1	22		T9	26		T23	14
values[6]	4133	1			T1	170		T9	74		T22	4
values[7]	3491	1			T12	18		T1	69		T16	28

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	386	1			T24	25		T30	13		T216	18
auto[0]	values[0]	values[1]	307	1			T30	9		T215	33		T242	16
auto[0]	values[0]	values[2]	184	1			T25	8		T29	11		T222	4
auto[0]	values[0]	values[3]	221	1			T9	9		T222	28		T274	9
auto[0]	values[0]	values[4]	242	1			T1	18		T9	13		T219	14
auto[0]	values[0]	values[5]	525	1			T25	14		T196	13		T218	36
auto[0]	values[0]	values[6]	271	1			T1	9		T25	23		T27	46
auto[0]	values[0]	values[7]	178	1			T1	17		T25	9		T27	14
auto[0]	values[1]	values[0]	247	1			T27	19		T275	14		T276	6
auto[0]	values[1]	values[1]	239	1			T25	9		T30	19		T219	23
auto[0]	values[1]	values[2]	484	1			T1	20		T24	6		T193	4
auto[0]	values[1]	values[3]	185	1			T277	20		T223	14		T30	34
auto[0]	values[1]	values[4]	343	1			T232	30		T27	7		T216	30
auto[0]	values[1]	values[5]	157	1			T1	10		T24	13		T278	14
auto[0]	values[1]	values[6]	554	1			T24	11		T26	99		T215	13
auto[0]	values[1]	values[7]	212	1			T24	11		T248	24		T222	10
auto[0]	values[2]	values[0]	184	1			T21	24		T242	9		T279	28
auto[0]	values[2]	values[1]	395	1			T24	9		T252	11		T276	19
auto[0]	values[2]	values[2]	400	1			T9	15		T20	22		T24	12
auto[0]	values[2]	values[3]	411	1			T1	33		T9	12		T25	9
auto[0]	values[2]	values[4]	280	1			T19	13		T24	17		T249	14
auto[0]	values[2]	values[5]	337	1			T26	11		T29	12		T258	13
auto[0]	values[2]	values[6]	322	1			T25	34		T215	76		T196	28
auto[0]	values[2]	values[7]	256	1			T16	28		T25	17		T280	10
auto[0]	values[3]	values[0]	408	1			T9	35		T24	26		T27	99
auto[0]	values[3]	values[1]	352	1			T280	8		T281	9		T282	22
auto[0]	values[3]	values[2]	565	1			T9	12		T25	12		T26	12
auto[0]	values[3]	values[3]	198	1			T242	6		T105	12		T274	12
auto[0]	values[3]	values[4]	263	1			T273	12		T25	9		T27	43
auto[0]	values[3]	values[5]	194	1			T242	11		T283	32		T284	6
auto[0]	values[3]	values[6]	267	1			T9	26		T22	4		T26	81
auto[0]	values[3]	values[7]	306	1			T27	7		T196	16		T222	18
auto[0]	values[4]	values[0]	202	1			T258	14		T215	11		T285	18
auto[0]	values[4]	values[1]	289	1			T24	29		T25	12		T225	10
auto[0]	values[4]	values[2]	413	1			T27	14		T226	67		T219	9
auto[0]	values[4]	values[3]	170	1			T286	11		T105	15		T274	13
auto[0]	values[4]	values[4]	381	1			T1	12		T36	22		T287	2
auto[0]	values[4]	values[5]	163	1			T255	14		T288	8		T276	13
auto[0]	values[4]	values[6]	194	1			T9	4		T24	18		T219	26
auto[0]	values[4]	values[7]	266	1			T1	9		T195	8		T105	12
auto[0]	values[5]	values[0]	232	1			T29	11		T219	12		T253	22
auto[0]	values[5]	values[1]	246	1			T1	10		T29	10		T30	25
auto[0]	values[5]	values[2]	416	1			T18	33		T19	16		T25	11
auto[0]	values[5]	values[3]	163	1			T24	10		T26	12		T27	9
auto[0]	values[5]	values[4]	280	1			T25	13		T26	11		T30	7
auto[0]	values[5]	values[5]	143	1			T30	17		T255	7		T228	13
auto[0]	values[5]	values[6]	347	1			T9	5		T25	20		T26	13
auto[0]	values[5]	values[7]	205	1			T1	13		T19	11		T24	11
auto[0]	values[6]	values[0]	289	1			T224	66		T286	9		T227	13
auto[0]	values[6]	values[1]	373	1			T219	11		T229	13		T281	15
auto[0]	values[6]	values[2]	264	1			T27	4		T29	28		T216	17
auto[0]	values[6]	values[3]	279	1			T19	9		T289	10		T213	23
auto[0]	values[6]	values[4]	182	1			T1	19		T30	24		T242	16
auto[0]	values[6]	values[5]	294	1			T9	13		T23	14		T24	75
auto[0]	values[6]	values[6]	191	1			T24	11		T241	30		T30	32
auto[0]	values[6]	values[7]	231	1			T24	10		T27	10		T290	6
auto[0]	values[7]	values[0]	399	1			T26	11		T27	10		T235	16
auto[0]	values[7]	values[1]	476	1			T1	9		T9	12		T24	10
auto[0]	values[7]	values[2]	352	1			T25	76		T219	8		T280	13
auto[0]	values[7]	values[3]	238	1			T27	58		T29	10		T258	11
auto[0]	values[7]	values[4]	193	1			T1	7		T24	15		T25	13
auto[0]	values[7]	values[5]	567	1			T30	17		T219	6		T216	15
auto[0]	values[7]	values[6]	368	1			T27	19		T219	11		T291	14
auto[0]	values[7]	values[7]	147	1			T25	13		T233	10		T27	23
auto[1]	values[0]	values[0]	220	1			T24	9		T30	7		T216	5
auto[1]	values[0]	values[1]	349	1			T30	35		T215	73		T292	16
auto[1]	values[0]	values[2]	209	1			T25	12		T29	9		T222	33
auto[1]	values[0]	values[3]	247	1			T9	11		T222	4		T293	28
auto[1]	values[0]	values[4]	223	1			T1	4		T9	10		T219	10
auto[1]	values[0]	values[5]	252	1			T25	6		T196	13		T229	31
auto[1]	values[0]	values[6]	297	1			T1	161		T25	7		T294	8
auto[1]	values[0]	values[7]	92	1			T1	10		T25	11		T27	6
auto[1]	values[1]	values[0]	180	1			T27	11		T275	15		T276	14
auto[1]	values[1]	values[1]	265	1			T25	86		T30	10		T219	9
auto[1]	values[1]	values[2]	379	1			T1	78		T24	14		T25	9
auto[1]	values[1]	values[3]	78	1			T30	8		T295	12		T296	8
auto[1]	values[1]	values[4]	241	1			T27	24		T216	10		T297	9
auto[1]	values[1]	values[5]	257	1			T1	12		T24	7		T222	9
auto[1]	values[1]	values[6]	231	1			T24	9		T26	10		T215	14
auto[1]	values[1]	values[7]	417	1			T24	9		T28	28		T222	54
auto[1]	values[2]	values[0]	119	1			T298	4		T242	11		T276	9
auto[1]	values[2]	values[1]	264	1			T24	16		T252	9		T276	8
auto[1]	values[2]	values[2]	267	1			T9	25		T24	8		T25	13
auto[1]	values[2]	values[3]	247	1			T1	8		T9	8		T25	11
auto[1]	values[2]	values[4]	267	1			T19	7		T24	10		T30	34
auto[1]	values[2]	values[5]	182	1			T26	9		T29	8		T258	7
auto[1]	values[2]	values[6]	226	1			T25	11		T215	13		T196	18
auto[1]	values[2]	values[7]	118	1			T25	9		T280	10		T105	6
auto[1]	values[3]	values[0]	339	1			T9	9		T24	11		T27	8
auto[1]	values[3]	values[1]	239	1			T280	12		T281	11		T252	32
auto[1]	values[3]	values[2]	169	1			T9	20		T25	8		T26	8
auto[1]	values[3]	values[3]	190	1			T242	14		T105	14		T274	8
auto[1]	values[3]	values[4]	294	1			T25	11		T27	12		T30	42
auto[1]	values[3]	values[5]	111	1			T242	29		T299	16		T300	8
auto[1]	values[3]	values[6]	219	1			T9	8		T26	8		T213	20
auto[1]	values[3]	values[7]	209	1			T27	27		T301	14		T196	7
auto[1]	values[4]	values[0]	141	1			T258	8		T215	9		T222	18
auto[1]	values[4]	values[1]	236	1			T24	18		T25	13		T225	10
auto[1]	values[4]	values[2]	245	1			T27	6		T219	11		T258	15
auto[1]	values[4]	values[3]	136	1			T286	9		T105	5		T274	7
auto[1]	values[4]	values[4]	274	1			T1	8		T239	16		T215	9
auto[1]	values[4]	values[5]	57	1			T255	6		T276	9		T296	6
auto[1]	values[4]	values[6]	174	1			T9	16		T24	2		T219	18
auto[1]	values[4]	values[7]	349	1			T1	13		T195	34		T105	8
auto[1]	values[5]	values[0]	263	1			T29	76		T219	10		T196	6
auto[1]	values[5]	values[1]	175	1			T1	12		T13	18		T29	10
auto[1]	values[5]	values[2]	327	1			T19	4		T25	9		T27	11
auto[1]	values[5]	values[3]	283	1			T24	10		T26	15		T27	17
auto[1]	values[5]	values[4]	167	1			T25	7		T26	9		T30	32
auto[1]	values[5]	values[5]	136	1			T30	5		T255	15		T228	7
auto[1]	values[5]	values[6]	254	1			T9	15		T25	4		T26	43
auto[1]	values[5]	values[7]	258	1			T12	18		T1	7		T19	13
auto[1]	values[6]	values[0]	254	1			T286	11		T227	7		T238	44
auto[1]	values[6]	values[1]	220	1			T219	9		T229	7		T281	41
auto[1]	values[6]	values[2]	171	1			T27	16		T29	12		T216	3
auto[1]	values[6]	values[3]	148	1			T19	11		T213	5		T302	3
auto[1]	values[6]	values[4]	148	1			T1	3		T17	20		T30	16
auto[1]	values[6]	values[5]	159	1			T9	13		T24	14		T30	14
auto[1]	values[6]	values[6]	68	1			T24	9		T30	8		T219	6
auto[1]	values[6]	values[7]	109	1			T24	10		T27	10		T196	10
auto[1]	values[7]	values[0]	168	1			T26	25		T27	10		T29	6
auto[1]	values[7]	values[1]	306	1			T1	33		T9	10		T24	10
auto[1]	values[7]	values[2]	230	1			T25	35		T219	12		T280	11
auto[1]	values[7]	values[3]	158	1			T27	13		T29	10		T258	11
auto[1]	values[7]	values[4]	172	1			T1	15		T24	9		T25	7
auto[1]	values[7]	values[5]	314	1			T30	23		T219	14		T216	5
auto[1]	values[7]	values[6]	150	1			T27	7		T219	9		T196	8
auto[1]	values[7]	values[7]	138	1			T25	7		T27	70		T280	12