Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	12	0	12	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6666855	1			T4	135		T6	1138		T12	1
all_pins[1]	6666855	1			T4	135		T6	1138		T12	1
all_pins[2]	6666855	1			T4	135		T6	1138		T12	1
all_pins[3]	6666855	1			T4	135		T6	1138		T12	1
all_pins[4]	6666855	1			T4	135		T6	1138		T12	1
all_pins[5]	6666855	1			T4	135		T6	1138		T12	1
all_pins[6]	6666855	1			T4	135		T6	1138		T12	1
all_pins[7]	6666855	1			T4	135		T6	1138		T12	1
all_pins[8]	6666855	1			T4	135		T6	1138		T12	1
all_pins[9]	6666855	1			T4	135		T6	1138		T12	1
all_pins[10]	6666855	1			T4	135		T6	1138		T12	1
all_pins[11]	6666855	1			T4	135		T6	1138		T12	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	79907473	1			T4	1620		T6	13656		T12	12
values[0x1]	94787	1			T2	1		T11	2		T14	1
transitions[0x0=>0x1]	93680	1			T2	1		T11	1		T14	1
transitions[0x1=>0x0]	93688	1			T2	1		T11	1		T14	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	6666315	1			T4	135		T6	1138		T12	1
all_pins[0]	values[0x1]	540	1			T15	1		T68	5		T70	2
all_pins[0]	transitions[0x0=>0x1]	339	1			T15	1		T68	5		T70	1
all_pins[0]	transitions[0x1=>0x0]	85176	1			T11	1		T46	1		T32	1
all_pins[1]	values[0x0]	6581478	1			T4	135		T6	1138		T12	1
all_pins[1]	values[0x1]	85377	1			T11	1		T46	1		T32	1
all_pins[1]	transitions[0x0=>0x1]	85268	1			T68	1		T70	4		T190	2
all_pins[1]	transitions[0x1=>0x0]	495	1			T2	1		T14	1		T69	2
all_pins[2]	values[0x0]	6666251	1			T4	135		T6	1138		T12	1
all_pins[2]	values[0x1]	604	1			T2	1		T11	1		T14	1
all_pins[2]	transitions[0x0=>0x1]	571	1			T2	1		T11	1		T14	1
all_pins[2]	transitions[0x1=>0x0]	79	1			T68	3		T69	1		T70	1
all_pins[3]	values[0x0]	6666743	1			T4	135		T6	1138		T12	1
all_pins[3]	values[0x1]	112	1			T68	3		T69	1		T70	1
all_pins[3]	transitions[0x0=>0x1]	86	1			T68	1		T70	1		T190	2
all_pins[3]	transitions[0x1=>0x0]	451	1			T69	2		T70	2		T190	2
all_pins[4]	values[0x0]	6666378	1			T4	135		T6	1138		T12	1
all_pins[4]	values[0x1]	477	1			T68	2		T69	3		T70	2
all_pins[4]	transitions[0x0=>0x1]	238	1			T69	3		T70	1		T134	5
all_pins[4]	transitions[0x1=>0x0]	1966	1			T68	2		T69	3		T190	2
all_pins[5]	values[0x0]	6664650	1			T4	135		T6	1138		T12	1
all_pins[5]	values[0x1]	2205	1			T68	4		T69	3		T70	1
all_pins[5]	transitions[0x0=>0x1]	2172	1			T68	3		T69	2		T70	1
all_pins[5]	transitions[0x1=>0x0]	783	1			T69	1		T70	2		T134	3
all_pins[6]	values[0x0]	6666039	1			T4	135		T6	1138		T12	1
all_pins[6]	values[0x1]	816	1			T68	1		T69	2		T70	2
all_pins[6]	transitions[0x0=>0x1]	524	1			T68	1		T69	2		T70	2
all_pins[6]	transitions[0x1=>0x0]	94	1			T68	4		T69	1		T70	1
all_pins[7]	values[0x0]	6666469	1			T4	135		T6	1138		T12	1
all_pins[7]	values[0x1]	386	1			T68	4		T69	1		T70	1
all_pins[7]	transitions[0x0=>0x1]	328	1			T68	3		T69	1		T70	1
all_pins[7]	transitions[0x1=>0x0]	183	1			T69	1		T70	4		T189	2
all_pins[8]	values[0x0]	6666614	1			T4	135		T6	1138		T12	1
all_pins[8]	values[0x1]	241	1			T68	1		T69	1		T70	4
all_pins[8]	transitions[0x0=>0x1]	207	1			T68	1		T69	1		T70	2
all_pins[8]	transitions[0x1=>0x0]	80	1			T69	4		T190	3		T192	3
all_pins[9]	values[0x0]	6666741	1			T4	135		T6	1138		T12	1
all_pins[9]	values[0x1]	114	1			T69	4		T70	2		T190	3
all_pins[9]	transitions[0x0=>0x1]	87	1			T69	4		T70	2		T190	2
all_pins[9]	transitions[0x1=>0x0]	70	1			T68	2		T69	1		T70	3
all_pins[10]	values[0x0]	6666758	1			T4	135		T6	1138		T12	1
all_pins[10]	values[0x1]	97	1			T68	2		T69	1		T70	3
all_pins[10]	transitions[0x0=>0x1]	71	1			T68	2		T69	1		T70	1
all_pins[10]	transitions[0x1=>0x0]	3792	1			T68	1		T69	2		T190	1
all_pins[11]	values[0x0]	6663037	1			T4	135		T6	1138		T12	1
all_pins[11]	values[0x1]	3818	1			T68	1		T69	2		T70	2
all_pins[11]	transitions[0x0=>0x1]	3789	1			T69	1		T70	1		T190	1
all_pins[11]	transitions[0x1=>0x0]	519	1			T15	1		T68	5		T70	1