Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	501	1			T1	1		T9	2		T21	8
auto[ReadAddrCrossIntoMailbox]	353	1			T9	2		T21	4		T19	4
auto[ReadAddrCrossOutOfMailbox]	344	1			T1	1		T9	3		T21	4
auto[ReadAddrCrossAllMailbox]	261	1			T1	1		T9	1		T21	6
auto[ReadAddrOutsideMailbox]	3929	1			T12	6		T1	47		T13	10

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2673

1

T12

3

T1

25

T13

5

auto[1]

2715

1

T12

3

T1

25

T13

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	896	1			T1	9		T9	9		T21	8
read_ops[0x0b]	947	1			T12	2		T1	8		T9	10
read_ops[0x3b]	909	1			T1	11		T17	8		T9	7
read_ops[0x6b]	894	1			T1	7		T13	2		T9	12
read_ops[0xbb]	932	1			T12	4		T1	5		T13	4
read_ops[0xeb]	810	1			T1	10		T13	4		T9	11

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T21	2		T25	1		T26	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T21	2		T258	1		T303	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T9	1		T21	1		T19	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T21	1		T19	1		T24	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T21	1		T25	1		T26	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T21	1		T19	1		T24	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T1	1		T25	1		T26	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T9	1		T30	3		T219	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	325	1			T1	6		T9	6		T18	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	340	1			T1	2		T9	1		T18	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	47	1			T21	1		T19	2		T25	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T1	1		T9	1		T21	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	37	1			T24	1		T25	1		T26	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T235	1		T258	1		T304	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T19	1		T27	1		T235	3
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T24	1		T25	1		T235	3
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T25	1		T30	2		T195	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T25	1		T219	1		T225	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	354	1			T12	1		T1	1		T9	4
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	330	1			T12	1		T1	6		T9	5
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T22	1		T241	1		T25	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T22	1		T241	1		T196	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T21	1		T241	1		T27	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	42	1			T21	1		T19	1		T241	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T1	1		T21	1		T241	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T21	1		T241	1		T27	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T21	2		T30	1		T305	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T21	2		T27	2		T29	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	332	1			T1	4		T17	4		T9	4
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	312	1			T1	6		T17	4		T9	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T19	1		T29	1		T30	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T19	1		T216	1		T196	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T19	1		T258	2		T216	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T9	1		T24	1		T219	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T9	1		T27	1		T225	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T24	2		T27	1		T30	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T19	1		T24	1		T306	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T306	1		T280	2		T248	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	330	1			T1	3		T13	1		T9	6
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	341	1			T1	4		T13	1		T9	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	50	1			T21	1		T24	2		T241	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	59	1			T9	1		T21	1		T24	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T24	2		T241	1		T25	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T241	1		T26	1		T29	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T29	1		T216	1		T280	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T216	1		T225	1		T248	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T21	1		T29	1		T30	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T21	1		T25	1		T29	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	345	1			T12	2		T1	4		T13	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	328	1			T12	2		T1	1		T13	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T23	1		T24	2		T27	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T23	1		T26	1		T27	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T27	2		T30	2		T216	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T24	4		T27	1		T30	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T27	1		T30	1		T216	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T9	2		T19	1		T259	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T27	1		T29	1		T259	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T19	1		T27	1		T259	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	288	1			T1	5		T13	2		T9	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	304	1			T1	5		T13	2		T9	8