Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3816	1			T12	18		T1	44		T9	20
values[1]	3566	1			T1	41		T9	44		T20	22
values[2]	4029	1			T1	147		T9	26		T273	12
values[3]	4244	1			T1	22		T17	20		T9	20
values[4]	4617	1			T36	22		T9	22		T18	33
values[5]	4246	1			T1	84		T9	92		T19	20
values[6]	3834	1			T1	42		T13	18		T16	28
values[7]	4259	1			T1	170		T9	77		T21	24

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4432	1			T1	20		T9	83		T24	76
values[1]	4569	1			T1	22		T9	40		T24	80
values[2]	3720	1			T12	18		T20	22		T19	20
values[3]	3444	1			T1	27		T17	20		T9	22
values[4]	4356	1			T1	41		T13	18		T16	28
values[5]	3646	1			T1	42		T21	24		T22	4
values[6]	4126	1			T1	278		T36	22		T9	24
values[7]	4318	1			T1	120		T9	72		T25	65

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32122

1

T12

18

T1

543

T13

18

auto[1]

489

1

T1

7

T17

2

T9

12

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	467	1			T307	6		T222	34		T242	49
auto[0]	values[0]	values[1]	654	1			T24	18		T229	65		T308	10
auto[0]	values[0]	values[2]	527	1			T12	18		T232	30		T213	28
auto[0]	values[0]	values[3]	489	1			T27	66		T219	24		T309	6
auto[0]	values[0]	values[4]	350	1			T9	19		T25	20		T258	26
auto[0]	values[0]	values[5]	458	1			T24	20		T287	2		T29	75
auto[0]	values[0]	values[6]	501	1			T1	44		T30	40		T225	20
auto[0]	values[0]	values[7]	307	1			T222	30		T105	19		T310	12
auto[0]	values[1]	values[0]	524	1			T24	25		T25	20		T30	20
auto[0]	values[1]	values[1]	564	1			T223	14		T311	32		T306	2
auto[0]	values[1]	values[2]	367	1			T20	22		T25	40		T27	28
auto[0]	values[1]	values[3]	310	1			T19	24		T213	34		T217	12
auto[0]	values[1]	values[4]	487	1			T1	41		T26	26		T30	20
auto[0]	values[1]	values[5]	506	1			T24	20		T29	20		T305	6
auto[0]	values[1]	values[6]	391	1			T9	23		T301	14		T312	8
auto[0]	values[1]	values[7]	349	1			T9	20		T274	20		T255	20
auto[0]	values[2]	values[0]	624	1			T1	18		T9	25		T193	4
auto[0]	values[2]	values[1]	350	1			T1	21		T24	20		T30	20
auto[0]	values[2]	values[2]	568	1			T24	61		T25	75		T249	14
auto[0]	values[2]	values[3]	417	1			T1	27		T19	20		T222	20
auto[0]	values[2]	values[4]	420	1			T273	12		T29	106		T30	44
auto[0]	values[2]	values[5]	423	1			T24	20		T229	20		T281	55
auto[0]	values[2]	values[6]	466	1			T19	20		T26	20		T27	34
auto[0]	values[2]	values[7]	704	1			T1	75		T25	20		T196	25
auto[0]	values[3]	values[0]	543	1			T30	35		T215	20		T280	20
auto[0]	values[3]	values[1]	621	1			T9	18		T24	20		T25	25
auto[0]	values[3]	values[2]	627	1			T24	20		T25	19		T290	6
auto[0]	values[3]	values[3]	366	1			T17	18		T25	19		T219	20
auto[0]	values[3]	values[4]	415	1			T26	36		T220	16		T216	34
auto[0]	values[3]	values[5]	447	1			T22	4		T219	20		T225	20
auto[0]	values[3]	values[6]	484	1			T1	22		T241	30		T25	30
auto[0]	values[3]	values[7]	683	1			T25	20		T27	74		T30	28
auto[0]	values[4]	values[0]	773	1			T24	25		T27	20		T225	20
auto[0]	values[4]	values[1]	333	1			T24	20		T216	23		T242	20
auto[0]	values[4]	values[2]	572	1			T24	28		T289	10		T219	40
auto[0]	values[4]	values[3]	665	1			T9	19		T219	22		T215	74
auto[0]	values[4]	values[4]	545	1			T30	20		T222	32		T252	20
auto[0]	values[4]	values[5]	553	1			T18	33		T303	14		T228	20
auto[0]	values[4]	values[6]	385	1			T36	22		T27	29		T258	22
auto[0]	values[4]	values[7]	725	1			T294	8		T27	71		T258	22
auto[0]	values[5]	values[0]	565	1			T24	24		T239	16		T27	31
auto[0]	values[5]	values[1]	653	1			T26	55		T27	20		T30	22
auto[0]	values[5]	values[2]	550	1			T19	20		T27	106		T235	16
auto[0]	values[5]	values[3]	400	1			T24	20		T258	25		T195	40
auto[0]	values[5]	values[4]	590	1			T9	39		T27	20		T313	4
auto[0]	values[5]	values[5]	342	1			T24	57		T292	16		T314	14
auto[0]	values[5]	values[6]	626	1			T1	41		T25	20		T277	20
auto[0]	values[5]	values[7]	433	1			T1	42		T9	52		T25	24
auto[0]	values[6]	values[0]	375	1			T25	20		T196	19		T227	20
auto[0]	values[6]	values[1]	517	1			T25	34		T28	26		T216	20
auto[0]	values[6]	values[2]	271	1			T24	46		T26	20		T30	81
auto[0]	values[6]	values[3]	347	1			T315	36		T276	39		T316	18
auto[0]	values[6]	values[4]	963	1			T13	18		T16	28		T23	14
auto[0]	values[6]	values[5]	364	1			T1	42		T24	20		T25	20
auto[0]	values[6]	values[6]	438	1			T27	20		T215	25		T304	16
auto[0]	values[6]	values[7]	514	1			T216	22		T215	20		T196	20
auto[0]	values[7]	values[0]	493	1			T9	54		T25	44		T29	20
auto[0]	values[7]	values[1]	806	1			T9	20		T26	104		T219	20
auto[0]	values[7]	values[2]	190	1			T25	20		T29	20		T317	53
auto[0]	values[7]	values[3]	368	1			T24	32		T27	20		T215	53
auto[0]	values[7]	values[4]	507	1			T27	52		T216	47		T196	47
auto[0]	values[7]	values[5]	516	1			T21	24		T233	10		T30	33
auto[0]	values[7]	values[6]	774	1			T1	170		T25	94		T26	89
auto[0]	values[7]	values[7]	560	1			T224	66		T227	20		T210	23
auto[1]	values[0]	values[0]	9	1			T242	3		T229	1		T228	1
auto[1]	values[0]	values[1]	13	1			T24	2		T318	2		T319	5
auto[1]	values[0]	values[2]	7	1			T229	1		T238	2		T302	3
auto[1]	values[0]	values[3]	10	1			T27	5		T320	1		T318	1
auto[1]	values[0]	values[4]	4	1			T9	1		T258	2		T225	1
auto[1]	values[0]	values[5]	7	1			T29	1		T234	1		T302	2
auto[1]	values[0]	values[6]	10	1			T255	2		T234	2		T231	1
auto[1]	values[0]	values[7]	3	1			T105	1		T276	2		-	-
auto[1]	values[1]	values[0]	8	1			T234	4		T318	2		T319	1
auto[1]	values[1]	values[1]	13	1			T276	7		T100	2		T321	2
auto[1]	values[1]	values[2]	6	1			T27	2		T30	2		T299	2
auto[1]	values[1]	values[3]	18	1			T213	2		T242	3		T212	2
auto[1]	values[1]	values[4]	9	1			T26	1		T242	4		T320	1
auto[1]	values[1]	values[5]	2	1			T105	1		T297	1		-	-
auto[1]	values[1]	values[6]	10	1			T9	1		T312	4		T322	4
auto[1]	values[1]	values[7]	2	1			T227	1		T323	1		-	-
auto[1]	values[2]	values[0]	12	1			T1	2		T9	1		T30	1
auto[1]	values[2]	values[1]	10	1			T1	1		T324	1		T325	1
auto[1]	values[2]	values[2]	3	1			T25	2		T326	1		-	-
auto[1]	values[2]	values[3]	6	1			T275	1		T327	4		T328	1
auto[1]	values[2]	values[4]	9	1			T29	1		T323	2		T329	2
auto[1]	values[2]	values[5]	6	1			T281	1		T210	3		T330	2
auto[1]	values[2]	values[6]	4	1			T222	1		T227	1		T276	1
auto[1]	values[2]	values[7]	7	1			T1	3		T196	1		T331	1
auto[1]	values[3]	values[0]	9	1			T30	1		T222	2		T105	1
auto[1]	values[3]	values[1]	10	1			T9	2		T25	1		T258	4
auto[1]	values[3]	values[2]	8	1			T25	1		T332	2		T325	2
auto[1]	values[3]	values[3]	8	1			T17	2		T25	1		T318	2
auto[1]	values[3]	values[4]	9	1			T216	2		T242	1		T333	2
auto[1]	values[3]	values[5]	4	1			T334	2		T325	2		-	-
auto[1]	values[3]	values[6]	3	1			T229	2		T318	1		-	-
auto[1]	values[3]	values[7]	7	1			T27	1		T30	1		T255	1
auto[1]	values[4]	values[0]	5	1			T24	2		T274	1		T317	1
auto[1]	values[4]	values[1]	2	1			T335	1		T332	1		-	-
auto[1]	values[4]	values[2]	6	1			T295	1		T238	2		T300	1
auto[1]	values[4]	values[3]	19	1			T9	3		T219	2		T222	1
auto[1]	values[4]	values[4]	11	1			T276	1		T302	2		T326	2
auto[1]	values[4]	values[5]	8	1			T317	1		T336	2		T330	1
auto[1]	values[4]	values[6]	13	1			T27	3		T321	1		T337	4
auto[1]	values[4]	values[7]	2	1			T320	2		-	-		-	-
auto[1]	values[5]	values[0]	16	1			T30	3		T338	2		T238	4
auto[1]	values[5]	values[1]	9	1			T26	1		T195	1		T196	1
auto[1]	values[5]	values[2]	8	1			T27	1		T219	1		T296	1
auto[1]	values[5]	values[3]	11	1			T195	2		T216	1		T339	3
auto[1]	values[5]	values[4]	19	1			T9	1		T280	1		T340	4
auto[1]	values[5]	values[5]	3	1			T339	3		-	-		-	-
auto[1]	values[5]	values[6]	10	1			T1	1		T213	1		T238	1
auto[1]	values[5]	values[7]	11	1			T25	1		T30	2		T222	1
auto[1]	values[6]	values[0]	3	1			T196	1		T323	2		-	-
auto[1]	values[6]	values[1]	4	1			T28	2		T341	1		T342	1
auto[1]	values[6]	values[2]	7	1			T24	1		T320	1		T343	2
auto[1]	values[6]	values[3]	4	1			T344	1		T323	2		T345	1
auto[1]	values[6]	values[4]	13	1			T27	1		T302	2		T346	6
auto[1]	values[6]	values[5]	1	1			T30	1		-	-		-	-
auto[1]	values[6]	values[6]	5	1			T215	2		T329	2		T325	1
auto[1]	values[6]	values[7]	8	1			T331	2		T335	2		T329	1
auto[1]	values[7]	values[0]	6	1			T9	3		T25	1		T329	1
auto[1]	values[7]	values[1]	10	1			T26	5		T238	2		T347	2
auto[1]	values[7]	values[2]	3	1			T327	2		T323	1		-	-
auto[1]	values[7]	values[3]	6	1			T24	2		T215	2		T210	1
auto[1]	values[7]	values[4]	5	1			T216	1		T196	1		T234	1
auto[1]	values[7]	values[5]	6	1			T219	1		T339	1		T348	2
auto[1]	values[7]	values[6]	6	1			T25	1		T349	1		T342	2
auto[1]	values[7]	values[7]	3	1			T327	1		T350	1		T351	1