Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2516

1

T1

6

T31

8

T103

6

auto[1]

2604

1

T1

2

T8

3

T31

6

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2490

1

T1

8

T8

3

T31

14

auto[1]

2630

1

T103

12

T9

4

T39

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4181

1

T1

6

T8

3

T31

8

auto[1]

939

1

T1

2

T31

6

T9

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	990	1			T1	4		T31	3		T103	2
valid[1]	1043	1			T1	1		T31	3		T103	2
valid[2]	1000	1			T1	2		T8	1		T31	1
valid[3]	1046	1			T1	1		T8	1		T31	1
valid[4]	1041	1			T8	1		T31	6		T103	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	149	1			T1	2		T31	2		T39	2
auto[0]	auto[0]	valid[0]	auto[1]	229	1			T103	1		T9	1		T61	2
auto[0]	auto[0]	valid[1]	auto[0]	151	1			T9	1		T39	2		T40	1
auto[0]	auto[0]	valid[1]	auto[1]	274	1			T103	1		T39	1		T61	1
auto[0]	auto[0]	valid[2]	auto[0]	160	1			T1	2		T39	4		T62	1
auto[0]	auto[0]	valid[2]	auto[1]	243	1			T103	2		T9	1		T61	3
auto[0]	auto[0]	valid[3]	auto[0]	164	1			T1	1		T9	2		T39	5
auto[0]	auto[0]	valid[3]	auto[1]	267	1			T103	1		T9	1		T61	2
auto[0]	auto[0]	valid[4]	auto[0]	158	1			T31	3		T9	1		T39	2
auto[0]	auto[0]	valid[4]	auto[1]	265	1			T103	1		T61	2		T104	5
auto[0]	auto[1]	valid[0]	auto[0]	155	1			T1	1		T31	1		T39	1
auto[0]	auto[1]	valid[0]	auto[1]	265	1			T103	1		T61	2		T47	2
auto[0]	auto[1]	valid[1]	auto[0]	155	1			T39	3		T19	1		T360	1
auto[0]	auto[1]	valid[1]	auto[1]	275	1			T103	1		T9	1		T39	1
auto[0]	auto[1]	valid[2]	auto[0]	148	1			T8	1		T39	2		T62	1
auto[0]	auto[1]	valid[2]	auto[1]	280	1			T103	4		T61	2		T104	6
auto[0]	auto[1]	valid[3]	auto[0]	157	1			T8	1		T31	1		T9	1
auto[0]	auto[1]	valid[3]	auto[1]	274	1			T61	1		T104	5		T108	1
auto[0]	auto[1]	valid[4]	auto[0]	154	1			T8	1		T31	1		T40	2
auto[0]	auto[1]	valid[4]	auto[1]	258	1			T61	3		T47	1		T104	6
auto[1]	auto[0]	valid[0]	auto[0]	91	1			T1	1		T9	2		T39	1
auto[1]	auto[0]	valid[1]	auto[0]	97	1			T31	1		T9	1		T39	4
auto[1]	auto[0]	valid[2]	auto[0]	81	1			T31	1		T39	3		T24	1
auto[1]	auto[0]	valid[3]	auto[0]	81	1			T39	2		T47	1		T360	1
auto[1]	auto[0]	valid[4]	auto[0]	106	1			T31	1		T9	1		T39	5
auto[1]	auto[1]	valid[0]	auto[0]	101	1			T9	1		T39	2		T25	1
auto[1]	auto[1]	valid[1]	auto[0]	91	1			T1	1		T31	2		T39	1
auto[1]	auto[1]	valid[2]	auto[0]	88	1			T62	1		T19	1		T24	1
auto[1]	auto[1]	valid[3]	auto[0]	103	1			T39	1		T360	2		T110	2
auto[1]	auto[1]	valid[4]	auto[0]	100	1			T31	1		T9	1		T39	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal