Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	72	2	70	97.22

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	72	2	70	97.22	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	468	1			T68	7		T69	7		T70	7
all_values[1]	468	1			T68	7		T69	7		T70	7
all_values[2]	468	1			T68	7		T69	7		T70	7
all_values[3]	468	1			T68	7		T69	7		T70	7
all_values[4]	468	1			T68	7		T69	7		T70	7
all_values[5]	468	1			T68	7		T69	7		T70	7
all_values[6]	468	1			T68	7		T69	7		T70	7
all_values[7]	468	1			T68	7		T69	7		T70	7
all_values[8]	468	1			T68	7		T69	7		T70	7
all_values[9]	468	1			T68	7		T69	7		T70	7
all_values[10]	468	1			T68	7		T69	7		T70	7
all_values[11]	468	1			T68	7		T69	7		T70	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2999

1

T68

44

T69

50

T70

48

auto[1]

2617

1

T68

40

T69

34

T70

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2118

1

T68

25

T69

25

T70

30

auto[1]

3498

1

T68

59

T69

59

T70

54

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3188

1

T68

44

T69

46

T70

45

auto[1]

2428

1

T68

40

T69

38

T70

39

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	2	70	97.22	2
Automatically Generated Cross Bins	72	2	70	97.22	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[11]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	106	1			T69	2		T70	2		T189	1
all_values[0]	auto[0]	auto[0]	auto[1]	41	1			T68	1		T69	2		T70	1
all_values[0]	auto[0]	auto[1]	auto[0]	86	1			T69	1		T190	1		T189	2
all_values[0]	auto[0]	auto[1]	auto[1]	44	1			T68	1		T190	1		T134	3
all_values[0]	auto[1]	auto[0]	auto[1]	102	1			T68	2		T69	2		T70	2
all_values[0]	auto[1]	auto[1]	auto[1]	89	1			T68	3		T70	2		T190	2
all_values[1]	auto[0]	auto[0]	auto[0]	75	1			T69	3		T190	2		T189	2
all_values[1]	auto[0]	auto[0]	auto[1]	61	1			T68	2		T191	1		T192	2
all_values[1]	auto[0]	auto[1]	auto[0]	62	1			T190	1		T191	1		T146	3
all_values[1]	auto[0]	auto[1]	auto[1]	45	1			T70	2		T190	2		T189	1
all_values[1]	auto[1]	auto[0]	auto[1]	126	1			T68	2		T69	2		T70	3
all_values[1]	auto[1]	auto[1]	auto[1]	99	1			T68	3		T69	2		T70	2
all_values[2]	auto[0]	auto[0]	auto[0]	93	1			T68	1		T70	3		T190	1
all_values[2]	auto[0]	auto[0]	auto[1]	41	1			T68	2		T189	1		T136	1
all_values[2]	auto[0]	auto[1]	auto[0]	84	1			T68	2		T69	2		T70	2
all_values[2]	auto[0]	auto[1]	auto[1]	54	1			T69	1		T134	1		T135	4
all_values[2]	auto[1]	auto[0]	auto[1]	104	1			T68	1		T69	1		T70	1
all_values[2]	auto[1]	auto[1]	auto[1]	92	1			T68	1		T69	3		T70	1
all_values[3]	auto[0]	auto[0]	auto[0]	98	1			T68	2		T69	3		T70	4
all_values[3]	auto[0]	auto[0]	auto[1]	41	1			T68	1		T69	1		T189	1
all_values[3]	auto[0]	auto[1]	auto[0]	80	1			T68	1		T70	1		T190	2
all_values[3]	auto[0]	auto[1]	auto[1]	50	1			T68	2		T190	1		T191	1
all_values[3]	auto[1]	auto[0]	auto[1]	115	1			T69	3		T70	1		T190	1
all_values[3]	auto[1]	auto[1]	auto[1]	84	1			T68	1		T70	1		T190	2
all_values[4]	auto[0]	auto[0]	auto[0]	88	1			T68	1		T70	1		T190	3
all_values[4]	auto[0]	auto[0]	auto[1]	54	1			T68	1		T69	2		T70	1
all_values[4]	auto[0]	auto[1]	auto[0]	79	1			T68	1		T190	1		T189	3
all_values[4]	auto[0]	auto[1]	auto[1]	44	1			T68	1		T69	1		T70	1
all_values[4]	auto[1]	auto[0]	auto[1]	113	1			T68	2		T69	3		T190	1
all_values[4]	auto[1]	auto[1]	auto[1]	90	1			T68	1		T69	1		T70	4
all_values[5]	auto[0]	auto[0]	auto[0]	74	1			T70	1		T190	1		T189	2
all_values[5]	auto[0]	auto[0]	auto[1]	46	1			T69	1		T70	2		T134	1
all_values[5]	auto[0]	auto[1]	auto[0]	79	1			T69	1		T190	2		T192	2
all_values[5]	auto[0]	auto[1]	auto[1]	51	1			T68	1		T69	2		T190	2
all_values[5]	auto[1]	auto[0]	auto[1]	124	1			T68	3		T69	1		T70	2
all_values[5]	auto[1]	auto[1]	auto[1]	94	1			T68	3		T69	2		T70	2
all_values[6]	auto[0]	auto[0]	auto[0]	82	1			T68	1		T70	1		T190	2
all_values[6]	auto[0]	auto[0]	auto[1]	66	1			T68	1		T69	1		T70	2
all_values[6]	auto[0]	auto[1]	auto[0]	75	1			T68	2		T70	1		T190	4
all_values[6]	auto[0]	auto[1]	auto[1]	38	1			T68	1		T69	1		T191	2
all_values[6]	auto[1]	auto[0]	auto[1]	120	1			T68	1		T69	3		T70	1
all_values[6]	auto[1]	auto[1]	auto[1]	87	1			T68	1		T69	2		T70	2
all_values[7]	auto[0]	auto[0]	auto[0]	82	1			T69	1		T70	2		T189	1
all_values[7]	auto[0]	auto[0]	auto[1]	45	1			T68	1		T69	3		T70	1
all_values[7]	auto[0]	auto[1]	auto[0]	77	1			T70	1		T136	1		T158	1
all_values[7]	auto[0]	auto[1]	auto[1]	61	1			T68	3		T190	4		T192	1
all_values[7]	auto[1]	auto[0]	auto[1]	114	1			T68	1		T69	3		T70	3
all_values[7]	auto[1]	auto[1]	auto[1]	89	1			T68	2		T190	2		T189	2
all_values[8]	auto[0]	auto[0]	auto[0]	80	1			T68	2		T69	2		T70	1
all_values[8]	auto[0]	auto[0]	auto[1]	47	1			T69	1		T192	1		T134	1
all_values[8]	auto[0]	auto[1]	auto[0]	92	1			T69	2		T70	1		T190	4
all_values[8]	auto[0]	auto[1]	auto[1]	50	1			T70	2		T189	1		T135	1
all_values[8]	auto[1]	auto[0]	auto[1]	107	1			T68	4		T69	1		T70	1
all_values[8]	auto[1]	auto[1]	auto[1]	92	1			T68	1		T69	1		T70	2
all_values[9]	auto[0]	auto[0]	auto[0]	95	1			T68	2		T70	1		T190	1
all_values[9]	auto[0]	auto[0]	auto[1]	41	1			T68	1		T134	1		T135	1
all_values[9]	auto[0]	auto[1]	auto[0]	89	1			T68	2		T70	1		T190	1
all_values[9]	auto[0]	auto[1]	auto[1]	48	1			T69	4		T70	1		T190	1
all_values[9]	auto[1]	auto[0]	auto[1]	103	1			T69	1		T70	3		T190	2
all_values[9]	auto[1]	auto[1]	auto[1]	92	1			T68	2		T69	2		T70	1
all_values[10]	auto[0]	auto[0]	auto[0]	99	1			T68	3		T69	1		T70	2
all_values[10]	auto[0]	auto[0]	auto[1]	58	1			T69	1		T70	2		T136	2
all_values[10]	auto[0]	auto[1]	auto[0]	80	1			T68	2		T69	3		T190	1
all_values[10]	auto[0]	auto[1]	auto[1]	44	1			T192	2		T136	2		T146	1
all_values[10]	auto[1]	auto[0]	auto[1]	105	1			T69	2		T70	1		T190	3
all_values[10]	auto[1]	auto[1]	auto[1]	82	1			T68	2		T70	2		T190	1
all_values[11]	auto[0]	auto[0]	auto[0]	148	1			T68	3		T69	4		T70	2
all_values[11]	auto[0]	auto[1]	auto[0]	115	1			T70	3		T190	3		T189	1
all_values[11]	auto[1]	auto[0]	auto[1]	105	1			T68	3		T70	1		T190	2
all_values[11]	auto[1]	auto[1]	auto[1]	100	1			T68	1		T69	3		T70	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal