Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

63298

1

T4

17

T6

14

T1

145

auto[1]

27521

1

T8

12

T103

12

T9

65

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67624

1

T4

12

T6

7

T1

108

auto[1]

23195

1

T4

5

T6

7

T1

37

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	46729	1			T4	5		T6	7		T1	75
others[1]	7686	1			T4	2		T6	3		T1	8
others[2]	7715	1			T4	2		T6	1		T1	16
others[3]	8766	1			T4	1		T6	1		T1	14
interest[1]	5025	1			T6	1		T1	11		T8	3
interest[4]	30497	1			T4	1		T6	4		T1	51
interest[64]	14898	1			T4	7		T6	1		T1	21

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	20485	1			T4	5		T6	3		T1	56
auto[0]	auto[0]	others[1]	3412	1			T4	1		T6	2		T1	5
auto[0]	auto[0]	others[2]	3464	1			T4	2		T6	1		T1	13
auto[0]	auto[0]	others[3]	3882	1			T4	1		T6	1		T1	10
auto[0]	auto[0]	interest[1]	2205	1			T1	10		T8	1		T31	12
auto[0]	auto[0]	interest[4]	13298	1			T4	1		T6	2		T1	40
auto[0]	auto[0]	interest[64]	6655	1			T4	3		T1	14		T8	7
auto[0]	auto[1]	others[0]	14386	1			T8	8		T103	12		T9	34
auto[0]	auto[1]	others[1]	2309	1			T8	1		T9	6		T39	5
auto[0]	auto[1]	others[2]	2325	1			T8	1		T9	6		T39	2
auto[0]	auto[1]	others[3]	2623	1			T9	7		T39	4		T47	6
auto[0]	auto[1]	interest[1]	1510	1			T8	1		T9	4		T39	1
auto[0]	auto[1]	interest[4]	9537	1			T8	5		T103	12		T9	21
auto[0]	auto[1]	interest[64]	4368	1			T8	1		T9	8		T39	3
auto[1]	auto[0]	others[0]	11858	1			T6	4		T1	19		T8	15
auto[1]	auto[0]	others[1]	1965	1			T4	1		T6	1		T1	3
auto[1]	auto[0]	others[2]	1926	1			T1	3		T8	1		T31	11
auto[1]	auto[0]	others[3]	2261	1			T1	4		T31	13		T9	14
auto[1]	auto[0]	interest[1]	1310	1			T6	1		T1	1		T8	1
auto[1]	auto[0]	interest[4]	7662	1			T6	2		T1	11		T8	9
auto[1]	auto[0]	interest[64]	3875	1			T4	4		T6	1		T1	7

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal