Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.10 99.01 96.32 98.63 92.06 98.05 95.86 99.76


Total test records in report: 1776
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T1751 /workspace/coverage/default/1.spi_device_flash_all.3234896495 Jan 17 03:28:43 PM PST 24 Jan 17 03:30:07 PM PST 24 21342481083 ps
T1752 /workspace/coverage/default/47.spi_device_csb_read.3489267903 Jan 17 03:37:53 PM PST 24 Jan 17 03:38:00 PM PST 24 24234848 ps
T1753 /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1568504286 Jan 17 03:36:58 PM PST 24 Jan 17 03:37:15 PM PST 24 18302600040 ps
T1754 /workspace/coverage/default/27.spi_device_mailbox.1711266847 Jan 17 03:33:38 PM PST 24 Jan 17 03:33:46 PM PST 24 206011565 ps
T1755 /workspace/coverage/default/11.spi_device_flash_and_tpm.1982105587 Jan 17 03:30:49 PM PST 24 Jan 17 03:38:47 PM PST 24 238345904436 ps
T1756 /workspace/coverage/default/48.spi_device_rx_timeout.3432798901 Jan 17 03:38:03 PM PST 24 Jan 17 03:38:09 PM PST 24 2457937240 ps
T1757 /workspace/coverage/default/19.spi_device_rx_async_fifo_reset.1946914724 Jan 17 03:32:19 PM PST 24 Jan 17 03:32:22 PM PST 24 19912771 ps
T1758 /workspace/coverage/default/13.spi_device_intercept.3848306362 Jan 17 03:31:00 PM PST 24 Jan 17 03:31:04 PM PST 24 293047323 ps
T1759 /workspace/coverage/default/21.spi_device_abort.3394625315 Jan 17 03:32:24 PM PST 24 Jan 17 03:32:25 PM PST 24 16066878 ps
T1760 /workspace/coverage/default/3.spi_device_read_buffer_direct.2281089224 Jan 17 03:29:12 PM PST 24 Jan 17 03:29:18 PM PST 24 1480368412 ps
T1761 /workspace/coverage/default/3.spi_device_ram_cfg.799097593 Jan 17 03:29:04 PM PST 24 Jan 17 03:29:06 PM PST 24 26915039 ps
T1762 /workspace/coverage/default/29.spi_device_bit_transfer.3833685036 Jan 17 03:33:58 PM PST 24 Jan 17 03:34:01 PM PST 24 671889874 ps
T1763 /workspace/coverage/default/14.spi_device_fifo_full.1422458585 Jan 17 03:31:03 PM PST 24 Jan 17 03:48:22 PM PST 24 36114787173 ps
T1764 /workspace/coverage/default/42.spi_device_intr.210784031 Jan 17 03:36:58 PM PST 24 Jan 17 03:37:43 PM PST 24 9362126520 ps
T1765 /workspace/coverage/default/20.spi_device_byte_transfer.3642992617 Jan 17 03:32:10 PM PST 24 Jan 17 03:32:14 PM PST 24 146733143 ps
T1766 /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2939766278 Jan 17 03:33:38 PM PST 24 Jan 17 03:34:33 PM PST 24 2089921418 ps
T1767 /workspace/coverage/default/0.spi_device_stress_all.2030828976 Jan 17 03:28:30 PM PST 24 Jan 17 03:43:27 PM PST 24 48701828361 ps
T1768 /workspace/coverage/default/43.spi_device_tx_async_fifo_reset.2560394923 Jan 17 03:37:03 PM PST 24 Jan 17 03:37:06 PM PST 24 17970316 ps
T1769 /workspace/coverage/default/2.spi_device_mailbox.3229578629 Jan 17 03:28:57 PM PST 24 Jan 17 03:29:29 PM PST 24 8587733318 ps
T1770 /workspace/coverage/default/41.spi_device_flash_all.2288504154 Jan 17 03:36:53 PM PST 24 Jan 17 03:37:53 PM PST 24 5540757497 ps
T1771 /workspace/coverage/default/30.spi_device_rx_timeout.3387164700 Jan 17 03:34:21 PM PST 24 Jan 17 03:34:29 PM PST 24 918136808 ps
T1772 /workspace/coverage/default/19.spi_device_flash_mode.561218536 Jan 17 03:32:09 PM PST 24 Jan 17 03:32:23 PM PST 24 3630805792 ps
T1773 /workspace/coverage/default/20.spi_device_perf.1625782701 Jan 17 03:32:13 PM PST 24 Jan 17 03:36:40 PM PST 24 36185612047 ps
T1774 /workspace/coverage/default/15.spi_device_tpm_rw.3442016786 Jan 17 03:31:15 PM PST 24 Jan 17 03:31:17 PM PST 24 292411567 ps
T1775 /workspace/coverage/default/45.spi_device_flash_and_tpm.3718275151 Jan 17 03:37:35 PM PST 24 Jan 17 03:41:14 PM PST 24 113450681310 ps
T1776 /workspace/coverage/default/18.spi_device_intr.931851459 Jan 17 03:31:50 PM PST 24 Jan 17 03:32:42 PM PST 24 47337122154 ps

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1216650962
Short name T1
Test name
Test status
Simulation time 112651594716 ps
CPU time 211.94 seconds
Started Jan 17 03:31:01 PM PST 24
Finished Jan 17 03:34:34 PM PST 24
Peak memory 266312 kb
Host smart-6f9f6ca7-7388-4fcc-9571-0a50cd77b4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216650962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1216650962
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_dummy_item_extra_dly.1861409017
Short name T32
Test name
Test status
Simulation time 67547903169 ps
CPU time 451.27 seconds
Started Jan 17 03:30:52 PM PST 24
Finished Jan 17 03:38:28 PM PST 24
Peak memory 299564 kb
Host smart-985e24fc-7237-450b-aafa-d631a14c6dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861409017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_dummy_item_extra_dly.1861409017
Directory /workspace/12.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2974499035
Short name T39
Test name
Test status
Simulation time 49575638763 ps
CPU time 548.89 seconds
Started Jan 17 03:36:29 PM PST 24
Finished Jan 17 03:45:41 PM PST 24
Peak memory 307712 kb
Host smart-540efd8c-f1e7-4f80-bb20-f1834425c5ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974499035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2974499035
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.116911791
Short name T117
Test name
Test status
Simulation time 1437889560 ps
CPU time 15.71 seconds
Started Jan 17 12:59:14 PM PST 24
Finished Jan 17 12:59:33 PM PST 24
Peak memory 216104 kb
Host smart-8a1d8045-2912-46c2-9207-661d4980c0eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116911791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.116911791
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3215758690
Short name T27
Test name
Test status
Simulation time 19628059629 ps
CPU time 190.92 seconds
Started Jan 17 03:30:55 PM PST 24
Finished Jan 17 03:34:07 PM PST 24
Peak memory 274180 kb
Host smart-8e3e2ede-0967-4019-8f17-58d71bd1f983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215758690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3215758690
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2815301020
Short name T70
Test name
Test status
Simulation time 27642242 ps
CPU time 0.76 seconds
Started Jan 17 12:59:25 PM PST 24
Finished Jan 17 12:59:29 PM PST 24
Peak memory 205060 kb
Host smart-37a5012e-b664-438f-84b5-91594c9f5a9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815301020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2815301020
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3462819359
Short name T9
Test name
Test status
Simulation time 180740400234 ps
CPU time 2913.93 seconds
Started Jan 17 03:32:07 PM PST 24
Finished Jan 17 04:20:42 PM PST 24
Peak memory 516864 kb
Host smart-c35bc7c4-5826-4fe5-b149-f8f7073b674d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462819359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3462819359
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2351760890
Short name T88
Test name
Test status
Simulation time 23696144 ps
CPU time 0.74 seconds
Started Jan 17 03:28:18 PM PST 24
Finished Jan 17 03:28:19 PM PST 24
Peak memory 217056 kb
Host smart-167f701f-2490-4c69-8c50-7496e29e3831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351760890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2351760890
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1987671463
Short name T25
Test name
Test status
Simulation time 45643842457 ps
CPU time 182.38 seconds
Started Jan 17 03:31:38 PM PST 24
Finished Jan 17 03:34:45 PM PST 24
Peak memory 273920 kb
Host smart-0447be63-416d-4bf8-b83a-05c1bf22fe95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987671463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1987671463
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3858217904
Short name T47
Test name
Test status
Simulation time 166817590651 ps
CPU time 307.96 seconds
Started Jan 17 03:30:02 PM PST 24
Finished Jan 17 03:35:12 PM PST 24
Peak memory 253352 kb
Host smart-606eefd0-6c0e-4e11-b799-463189287854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858217904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3858217904
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2000316104
Short name T24
Test name
Test status
Simulation time 74414819441 ps
CPU time 495.6 seconds
Started Jan 17 03:32:51 PM PST 24
Finished Jan 17 03:41:07 PM PST 24
Peak memory 271452 kb
Host smart-cb72a479-5ef9-476b-9084-25d630217941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000316104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2000316104
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_rx_timeout.2573176638
Short name T58
Test name
Test status
Simulation time 972396571 ps
CPU time 7.48 seconds
Started Jan 17 03:37:22 PM PST 24
Finished Jan 17 03:37:36 PM PST 24
Peak memory 217092 kb
Host smart-09c05ed5-ce92-4965-9124-bd218c874edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573176638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_rx_timeout.2573176638
Directory /workspace/44.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3778074682
Short name T169
Test name
Test status
Simulation time 3724210619 ps
CPU time 29.86 seconds
Started Jan 17 03:32:51 PM PST 24
Finished Jan 17 03:33:22 PM PST 24
Peak memory 241808 kb
Host smart-aa7f5133-9ac4-4674-b51c-730dc63897e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778074682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3778074682
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.588058837
Short name T105
Test name
Test status
Simulation time 294825838949 ps
CPU time 977.92 seconds
Started Jan 17 03:30:46 PM PST 24
Finished Jan 17 03:47:06 PM PST 24
Peak memory 586196 kb
Host smart-d525b0cb-8459-4d3c-865e-6737403a1e69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588058837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.588058837
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1153593915
Short name T86
Test name
Test status
Simulation time 776449390 ps
CPU time 5.64 seconds
Started Jan 17 12:58:37 PM PST 24
Finished Jan 17 12:58:44 PM PST 24
Peak memory 216132 kb
Host smart-51b827c9-5097-4d61-9509-8af14f4f580e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153593915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
153593915
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2839804301
Short name T234
Test name
Test status
Simulation time 152373417403 ps
CPU time 360.08 seconds
Started Jan 17 03:28:57 PM PST 24
Finished Jan 17 03:35:05 PM PST 24
Peak memory 266432 kb
Host smart-e45a2176-b9e5-40ae-943d-3e3625bce8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839804301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2839804301
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.857589212
Short name T74
Test name
Test status
Simulation time 632990399593 ps
CPU time 555.04 seconds
Started Jan 17 03:34:09 PM PST 24
Finished Jan 17 03:43:26 PM PST 24
Peak memory 429624 kb
Host smart-f5c7269c-f07b-4431-b353-0bba12c5eebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857589212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.857589212
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1063878875
Short name T158
Test name
Test status
Simulation time 15616202 ps
CPU time 0.78 seconds
Started Jan 17 12:59:23 PM PST 24
Finished Jan 17 12:59:27 PM PST 24
Peak memory 205020 kb
Host smart-baafbf0d-fffd-405d-86d8-9786c1406a68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063878875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1063878875
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2378981164
Short name T67
Test name
Test status
Simulation time 44861677 ps
CPU time 1.32 seconds
Started Jan 17 12:58:15 PM PST 24
Finished Jan 17 12:58:18 PM PST 24
Peak memory 207788 kb
Host smart-4621ebc4-829f-484f-93a5-7d9f498be2c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378981164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2378981164
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.4018688563
Short name T242
Test name
Test status
Simulation time 16740369284 ps
CPU time 134.7 seconds
Started Jan 17 03:33:37 PM PST 24
Finished Jan 17 03:35:52 PM PST 24
Peak memory 264184 kb
Host smart-078c65e8-f0db-4364-9685-c2284bddc2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018688563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.4018688563
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2398529921
Short name T276
Test name
Test status
Simulation time 118065453410 ps
CPU time 382.58 seconds
Started Jan 17 03:30:01 PM PST 24
Finished Jan 17 03:36:26 PM PST 24
Peak memory 372084 kb
Host smart-0772516a-e3da-4e14-83cc-6515346d40a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398529921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2398529921
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3738499195
Short name T110
Test name
Test status
Simulation time 368564098803 ps
CPU time 299.97 seconds
Started Jan 17 03:29:51 PM PST 24
Finished Jan 17 03:34:53 PM PST 24
Peak memory 251092 kb
Host smart-b0017568-1a24-4bb0-830f-37378a5ea13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738499195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3738499195
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.140073495
Short name T323
Test name
Test status
Simulation time 18006141655 ps
CPU time 235.32 seconds
Started Jan 17 03:30:14 PM PST 24
Finished Jan 17 03:34:11 PM PST 24
Peak memory 274612 kb
Host smart-fd25b755-38a2-4dda-a1f1-ffa28e669eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140073495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
140073495
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3418321659
Short name T92
Test name
Test status
Simulation time 309618660 ps
CPU time 1.2 seconds
Started Jan 17 03:28:28 PM PST 24
Finished Jan 17 03:28:35 PM PST 24
Peak memory 236104 kb
Host smart-7bc5ee52-fd94-4a99-ad15-fcdb81e4085a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418321659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3418321659
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1851540248
Short name T30
Test name
Test status
Simulation time 331512988207 ps
CPU time 443.78 seconds
Started Jan 17 03:32:57 PM PST 24
Finished Jan 17 03:40:22 PM PST 24
Peak memory 268476 kb
Host smart-726dfeec-ed96-4bd0-ae57-38c853265b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851540248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1851540248
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1845181264
Short name T222
Test name
Test status
Simulation time 44883189627 ps
CPU time 312.31 seconds
Started Jan 17 03:32:45 PM PST 24
Finished Jan 17 03:37:58 PM PST 24
Peak memory 272584 kb
Host smart-2a06031f-ca4c-4b20-9ae4-5b496482502d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845181264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1845181264
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4057714128
Short name T134
Test name
Test status
Simulation time 15835012 ps
CPU time 0.73 seconds
Started Jan 17 12:59:37 PM PST 24
Finished Jan 17 12:59:39 PM PST 24
Peak memory 204992 kb
Host smart-f0a5e982-ceeb-4dfd-bdd2-7eb612ba52bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057714128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
4057714128
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2835772497
Short name T326
Test name
Test status
Simulation time 263119395622 ps
CPU time 323.39 seconds
Started Jan 17 03:32:02 PM PST 24
Finished Jan 17 03:37:31 PM PST 24
Peak memory 269828 kb
Host smart-9c5218ea-7fa9-4bbd-a1b1-3be9adfc7434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835772497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2835772497
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.525434735
Short name T141
Test name
Test status
Simulation time 563856467 ps
CPU time 14.83 seconds
Started Jan 17 12:59:09 PM PST 24
Finished Jan 17 12:59:24 PM PST 24
Peak memory 215928 kb
Host smart-d4eed7fb-ba5d-41f8-b3cb-9ea70bfc8c53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525434735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.525434735
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/23.spi_device_bit_transfer.1555704707
Short name T59
Test name
Test status
Simulation time 170990955 ps
CPU time 2.37 seconds
Started Jan 17 03:32:49 PM PST 24
Finished Jan 17 03:32:52 PM PST 24
Peak memory 217112 kb
Host smart-17a8e6cd-2b4d-47c1-8182-ae31b7f4370b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555704707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_bit_transfer.1555704707
Directory /workspace/23.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3092559753
Short name T1114
Test name
Test status
Simulation time 44010369 ps
CPU time 0.99 seconds
Started Jan 17 03:30:18 PM PST 24
Finished Jan 17 03:30:20 PM PST 24
Peak memory 219188 kb
Host smart-f840a138-9d2b-48ef-8078-09e3139520f4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092559753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3092559753
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1469369610
Short name T5
Test name
Test status
Simulation time 127785831 ps
CPU time 0.73 seconds
Started Jan 17 03:30:39 PM PST 24
Finished Jan 17 03:30:41 PM PST 24
Peak memory 206808 kb
Host smart-22e59f27-06f3-4b78-b01b-805dea9ead11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469369610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1469369610
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2988348012
Short name T329
Test name
Test status
Simulation time 374053304296 ps
CPU time 3222.09 seconds
Started Jan 17 03:30:55 PM PST 24
Finished Jan 17 04:24:39 PM PST 24
Peak memory 420324 kb
Host smart-05e912dc-4230-4f99-8732-dbf3b3f3cdd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988348012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2988348012
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3230730419
Short name T130
Test name
Test status
Simulation time 187115751501 ps
CPU time 2257.15 seconds
Started Jan 17 03:35:53 PM PST 24
Finished Jan 17 04:13:34 PM PST 24
Peak memory 379108 kb
Host smart-dc85a91f-6466-457d-9580-70397b9f06ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230730419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3230730419
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.997997445
Short name T205
Test name
Test status
Simulation time 313173252 ps
CPU time 19.31 seconds
Started Jan 17 12:58:18 PM PST 24
Finished Jan 17 12:58:40 PM PST 24
Peak memory 216020 kb
Host smart-628506b6-a05c-41fe-882d-5d8fcac0ede2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997997445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.997997445
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.697177214
Short name T231
Test name
Test status
Simulation time 189927117844 ps
CPU time 404.82 seconds
Started Jan 17 03:28:47 PM PST 24
Finished Jan 17 03:35:33 PM PST 24
Peak memory 273648 kb
Host smart-e9d4aa6a-427d-45d2-9c3b-d8de00f061a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697177214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.697177214
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_fifo_underflow_overflow.2584691156
Short name T33
Test name
Test status
Simulation time 349464543060 ps
CPU time 208.29 seconds
Started Jan 17 03:31:35 PM PST 24
Finished Jan 17 03:35:08 PM PST 24
Peak memory 406708 kb
Host smart-7243f22d-eac2-4623-87fa-ccab7835bc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584691156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_fifo_underflow_overf
low.2584691156
Directory /workspace/17.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3571134222
Short name T146
Test name
Test status
Simulation time 17882492 ps
CPU time 0.77 seconds
Started Jan 17 12:59:07 PM PST 24
Finished Jan 17 12:59:08 PM PST 24
Peak memory 205004 kb
Host smart-c059176b-fb3f-4a7c-86d3-be2a8b54007f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571134222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3571134222
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1754417007
Short name T339
Test name
Test status
Simulation time 243274782324 ps
CPU time 326.17 seconds
Started Jan 17 03:30:28 PM PST 24
Finished Jan 17 03:35:55 PM PST 24
Peak memory 268428 kb
Host smart-36e739c4-43df-40db-9cc0-499305ac08e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754417007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1754417007
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1019134157
Short name T330
Test name
Test status
Simulation time 40123377937 ps
CPU time 330.02 seconds
Started Jan 17 03:31:46 PM PST 24
Finished Jan 17 03:37:17 PM PST 24
Peak memory 271472 kb
Host smart-a2f09f14-1840-47cc-b867-52ac6a04d0b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019134157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1019134157
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1637261232
Short name T127
Test name
Test status
Simulation time 54737938986 ps
CPU time 664.25 seconds
Started Jan 17 03:28:56 PM PST 24
Finished Jan 17 03:40:01 PM PST 24
Peak memory 302664 kb
Host smart-a7db1754-7b74-4387-a507-bf11228a3baa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637261232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1637261232
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3566220440
Short name T275
Test name
Test status
Simulation time 15422585722 ps
CPU time 180.09 seconds
Started Jan 17 03:33:35 PM PST 24
Finished Jan 17 03:36:36 PM PST 24
Peak memory 274500 kb
Host smart-1b087948-5178-444a-b115-9957049a7766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566220440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3566220440
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2531458821
Short name T342
Test name
Test status
Simulation time 182946140506 ps
CPU time 547.77 seconds
Started Jan 17 03:29:15 PM PST 24
Finished Jan 17 03:38:24 PM PST 24
Peak memory 268560 kb
Host smart-8895e5c3-6653-4d85-a13b-5adef23a9ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531458821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2531458821
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3975745813
Short name T17
Test name
Test status
Simulation time 21467750266 ps
CPU time 22.83 seconds
Started Jan 17 03:37:05 PM PST 24
Finished Jan 17 03:37:29 PM PST 24
Peak memory 233628 kb
Host smart-9af159ff-7900-4b22-9c53-d3521b3ac0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975745813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3975745813
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1304555557
Short name T167
Test name
Test status
Simulation time 112129788193 ps
CPU time 35.26 seconds
Started Jan 17 03:31:24 PM PST 24
Finished Jan 17 03:32:00 PM PST 24
Peak memory 250868 kb
Host smart-fca9be29-eb42-4351-bb33-377a84c47909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304555557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1304555557
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3868892625
Short name T119
Test name
Test status
Simulation time 979210153 ps
CPU time 5.4 seconds
Started Jan 17 12:58:44 PM PST 24
Finished Jan 17 12:58:52 PM PST 24
Peak memory 215992 kb
Host smart-316a4a46-23ba-4385-801b-d3ea150ab220
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868892625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3868892625
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4086111369
Short name T394
Test name
Test status
Simulation time 62515542 ps
CPU time 2.02 seconds
Started Jan 17 12:58:16 PM PST 24
Finished Jan 17 12:58:22 PM PST 24
Peak memory 218780 kb
Host smart-746b6ca3-4757-4ed2-9bd9-b20420f4c141
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086111369 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4086111369
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3541586670
Short name T204
Test name
Test status
Simulation time 1290259149 ps
CPU time 18.72 seconds
Started Jan 17 12:58:15 PM PST 24
Finished Jan 17 12:58:36 PM PST 24
Peak memory 216072 kb
Host smart-2b8a5a18-0ebc-4a14-a2dc-1026e6544c94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541586670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3541586670
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.18535458
Short name T238
Test name
Test status
Simulation time 20641277174 ps
CPU time 140.44 seconds
Started Jan 17 03:28:24 PM PST 24
Finished Jan 17 03:30:46 PM PST 24
Peak memory 273672 kb
Host smart-77864b4b-9a7d-488b-af2e-58d069e3d272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18535458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.18535458
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_extreme_fifo_size.606705012
Short name T989
Test name
Test status
Simulation time 459132714979 ps
CPU time 3237.89 seconds
Started Jan 17 03:30:41 PM PST 24
Finished Jan 17 04:24:40 PM PST 24
Peak memory 225460 kb
Host smart-7ac16d29-7aff-4c33-a476-f2ac28252634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606705012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_extreme_fifo_size.606705012
Directory /workspace/11.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1647358245
Short name T335
Test name
Test status
Simulation time 269106098427 ps
CPU time 323.95 seconds
Started Jan 17 03:31:24 PM PST 24
Finished Jan 17 03:36:49 PM PST 24
Peak memory 271620 kb
Host smart-14143aba-db26-46ab-b229-f23ecc954a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647358245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1647358245
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_dummy_item_extra_dly.125315732
Short name T272
Test name
Test status
Simulation time 80654445944 ps
CPU time 1280.12 seconds
Started Jan 17 03:31:43 PM PST 24
Finished Jan 17 03:53:05 PM PST 24
Peak memory 312772 kb
Host smart-fa579ce7-a18a-476a-8299-8a8609910a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125315732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_dummy_item_extra_dly.125315732
Directory /workspace/17.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.716995094
Short name T320
Test name
Test status
Simulation time 55169284367 ps
CPU time 447.62 seconds
Started Jan 17 03:31:55 PM PST 24
Finished Jan 17 03:39:25 PM PST 24
Peak memory 270148 kb
Host smart-a1064fcd-6eea-456a-b0c8-24cbf9022e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716995094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.716995094
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_intr.1380279969
Short name T1636
Test name
Test status
Simulation time 192642668504 ps
CPU time 84.17 seconds
Started Jan 17 03:28:56 PM PST 24
Finished Jan 17 03:30:28 PM PST 24
Peak memory 240936 kb
Host smart-7ad1cf3c-7c2c-4968-bab9-a85d82896265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380279969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intr.1380279969
Directory /workspace/2.spi_device_intr/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2011988359
Short name T210
Test name
Test status
Simulation time 67548795116 ps
CPU time 90.19 seconds
Started Jan 17 03:33:51 PM PST 24
Finished Jan 17 03:35:22 PM PST 24
Peak memory 252420 kb
Host smart-9d309027-8588-4c8e-8a26-da8dde10e5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011988359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2011988359
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2789730382
Short name T318
Test name
Test status
Simulation time 13180717108 ps
CPU time 124.33 seconds
Started Jan 17 03:34:08 PM PST 24
Finished Jan 17 03:36:14 PM PST 24
Peak memory 251348 kb
Host smart-362649f2-3378-47e4-9d49-9b123da42f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789730382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2789730382
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.23906276
Short name T325
Test name
Test status
Simulation time 6264619098 ps
CPU time 106.38 seconds
Started Jan 17 03:34:50 PM PST 24
Finished Jan 17 03:36:37 PM PST 24
Peak memory 267512 kb
Host smart-366e00bb-d8fd-4f3a-a730-f920ce4d2a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23906276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.23906276
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1862898278
Short name T351
Test name
Test status
Simulation time 35399770793 ps
CPU time 89.69 seconds
Started Jan 17 03:36:00 PM PST 24
Finished Jan 17 03:37:31 PM PST 24
Peak memory 267824 kb
Host smart-9fe6b078-ea8a-4645-b0f6-4c4c38f7a891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862898278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1862898278
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_extreme_fifo_size.2907094752
Short name T180
Test name
Test status
Simulation time 2370190880 ps
CPU time 28.59 seconds
Started Jan 17 03:29:20 PM PST 24
Finished Jan 17 03:29:50 PM PST 24
Peak memory 238312 kb
Host smart-2843a32a-6cbd-4279-b688-70cbaecadc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907094752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_extreme_fifo_size.2907094752
Directory /workspace/4.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/17.spi_device_abort.1336462287
Short name T76
Test name
Test status
Simulation time 14219074 ps
CPU time 0.78 seconds
Started Jan 17 03:31:47 PM PST 24
Finished Jan 17 03:31:49 PM PST 24
Peak memory 206976 kb
Host smart-385dd81a-bae0-458e-93dd-20c8ab6956dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336462287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_abort.1336462287
Directory /workspace/17.spi_device_abort/latest

Test location /workspace/coverage/default/1.spi_device_rx_async_fifo_reset.3313754858
Short name T596
Test name
Test status
Simulation time 182133225 ps
CPU time 0.94 seconds
Started Jan 17 03:28:40 PM PST 24
Finished Jan 17 03:28:42 PM PST 24
Peak memory 208800 kb
Host smart-1e452d63-4ee1-4076-9b6a-a9acb1f65652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313754858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_rx_async_fifo_reset.3313754858
Directory /workspace/1.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/13.spi_device_tx_async_fifo_reset.332952580
Short name T550
Test name
Test status
Simulation time 19613764 ps
CPU time 0.8 seconds
Started Jan 17 03:30:59 PM PST 24
Finished Jan 17 03:31:00 PM PST 24
Peak memory 208796 kb
Host smart-d5c9f2dd-0a2f-4e3d-969d-5e3204784687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332952580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tx_async_fifo_reset.332952580
Directory /workspace/13.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.594377960
Short name T406
Test name
Test status
Simulation time 129481572 ps
CPU time 8.72 seconds
Started Jan 17 12:58:14 PM PST 24
Finished Jan 17 12:58:25 PM PST 24
Peak memory 215940 kb
Host smart-a33fdd22-9549-489d-93dc-45dec791ab39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594377960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.594377960
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3908808777
Short name T386
Test name
Test status
Simulation time 4286705401 ps
CPU time 25.82 seconds
Started Jan 17 12:58:14 PM PST 24
Finished Jan 17 12:58:40 PM PST 24
Peak memory 216044 kb
Host smart-82d49d72-5d0a-4e8a-8df8-cdc0a5db2d76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908808777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3908808777
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.637344679
Short name T414
Test name
Test status
Simulation time 177374801 ps
CPU time 2.52 seconds
Started Jan 17 12:58:16 PM PST 24
Finished Jan 17 12:58:23 PM PST 24
Peak memory 215864 kb
Host smart-f046d1e1-41a3-4fb4-a822-b0e350eecdad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637344679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.637344679
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3584415210
Short name T367
Test name
Test status
Simulation time 64283737 ps
CPU time 0.75 seconds
Started Jan 17 12:58:21 PM PST 24
Finished Jan 17 12:58:22 PM PST 24
Peak memory 205060 kb
Host smart-ccbd9c76-e985-46cb-9574-f5b650eb9483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584415210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
584415210
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1983295752
Short name T142
Test name
Test status
Simulation time 360740623 ps
CPU time 7.48 seconds
Started Jan 17 12:58:15 PM PST 24
Finished Jan 17 12:58:24 PM PST 24
Peak memory 215884 kb
Host smart-b01bf16d-666a-49ff-addf-a4e45ea70304
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983295752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1983295752
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.583309469
Short name T366
Test name
Test status
Simulation time 6146309178 ps
CPU time 15.42 seconds
Started Jan 17 12:58:15 PM PST 24
Finished Jan 17 12:58:32 PM PST 24
Peak memory 215952 kb
Host smart-754e5b76-7e8b-4360-b4e9-e0601cefd9dd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583309469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.583309469
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2493010425
Short name T470
Test name
Test status
Simulation time 58649317 ps
CPU time 1.89 seconds
Started Jan 17 12:58:15 PM PST 24
Finished Jan 17 12:58:18 PM PST 24
Peak memory 215984 kb
Host smart-9f2a6879-0d46-40d6-8561-b61748d43831
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493010425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2493010425
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2796827571
Short name T118
Test name
Test status
Simulation time 270384916 ps
CPU time 3.75 seconds
Started Jan 17 12:58:12 PM PST 24
Finished Jan 17 12:58:16 PM PST 24
Peak memory 216068 kb
Host smart-e97f5bb1-e5cf-4bb3-bb69-f7069e7c9463
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796827571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
796827571
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2183276118
Short name T472
Test name
Test status
Simulation time 540304325 ps
CPU time 9.66 seconds
Started Jan 17 12:58:20 PM PST 24
Finished Jan 17 12:58:31 PM PST 24
Peak memory 207740 kb
Host smart-f8339c43-f7dc-4e19-951f-7c82f38c711a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183276118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2183276118
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1743069689
Short name T466
Test name
Test status
Simulation time 1130152606 ps
CPU time 36.37 seconds
Started Jan 17 12:58:21 PM PST 24
Finished Jan 17 12:58:58 PM PST 24
Peak memory 207696 kb
Host smart-e8600f58-1d90-43b3-8ba0-a5e9270a57c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743069689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1743069689
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3788563712
Short name T467
Test name
Test status
Simulation time 49713612 ps
CPU time 1.46 seconds
Started Jan 17 12:58:20 PM PST 24
Finished Jan 17 12:58:23 PM PST 24
Peak memory 207664 kb
Host smart-783783d9-f7f7-4367-8afe-efee807daf3d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788563712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3788563712
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4118229889
Short name T171
Test name
Test status
Simulation time 26706415 ps
CPU time 1.47 seconds
Started Jan 17 12:58:30 PM PST 24
Finished Jan 17 12:58:32 PM PST 24
Peak memory 217656 kb
Host smart-16d9d11b-a353-401d-9f13-d0afc3762855
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118229889 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4118229889
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3776517960
Short name T154
Test name
Test status
Simulation time 83046055 ps
CPU time 2.31 seconds
Started Jan 17 12:58:23 PM PST 24
Finished Jan 17 12:58:26 PM PST 24
Peak memory 215928 kb
Host smart-d67a77a0-42cb-4790-b129-034d8e1c2ab3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776517960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
776517960
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1580735610
Short name T369
Test name
Test status
Simulation time 69885489 ps
CPU time 0.76 seconds
Started Jan 17 12:58:18 PM PST 24
Finished Jan 17 12:58:21 PM PST 24
Peak memory 204984 kb
Host smart-34b0d26b-5b3d-48e5-a041-04d8a5ca1b81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580735610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
580735610
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.644391281
Short name T156
Test name
Test status
Simulation time 32417469 ps
CPU time 2.29 seconds
Started Jan 17 12:58:21 PM PST 24
Finished Jan 17 12:58:24 PM PST 24
Peak memory 215904 kb
Host smart-42e90c46-8927-4c8e-b0a6-c0c0d52e2fea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644391281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.644391281
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3891701766
Short name T174
Test name
Test status
Simulation time 295948109 ps
CPU time 4.88 seconds
Started Jan 17 12:58:18 PM PST 24
Finished Jan 17 12:58:25 PM PST 24
Peak memory 215960 kb
Host smart-e78b2bc1-677c-4242-904f-10e28ad4e89a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891701766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3891701766
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.813058287
Short name T374
Test name
Test status
Simulation time 32113137 ps
CPU time 1.84 seconds
Started Jan 17 12:58:21 PM PST 24
Finished Jan 17 12:58:23 PM PST 24
Peak memory 207840 kb
Host smart-a814ceba-bebd-4373-b4cd-1a82f644e32d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813058287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.813058287
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2584707731
Short name T384
Test name
Test status
Simulation time 89333776 ps
CPU time 2.76 seconds
Started Jan 17 12:58:15 PM PST 24
Finished Jan 17 12:58:19 PM PST 24
Peak memory 216068 kb
Host smart-bc379dba-afbd-40d1-9688-0d0767d5a4b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584707731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
584707731
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.556612485
Short name T400
Test name
Test status
Simulation time 20568851 ps
CPU time 1.52 seconds
Started Jan 17 12:58:44 PM PST 24
Finished Jan 17 12:58:48 PM PST 24
Peak memory 217452 kb
Host smart-a81b5002-9d33-463f-b66e-f0d3020c9437
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556612485 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.556612485
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3759990931
Short name T153
Test name
Test status
Simulation time 81419619 ps
CPU time 2.47 seconds
Started Jan 17 12:58:48 PM PST 24
Finished Jan 17 12:58:51 PM PST 24
Peak memory 215924 kb
Host smart-32bee638-113e-4ed1-84cb-77b767d213b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759990931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3759990931
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1542467046
Short name T396
Test name
Test status
Simulation time 31265496 ps
CPU time 0.73 seconds
Started Jan 17 12:58:43 PM PST 24
Finished Jan 17 12:58:47 PM PST 24
Peak memory 205020 kb
Host smart-7f858913-de06-4e5a-9c51-80b0f9803739
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542467046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1542467046
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.456496003
Short name T377
Test name
Test status
Simulation time 359881084 ps
CPU time 4.49 seconds
Started Jan 17 12:58:43 PM PST 24
Finished Jan 17 12:58:51 PM PST 24
Peak memory 215984 kb
Host smart-95749f3b-ea2b-4b78-8fc1-46adfb44fbfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456496003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.456496003
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1971734872
Short name T461
Test name
Test status
Simulation time 301835069 ps
CPU time 3.61 seconds
Started Jan 17 12:58:54 PM PST 24
Finished Jan 17 12:58:59 PM PST 24
Peak memory 216104 kb
Host smart-7e4de7a8-c42f-4573-85e7-bddc9c574756
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971734872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1971734872
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3694615741
Short name T433
Test name
Test status
Simulation time 11308338258 ps
CPU time 15.1 seconds
Started Jan 17 12:58:47 PM PST 24
Finished Jan 17 12:59:03 PM PST 24
Peak memory 216064 kb
Host smart-0f859ce9-8fdb-4b1f-9743-effa4eae1556
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694615741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3694615741
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.812253915
Short name T378
Test name
Test status
Simulation time 39345129 ps
CPU time 2.34 seconds
Started Jan 17 12:59:05 PM PST 24
Finished Jan 17 12:59:08 PM PST 24
Peak memory 217968 kb
Host smart-48183391-897e-4495-a62a-609fb762bda4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812253915 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.812253915
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3931444916
Short name T148
Test name
Test status
Simulation time 21644469 ps
CPU time 1.24 seconds
Started Jan 17 12:58:42 PM PST 24
Finished Jan 17 12:58:48 PM PST 24
Peak memory 207748 kb
Host smart-b12f3dcd-4b6f-42e6-83a6-3a01588043c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931444916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3931444916
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.187315921
Short name T136
Test name
Test status
Simulation time 16226840 ps
CPU time 0.72 seconds
Started Jan 17 12:58:44 PM PST 24
Finished Jan 17 12:58:47 PM PST 24
Peak memory 205036 kb
Host smart-79c41dc7-ece0-4694-8314-82acbe65b50b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187315921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.187315921
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2601211189
Short name T143
Test name
Test status
Simulation time 63360617 ps
CPU time 4.17 seconds
Started Jan 17 12:59:04 PM PST 24
Finished Jan 17 12:59:09 PM PST 24
Peak memory 215940 kb
Host smart-720a3dce-af66-4b62-b1e4-939aa54441d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601211189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2601211189
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1173114841
Short name T85
Test name
Test status
Simulation time 5745963355 ps
CPU time 20.28 seconds
Started Jan 17 12:58:44 PM PST 24
Finished Jan 17 12:59:07 PM PST 24
Peak memory 216016 kb
Host smart-4aa07494-0b5f-49e4-89bc-512501e308c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173114841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1173114841
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3783574569
Short name T402
Test name
Test status
Simulation time 45542531 ps
CPU time 2.09 seconds
Started Jan 17 12:58:58 PM PST 24
Finished Jan 17 12:59:02 PM PST 24
Peak memory 219300 kb
Host smart-c9448cde-dfda-4d27-a341-50027ff5165e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783574569 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3783574569
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2127530749
Short name T418
Test name
Test status
Simulation time 28400515 ps
CPU time 1.84 seconds
Started Jan 17 12:58:59 PM PST 24
Finished Jan 17 12:59:02 PM PST 24
Peak memory 215984 kb
Host smart-d8a94334-f94e-4c5d-86f6-626118b689ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127530749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2127530749
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3576472181
Short name T381
Test name
Test status
Simulation time 42597065 ps
CPU time 0.73 seconds
Started Jan 17 12:59:02 PM PST 24
Finished Jan 17 12:59:03 PM PST 24
Peak memory 205056 kb
Host smart-d9848612-b118-44b3-86d4-cd96ad862371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576472181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3576472181
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2813801116
Short name T391
Test name
Test status
Simulation time 705658562 ps
CPU time 4.35 seconds
Started Jan 17 12:58:58 PM PST 24
Finished Jan 17 12:59:04 PM PST 24
Peak memory 215776 kb
Host smart-bc4729ba-4eb2-4351-a38b-641b48dac60c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813801116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2813801116
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1362632300
Short name T431
Test name
Test status
Simulation time 178471847 ps
CPU time 5.16 seconds
Started Jan 17 12:58:58 PM PST 24
Finished Jan 17 12:59:05 PM PST 24
Peak memory 215924 kb
Host smart-c39d03f8-33d6-4c77-b846-cb103ddbc5b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362632300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1362632300
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3550696274
Short name T201
Test name
Test status
Simulation time 605548348 ps
CPU time 18.58 seconds
Started Jan 17 12:59:04 PM PST 24
Finished Jan 17 12:59:24 PM PST 24
Peak memory 216008 kb
Host smart-a59b45ad-5457-4086-b10f-a0721d71df5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550696274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3550696274
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.769881783
Short name T151
Test name
Test status
Simulation time 43834447 ps
CPU time 2.46 seconds
Started Jan 17 12:59:01 PM PST 24
Finished Jan 17 12:59:05 PM PST 24
Peak memory 218296 kb
Host smart-050967b9-24d2-4689-ac3e-00bcc729fc3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769881783 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.769881783
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.320035256
Short name T448
Test name
Test status
Simulation time 531823422 ps
CPU time 3.25 seconds
Started Jan 17 12:59:03 PM PST 24
Finished Jan 17 12:59:08 PM PST 24
Peak memory 216204 kb
Host smart-f10b85ef-08f4-42e6-89ea-fb7a7e948df5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320035256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.320035256
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1857643216
Short name T449
Test name
Test status
Simulation time 31973772 ps
CPU time 0.82 seconds
Started Jan 17 12:59:01 PM PST 24
Finished Jan 17 12:59:02 PM PST 24
Peak memory 204996 kb
Host smart-7f8a88a2-8279-4801-b8c5-854fd2fe63a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857643216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1857643216
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3651997187
Short name T451
Test name
Test status
Simulation time 2199668317 ps
CPU time 4.15 seconds
Started Jan 17 12:58:59 PM PST 24
Finished Jan 17 12:59:04 PM PST 24
Peak memory 216016 kb
Host smart-8487d774-cd80-4a10-81d6-a8a3d6bfbb47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651997187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3651997187
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.208221983
Short name T425
Test name
Test status
Simulation time 159671846 ps
CPU time 3.13 seconds
Started Jan 17 12:59:00 PM PST 24
Finished Jan 17 12:59:04 PM PST 24
Peak memory 216104 kb
Host smart-95c98367-03b4-49c0-8698-1b35531d65a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208221983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.208221983
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.486729424
Short name T199
Test name
Test status
Simulation time 273572875 ps
CPU time 7.69 seconds
Started Jan 17 12:58:58 PM PST 24
Finished Jan 17 12:59:08 PM PST 24
Peak memory 216032 kb
Host smart-b9f34d34-e7ac-4fe9-839b-1c80d771fba8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486729424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.486729424
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.276196216
Short name T133
Test name
Test status
Simulation time 61676359 ps
CPU time 1.76 seconds
Started Jan 17 12:59:07 PM PST 24
Finished Jan 17 12:59:10 PM PST 24
Peak memory 218016 kb
Host smart-cb15dbf8-72e2-4906-b6f6-2ab8c1def3c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276196216 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.276196216
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1712185258
Short name T144
Test name
Test status
Simulation time 113389874 ps
CPU time 2.08 seconds
Started Jan 17 12:59:00 PM PST 24
Finished Jan 17 12:59:03 PM PST 24
Peak memory 215928 kb
Host smart-b669127f-0fc6-4ea7-80fb-07ff15e7127e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712185258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1712185258
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.613198912
Short name T191
Test name
Test status
Simulation time 24090019 ps
CPU time 0.7 seconds
Started Jan 17 12:59:02 PM PST 24
Finished Jan 17 12:59:03 PM PST 24
Peak memory 204948 kb
Host smart-881dd2ce-3927-4af5-946c-630cc8a27a6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613198912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.613198912
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.736701552
Short name T468
Test name
Test status
Simulation time 144658027 ps
CPU time 3.34 seconds
Started Jan 17 12:59:08 PM PST 24
Finished Jan 17 12:59:12 PM PST 24
Peak memory 216028 kb
Host smart-b6d77d52-f869-41a3-a34d-2b90e2206d7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736701552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.736701552
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3218039100
Short name T116
Test name
Test status
Simulation time 29981609 ps
CPU time 2 seconds
Started Jan 17 12:59:18 PM PST 24
Finished Jan 17 12:59:28 PM PST 24
Peak memory 216080 kb
Host smart-81298af8-7df2-4c29-9520-8d3c536ced3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218039100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3218039100
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1472961987
Short name T172
Test name
Test status
Simulation time 132554509 ps
CPU time 1.89 seconds
Started Jan 17 12:59:06 PM PST 24
Finished Jan 17 12:59:08 PM PST 24
Peak memory 218208 kb
Host smart-c17dd934-395a-41fc-bd59-b7a45c9b72d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472961987 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1472961987
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1456516588
Short name T421
Test name
Test status
Simulation time 51032327 ps
CPU time 1.51 seconds
Started Jan 17 12:59:15 PM PST 24
Finished Jan 17 12:59:19 PM PST 24
Peak memory 215956 kb
Host smart-d782a953-0bd1-4bb8-9b2b-73a690d2356f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456516588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1456516588
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.719790982
Short name T162
Test name
Test status
Simulation time 91029176 ps
CPU time 1.67 seconds
Started Jan 17 12:59:20 PM PST 24
Finished Jan 17 12:59:28 PM PST 24
Peak memory 215872 kb
Host smart-8f35c7b6-1723-4209-9499-b9e87c69fe80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719790982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.719790982
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3741241882
Short name T395
Test name
Test status
Simulation time 256215743 ps
CPU time 5.24 seconds
Started Jan 17 12:59:05 PM PST 24
Finished Jan 17 12:59:11 PM PST 24
Peak memory 216196 kb
Host smart-39dbec5c-6bee-4f69-8a62-e88990ca6a18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741241882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3741241882
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2405545797
Short name T434
Test name
Test status
Simulation time 2349805269 ps
CPU time 14.39 seconds
Started Jan 17 12:59:07 PM PST 24
Finished Jan 17 12:59:22 PM PST 24
Peak memory 216044 kb
Host smart-8a657888-fa68-4235-b82f-f9199d3e706b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405545797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2405545797
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1524013893
Short name T373
Test name
Test status
Simulation time 73975273 ps
CPU time 2.43 seconds
Started Jan 17 12:59:11 PM PST 24
Finished Jan 17 12:59:16 PM PST 24
Peak memory 219540 kb
Host smart-6e18d8ec-1fda-4420-98c5-16df0d7445a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524013893 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1524013893
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2085818459
Short name T462
Test name
Test status
Simulation time 430366357 ps
CPU time 2.59 seconds
Started Jan 17 12:59:06 PM PST 24
Finished Jan 17 12:59:09 PM PST 24
Peak memory 207632 kb
Host smart-e06a484e-4da8-43a8-ad9b-37f04745710e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085818459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2085818459
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2026627604
Short name T446
Test name
Test status
Simulation time 50305169 ps
CPU time 0.73 seconds
Started Jan 17 12:59:15 PM PST 24
Finished Jan 17 12:59:18 PM PST 24
Peak memory 204984 kb
Host smart-d502dfab-bb3a-4e4f-a612-e12da91d16c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026627604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2026627604
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1900360817
Short name T372
Test name
Test status
Simulation time 442912162 ps
CPU time 3.25 seconds
Started Jan 17 12:59:14 PM PST 24
Finished Jan 17 12:59:20 PM PST 24
Peak memory 217156 kb
Host smart-0a2bdeb0-6815-4854-b120-b0c2c9dda721
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900360817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1900360817
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1105755383
Short name T411
Test name
Test status
Simulation time 106563890 ps
CPU time 3.47 seconds
Started Jan 17 12:59:12 PM PST 24
Finished Jan 17 12:59:17 PM PST 24
Peak memory 216184 kb
Host smart-2444eca2-2fcc-4eb1-b221-c38447b03d48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105755383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1105755383
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.464049136
Short name T458
Test name
Test status
Simulation time 1519691398 ps
CPU time 9.01 seconds
Started Jan 17 12:59:07 PM PST 24
Finished Jan 17 12:59:17 PM PST 24
Peak memory 216048 kb
Host smart-170ed163-47a9-41e5-9bdd-e48541522edd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464049136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.464049136
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.956445721
Short name T426
Test name
Test status
Simulation time 70359571 ps
CPU time 2.28 seconds
Started Jan 17 12:59:14 PM PST 24
Finished Jan 17 12:59:19 PM PST 24
Peak memory 219860 kb
Host smart-668fe312-e8de-465a-b333-7947b519f714
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956445721 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.956445721
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.138639575
Short name T163
Test name
Test status
Simulation time 272265314 ps
CPU time 2.19 seconds
Started Jan 17 12:59:05 PM PST 24
Finished Jan 17 12:59:08 PM PST 24
Peak memory 215948 kb
Host smart-59002e33-66cc-4b50-a4aa-a6f65a9d4a0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138639575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.138639575
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.406409252
Short name T427
Test name
Test status
Simulation time 12922236 ps
CPU time 0.7 seconds
Started Jan 17 12:59:15 PM PST 24
Finished Jan 17 12:59:18 PM PST 24
Peak memory 204948 kb
Host smart-0e5e789c-9d90-4581-af48-2ca9ec8b419f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406409252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.406409252
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2758383154
Short name T453
Test name
Test status
Simulation time 186600000 ps
CPU time 4.12 seconds
Started Jan 17 12:59:17 PM PST 24
Finished Jan 17 12:59:29 PM PST 24
Peak memory 215996 kb
Host smart-8d6081f6-9d9d-4b5c-a3d2-7d4881b93546
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758383154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2758383154
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.215967540
Short name T389
Test name
Test status
Simulation time 87999882 ps
CPU time 2.54 seconds
Started Jan 17 12:59:22 PM PST 24
Finished Jan 17 12:59:29 PM PST 24
Peak memory 216072 kb
Host smart-e72bc446-0268-439a-8c4c-2b666dfa7fb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215967540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.215967540
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2168828608
Short name T460
Test name
Test status
Simulation time 570816122 ps
CPU time 8.5 seconds
Started Jan 17 12:59:08 PM PST 24
Finished Jan 17 12:59:18 PM PST 24
Peak memory 215912 kb
Host smart-a891c831-a5ca-4878-b008-fb4d3b59fe2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168828608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2168828608
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4125120662
Short name T175
Test name
Test status
Simulation time 145588908 ps
CPU time 2.19 seconds
Started Jan 17 12:59:24 PM PST 24
Finished Jan 17 12:59:29 PM PST 24
Peak memory 218340 kb
Host smart-e57b9e32-c056-4ac8-9db3-799e00bffd7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125120662 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4125120662
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3721190736
Short name T452
Test name
Test status
Simulation time 60453275 ps
CPU time 1.85 seconds
Started Jan 17 12:59:14 PM PST 24
Finished Jan 17 12:59:18 PM PST 24
Peak memory 207712 kb
Host smart-999a6138-9746-4f63-a681-bc4cf482d07a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721190736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3721190736
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1348156963
Short name T189
Test name
Test status
Simulation time 15849520 ps
CPU time 0.71 seconds
Started Jan 17 12:59:17 PM PST 24
Finished Jan 17 12:59:19 PM PST 24
Peak memory 204984 kb
Host smart-9d4e0510-2470-4695-9b1c-c07be5be49ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348156963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1348156963
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2920604504
Short name T149
Test name
Test status
Simulation time 113763944 ps
CPU time 1.89 seconds
Started Jan 17 12:59:13 PM PST 24
Finished Jan 17 12:59:17 PM PST 24
Peak memory 215984 kb
Host smart-07d3459f-791f-40ef-8a1c-273b735a206c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920604504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2920604504
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2467114701
Short name T115
Test name
Test status
Simulation time 105135682 ps
CPU time 2.46 seconds
Started Jan 17 12:59:15 PM PST 24
Finished Jan 17 12:59:20 PM PST 24
Peak memory 216196 kb
Host smart-49eb9c27-e321-4c60-b488-56f0d0387567
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467114701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2467114701
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4037972140
Short name T403
Test name
Test status
Simulation time 726964438 ps
CPU time 15.73 seconds
Started Jan 17 12:59:13 PM PST 24
Finished Jan 17 12:59:31 PM PST 24
Peak memory 216040 kb
Host smart-5d46d80d-8317-4ddc-9474-7ec4d0f7409d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037972140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.4037972140
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.327632250
Short name T471
Test name
Test status
Simulation time 66218882 ps
CPU time 1.46 seconds
Started Jan 17 12:59:17 PM PST 24
Finished Jan 17 12:59:19 PM PST 24
Peak memory 217428 kb
Host smart-3dc36af2-108a-4b8b-90ed-a57d465b8087
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327632250 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.327632250
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.173397053
Short name T145
Test name
Test status
Simulation time 21173789 ps
CPU time 1.32 seconds
Started Jan 17 12:59:22 PM PST 24
Finished Jan 17 12:59:28 PM PST 24
Peak memory 207668 kb
Host smart-fbfe6485-b829-4a38-9266-c25c71bb48ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173397053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.173397053
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1828159311
Short name T69
Test name
Test status
Simulation time 17040837 ps
CPU time 0.75 seconds
Started Jan 17 12:59:15 PM PST 24
Finished Jan 17 12:59:18 PM PST 24
Peak memory 205032 kb
Host smart-202e818e-2a5c-4ca2-b07e-96df57cb0f7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828159311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1828159311
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2678189284
Short name T137
Test name
Test status
Simulation time 283040507 ps
CPU time 2.01 seconds
Started Jan 17 12:59:15 PM PST 24
Finished Jan 17 12:59:19 PM PST 24
Peak memory 215912 kb
Host smart-e15ca317-31f6-499e-9ae0-c27cd6b8903b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678189284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2678189284
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3662428653
Short name T120
Test name
Test status
Simulation time 269410585 ps
CPU time 6 seconds
Started Jan 17 12:59:18 PM PST 24
Finished Jan 17 12:59:31 PM PST 24
Peak memory 216224 kb
Host smart-0a63523a-647a-4489-9de8-3da81ac92eac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662428653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3662428653
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2384039322
Short name T161
Test name
Test status
Simulation time 1901617822 ps
CPU time 10.51 seconds
Started Jan 17 12:58:32 PM PST 24
Finished Jan 17 12:58:45 PM PST 24
Peak memory 207692 kb
Host smart-eac5be95-efaf-4975-af11-741175903900
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384039322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2384039322
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3414030357
Short name T155
Test name
Test status
Simulation time 2072599336 ps
CPU time 28.89 seconds
Started Jan 17 12:58:24 PM PST 24
Finished Jan 17 12:58:53 PM PST 24
Peak memory 207756 kb
Host smart-4b5b7a9e-f871-4793-8ae5-210690554dd8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414030357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3414030357
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2188233915
Short name T445
Test name
Test status
Simulation time 111968177 ps
CPU time 1.23 seconds
Started Jan 17 12:58:28 PM PST 24
Finished Jan 17 12:58:30 PM PST 24
Peak memory 207732 kb
Host smart-c9398557-ccc7-4cdd-a241-5c29fb26fea8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188233915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2188233915
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1777117720
Short name T415
Test name
Test status
Simulation time 31297259 ps
CPU time 2 seconds
Started Jan 17 12:58:28 PM PST 24
Finished Jan 17 12:58:30 PM PST 24
Peak memory 217728 kb
Host smart-567b0512-5e6b-4932-885a-ccf0b3e87043
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777117720 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1777117720
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1870971707
Short name T375
Test name
Test status
Simulation time 92747369 ps
CPU time 2.53 seconds
Started Jan 17 12:58:33 PM PST 24
Finished Jan 17 12:58:38 PM PST 24
Peak memory 215988 kb
Host smart-9271685c-2c0a-4360-b33d-aadf321d7a56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870971707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
870971707
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3558478246
Short name T423
Test name
Test status
Simulation time 62914366 ps
CPU time 0.7 seconds
Started Jan 17 12:58:32 PM PST 24
Finished Jan 17 12:58:35 PM PST 24
Peak memory 205004 kb
Host smart-3a8c8af6-84a9-428b-aecd-9977dff80dc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558478246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
558478246
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2849610998
Short name T159
Test name
Test status
Simulation time 74464120 ps
CPU time 7.83 seconds
Started Jan 17 12:58:28 PM PST 24
Finished Jan 17 12:58:37 PM PST 24
Peak memory 216000 kb
Host smart-7ed661f4-ae57-45f3-b870-2b2f42064e97
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849610998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2849610998
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1496636751
Short name T138
Test name
Test status
Simulation time 545027595 ps
CPU time 10.12 seconds
Started Jan 17 12:58:27 PM PST 24
Finished Jan 17 12:58:38 PM PST 24
Peak memory 215988 kb
Host smart-c146ef16-1211-4f6c-a4e0-c739eab3a556
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496636751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1496636751
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2982822183
Short name T368
Test name
Test status
Simulation time 50573243 ps
CPU time 1.78 seconds
Started Jan 17 12:58:29 PM PST 24
Finished Jan 17 12:58:32 PM PST 24
Peak memory 215944 kb
Host smart-00c95e2f-a4a3-4193-be9b-c42d942c48a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982822183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2982822183
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1598954697
Short name T419
Test name
Test status
Simulation time 132754542 ps
CPU time 1.48 seconds
Started Jan 17 12:58:29 PM PST 24
Finished Jan 17 12:58:31 PM PST 24
Peak memory 216052 kb
Host smart-1cdb1df7-dce4-4ac1-a65f-1ed31d29009c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598954697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
598954697
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2780404857
Short name T469
Test name
Test status
Simulation time 773892986 ps
CPU time 15.38 seconds
Started Jan 17 12:58:33 PM PST 24
Finished Jan 17 12:58:51 PM PST 24
Peak memory 224008 kb
Host smart-bb109ecf-ba2c-4507-9532-8d7d407cf823
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780404857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2780404857
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2536393379
Short name T473
Test name
Test status
Simulation time 20321597 ps
CPU time 0.73 seconds
Started Jan 17 12:59:22 PM PST 24
Finished Jan 17 12:59:27 PM PST 24
Peak memory 204920 kb
Host smart-c44048af-b924-40e8-bd07-6ece1b396151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536393379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2536393379
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2040663536
Short name T379
Test name
Test status
Simulation time 16212378 ps
CPU time 0.7 seconds
Started Jan 17 12:59:24 PM PST 24
Finished Jan 17 12:59:27 PM PST 24
Peak memory 205004 kb
Host smart-38f2ad92-aaff-4c32-9d66-df94e02372ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040663536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2040663536
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1387625066
Short name T428
Test name
Test status
Simulation time 18849846 ps
CPU time 0.76 seconds
Started Jan 17 12:59:21 PM PST 24
Finished Jan 17 12:59:27 PM PST 24
Peak memory 205028 kb
Host smart-23da692c-fb33-4d55-a54c-a722698ccc8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387625066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1387625066
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3100530053
Short name T176
Test name
Test status
Simulation time 24768992 ps
CPU time 0.77 seconds
Started Jan 17 12:59:21 PM PST 24
Finished Jan 17 12:59:27 PM PST 24
Peak memory 204956 kb
Host smart-ea713df2-67bd-45db-b207-d36030d41a51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100530053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3100530053
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.956882046
Short name T463
Test name
Test status
Simulation time 46910407 ps
CPU time 0.75 seconds
Started Jan 17 12:59:23 PM PST 24
Finished Jan 17 12:59:27 PM PST 24
Peak memory 205048 kb
Host smart-e4f3f4a1-202e-4ffa-b35b-1706621f805c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956882046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.956882046
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2276278640
Short name T376
Test name
Test status
Simulation time 14290771 ps
CPU time 0.71 seconds
Started Jan 17 12:59:22 PM PST 24
Finished Jan 17 12:59:27 PM PST 24
Peak memory 205024 kb
Host smart-0bd608e6-946a-44d5-a68e-03e1370e9c78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276278640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2276278640
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4292272487
Short name T455
Test name
Test status
Simulation time 43485344 ps
CPU time 0.76 seconds
Started Jan 17 12:59:19 PM PST 24
Finished Jan 17 12:59:27 PM PST 24
Peak memory 205288 kb
Host smart-002fd292-d11c-4f25-8279-add3e974c2b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292272487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
4292272487
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1565643372
Short name T398
Test name
Test status
Simulation time 14025777 ps
CPU time 0.72 seconds
Started Jan 17 12:59:23 PM PST 24
Finished Jan 17 12:59:27 PM PST 24
Peak memory 204956 kb
Host smart-061a073e-d1e2-4ea7-ac84-23615c1a2806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565643372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1565643372
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3606187846
Short name T456
Test name
Test status
Simulation time 39762096 ps
CPU time 0.79 seconds
Started Jan 17 12:59:25 PM PST 24
Finished Jan 17 12:59:27 PM PST 24
Peak memory 205064 kb
Host smart-0902b9cf-937c-4538-9b0f-ab6e51d48245
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606187846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3606187846
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3616861185
Short name T438
Test name
Test status
Simulation time 780799416 ps
CPU time 9.91 seconds
Started Jan 17 12:58:31 PM PST 24
Finished Jan 17 12:58:41 PM PST 24
Peak memory 217076 kb
Host smart-d4416cd8-ad98-429b-ad98-0b02d3865818
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616861185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3616861185
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3577338638
Short name T365
Test name
Test status
Simulation time 732013500 ps
CPU time 26.16 seconds
Started Jan 17 12:58:30 PM PST 24
Finished Jan 17 12:58:57 PM PST 24
Peak memory 207720 kb
Host smart-60fc5723-e65b-47b6-a99f-a5c879cdbfbc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577338638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3577338638
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3034921066
Short name T444
Test name
Test status
Simulation time 127740198 ps
CPU time 0.94 seconds
Started Jan 17 12:58:34 PM PST 24
Finished Jan 17 12:58:38 PM PST 24
Peak memory 207592 kb
Host smart-e575334d-3c24-4613-8b1b-1afac84b7bbe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034921066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3034921066
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2300825960
Short name T150
Test name
Test status
Simulation time 144696687 ps
CPU time 1.94 seconds
Started Jan 17 12:58:33 PM PST 24
Finished Jan 17 12:58:37 PM PST 24
Peak memory 217772 kb
Host smart-0a909fc1-a013-4274-a3e5-d10d9b77f5bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300825960 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2300825960
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.861060194
Short name T71
Test name
Test status
Simulation time 136109539 ps
CPU time 1.75 seconds
Started Jan 17 12:58:31 PM PST 24
Finished Jan 17 12:58:33 PM PST 24
Peak memory 215924 kb
Host smart-e1b60f2f-ae20-49f0-90f3-1b6f5fc80cae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861060194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.861060194
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2637562443
Short name T401
Test name
Test status
Simulation time 52293629 ps
CPU time 0.77 seconds
Started Jan 17 12:58:28 PM PST 24
Finished Jan 17 12:58:29 PM PST 24
Peak memory 204928 kb
Host smart-a548dfcb-c69c-4e46-9856-aa38d4ea1309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637562443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
637562443
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1821387069
Short name T457
Test name
Test status
Simulation time 79134027 ps
CPU time 2.59 seconds
Started Jan 17 12:58:29 PM PST 24
Finished Jan 17 12:58:32 PM PST 24
Peak memory 215936 kb
Host smart-cb79e4a7-13da-41cc-8c8f-44a19872bd50
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821387069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1821387069
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.888176076
Short name T364
Test name
Test status
Simulation time 3908119637 ps
CPU time 15.97 seconds
Started Jan 17 12:58:32 PM PST 24
Finished Jan 17 12:58:50 PM PST 24
Peak memory 215964 kb
Host smart-b0fe9380-1624-4f21-b8ac-6842f029db11
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888176076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.888176076
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1318797908
Short name T422
Test name
Test status
Simulation time 176661482 ps
CPU time 4.32 seconds
Started Jan 17 12:58:32 PM PST 24
Finished Jan 17 12:58:37 PM PST 24
Peak memory 215924 kb
Host smart-9ce2ad1e-a6a9-4bfd-aba3-a9c5913b6683
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318797908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1318797908
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2522010164
Short name T383
Test name
Test status
Simulation time 52058413 ps
CPU time 4.1 seconds
Started Jan 17 12:58:27 PM PST 24
Finished Jan 17 12:58:31 PM PST 24
Peak memory 215976 kb
Host smart-3a5df978-0017-4c7d-a507-c1cac34dce4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522010164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
522010164
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2994017370
Short name T139
Test name
Test status
Simulation time 1234701063 ps
CPU time 8.69 seconds
Started Jan 17 12:58:27 PM PST 24
Finished Jan 17 12:58:36 PM PST 24
Peak memory 215864 kb
Host smart-cbdfc545-1522-4145-8ebd-bb25fd613bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994017370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2994017370
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1610288096
Short name T443
Test name
Test status
Simulation time 12988505 ps
CPU time 0.78 seconds
Started Jan 17 12:59:23 PM PST 24
Finished Jan 17 12:59:27 PM PST 24
Peak memory 205028 kb
Host smart-f6440c5d-1445-4923-97a3-6ef4063ece69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610288096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1610288096
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3292969272
Short name T192
Test name
Test status
Simulation time 14681173 ps
CPU time 0.73 seconds
Started Jan 17 12:59:22 PM PST 24
Finished Jan 17 12:59:27 PM PST 24
Peak memory 205028 kb
Host smart-f3958f0d-3f72-4469-a436-6d8bddabd290
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292969272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3292969272
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2877874715
Short name T404
Test name
Test status
Simulation time 18874333 ps
CPU time 0.78 seconds
Started Jan 17 12:59:23 PM PST 24
Finished Jan 17 12:59:27 PM PST 24
Peak memory 205020 kb
Host smart-6fb2c618-2b27-4d2a-9f81-89159bc3a066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877874715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2877874715
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2514839958
Short name T416
Test name
Test status
Simulation time 46668566 ps
CPU time 0.76 seconds
Started Jan 17 12:59:23 PM PST 24
Finished Jan 17 12:59:27 PM PST 24
Peak memory 204996 kb
Host smart-bc90bacc-35e9-4f60-914e-b839306d5df3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514839958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2514839958
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.500742673
Short name T412
Test name
Test status
Simulation time 44874441 ps
CPU time 0.7 seconds
Started Jan 17 12:59:38 PM PST 24
Finished Jan 17 12:59:39 PM PST 24
Peak memory 205000 kb
Host smart-bb2f7e15-3d11-4a7d-8094-a7d64babb4b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500742673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.500742673
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1214200201
Short name T190
Test name
Test status
Simulation time 14427013 ps
CPU time 0.74 seconds
Started Jan 17 12:59:30 PM PST 24
Finished Jan 17 12:59:32 PM PST 24
Peak memory 205032 kb
Host smart-c15b0d39-ab21-4a53-a329-47b59f1f3662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214200201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1214200201
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.449305588
Short name T432
Test name
Test status
Simulation time 51189431 ps
CPU time 0.72 seconds
Started Jan 17 12:59:29 PM PST 24
Finished Jan 17 12:59:31 PM PST 24
Peak memory 205028 kb
Host smart-1480ea45-8c4c-4f66-92ad-dccfef9fa714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449305588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.449305588
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2283318747
Short name T454
Test name
Test status
Simulation time 15176381 ps
CPU time 0.75 seconds
Started Jan 17 12:59:38 PM PST 24
Finished Jan 17 12:59:40 PM PST 24
Peak memory 205008 kb
Host smart-535c1398-1cc5-4b1e-a5b4-c2f35f2fe733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283318747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2283318747
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3844442415
Short name T435
Test name
Test status
Simulation time 938288976 ps
CPU time 9.29 seconds
Started Jan 17 12:58:38 PM PST 24
Finished Jan 17 12:58:48 PM PST 24
Peak memory 207628 kb
Host smart-7672060a-046e-4e44-a76e-594c55ff215a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844442415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3844442415
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1950719910
Short name T157
Test name
Test status
Simulation time 2002447235 ps
CPU time 29.45 seconds
Started Jan 17 12:58:37 PM PST 24
Finished Jan 17 12:59:08 PM PST 24
Peak memory 215980 kb
Host smart-e1bafffc-7c11-43a5-bfce-742d2b5ef926
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950719910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1950719910
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3281729980
Short name T160
Test name
Test status
Simulation time 27736460 ps
CPU time 1.04 seconds
Started Jan 17 12:58:34 PM PST 24
Finished Jan 17 12:58:38 PM PST 24
Peak memory 207624 kb
Host smart-34b9ad4a-093e-4c2c-bd7e-858b11fdec1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281729980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3281729980
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.785600273
Short name T178
Test name
Test status
Simulation time 22829171 ps
CPU time 1.38 seconds
Started Jan 17 12:58:37 PM PST 24
Finished Jan 17 12:58:40 PM PST 24
Peak memory 217420 kb
Host smart-5d0d70d3-8245-4483-b3a8-9165a2a3a1d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785600273 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.785600273
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2255078932
Short name T147
Test name
Test status
Simulation time 306477771 ps
CPU time 2.48 seconds
Started Jan 17 12:58:31 PM PST 24
Finished Jan 17 12:58:34 PM PST 24
Peak memory 215980 kb
Host smart-0bbbfd85-68c8-449c-9788-10de2ecf57d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255078932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
255078932
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1569789975
Short name T68
Test name
Test status
Simulation time 14250701 ps
CPU time 0.73 seconds
Started Jan 17 12:58:32 PM PST 24
Finished Jan 17 12:58:34 PM PST 24
Peak memory 205020 kb
Host smart-dec4f19d-3b21-48af-9e45-dff9bdb76312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569789975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
569789975
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2386619621
Short name T405
Test name
Test status
Simulation time 207996168 ps
CPU time 7.29 seconds
Started Jan 17 12:58:30 PM PST 24
Finished Jan 17 12:58:38 PM PST 24
Peak memory 215948 kb
Host smart-7ba83ea9-0325-4ecb-b39c-08c038f5f390
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386619621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2386619621
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.531624577
Short name T450
Test name
Test status
Simulation time 1326724200 ps
CPU time 6.21 seconds
Started Jan 17 12:58:27 PM PST 24
Finished Jan 17 12:58:34 PM PST 24
Peak memory 215908 kb
Host smart-9b6606b6-f0ea-4980-8ae2-4fd197fd2cc3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531624577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.531624577
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3014804090
Short name T447
Test name
Test status
Simulation time 162373415 ps
CPU time 3.37 seconds
Started Jan 17 12:58:36 PM PST 24
Finished Jan 17 12:58:42 PM PST 24
Peak memory 215928 kb
Host smart-905d9b7c-e464-42ce-8012-6739e67f2351
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014804090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3014804090
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3105862186
Short name T140
Test name
Test status
Simulation time 66137012 ps
CPU time 2.15 seconds
Started Jan 17 12:58:29 PM PST 24
Finished Jan 17 12:58:32 PM PST 24
Peak memory 216108 kb
Host smart-4b1356dc-fc0f-4811-ada5-8729e6e05d86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105862186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
105862186
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3584170782
Short name T203
Test name
Test status
Simulation time 410526340 ps
CPU time 13.08 seconds
Started Jan 17 12:58:31 PM PST 24
Finished Jan 17 12:58:44 PM PST 24
Peak memory 215976 kb
Host smart-3d23151f-171d-4dfa-a3c5-cbbea039cdc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584170782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3584170782
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4236050446
Short name T387
Test name
Test status
Simulation time 95410982 ps
CPU time 0.7 seconds
Started Jan 17 12:59:30 PM PST 24
Finished Jan 17 12:59:32 PM PST 24
Peak memory 205008 kb
Host smart-b9fa2c86-a70d-42cf-b417-087d60a20646
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236050446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
4236050446
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1185122732
Short name T437
Test name
Test status
Simulation time 42736808 ps
CPU time 0.71 seconds
Started Jan 17 12:59:31 PM PST 24
Finished Jan 17 12:59:33 PM PST 24
Peak memory 205028 kb
Host smart-ebfd4152-40e3-4730-852e-51b7c2d9f0dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185122732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1185122732
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.558174277
Short name T393
Test name
Test status
Simulation time 14789863 ps
CPU time 0.71 seconds
Started Jan 17 12:59:30 PM PST 24
Finished Jan 17 12:59:32 PM PST 24
Peak memory 204988 kb
Host smart-6b18bcac-9abf-45f4-a6d9-af00d009c125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558174277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.558174277
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4036512960
Short name T390
Test name
Test status
Simulation time 14753838 ps
CPU time 0.76 seconds
Started Jan 17 12:59:30 PM PST 24
Finished Jan 17 12:59:33 PM PST 24
Peak memory 205028 kb
Host smart-2f1001f5-63f5-41a8-a75b-cdb2998ce804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036512960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
4036512960
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2352731301
Short name T417
Test name
Test status
Simulation time 16764742 ps
CPU time 0.72 seconds
Started Jan 17 12:59:29 PM PST 24
Finished Jan 17 12:59:31 PM PST 24
Peak memory 205004 kb
Host smart-648f2084-0bde-4ca1-8e9b-51a2177dec63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352731301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2352731301
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1002860660
Short name T135
Test name
Test status
Simulation time 54786469 ps
CPU time 0.78 seconds
Started Jan 17 12:59:33 PM PST 24
Finished Jan 17 12:59:35 PM PST 24
Peak memory 205028 kb
Host smart-ea3225f3-a510-4e86-8fc4-c4d0a016a1ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002860660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1002860660
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.579934543
Short name T420
Test name
Test status
Simulation time 46577780 ps
CPU time 0.82 seconds
Started Jan 17 12:59:33 PM PST 24
Finished Jan 17 12:59:35 PM PST 24
Peak memory 205040 kb
Host smart-301f7f0d-98f5-4ba7-b890-a242b0aa5a01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579934543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.579934543
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3341064285
Short name T442
Test name
Test status
Simulation time 14170132 ps
CPU time 0.75 seconds
Started Jan 17 12:59:30 PM PST 24
Finished Jan 17 12:59:32 PM PST 24
Peak memory 205012 kb
Host smart-683a8766-9bf6-4a79-b11e-811ac8e07a35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341064285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3341064285
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1536765164
Short name T408
Test name
Test status
Simulation time 19402671 ps
CPU time 0.74 seconds
Started Jan 17 12:59:30 PM PST 24
Finished Jan 17 12:59:33 PM PST 24
Peak memory 204860 kb
Host smart-25a47f2b-0ce7-430f-9815-c83cd553b10d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536765164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1536765164
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3968462053
Short name T429
Test name
Test status
Simulation time 13504660 ps
CPU time 0.73 seconds
Started Jan 17 12:59:30 PM PST 24
Finished Jan 17 12:59:33 PM PST 24
Peak memory 204856 kb
Host smart-884dccaa-de68-46a3-8ab6-fbc79f82210c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968462053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3968462053
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2457369499
Short name T382
Test name
Test status
Simulation time 74290709 ps
CPU time 1.8 seconds
Started Jan 17 12:58:36 PM PST 24
Finished Jan 17 12:58:40 PM PST 24
Peak memory 217564 kb
Host smart-f7974c48-8adc-4c1a-b591-d067082fb4f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457369499 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2457369499
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3377676575
Short name T152
Test name
Test status
Simulation time 168713337 ps
CPU time 2.52 seconds
Started Jan 17 12:58:36 PM PST 24
Finished Jan 17 12:58:41 PM PST 24
Peak memory 216056 kb
Host smart-5ab89d3c-79fe-4687-911d-e70a25f61be1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377676575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
377676575
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2638958669
Short name T371
Test name
Test status
Simulation time 14269757 ps
CPU time 0.74 seconds
Started Jan 17 12:58:37 PM PST 24
Finished Jan 17 12:58:40 PM PST 24
Peak memory 205028 kb
Host smart-9ff286a0-1227-4fa3-a4d6-306466288a9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638958669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
638958669
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3201733840
Short name T413
Test name
Test status
Simulation time 597446176 ps
CPU time 3.36 seconds
Started Jan 17 12:58:37 PM PST 24
Finished Jan 17 12:58:42 PM PST 24
Peak memory 215996 kb
Host smart-42052fb6-26f0-42f6-a137-4d4f47df478a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201733840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3201733840
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3119603465
Short name T410
Test name
Test status
Simulation time 246822127 ps
CPU time 6.64 seconds
Started Jan 17 12:58:32 PM PST 24
Finished Jan 17 12:58:41 PM PST 24
Peak memory 215992 kb
Host smart-63bdb9e5-1a3d-4c40-9be4-fcf01ce2d2df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119603465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3119603465
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1728246481
Short name T177
Test name
Test status
Simulation time 87903331 ps
CPU time 1.47 seconds
Started Jan 17 12:58:35 PM PST 24
Finished Jan 17 12:58:40 PM PST 24
Peak memory 217268 kb
Host smart-4355a06d-790d-4e17-8a30-510015e843a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728246481 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1728246481
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1521813577
Short name T464
Test name
Test status
Simulation time 382974377 ps
CPU time 2.5 seconds
Started Jan 17 12:58:35 PM PST 24
Finished Jan 17 12:58:41 PM PST 24
Peak memory 207728 kb
Host smart-35524472-b3ab-4de8-976f-ab2e3f6a1d44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521813577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
521813577
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.819738754
Short name T436
Test name
Test status
Simulation time 85283707 ps
CPU time 0.74 seconds
Started Jan 17 12:58:34 PM PST 24
Finished Jan 17 12:58:38 PM PST 24
Peak memory 205044 kb
Host smart-b7ed71f7-ef53-416c-90f6-0611e3120332
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819738754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.819738754
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2313893594
Short name T459
Test name
Test status
Simulation time 226556320 ps
CPU time 1.94 seconds
Started Jan 17 12:58:34 PM PST 24
Finished Jan 17 12:58:39 PM PST 24
Peak memory 217116 kb
Host smart-125a7458-eeb9-488a-a18e-23fca7922a96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313893594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2313893594
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3340451894
Short name T121
Test name
Test status
Simulation time 385311838 ps
CPU time 4.24 seconds
Started Jan 17 12:58:37 PM PST 24
Finished Jan 17 12:58:43 PM PST 24
Peak memory 216072 kb
Host smart-772299bb-3f86-49b9-b624-dee8d54f3d37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340451894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
340451894
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1696015075
Short name T424
Test name
Test status
Simulation time 211272662 ps
CPU time 6.74 seconds
Started Jan 17 12:58:38 PM PST 24
Finished Jan 17 12:58:46 PM PST 24
Peak memory 215956 kb
Host smart-3fb67db6-3b06-48b0-bd44-a6e375f3c21d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696015075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1696015075
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.166175962
Short name T441
Test name
Test status
Simulation time 28272006 ps
CPU time 1.54 seconds
Started Jan 17 12:58:41 PM PST 24
Finished Jan 17 12:58:48 PM PST 24
Peak memory 217456 kb
Host smart-ee6b1c65-161f-476e-9199-0777cf51a9cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166175962 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.166175962
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3718381223
Short name T370
Test name
Test status
Simulation time 97158978 ps
CPU time 1.9 seconds
Started Jan 17 12:58:38 PM PST 24
Finished Jan 17 12:58:41 PM PST 24
Peak memory 215904 kb
Host smart-a65af7d8-b5b9-4bc4-a711-8740b8750cd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718381223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
718381223
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1743016142
Short name T409
Test name
Test status
Simulation time 50410971 ps
CPU time 0.72 seconds
Started Jan 17 12:58:41 PM PST 24
Finished Jan 17 12:58:47 PM PST 24
Peak memory 204884 kb
Host smart-807ccc26-d51e-48eb-9a13-c55e8bec7895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743016142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
743016142
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3938377366
Short name T430
Test name
Test status
Simulation time 90284845 ps
CPU time 2.91 seconds
Started Jan 17 12:58:42 PM PST 24
Finished Jan 17 12:58:50 PM PST 24
Peak memory 215980 kb
Host smart-2c0a5bfc-133e-4c33-be78-9b768733bc5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938377366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3938377366
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.587875799
Short name T439
Test name
Test status
Simulation time 27697479 ps
CPU time 1.9 seconds
Started Jan 17 12:58:36 PM PST 24
Finished Jan 17 12:58:40 PM PST 24
Peak memory 215980 kb
Host smart-b608a470-9b43-46d2-9a55-ad44cf68bae3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587875799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.587875799
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1210875550
Short name T84
Test name
Test status
Simulation time 1077132659 ps
CPU time 14.7 seconds
Started Jan 17 12:58:41 PM PST 24
Finished Jan 17 12:59:01 PM PST 24
Peak memory 215836 kb
Host smart-0bd552b0-a109-4d81-a0a5-5c41c86bf7e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210875550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1210875550
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3889923437
Short name T380
Test name
Test status
Simulation time 126130141 ps
CPU time 2.31 seconds
Started Jan 17 12:58:37 PM PST 24
Finished Jan 17 12:58:41 PM PST 24
Peak memory 218692 kb
Host smart-b8af0e92-361a-49c5-ba46-2c2f8d083282
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889923437 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3889923437
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1766226705
Short name T385
Test name
Test status
Simulation time 164516028 ps
CPU time 2.57 seconds
Started Jan 17 12:58:41 PM PST 24
Finished Jan 17 12:58:49 PM PST 24
Peak memory 215836 kb
Host smart-46b7c8b9-2be8-4c94-94bf-bf9c10ffbca9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766226705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
766226705
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1818211153
Short name T440
Test name
Test status
Simulation time 14090217 ps
CPU time 0.78 seconds
Started Jan 17 12:58:40 PM PST 24
Finished Jan 17 12:58:47 PM PST 24
Peak memory 204928 kb
Host smart-84639420-b491-48bc-a324-ac69c9c3ccbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818211153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
818211153
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.404129998
Short name T392
Test name
Test status
Simulation time 87658426 ps
CPU time 3.03 seconds
Started Jan 17 12:58:40 PM PST 24
Finished Jan 17 12:58:50 PM PST 24
Peak memory 215936 kb
Host smart-eb0e85ca-e0b4-4db8-a7aa-9e0315138b24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404129998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.404129998
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2883870680
Short name T399
Test name
Test status
Simulation time 1592606979 ps
CPU time 5.65 seconds
Started Jan 17 12:58:36 PM PST 24
Finished Jan 17 12:58:44 PM PST 24
Peak memory 215940 kb
Host smart-ce410fe0-324a-4c65-a5de-2136ea9a23f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883870680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
883870680
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2091436959
Short name T200
Test name
Test status
Simulation time 1219286221 ps
CPU time 15.14 seconds
Started Jan 17 12:58:40 PM PST 24
Finished Jan 17 12:59:02 PM PST 24
Peak memory 216212 kb
Host smart-814b3f37-1a8c-4ca3-b415-d9ecb073dc5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091436959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2091436959
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2723639926
Short name T173
Test name
Test status
Simulation time 48457422 ps
CPU time 1.39 seconds
Started Jan 17 12:58:46 PM PST 24
Finished Jan 17 12:58:48 PM PST 24
Peak memory 217380 kb
Host smart-859c79fd-b489-49b0-9e7d-c727a564318b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723639926 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2723639926
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.375958556
Short name T407
Test name
Test status
Simulation time 34817376 ps
CPU time 1.83 seconds
Started Jan 17 12:58:54 PM PST 24
Finished Jan 17 12:58:57 PM PST 24
Peak memory 220244 kb
Host smart-815876d9-14c6-4dfb-baba-c3c034dde9da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375958556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.375958556
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2651933648
Short name T388
Test name
Test status
Simulation time 24288398 ps
CPU time 0.74 seconds
Started Jan 17 12:58:44 PM PST 24
Finished Jan 17 12:58:47 PM PST 24
Peak memory 205032 kb
Host smart-06b99035-3177-4909-8f97-46dfeeef3742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651933648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
651933648
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3845636209
Short name T397
Test name
Test status
Simulation time 132267824 ps
CPU time 3.95 seconds
Started Jan 17 12:58:47 PM PST 24
Finished Jan 17 12:58:52 PM PST 24
Peak memory 215852 kb
Host smart-c68c47d1-dc48-48e2-9003-c62a340fc909
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845636209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3845636209
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3051867505
Short name T465
Test name
Test status
Simulation time 70814145 ps
CPU time 5.22 seconds
Started Jan 17 12:58:54 PM PST 24
Finished Jan 17 12:59:00 PM PST 24
Peak memory 215916 kb
Host smart-1557c607-0714-4912-9485-6113e47d513c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051867505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
051867505
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1212176944
Short name T202
Test name
Test status
Simulation time 3474115654 ps
CPU time 25.86 seconds
Started Jan 17 12:58:48 PM PST 24
Finished Jan 17 12:59:14 PM PST 24
Peak memory 216108 kb
Host smart-7aecbb24-919a-4764-849e-65c66d7e9c29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212176944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1212176944
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_abort.2550300017
Short name T759
Test name
Test status
Simulation time 39139075 ps
CPU time 0.75 seconds
Started Jan 17 03:28:22 PM PST 24
Finished Jan 17 03:28:23 PM PST 24
Peak memory 206920 kb
Host smart-97992f96-54cf-41b2-b870-bbf17b301509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550300017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_abort.2550300017
Directory /workspace/0.spi_device_abort/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.4198339973
Short name T665
Test name
Test status
Simulation time 21814975 ps
CPU time 0.7 seconds
Started Jan 17 03:28:31 PM PST 24
Finished Jan 17 03:28:35 PM PST 24
Peak memory 206716 kb
Host smart-f36ad856-fbc5-4856-b451-ee0e284d040c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198339973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4
198339973
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_bit_transfer.176034712
Short name T551
Test name
Test status
Simulation time 339502368 ps
CPU time 2.13 seconds
Started Jan 17 03:28:19 PM PST 24
Finished Jan 17 03:28:22 PM PST 24
Peak memory 217172 kb
Host smart-b167195d-5ddb-43b7-bc09-cb294e385cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176034712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_bit_transfer.176034712
Directory /workspace/0.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/0.spi_device_byte_transfer.1453962316
Short name T1038
Test name
Test status
Simulation time 162108340 ps
CPU time 2.49 seconds
Started Jan 17 03:28:17 PM PST 24
Finished Jan 17 03:28:20 PM PST 24
Peak memory 217052 kb
Host smart-566fca08-a474-41b9-b193-86e96d6a24f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453962316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_byte_transfer.1453962316
Directory /workspace/0.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.976466018
Short name T1145
Test name
Test status
Simulation time 470021194 ps
CPU time 3.69 seconds
Started Jan 17 03:28:26 PM PST 24
Finished Jan 17 03:28:31 PM PST 24
Peak memory 238980 kb
Host smart-01b223c4-2e62-418c-9dbb-eda2a5125613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976466018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.976466018
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2856763637
Short name T111
Test name
Test status
Simulation time 35596726 ps
CPU time 0.79 seconds
Started Jan 17 03:28:18 PM PST 24
Finished Jan 17 03:28:19 PM PST 24
Peak memory 207972 kb
Host smart-54040987-c5e9-4bef-b3d4-669b720f75dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856763637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2856763637
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_dummy_item_extra_dly.2613323447
Short name T641
Test name
Test status
Simulation time 64641436910 ps
CPU time 539.7 seconds
Started Jan 17 03:28:21 PM PST 24
Finished Jan 17 03:37:21 PM PST 24
Peak memory 286360 kb
Host smart-6f509ab9-0c67-4a37-90f7-fcc9ee011a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613323447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_dummy_item_extra_dly.2613323447
Directory /workspace/0.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/0.spi_device_extreme_fifo_size.1100128091
Short name T1568
Test name
Test status
Simulation time 229633059898 ps
CPU time 516.69 seconds
Started Jan 17 03:28:21 PM PST 24
Finished Jan 17 03:36:58 PM PST 24
Peak memory 225220 kb
Host smart-ab96cdf9-ad39-41d6-b0e1-ac1b04c3e28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100128091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_extreme_fifo_size.1100128091
Directory /workspace/0.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/0.spi_device_fifo_full.3873296367
Short name T1579
Test name
Test status
Simulation time 114200008824 ps
CPU time 587.41 seconds
Started Jan 17 03:28:12 PM PST 24
Finished Jan 17 03:38:00 PM PST 24
Peak memory 274140 kb
Host smart-6e1c2e1c-a4f6-460f-9b34-e9f912914c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873296367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_fifo_full.3873296367
Directory /workspace/0.spi_device_fifo_full/latest

Test location /workspace/coverage/default/0.spi_device_fifo_underflow_overflow.2059108210
Short name T837
Test name
Test status
Simulation time 171040675386 ps
CPU time 245.76 seconds
Started Jan 17 03:28:10 PM PST 24
Finished Jan 17 03:32:17 PM PST 24
Peak memory 290028 kb
Host smart-db7f4768-61ee-4388-a6c5-4d24d2da1067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059108210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_fifo_underflow_overfl
ow.2059108210
Directory /workspace/0.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3107481207
Short name T195
Test name
Test status
Simulation time 11001527766 ps
CPU time 54.36 seconds
Started Jan 17 03:28:22 PM PST 24
Finished Jan 17 03:29:17 PM PST 24
Peak memory 250044 kb
Host smart-96759d91-eea2-401e-8dbf-7c47973b7215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107481207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3107481207
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3505661019
Short name T1001
Test name
Test status
Simulation time 23653770200 ps
CPU time 80.16 seconds
Started Jan 17 03:28:23 PM PST 24
Finished Jan 17 03:29:45 PM PST 24
Peak memory 263264 kb
Host smart-48f608b1-7761-412b-9bd9-e2999b279fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505661019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3505661019
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2461590922
Short name T730
Test name
Test status
Simulation time 2974545857 ps
CPU time 19.83 seconds
Started Jan 17 03:28:24 PM PST 24
Finished Jan 17 03:28:47 PM PST 24
Peak memory 248024 kb
Host smart-79bfca04-f4fb-414d-b036-411700658c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461590922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2461590922
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1669625
Short name T868
Test name
Test status
Simulation time 1122135366 ps
CPU time 7.02 seconds
Started Jan 17 03:28:26 PM PST 24
Finished Jan 17 03:28:34 PM PST 24
Peak memory 239660 kb
Host smart-298a85b0-5555-4fac-9bab-741d86f39ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1669625
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_intr.3596180682
Short name T1580
Test name
Test status
Simulation time 2961170573 ps
CPU time 23.61 seconds
Started Jan 17 03:28:20 PM PST 24
Finished Jan 17 03:28:44 PM PST 24
Peak memory 240892 kb
Host smart-7ddbd580-7868-4d40-afef-b2cf01ceccce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596180682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intr.3596180682
Directory /workspace/0.spi_device_intr/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4289592203
Short name T214
Test name
Test status
Simulation time 63136202529 ps
CPU time 48.56 seconds
Started Jan 17 03:28:23 PM PST 24
Finished Jan 17 03:29:14 PM PST 24
Peak memory 254936 kb
Host smart-0303c473-faaa-48c6-815b-12d88b54e486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289592203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4289592203
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2504108875
Short name T1249
Test name
Test status
Simulation time 49995311 ps
CPU time 1.08 seconds
Started Jan 17 03:28:19 PM PST 24
Finished Jan 17 03:28:20 PM PST 24
Peak memory 219096 kb
Host smart-e530e812-0640-470b-85cd-f3d963aa08ba
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504108875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2504108875
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1404218387
Short name T338
Test name
Test status
Simulation time 7185493745 ps
CPU time 27.93 seconds
Started Jan 17 03:28:26 PM PST 24
Finished Jan 17 03:28:55 PM PST 24
Peak memory 235288 kb
Host smart-a17f92b5-f85e-47e6-ad15-473f740961be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404218387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1404218387
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1226005488
Short name T1052
Test name
Test status
Simulation time 1515031874 ps
CPU time 10.61 seconds
Started Jan 17 03:28:24 PM PST 24
Finished Jan 17 03:28:37 PM PST 24
Peak memory 221020 kb
Host smart-66b5cbc5-bee3-4b7d-b258-a1285be4b992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226005488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1226005488
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_perf.1427757921
Short name T983
Test name
Test status
Simulation time 40533892710 ps
CPU time 294.97 seconds
Started Jan 17 03:28:19 PM PST 24
Finished Jan 17 03:33:15 PM PST 24
Peak memory 308040 kb
Host smart-d0a89338-aedb-4e54-af26-ece18595f435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427757921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_perf.1427757921
Directory /workspace/0.spi_device_perf/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3004952582
Short name T1460
Test name
Test status
Simulation time 2910642636 ps
CPU time 6.71 seconds
Started Jan 17 03:28:26 PM PST 24
Finished Jan 17 03:28:34 PM PST 24
Peak memory 219300 kb
Host smart-6e6b695f-bf9e-403d-8f85-255426e894c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3004952582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3004952582
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_rx_async_fifo_reset.3012531876
Short name T102
Test name
Test status
Simulation time 53924140 ps
CPU time 0.86 seconds
Started Jan 17 03:28:19 PM PST 24
Finished Jan 17 03:28:20 PM PST 24
Peak memory 208740 kb
Host smart-4f340d77-1577-4a5f-b280-370a011d687f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012531876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_rx_async_fifo_reset.3012531876
Directory /workspace/0.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/0.spi_device_rx_timeout.2728065397
Short name T1431
Test name
Test status
Simulation time 1086989135 ps
CPU time 5.48 seconds
Started Jan 17 03:28:21 PM PST 24
Finished Jan 17 03:28:27 PM PST 24
Peak memory 217088 kb
Host smart-838f97a5-b2d2-45d5-88b6-7ba3654e00d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728065397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_rx_timeout.2728065397
Directory /workspace/0.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/0.spi_device_smoke.1691301992
Short name T1418
Test name
Test status
Simulation time 74021591 ps
CPU time 1.06 seconds
Started Jan 17 03:28:17 PM PST 24
Finished Jan 17 03:28:19 PM PST 24
Peak memory 208332 kb
Host smart-a1d3c10b-93e5-445e-86c3-150d59cb5d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691301992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_smoke.1691301992
Directory /workspace/0.spi_device_smoke/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2030828976
Short name T1767
Test name
Test status
Simulation time 48701828361 ps
CPU time 893.27 seconds
Started Jan 17 03:28:30 PM PST 24
Finished Jan 17 03:43:27 PM PST 24
Peak memory 399756 kb
Host smart-0c1d29d9-25f1-46cd-9b5e-91d279325242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030828976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2030828976
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.470010318
Short name T357
Test name
Test status
Simulation time 9302360969 ps
CPU time 187.29 seconds
Started Jan 17 03:28:17 PM PST 24
Finished Jan 17 03:31:25 PM PST 24
Peak memory 217200 kb
Host smart-18cc5630-2077-4d17-8a1b-e1aa97628619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470010318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.470010318
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1367201556
Short name T941
Test name
Test status
Simulation time 1846627720 ps
CPU time 3.44 seconds
Started Jan 17 03:28:18 PM PST 24
Finished Jan 17 03:28:22 PM PST 24
Peak memory 217144 kb
Host smart-18fb2088-d3e2-4ca2-8f3f-f21fb2ffb55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367201556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1367201556
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2668685259
Short name T794
Test name
Test status
Simulation time 46410830 ps
CPU time 1.65 seconds
Started Jan 17 03:28:24 PM PST 24
Finished Jan 17 03:28:28 PM PST 24
Peak memory 208968 kb
Host smart-a68bae45-7793-4acf-a60a-821f38adb273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668685259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2668685259
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3553396287
Short name T838
Test name
Test status
Simulation time 271365036 ps
CPU time 1.01 seconds
Started Jan 17 03:28:19 PM PST 24
Finished Jan 17 03:28:21 PM PST 24
Peak memory 208632 kb
Host smart-daa7003e-3ef8-4f2b-9c71-8c65d71b4603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553396287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3553396287
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_tx_async_fifo_reset.1813251982
Short name T803
Test name
Test status
Simulation time 47857127 ps
CPU time 0.74 seconds
Started Jan 17 03:28:18 PM PST 24
Finished Jan 17 03:28:20 PM PST 24
Peak memory 208744 kb
Host smart-7224ba6f-c9bd-43f2-9f97-dc0f2beac419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813251982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tx_async_fifo_reset.1813251982
Directory /workspace/0.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/0.spi_device_txrx.1535153708
Short name T1542
Test name
Test status
Simulation time 55137344249 ps
CPU time 517.12 seconds
Started Jan 17 03:28:11 PM PST 24
Finished Jan 17 03:36:49 PM PST 24
Peak memory 250044 kb
Host smart-49e9c5cf-3717-4378-9d57-1fbb6a41a7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535153708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_txrx.1535153708
Directory /workspace/0.spi_device_txrx/latest

Test location /workspace/coverage/default/0.spi_device_upload.1965688032
Short name T855
Test name
Test status
Simulation time 1127180082 ps
CPU time 8.15 seconds
Started Jan 17 03:28:23 PM PST 24
Finished Jan 17 03:28:33 PM PST 24
Peak memory 237716 kb
Host smart-4d7cda5b-0b81-4246-b0dc-67ba0ed8e0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965688032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1965688032
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_abort.1139686295
Short name T1557
Test name
Test status
Simulation time 40523176 ps
CPU time 0.77 seconds
Started Jan 17 03:28:42 PM PST 24
Finished Jan 17 03:28:43 PM PST 24
Peak memory 207012 kb
Host smart-debc7405-9de4-4a51-ac72-e236193f7db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139686295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_abort.1139686295
Directory /workspace/1.spi_device_abort/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2802918533
Short name T841
Test name
Test status
Simulation time 17422931 ps
CPU time 0.69 seconds
Started Jan 17 03:28:48 PM PST 24
Finished Jan 17 03:28:49 PM PST 24
Peak memory 206788 kb
Host smart-892c3257-e084-4fba-9f54-8ed8f6ebd08f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802918533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
802918533
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_bit_transfer.3656451541
Short name T856
Test name
Test status
Simulation time 270122171 ps
CPU time 2.82 seconds
Started Jan 17 03:28:35 PM PST 24
Finished Jan 17 03:28:39 PM PST 24
Peak memory 217128 kb
Host smart-5c077814-f82f-4837-92e1-830a989a82c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656451541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_bit_transfer.3656451541
Directory /workspace/1.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/1.spi_device_byte_transfer.1941344820
Short name T587
Test name
Test status
Simulation time 210631835 ps
CPU time 2.61 seconds
Started Jan 17 03:28:38 PM PST 24
Finished Jan 17 03:28:43 PM PST 24
Peak memory 217112 kb
Host smart-81269ce7-027b-4468-8b5d-e830d014a63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941344820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_byte_transfer.1941344820
Directory /workspace/1.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3349153772
Short name T729
Test name
Test status
Simulation time 574582922 ps
CPU time 3.88 seconds
Started Jan 17 03:28:42 PM PST 24
Finished Jan 17 03:28:46 PM PST 24
Peak memory 219016 kb
Host smart-54d6a095-ad77-445e-8e62-568b91230684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349153772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3349153772
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1830583122
Short name T1050
Test name
Test status
Simulation time 59504109 ps
CPU time 0.74 seconds
Started Jan 17 03:28:40 PM PST 24
Finished Jan 17 03:28:42 PM PST 24
Peak memory 206956 kb
Host smart-f944c3a2-cae2-4a1e-9955-c2874728b4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830583122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1830583122
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_dummy_item_extra_dly.4217118584
Short name T1428
Test name
Test status
Simulation time 90008167571 ps
CPU time 810.35 seconds
Started Jan 17 03:28:31 PM PST 24
Finished Jan 17 03:42:04 PM PST 24
Peak memory 268488 kb
Host smart-252f0e5c-74ad-493e-8808-cec8cdf22c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217118584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_dummy_item_extra_dly.4217118584
Directory /workspace/1.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/1.spi_device_extreme_fifo_size.141974685
Short name T1329
Test name
Test status
Simulation time 189112909771 ps
CPU time 2178.43 seconds
Started Jan 17 03:28:28 PM PST 24
Finished Jan 17 04:04:52 PM PST 24
Peak memory 218352 kb
Host smart-8583aebf-0a29-4347-baa3-766a7ecab1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141974685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_extreme_fifo_size.141974685
Directory /workspace/1.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/1.spi_device_fifo_full.480840641
Short name T491
Test name
Test status
Simulation time 213895219465 ps
CPU time 2730.46 seconds
Started Jan 17 03:28:29 PM PST 24
Finished Jan 17 04:14:05 PM PST 24
Peak memory 307280 kb
Host smart-42a8db7a-519e-4480-9b08-941c92f97202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480840641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_fifo_full.480840641
Directory /workspace/1.spi_device_fifo_full/latest

Test location /workspace/coverage/default/1.spi_device_fifo_underflow_overflow.2471793725
Short name T1288
Test name
Test status
Simulation time 66835831103 ps
CPU time 360.92 seconds
Started Jan 17 03:28:27 PM PST 24
Finished Jan 17 03:34:29 PM PST 24
Peak memory 333440 kb
Host smart-1883ac03-acb7-483b-a98e-d370f706a061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471793725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_fifo_underflow_overfl
ow.2471793725
Directory /workspace/1.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3234896495
Short name T1751
Test name
Test status
Simulation time 21342481083 ps
CPU time 83.37 seconds
Started Jan 17 03:28:43 PM PST 24
Finished Jan 17 03:30:07 PM PST 24
Peak memory 255568 kb
Host smart-63f9f710-0151-4b1d-8c85-3bcc340ff49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234896495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3234896495
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1202547676
Short name T336
Test name
Test status
Simulation time 17384760111 ps
CPU time 79.86 seconds
Started Jan 17 03:28:41 PM PST 24
Finished Jan 17 03:30:01 PM PST 24
Peak memory 256920 kb
Host smart-65939f49-bc0d-4202-a5df-fee165e2b74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202547676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1202547676
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3706392454
Short name T299
Test name
Test status
Simulation time 31010428994 ps
CPU time 303.96 seconds
Started Jan 17 03:28:46 PM PST 24
Finished Jan 17 03:33:51 PM PST 24
Peak memory 262232 kb
Host smart-f1843985-05bb-4463-8f91-d870f6979dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706392454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3706392454
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1742040805
Short name T1131
Test name
Test status
Simulation time 9640547736 ps
CPU time 10.18 seconds
Started Jan 17 03:28:46 PM PST 24
Finished Jan 17 03:28:57 PM PST 24
Peak memory 238784 kb
Host smart-fa674dd3-b3bf-4483-8cfd-860429dca8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742040805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1742040805
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_intr.2104125858
Short name T1051
Test name
Test status
Simulation time 16560465997 ps
CPU time 30.06 seconds
Started Jan 17 03:28:30 PM PST 24
Finished Jan 17 03:29:04 PM PST 24
Peak memory 234528 kb
Host smart-da5c2657-39e1-48b0-9ff5-9ce77d321ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104125858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intr.2104125858
Directory /workspace/1.spi_device_intr/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.761274968
Short name T1750
Test name
Test status
Simulation time 25106023614 ps
CPU time 37.44 seconds
Started Jan 17 03:28:45 PM PST 24
Finished Jan 17 03:29:23 PM PST 24
Peak memory 233652 kb
Host smart-95ff975d-e6fc-40cb-bd13-f6cc342a7538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761274968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.761274968
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1666072556
Short name T1267
Test name
Test status
Simulation time 32814720 ps
CPU time 1.09 seconds
Started Jan 17 03:28:40 PM PST 24
Finished Jan 17 03:28:42 PM PST 24
Peak memory 219124 kb
Host smart-8d40b3a4-1e7b-4f43-a703-dd9f8e25542c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666072556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1666072556
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3225314010
Short name T28
Test name
Test status
Simulation time 31505696085 ps
CPU time 43.14 seconds
Started Jan 17 03:28:42 PM PST 24
Finished Jan 17 03:29:26 PM PST 24
Peak memory 236324 kb
Host smart-2fea97d0-c3dc-4cfd-8c5f-9c687925b34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225314010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3225314010
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.364436970
Short name T1074
Test name
Test status
Simulation time 21454787396 ps
CPU time 26.35 seconds
Started Jan 17 03:28:43 PM PST 24
Finished Jan 17 03:29:10 PM PST 24
Peak memory 241852 kb
Host smart-59a61434-0357-4109-8e3b-c8caffebc278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364436970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.364436970
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_perf.3404198781
Short name T1217
Test name
Test status
Simulation time 59771108672 ps
CPU time 353.14 seconds
Started Jan 17 03:28:37 PM PST 24
Finished Jan 17 03:34:31 PM PST 24
Peak memory 271744 kb
Host smart-70e7e10d-89e9-4652-b2cc-d3a9b9dfb765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404198781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_perf.3404198781
Directory /workspace/1.spi_device_perf/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.625852959
Short name T777
Test name
Test status
Simulation time 68866898 ps
CPU time 0.74 seconds
Started Jan 17 03:28:39 PM PST 24
Finished Jan 17 03:28:41 PM PST 24
Peak memory 217084 kb
Host smart-7fd3246d-ec8f-48b2-aadf-e349f0d329ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625852959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.625852959
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.72523351
Short name T1711
Test name
Test status
Simulation time 478800227 ps
CPU time 4.59 seconds
Started Jan 17 03:28:43 PM PST 24
Finished Jan 17 03:28:48 PM PST 24
Peak memory 234636 kb
Host smart-47b15400-b92b-43a2-888e-ad40bd88fbd1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=72523351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct
.72523351
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_rx_timeout.2790686476
Short name T796
Test name
Test status
Simulation time 1344395221 ps
CPU time 5.95 seconds
Started Jan 17 03:28:38 PM PST 24
Finished Jan 17 03:28:45 PM PST 24
Peak memory 217084 kb
Host smart-3da7cd6e-38df-4528-8ab6-062ecb7d81db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790686476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_rx_timeout.2790686476
Directory /workspace/1.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3053836272
Short name T90
Test name
Test status
Simulation time 238093255 ps
CPU time 1.07 seconds
Started Jan 17 03:28:49 PM PST 24
Finished Jan 17 03:28:51 PM PST 24
Peak memory 238188 kb
Host smart-c0b6a068-eee3-4aea-8650-0f3519bff2d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053836272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3053836272
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_smoke.2732506132
Short name T1218
Test name
Test status
Simulation time 381082559 ps
CPU time 1.19 seconds
Started Jan 17 03:28:29 PM PST 24
Finished Jan 17 03:28:35 PM PST 24
Peak memory 216956 kb
Host smart-1c6c13ea-a03d-4f8e-822e-4bc79061e9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732506132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_smoke.2732506132
Directory /workspace/1.spi_device_smoke/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1992984936
Short name T915
Test name
Test status
Simulation time 7056691713 ps
CPU time 57.1 seconds
Started Jan 17 03:28:37 PM PST 24
Finished Jan 17 03:29:35 PM PST 24
Peak memory 221736 kb
Host smart-8de579ab-0b16-4c8f-8d7a-18b2104cc82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992984936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1992984936
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.66955489
Short name T530
Test name
Test status
Simulation time 2002972710 ps
CPU time 9.64 seconds
Started Jan 17 03:28:38 PM PST 24
Finished Jan 17 03:28:50 PM PST 24
Peak memory 217116 kb
Host smart-665ef9df-f1e4-498b-8a53-84f389d539a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66955489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.66955489
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2450871340
Short name T1447
Test name
Test status
Simulation time 401704483 ps
CPU time 8.18 seconds
Started Jan 17 03:28:44 PM PST 24
Finished Jan 17 03:28:53 PM PST 24
Peak memory 217128 kb
Host smart-a83b9edb-2c2a-4f3d-b34f-301c8d754abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450871340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2450871340
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.407053657
Short name T1259
Test name
Test status
Simulation time 181697071 ps
CPU time 0.84 seconds
Started Jan 17 03:28:43 PM PST 24
Finished Jan 17 03:28:44 PM PST 24
Peak memory 207284 kb
Host smart-0301d475-244c-44cb-9991-40d295bf5286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407053657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.407053657
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_tx_async_fifo_reset.4116696964
Short name T1604
Test name
Test status
Simulation time 55566971 ps
CPU time 0.74 seconds
Started Jan 17 03:28:38 PM PST 24
Finished Jan 17 03:28:40 PM PST 24
Peak memory 208740 kb
Host smart-11f0c1f6-30b3-4565-99fe-3dc707360140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116696964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tx_async_fifo_reset.4116696964
Directory /workspace/1.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/1.spi_device_txrx.2208565722
Short name T805
Test name
Test status
Simulation time 58837829967 ps
CPU time 321.91 seconds
Started Jan 17 03:28:28 PM PST 24
Finished Jan 17 03:33:56 PM PST 24
Peak memory 273996 kb
Host smart-7f68b44f-dfa8-4206-8c26-d7b1cace96e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208565722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_txrx.2208565722
Directory /workspace/1.spi_device_txrx/latest

Test location /workspace/coverage/default/1.spi_device_upload.3395082895
Short name T224
Test name
Test status
Simulation time 932670194 ps
CPU time 5.54 seconds
Started Jan 17 03:28:42 PM PST 24
Finished Jan 17 03:28:48 PM PST 24
Peak memory 249940 kb
Host smart-f460bd5a-82ad-41e9-b350-42631ba54d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395082895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3395082895
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_abort.832519371
Short name T938
Test name
Test status
Simulation time 53631145 ps
CPU time 0.76 seconds
Started Jan 17 03:30:26 PM PST 24
Finished Jan 17 03:30:28 PM PST 24
Peak memory 206960 kb
Host smart-49efc336-6fa1-4c41-9eb6-e8c31d502322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832519371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_abort.832519371
Directory /workspace/10.spi_device_abort/latest

Test location /workspace/coverage/default/10.spi_device_bit_transfer.1327282219
Short name T679
Test name
Test status
Simulation time 812639788 ps
CPU time 3.74 seconds
Started Jan 17 03:30:25 PM PST 24
Finished Jan 17 03:30:30 PM PST 24
Peak memory 217200 kb
Host smart-f2a37317-1b6b-49b1-a8cb-baa8d3d3656d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327282219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_bit_transfer.1327282219
Directory /workspace/10.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/10.spi_device_byte_transfer.2263585208
Short name T1060
Test name
Test status
Simulation time 173562050 ps
CPU time 3.06 seconds
Started Jan 17 03:30:25 PM PST 24
Finished Jan 17 03:30:30 PM PST 24
Peak memory 217184 kb
Host smart-ffb1b986-ee20-4494-8798-b7ee29e2649e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263585208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_byte_transfer.2263585208
Directory /workspace/10.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3009355016
Short name T284
Test name
Test status
Simulation time 166221298 ps
CPU time 3.75 seconds
Started Jan 17 03:30:24 PM PST 24
Finished Jan 17 03:30:29 PM PST 24
Peak memory 238116 kb
Host smart-7c1d1949-f10a-4bc9-acc4-250c9b5696e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009355016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3009355016
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2200896036
Short name T935
Test name
Test status
Simulation time 31141449 ps
CPU time 0.81 seconds
Started Jan 17 03:30:20 PM PST 24
Finished Jan 17 03:30:26 PM PST 24
Peak memory 207960 kb
Host smart-fa6bc31f-cd99-4a4e-82ff-4e15778c1c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200896036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2200896036
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_dummy_item_extra_dly.3961785008
Short name T578
Test name
Test status
Simulation time 59494556015 ps
CPU time 1329.89 seconds
Started Jan 17 03:30:19 PM PST 24
Finished Jan 17 03:52:35 PM PST 24
Peak memory 249640 kb
Host smart-40fb55ca-d5e2-4739-aa9a-3b2f768a98f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961785008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_dummy_item_extra_dly.3961785008
Directory /workspace/10.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/10.spi_device_extreme_fifo_size.622477880
Short name T1660
Test name
Test status
Simulation time 20322095911 ps
CPU time 47.03 seconds
Started Jan 17 03:30:21 PM PST 24
Finished Jan 17 03:31:13 PM PST 24
Peak memory 235576 kb
Host smart-1c6f8027-2ba3-4c3c-be98-038796a17ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622477880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_extreme_fifo_size.622477880
Directory /workspace/10.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/10.spi_device_fifo_full.3032736694
Short name T34
Test name
Test status
Simulation time 18980290863 ps
CPU time 330.08 seconds
Started Jan 17 03:30:19 PM PST 24
Finished Jan 17 03:35:55 PM PST 24
Peak memory 266960 kb
Host smart-59bec1e0-d287-483a-932b-331f84019144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032736694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_fifo_full.3032736694
Directory /workspace/10.spi_device_fifo_full/latest

Test location /workspace/coverage/default/10.spi_device_fifo_underflow_overflow.3968426380
Short name T682
Test name
Test status
Simulation time 508616039372 ps
CPU time 819.88 seconds
Started Jan 17 03:30:17 PM PST 24
Finished Jan 17 03:43:59 PM PST 24
Peak memory 592764 kb
Host smart-e24a1bed-8889-4986-81da-c779a128af79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968426380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_fifo_underflow_overf
low.3968426380
Directory /workspace/10.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3484492161
Short name T1127
Test name
Test status
Simulation time 2973674029 ps
CPU time 44.53 seconds
Started Jan 17 03:30:26 PM PST 24
Finished Jan 17 03:31:12 PM PST 24
Peak memory 225436 kb
Host smart-79f8d675-7cd0-40ea-a8aa-bb634861d8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484492161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3484492161
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3869951185
Short name T960
Test name
Test status
Simulation time 3118232161 ps
CPU time 11.29 seconds
Started Jan 17 03:30:24 PM PST 24
Finished Jan 17 03:30:37 PM PST 24
Peak memory 237516 kb
Host smart-f0e88734-56fe-42d9-ba1a-de830756a412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869951185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3869951185
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.632792764
Short name T1224
Test name
Test status
Simulation time 897592759 ps
CPU time 4.58 seconds
Started Jan 17 03:30:23 PM PST 24
Finished Jan 17 03:30:30 PM PST 24
Peak memory 233620 kb
Host smart-eb6b7430-19d2-4633-b002-c1382ae96ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632792764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.632792764
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_intr.2792010383
Short name T561
Test name
Test status
Simulation time 67293505190 ps
CPU time 41.84 seconds
Started Jan 17 03:30:28 PM PST 24
Finished Jan 17 03:31:10 PM PST 24
Peak memory 239752 kb
Host smart-f2f5361c-e09a-457f-9af3-811d431ffdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792010383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intr.2792010383
Directory /workspace/10.spi_device_intr/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1848706937
Short name T306
Test name
Test status
Simulation time 1449018200 ps
CPU time 4.62 seconds
Started Jan 17 03:30:24 PM PST 24
Finished Jan 17 03:30:30 PM PST 24
Peak memory 226576 kb
Host smart-2b1e6ff7-ffef-4e06-b2df-942ad09980dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848706937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1848706937
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3536636648
Short name T597
Test name
Test status
Simulation time 23920748593 ps
CPU time 39.09 seconds
Started Jan 17 03:30:23 PM PST 24
Finished Jan 17 03:31:05 PM PST 24
Peak memory 241628 kb
Host smart-0523ef53-f930-43c8-b00b-a678bce1d5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536636648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3536636648
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3415603473
Short name T1713
Test name
Test status
Simulation time 11192590825 ps
CPU time 22.2 seconds
Started Jan 17 03:30:25 PM PST 24
Finished Jan 17 03:30:48 PM PST 24
Peak memory 230528 kb
Host smart-ab880187-24ef-4412-8ceb-328cbf9fba0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415603473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3415603473
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_perf.3340675357
Short name T1244
Test name
Test status
Simulation time 36498938527 ps
CPU time 434 seconds
Started Jan 17 03:30:17 PM PST 24
Finished Jan 17 03:37:33 PM PST 24
Peak memory 272984 kb
Host smart-2daca296-8d0a-4c1d-b454-a7613c2e2954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340675357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_perf.3340675357
Directory /workspace/10.spi_device_perf/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.3816446445
Short name T1324
Test name
Test status
Simulation time 19118273 ps
CPU time 0.81 seconds
Started Jan 17 03:30:17 PM PST 24
Finished Jan 17 03:30:20 PM PST 24
Peak memory 217100 kb
Host smart-96af51c7-7858-4483-9233-34df03353876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816446445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.3816446445
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3845657127
Short name T496
Test name
Test status
Simulation time 181912546 ps
CPU time 4.17 seconds
Started Jan 17 03:30:23 PM PST 24
Finished Jan 17 03:30:30 PM PST 24
Peak memory 219196 kb
Host smart-4bbbc5e7-eff8-4ded-8b52-aa1a3cd168bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3845657127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3845657127
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_rx_async_fifo_reset.1800797057
Short name T909
Test name
Test status
Simulation time 24757190 ps
CPU time 0.95 seconds
Started Jan 17 03:30:22 PM PST 24
Finished Jan 17 03:30:26 PM PST 24
Peak memory 208836 kb
Host smart-2e516af5-dc3d-4f79-b868-6b4b9616a554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800797057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_rx_async_fifo_reset.1800797057
Directory /workspace/10.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/10.spi_device_rx_timeout.1110202615
Short name T1588
Test name
Test status
Simulation time 659223941 ps
CPU time 5.66 seconds
Started Jan 17 03:30:28 PM PST 24
Finished Jan 17 03:30:34 PM PST 24
Peak memory 217100 kb
Host smart-4e49a5c8-0549-47cd-864f-5f2684198d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110202615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_rx_timeout.1110202615
Directory /workspace/10.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/10.spi_device_smoke.4251632344
Short name T1047
Test name
Test status
Simulation time 1059830741 ps
CPU time 1.45 seconds
Started Jan 17 03:30:19 PM PST 24
Finished Jan 17 03:30:25 PM PST 24
Peak memory 217244 kb
Host smart-190a0515-33eb-4d5f-90c3-e94aced0d811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251632344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_smoke.4251632344
Directory /workspace/10.spi_device_smoke/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3411576893
Short name T784
Test name
Test status
Simulation time 620699486911 ps
CPU time 6122.09 seconds
Started Jan 17 03:30:23 PM PST 24
Finished Jan 17 05:12:28 PM PST 24
Peak memory 741648 kb
Host smart-c735722b-86e0-42f3-ae55-b5318059d519
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411576893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3411576893
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3018875584
Short name T359
Test name
Test status
Simulation time 25674550676 ps
CPU time 25 seconds
Started Jan 17 03:30:25 PM PST 24
Finished Jan 17 03:30:52 PM PST 24
Peak memory 217608 kb
Host smart-bc5d62d2-8470-4f47-905a-c0946c4333c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018875584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3018875584
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.696731382
Short name T894
Test name
Test status
Simulation time 5003950602 ps
CPU time 17.67 seconds
Started Jan 17 03:30:23 PM PST 24
Finished Jan 17 03:30:43 PM PST 24
Peak memory 217100 kb
Host smart-3614ad91-d873-4073-abe2-952f2bfc6626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696731382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.696731382
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.620081160
Short name T1693
Test name
Test status
Simulation time 510994481 ps
CPU time 7.74 seconds
Started Jan 17 03:30:26 PM PST 24
Finished Jan 17 03:30:35 PM PST 24
Peak memory 217188 kb
Host smart-7f285617-152c-4d44-8fe6-f63a45872a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620081160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.620081160
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.4183894737
Short name T1467
Test name
Test status
Simulation time 535690900 ps
CPU time 0.92 seconds
Started Jan 17 03:30:23 PM PST 24
Finished Jan 17 03:30:26 PM PST 24
Peak memory 208340 kb
Host smart-72ebd198-106e-4f1d-9cfa-9792650bdf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183894737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4183894737
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_tx_async_fifo_reset.2261226795
Short name T1547
Test name
Test status
Simulation time 29151457 ps
CPU time 0.78 seconds
Started Jan 17 03:30:24 PM PST 24
Finished Jan 17 03:30:26 PM PST 24
Peak memory 208748 kb
Host smart-7d6c2106-671f-47c1-9be7-bf51dfb40b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261226795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tx_async_fifo_reset.2261226795
Directory /workspace/10.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/10.spi_device_txrx.4179366150
Short name T1338
Test name
Test status
Simulation time 145048047151 ps
CPU time 408.04 seconds
Started Jan 17 03:30:18 PM PST 24
Finished Jan 17 03:37:07 PM PST 24
Peak memory 282796 kb
Host smart-f590265c-8198-42d4-99ba-9c82cdcdbae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179366150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_txrx.4179366150
Directory /workspace/10.spi_device_txrx/latest

Test location /workspace/coverage/default/10.spi_device_upload.1278254041
Short name T289
Test name
Test status
Simulation time 136581977877 ps
CPU time 30.7 seconds
Started Jan 17 03:30:23 PM PST 24
Finished Jan 17 03:30:56 PM PST 24
Peak memory 228816 kb
Host smart-688a6ffe-79d9-42e5-9c4a-5f61866655a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278254041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1278254041
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_abort.3643426610
Short name T1360
Test name
Test status
Simulation time 59851481 ps
CPU time 0.77 seconds
Started Jan 17 03:30:51 PM PST 24
Finished Jan 17 03:30:57 PM PST 24
Peak memory 206944 kb
Host smart-89712e0c-0f21-4364-80f6-a17731ed8c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643426610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_abort.3643426610
Directory /workspace/11.spi_device_abort/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3128133209
Short name T83
Test name
Test status
Simulation time 41453206 ps
CPU time 0.72 seconds
Started Jan 17 03:30:48 PM PST 24
Finished Jan 17 03:30:50 PM PST 24
Peak memory 206716 kb
Host smart-83647116-71e9-4d93-a980-b3745241ffb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128133209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3128133209
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_bit_transfer.3096638986
Short name T1587
Test name
Test status
Simulation time 911213169 ps
CPU time 2.43 seconds
Started Jan 17 03:30:48 PM PST 24
Finished Jan 17 03:30:51 PM PST 24
Peak memory 217120 kb
Host smart-7e500a2c-78ae-4018-8674-9ff7549ad060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096638986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_bit_transfer.3096638986
Directory /workspace/11.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/11.spi_device_byte_transfer.1204471817
Short name T1501
Test name
Test status
Simulation time 175786955 ps
CPU time 3.27 seconds
Started Jan 17 03:30:36 PM PST 24
Finished Jan 17 03:30:40 PM PST 24
Peak memory 217084 kb
Host smart-b3d56cbc-27f9-499c-b234-7ffd5b116478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204471817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_byte_transfer.1204471817
Directory /workspace/11.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3880401572
Short name T1486
Test name
Test status
Simulation time 19990045041 ps
CPU time 6.32 seconds
Started Jan 17 03:30:45 PM PST 24
Finished Jan 17 03:30:53 PM PST 24
Peak memory 238656 kb
Host smart-09cd4dd2-aa0a-4344-ac51-e51c07f2311c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880401572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3880401572
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2998029571
Short name T1502
Test name
Test status
Simulation time 17370277 ps
CPU time 0.76 seconds
Started Jan 17 03:30:35 PM PST 24
Finished Jan 17 03:30:37 PM PST 24
Peak memory 206952 kb
Host smart-e7b45fc6-e862-4520-a04f-87d8fab031ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998029571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2998029571
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_dummy_item_extra_dly.4238934253
Short name T1725
Test name
Test status
Simulation time 124553049793 ps
CPU time 193.24 seconds
Started Jan 17 03:30:40 PM PST 24
Finished Jan 17 03:33:54 PM PST 24
Peak memory 252104 kb
Host smart-cbb5af60-a665-43cb-8986-a0fc38f365b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238934253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_dummy_item_extra_dly.4238934253
Directory /workspace/11.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/11.spi_device_fifo_full.1527616668
Short name T1339
Test name
Test status
Simulation time 21422128332 ps
CPU time 413.22 seconds
Started Jan 17 03:30:37 PM PST 24
Finished Jan 17 03:37:31 PM PST 24
Peak memory 290596 kb
Host smart-ec8472d0-e93a-424e-be6d-e52f7fb1c53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527616668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_fifo_full.1527616668
Directory /workspace/11.spi_device_fifo_full/latest

Test location /workspace/coverage/default/11.spi_device_fifo_underflow_overflow.939807263
Short name T184
Test name
Test status
Simulation time 392524448858 ps
CPU time 810.7 seconds
Started Jan 17 03:30:41 PM PST 24
Finished Jan 17 03:44:12 PM PST 24
Peak memory 725536 kb
Host smart-324382d3-f9e9-4eec-8c93-c00ca6fb1ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939807263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_fifo_underflow_overfl
ow.939807263
Directory /workspace/11.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1428602901
Short name T920
Test name
Test status
Simulation time 684121982 ps
CPU time 14.08 seconds
Started Jan 17 03:30:48 PM PST 24
Finished Jan 17 03:31:04 PM PST 24
Peak memory 239648 kb
Host smart-7a5bf226-db02-4a85-952a-762551226c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428602901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1428602901
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1982105587
Short name T1755
Test name
Test status
Simulation time 238345904436 ps
CPU time 471.92 seconds
Started Jan 17 03:30:49 PM PST 24
Finished Jan 17 03:38:47 PM PST 24
Peak memory 262176 kb
Host smart-44eb7d3c-010e-4099-813e-fd01190cef72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982105587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1982105587
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2942673883
Short name T227
Test name
Test status
Simulation time 126884573076 ps
CPU time 491.76 seconds
Started Jan 17 03:30:47 PM PST 24
Finished Jan 17 03:39:00 PM PST 24
Peak memory 250136 kb
Host smart-e72c5fd3-e214-4cab-bdc7-3fc241de44eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942673883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2942673883
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3110262445
Short name T1681
Test name
Test status
Simulation time 352681567 ps
CPU time 11.91 seconds
Started Jan 17 03:30:45 PM PST 24
Finished Jan 17 03:30:58 PM PST 24
Peak memory 249056 kb
Host smart-f52c9ff4-ba77-4a3b-89fb-4040bd32de34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110262445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3110262445
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.911031068
Short name T1516
Test name
Test status
Simulation time 2382873701 ps
CPU time 6.35 seconds
Started Jan 17 03:30:52 PM PST 24
Finished Jan 17 03:31:03 PM PST 24
Peak memory 221092 kb
Host smart-1491b95e-9a4d-468b-b73f-dbaa86683247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911031068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.911031068
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_intr.4032826329
Short name T1649
Test name
Test status
Simulation time 10152358428 ps
CPU time 9.34 seconds
Started Jan 17 03:30:44 PM PST 24
Finished Jan 17 03:30:53 PM PST 24
Peak memory 217188 kb
Host smart-2c660e0f-56be-497b-9e5d-c4782912646f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032826329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intr.4032826329
Directory /workspace/11.spi_device_intr/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3879240493
Short name T879
Test name
Test status
Simulation time 9457147459 ps
CPU time 14.96 seconds
Started Jan 17 03:30:47 PM PST 24
Finished Jan 17 03:31:04 PM PST 24
Peak memory 233652 kb
Host smart-7999efd2-f911-4106-b76d-2851f7315a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879240493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3879240493
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1935676567
Short name T1666
Test name
Test status
Simulation time 44419507 ps
CPU time 1.02 seconds
Started Jan 17 03:30:35 PM PST 24
Finished Jan 17 03:30:37 PM PST 24
Peak memory 219088 kb
Host smart-f9ba539c-4429-42ed-8fbd-884764f51544
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935676567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1935676567
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1815130797
Short name T343
Test name
Test status
Simulation time 11854345289 ps
CPU time 12.36 seconds
Started Jan 17 03:30:44 PM PST 24
Finished Jan 17 03:30:57 PM PST 24
Peak memory 244024 kb
Host smart-48692da0-1b02-4d0c-bfcd-a516a5989215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815130797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1815130797
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2332186521
Short name T1231
Test name
Test status
Simulation time 133113936 ps
CPU time 2.8 seconds
Started Jan 17 03:30:48 PM PST 24
Finished Jan 17 03:30:53 PM PST 24
Peak memory 219000 kb
Host smart-40e723fb-110d-4aaa-bb9c-a490272d9890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332186521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2332186521
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_perf.3120704723
Short name T1093
Test name
Test status
Simulation time 16828915075 ps
CPU time 1091.66 seconds
Started Jan 17 03:30:45 PM PST 24
Finished Jan 17 03:48:58 PM PST 24
Peak memory 249136 kb
Host smart-a19b1d74-5e79-46ed-b985-f8845fa12399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120704723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_perf.3120704723
Directory /workspace/11.spi_device_perf/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3693802691
Short name T734
Test name
Test status
Simulation time 19826268 ps
CPU time 0.74 seconds
Started Jan 17 03:30:47 PM PST 24
Finished Jan 17 03:30:49 PM PST 24
Peak memory 216992 kb
Host smart-8d8adea7-d928-4068-afe0-a3994bd48278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693802691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3693802691
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1209537152
Short name T1219
Test name
Test status
Simulation time 1729111132 ps
CPU time 5.78 seconds
Started Jan 17 03:30:48 PM PST 24
Finished Jan 17 03:30:55 PM PST 24
Peak memory 234884 kb
Host smart-2b6fdc73-d6ef-4267-8ef0-2f76ad6fb65a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1209537152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1209537152
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_rx_async_fifo_reset.3194465099
Short name T542
Test name
Test status
Simulation time 177045600 ps
CPU time 0.96 seconds
Started Jan 17 03:30:51 PM PST 24
Finished Jan 17 03:30:57 PM PST 24
Peak memory 208788 kb
Host smart-d95a3939-89f8-4692-97ef-545a61fa5ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194465099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_rx_async_fifo_reset.3194465099
Directory /workspace/11.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/11.spi_device_rx_timeout.2227385259
Short name T1063
Test name
Test status
Simulation time 1446926728 ps
CPU time 5.56 seconds
Started Jan 17 03:30:36 PM PST 24
Finished Jan 17 03:30:42 PM PST 24
Peak memory 217056 kb
Host smart-e91ed7bd-bae7-4176-bf88-1b9d812afa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227385259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_rx_timeout.2227385259
Directory /workspace/11.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/11.spi_device_smoke.980165292
Short name T589
Test name
Test status
Simulation time 145031642 ps
CPU time 1.33 seconds
Started Jan 17 03:30:45 PM PST 24
Finished Jan 17 03:30:47 PM PST 24
Peak memory 217120 kb
Host smart-c8edb21b-d53a-4332-aefa-60f2e0a5e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980165292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_smoke.980165292
Directory /workspace/11.spi_device_smoke/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2074579302
Short name T1698
Test name
Test status
Simulation time 7167945561 ps
CPU time 10.35 seconds
Started Jan 17 03:30:46 PM PST 24
Finished Jan 17 03:30:58 PM PST 24
Peak memory 217356 kb
Host smart-ebf779f1-910d-4a9b-9949-56b6b86a934a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074579302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2074579302
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3398301782
Short name T104
Test name
Test status
Simulation time 5037922074 ps
CPU time 7.91 seconds
Started Jan 17 03:30:45 PM PST 24
Finished Jan 17 03:30:54 PM PST 24
Peak memory 217132 kb
Host smart-a92b1e93-dcf5-4015-b94a-c7ae019ce775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398301782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3398301782
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2568272672
Short name T1273
Test name
Test status
Simulation time 17333316 ps
CPU time 0.78 seconds
Started Jan 17 03:30:49 PM PST 24
Finished Jan 17 03:30:56 PM PST 24
Peak memory 207208 kb
Host smart-3a4d5dbf-1b28-4a97-84ba-24703b5cce47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568272672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2568272672
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.784291911
Short name T1412
Test name
Test status
Simulation time 1061530586 ps
CPU time 0.99 seconds
Started Jan 17 03:30:47 PM PST 24
Finished Jan 17 03:30:50 PM PST 24
Peak memory 207268 kb
Host smart-522756f3-3e62-47ea-aa27-4757bb6d38a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784291911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.784291911
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_tx_async_fifo_reset.3332527699
Short name T1543
Test name
Test status
Simulation time 24785762 ps
CPU time 0.8 seconds
Started Jan 17 03:30:45 PM PST 24
Finished Jan 17 03:30:47 PM PST 24
Peak memory 208776 kb
Host smart-09c7ff14-f2ee-4f98-9872-53dd99e9ec33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332527699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tx_async_fifo_reset.3332527699
Directory /workspace/11.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/11.spi_device_txrx.3434090364
Short name T1675
Test name
Test status
Simulation time 7448500358 ps
CPU time 70.9 seconds
Started Jan 17 03:30:39 PM PST 24
Finished Jan 17 03:31:50 PM PST 24
Peak memory 250052 kb
Host smart-aff3fb48-d520-4535-a502-2f4ca733b378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434090364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_txrx.3434090364
Directory /workspace/11.spi_device_txrx/latest

Test location /workspace/coverage/default/11.spi_device_upload.360716679
Short name T607
Test name
Test status
Simulation time 9892224713 ps
CPU time 8.69 seconds
Started Jan 17 03:30:48 PM PST 24
Finished Jan 17 03:30:58 PM PST 24
Peak memory 221480 kb
Host smart-11690d2a-f481-418c-8359-2dbfbfaeb33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360716679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.360716679
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_abort.2793360412
Short name T1746
Test name
Test status
Simulation time 25572412 ps
CPU time 0.74 seconds
Started Jan 17 03:30:55 PM PST 24
Finished Jan 17 03:30:57 PM PST 24
Peak memory 206992 kb
Host smart-de1ea0cb-2e80-4d39-9c3f-0395fc065957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793360412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_abort.2793360412
Directory /workspace/12.spi_device_abort/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2531850681
Short name T832
Test name
Test status
Simulation time 59011592 ps
CPU time 0.73 seconds
Started Jan 17 03:30:55 PM PST 24
Finished Jan 17 03:30:57 PM PST 24
Peak memory 206812 kb
Host smart-3477855a-3d80-4435-b671-062aca5c7caa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531850681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2531850681
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_bit_transfer.4039065135
Short name T528
Test name
Test status
Simulation time 492954632 ps
CPU time 2.61 seconds
Started Jan 17 03:30:54 PM PST 24
Finished Jan 17 03:30:59 PM PST 24
Peak memory 217176 kb
Host smart-034a1c2a-b14d-49a8-a325-9499fc656cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039065135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_bit_transfer.4039065135
Directory /workspace/12.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/12.spi_device_byte_transfer.2346460627
Short name T478
Test name
Test status
Simulation time 447561493 ps
CPU time 2.86 seconds
Started Jan 17 03:30:53 PM PST 24
Finished Jan 17 03:30:59 PM PST 24
Peak memory 217216 kb
Host smart-99b9690c-df79-44a2-892e-e841c18b1fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346460627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_byte_transfer.2346460627
Directory /workspace/12.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1397942831
Short name T288
Test name
Test status
Simulation time 3404983645 ps
CPU time 5.3 seconds
Started Jan 17 03:30:50 PM PST 24
Finished Jan 17 03:31:01 PM PST 24
Peak memory 221100 kb
Host smart-151f1a67-1cf7-43dd-b1e1-7f9872d9f313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397942831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1397942831
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.383441310
Short name T474
Test name
Test status
Simulation time 40044674 ps
CPU time 0.75 seconds
Started Jan 17 03:30:51 PM PST 24
Finished Jan 17 03:30:57 PM PST 24
Peak memory 206936 kb
Host smart-be074d60-bc20-4ba6-ae55-0a1f5ef319fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383441310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.383441310
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_extreme_fifo_size.141030661
Short name T1427
Test name
Test status
Simulation time 69186807228 ps
CPU time 1102 seconds
Started Jan 17 03:30:52 PM PST 24
Finished Jan 17 03:49:18 PM PST 24
Peak memory 220256 kb
Host smart-af07ffad-c991-490e-a8de-b400880d8cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141030661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_extreme_fifo_size.141030661
Directory /workspace/12.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/12.spi_device_fifo_full.2900700737
Short name T2
Test name
Test status
Simulation time 67017976471 ps
CPU time 2093.45 seconds
Started Jan 17 03:30:50 PM PST 24
Finished Jan 17 04:05:50 PM PST 24
Peak memory 266416 kb
Host smart-04443bc3-c6d5-4db7-b49b-d7ece937fe56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900700737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_fifo_full.2900700737
Directory /workspace/12.spi_device_fifo_full/latest

Test location /workspace/coverage/default/12.spi_device_fifo_underflow_overflow.2868946486
Short name T185
Test name
Test status
Simulation time 359447100420 ps
CPU time 498.57 seconds
Started Jan 17 03:30:50 PM PST 24
Finished Jan 17 03:39:15 PM PST 24
Peak memory 446224 kb
Host smart-3e859d30-6225-4a20-a8bd-907d968f7902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868946486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_fifo_underflow_overf
low.2868946486
Directory /workspace/12.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.818907783
Short name T344
Test name
Test status
Simulation time 34590111708 ps
CPU time 166.62 seconds
Started Jan 17 03:30:53 PM PST 24
Finished Jan 17 03:33:43 PM PST 24
Peak memory 253960 kb
Host smart-60d48e3e-4536-429d-901b-0dcf1f718e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818907783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.818907783
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.498116584
Short name T345
Test name
Test status
Simulation time 70925645309 ps
CPU time 462.73 seconds
Started Jan 17 03:30:56 PM PST 24
Finished Jan 17 03:38:39 PM PST 24
Peak memory 261828 kb
Host smart-49b0ff71-4c68-40a2-a05d-6d51e8220ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498116584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.498116584
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1070154248
Short name T592
Test name
Test status
Simulation time 13881312402 ps
CPU time 26.06 seconds
Started Jan 17 03:30:50 PM PST 24
Finished Jan 17 03:31:22 PM PST 24
Peak memory 250044 kb
Host smart-3c84ac27-34a1-46a5-b962-70b858bd2635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070154248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1070154248
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.232713194
Short name T217
Test name
Test status
Simulation time 615088190 ps
CPU time 6.34 seconds
Started Jan 17 03:30:50 PM PST 24
Finished Jan 17 03:31:02 PM PST 24
Peak memory 241680 kb
Host smart-e5ed29aa-56e6-4202-aba4-3046540ba80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232713194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.232713194
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_intr.4293279999
Short name T1510
Test name
Test status
Simulation time 58353550717 ps
CPU time 55.49 seconds
Started Jan 17 03:30:53 PM PST 24
Finished Jan 17 03:31:52 PM PST 24
Peak memory 225264 kb
Host smart-819b50a7-299c-4e5c-8dc7-b3c6dcb532db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293279999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intr.4293279999
Directory /workspace/12.spi_device_intr/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.4216330408
Short name T1015
Test name
Test status
Simulation time 558575953 ps
CPU time 7.28 seconds
Started Jan 17 03:30:54 PM PST 24
Finished Jan 17 03:31:04 PM PST 24
Peak memory 222452 kb
Host smart-54f410c7-dce2-4b73-a972-a8ca57125ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216330408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4216330408
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3508272024
Short name T44
Test name
Test status
Simulation time 48250755 ps
CPU time 1.08 seconds
Started Jan 17 03:30:55 PM PST 24
Finished Jan 17 03:30:57 PM PST 24
Peak memory 218824 kb
Host smart-d04ab8e1-1ef9-4798-8b77-5040edba94f1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508272024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3508272024
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3721548780
Short name T1378
Test name
Test status
Simulation time 1042620518 ps
CPU time 6.39 seconds
Started Jan 17 03:30:51 PM PST 24
Finished Jan 17 03:31:03 PM PST 24
Peak memory 236532 kb
Host smart-b77fd8cf-e3fb-4d0b-9895-f88c1649d57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721548780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3721548780
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1287800649
Short name T1247
Test name
Test status
Simulation time 8819119899 ps
CPU time 16.56 seconds
Started Jan 17 03:30:51 PM PST 24
Finished Jan 17 03:31:13 PM PST 24
Peak memory 236908 kb
Host smart-a1169cce-312b-4f80-9b16-fd1a43c82395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287800649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1287800649
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_perf.1897745567
Short name T536
Test name
Test status
Simulation time 43090328661 ps
CPU time 1058.61 seconds
Started Jan 17 03:30:47 PM PST 24
Finished Jan 17 03:48:28 PM PST 24
Peak memory 260764 kb
Host smart-da473820-6cf8-4ad7-b1b6-45b9dceb0934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897745567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_perf.1897745567
Directory /workspace/12.spi_device_perf/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.1804567364
Short name T1009
Test name
Test status
Simulation time 21731174 ps
CPU time 0.73 seconds
Started Jan 17 03:30:51 PM PST 24
Finished Jan 17 03:30:57 PM PST 24
Peak memory 217088 kb
Host smart-2dc35375-7d67-4279-8945-838a3ce9ff56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804567364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.1804567364
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1050615734
Short name T1618
Test name
Test status
Simulation time 204507703 ps
CPU time 3.55 seconds
Started Jan 17 03:30:54 PM PST 24
Finished Jan 17 03:31:00 PM PST 24
Peak memory 220116 kb
Host smart-80412bf9-f6d3-49b3-89b2-85b7c150a555
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1050615734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1050615734
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_rx_async_fifo_reset.1281527405
Short name T80
Test name
Test status
Simulation time 63185501 ps
CPU time 0.89 seconds
Started Jan 17 03:30:54 PM PST 24
Finished Jan 17 03:30:57 PM PST 24
Peak memory 208796 kb
Host smart-78a48ced-c6e2-4f4a-a109-9220132e7eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281527405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_rx_async_fifo_reset.1281527405
Directory /workspace/12.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/12.spi_device_rx_timeout.339954304
Short name T1483
Test name
Test status
Simulation time 3406056223 ps
CPU time 5.76 seconds
Started Jan 17 03:30:50 PM PST 24
Finished Jan 17 03:31:02 PM PST 24
Peak memory 217124 kb
Host smart-09499c50-8654-4d85-9f41-52463905ef87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339954304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_rx_timeout.339954304
Directory /workspace/12.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/12.spi_device_smoke.566417880
Short name T598
Test name
Test status
Simulation time 56330431 ps
CPU time 1.26 seconds
Started Jan 17 03:30:47 PM PST 24
Finished Jan 17 03:30:50 PM PST 24
Peak memory 217188 kb
Host smart-997407dd-007d-49d5-bef5-4f6883cbb25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566417880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_smoke.566417880
Directory /workspace/12.spi_device_smoke/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.653883456
Short name T507
Test name
Test status
Simulation time 1018330767 ps
CPU time 18.23 seconds
Started Jan 17 03:30:53 PM PST 24
Finished Jan 17 03:31:14 PM PST 24
Peak memory 217120 kb
Host smart-03d0648a-e724-4c72-8b13-33e4e1c7ef59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653883456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.653883456
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3445443022
Short name T1607
Test name
Test status
Simulation time 4521755765 ps
CPU time 9.87 seconds
Started Jan 17 03:30:55 PM PST 24
Finished Jan 17 03:31:06 PM PST 24
Peak memory 217224 kb
Host smart-094353b4-0eea-4c8b-82b2-372a771d46f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445443022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3445443022
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3432199860
Short name T1021
Test name
Test status
Simulation time 66726465 ps
CPU time 3.16 seconds
Started Jan 17 03:30:55 PM PST 24
Finished Jan 17 03:31:00 PM PST 24
Peak memory 217164 kb
Host smart-978787b1-447f-470f-b5b0-a6806855a296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432199860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3432199860
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1041004912
Short name T1513
Test name
Test status
Simulation time 163861546 ps
CPU time 0.8 seconds
Started Jan 17 03:30:55 PM PST 24
Finished Jan 17 03:30:57 PM PST 24
Peak memory 207276 kb
Host smart-ccc686b2-6d92-43a5-9970-cad48ab03c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041004912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1041004912
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_tx_async_fifo_reset.741572654
Short name T1351
Test name
Test status
Simulation time 56565784 ps
CPU time 0.79 seconds
Started Jan 17 03:30:54 PM PST 24
Finished Jan 17 03:30:57 PM PST 24
Peak memory 208732 kb
Host smart-a34dc25c-c943-4df5-ad71-d726003ae6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741572654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tx_async_fifo_reset.741572654
Directory /workspace/12.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/12.spi_device_txrx.693402894
Short name T603
Test name
Test status
Simulation time 44751799748 ps
CPU time 828.97 seconds
Started Jan 17 03:30:49 PM PST 24
Finished Jan 17 03:44:39 PM PST 24
Peak memory 259484 kb
Host smart-370e68e2-a48a-4860-b10f-33a37a52c519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693402894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_txrx.693402894
Directory /workspace/12.spi_device_txrx/latest

Test location /workspace/coverage/default/12.spi_device_upload.2211238719
Short name T994
Test name
Test status
Simulation time 178345147 ps
CPU time 4.51 seconds
Started Jan 17 03:30:52 PM PST 24
Finished Jan 17 03:31:01 PM PST 24
Peak memory 241708 kb
Host smart-8a47206f-1c45-4c57-854c-a33ba61e93b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211238719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2211238719
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_abort.1178817158
Short name T913
Test name
Test status
Simulation time 39138116 ps
CPU time 0.76 seconds
Started Jan 17 03:31:05 PM PST 24
Finished Jan 17 03:31:06 PM PST 24
Peak memory 206960 kb
Host smart-6cdb25a2-ed0b-435d-b881-a8d58d73484d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178817158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_abort.1178817158
Directory /workspace/13.spi_device_abort/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1651966945
Short name T1216
Test name
Test status
Simulation time 12889307 ps
CPU time 0.72 seconds
Started Jan 17 03:31:09 PM PST 24
Finished Jan 17 03:31:11 PM PST 24
Peak memory 206832 kb
Host smart-c8c736da-7355-420c-bb54-29ff64efad08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651966945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1651966945
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_bit_transfer.2959480634
Short name T1345
Test name
Test status
Simulation time 248581670 ps
CPU time 2.8 seconds
Started Jan 17 03:31:00 PM PST 24
Finished Jan 17 03:31:04 PM PST 24
Peak memory 217116 kb
Host smart-35b6459c-4555-4021-96f5-afd310f61b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959480634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_bit_transfer.2959480634
Directory /workspace/13.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/13.spi_device_byte_transfer.3725714006
Short name T1623
Test name
Test status
Simulation time 543620202 ps
CPU time 3.42 seconds
Started Jan 17 03:30:54 PM PST 24
Finished Jan 17 03:31:00 PM PST 24
Peak memory 217116 kb
Host smart-c7991565-91dd-4cfe-91ae-2b7065e5948b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725714006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_byte_transfer.3725714006
Directory /workspace/13.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3932568521
Short name T1163
Test name
Test status
Simulation time 468137158 ps
CPU time 3.1 seconds
Started Jan 17 03:31:01 PM PST 24
Finished Jan 17 03:31:06 PM PST 24
Peak memory 218852 kb
Host smart-c9a1e001-2fa0-406d-90df-1067e6483c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932568521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3932568521
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.665195961
Short name T1143
Test name
Test status
Simulation time 13390771 ps
CPU time 0.73 seconds
Started Jan 17 03:30:52 PM PST 24
Finished Jan 17 03:30:57 PM PST 24
Peak memory 206956 kb
Host smart-95957ad9-10ee-4618-8708-56b15327899a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665195961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.665195961
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_dummy_item_extra_dly.1615074346
Short name T1644
Test name
Test status
Simulation time 211257080524 ps
CPU time 1007.83 seconds
Started Jan 17 03:30:54 PM PST 24
Finished Jan 17 03:47:44 PM PST 24
Peak memory 253216 kb
Host smart-ed759934-530c-45d4-abe0-e536a429dba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615074346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_dummy_item_extra_dly.1615074346
Directory /workspace/13.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/13.spi_device_extreme_fifo_size.821494792
Short name T742
Test name
Test status
Simulation time 72035968030 ps
CPU time 3475.31 seconds
Started Jan 17 03:30:55 PM PST 24
Finished Jan 17 04:28:52 PM PST 24
Peak memory 221372 kb
Host smart-a9c9d547-c639-4345-9b73-2d9de26edabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821494792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_extreme_fifo_size.821494792
Directory /workspace/13.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/13.spi_device_fifo_full.2100785118
Short name T48
Test name
Test status
Simulation time 94206874530 ps
CPU time 349.06 seconds
Started Jan 17 03:30:55 PM PST 24
Finished Jan 17 03:36:45 PM PST 24
Peak memory 299092 kb
Host smart-ceb3ad9d-b0a5-4210-a49e-0629e1b60cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100785118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_fifo_full.2100785118
Directory /workspace/13.spi_device_fifo_full/latest

Test location /workspace/coverage/default/13.spi_device_fifo_underflow_overflow.3077685377
Short name T1364
Test name
Test status
Simulation time 10233290020 ps
CPU time 133.47 seconds
Started Jan 17 03:30:53 PM PST 24
Finished Jan 17 03:33:10 PM PST 24
Peak memory 327272 kb
Host smart-eca9e6e0-886b-41b5-82d6-8139e6c9b26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077685377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_fifo_underflow_overf
low.3077685377
Directory /workspace/13.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1031996272
Short name T1556
Test name
Test status
Simulation time 493082799 ps
CPU time 6.97 seconds
Started Jan 17 03:31:05 PM PST 24
Finished Jan 17 03:31:12 PM PST 24
Peak memory 237740 kb
Host smart-15da48d0-78ed-4531-9a15-20855f92bf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031996272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1031996272
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.423222311
Short name T341
Test name
Test status
Simulation time 83705666456 ps
CPU time 394.94 seconds
Started Jan 17 03:31:03 PM PST 24
Finished Jan 17 03:37:39 PM PST 24
Peak memory 258336 kb
Host smart-251a99d0-f5f7-41e2-a213-f4771ede2f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423222311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.423222311
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3860240992
Short name T1105
Test name
Test status
Simulation time 6625426301 ps
CPU time 36.17 seconds
Started Jan 17 03:31:09 PM PST 24
Finished Jan 17 03:31:46 PM PST 24
Peak memory 250836 kb
Host smart-ad4c7994-f0d1-4a30-abe0-b5062c9ae2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860240992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3860240992
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3848306362
Short name T1758
Test name
Test status
Simulation time 293047323 ps
CPU time 3.05 seconds
Started Jan 17 03:31:00 PM PST 24
Finished Jan 17 03:31:04 PM PST 24
Peak memory 225320 kb
Host smart-5e3307e3-1485-423b-8c48-e7d370b207ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848306362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3848306362
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_intr.12318718
Short name T1332
Test name
Test status
Simulation time 6265232177 ps
CPU time 24.99 seconds
Started Jan 17 03:30:53 PM PST 24
Finished Jan 17 03:31:21 PM PST 24
Peak memory 219028 kb
Host smart-2aaa9d23-7cff-4f8f-8df7-19385acca258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12318718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intr.12318718
Directory /workspace/13.spi_device_intr/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.862208661
Short name T248
Test name
Test status
Simulation time 3107502447 ps
CPU time 15.72 seconds
Started Jan 17 03:31:02 PM PST 24
Finished Jan 17 03:31:19 PM PST 24
Peak memory 230232 kb
Host smart-2a2aef11-8c75-4a29-acaa-bbe8cef34063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862208661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.862208661
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.216680323
Short name T1235
Test name
Test status
Simulation time 25739647 ps
CPU time 1.02 seconds
Started Jan 17 03:30:58 PM PST 24
Finished Jan 17 03:31:00 PM PST 24
Peak memory 218108 kb
Host smart-b9db57e9-26f5-4f51-84a0-18e0ca57bb96
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216680323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.216680323
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3126261844
Short name T1309
Test name
Test status
Simulation time 15081334548 ps
CPU time 29.73 seconds
Started Jan 17 03:31:06 PM PST 24
Finished Jan 17 03:31:36 PM PST 24
Peak memory 220068 kb
Host smart-bca97745-fb77-4c56-a232-f5bf3449c3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126261844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3126261844
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3589794623
Short name T826
Test name
Test status
Simulation time 3060598189 ps
CPU time 9.77 seconds
Started Jan 17 03:31:00 PM PST 24
Finished Jan 17 03:31:11 PM PST 24
Peak memory 238612 kb
Host smart-30d8ceec-db5a-4467-8496-5f79da5497f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589794623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3589794623
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_perf.2150390684
Short name T1393
Test name
Test status
Simulation time 55844829740 ps
CPU time 616.24 seconds
Started Jan 17 03:30:54 PM PST 24
Finished Jan 17 03:41:13 PM PST 24
Peak memory 266432 kb
Host smart-c4019aed-a03f-497a-be61-095d387594b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150390684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_perf.2150390684
Directory /workspace/13.spi_device_perf/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.1478740217
Short name T1045
Test name
Test status
Simulation time 17343033 ps
CPU time 0.79 seconds
Started Jan 17 03:31:06 PM PST 24
Finished Jan 17 03:31:07 PM PST 24
Peak memory 217052 kb
Host smart-79c31503-306b-44b4-a5e6-f2a8e19d16d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478740217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.1478740217
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2404071743
Short name T585
Test name
Test status
Simulation time 283596738 ps
CPU time 4.44 seconds
Started Jan 17 03:31:05 PM PST 24
Finished Jan 17 03:31:10 PM PST 24
Peak memory 220364 kb
Host smart-5b16f3fc-3692-4dc6-8331-3b12c7da609a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2404071743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2404071743
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_rx_async_fifo_reset.1900232725
Short name T797
Test name
Test status
Simulation time 125773615 ps
CPU time 0.92 seconds
Started Jan 17 03:30:59 PM PST 24
Finished Jan 17 03:31:01 PM PST 24
Peak memory 208804 kb
Host smart-59ada4fa-d87c-4871-a006-4dac7d557083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900232725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_rx_async_fifo_reset.1900232725
Directory /workspace/13.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/13.spi_device_rx_timeout.3196148068
Short name T738
Test name
Test status
Simulation time 2347431540 ps
CPU time 5.6 seconds
Started Jan 17 03:30:54 PM PST 24
Finished Jan 17 03:31:02 PM PST 24
Peak memory 217264 kb
Host smart-19565561-0f09-4598-bc00-f0d2ce79f8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196148068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_rx_timeout.3196148068
Directory /workspace/13.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/13.spi_device_smoke.1563670469
Short name T1475
Test name
Test status
Simulation time 601032044 ps
CPU time 1.39 seconds
Started Jan 17 03:30:53 PM PST 24
Finished Jan 17 03:30:58 PM PST 24
Peak memory 217136 kb
Host smart-7760b042-6238-4666-a890-4f6a4c98b6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563670469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_smoke.1563670469
Directory /workspace/13.spi_device_smoke/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1618217920
Short name T1638
Test name
Test status
Simulation time 486075504267 ps
CPU time 1299.05 seconds
Started Jan 17 03:31:00 PM PST 24
Finished Jan 17 03:52:40 PM PST 24
Peak memory 388428 kb
Host smart-7eafe945-dab8-47fa-8ae0-80d0d584d04c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618217920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1618217920
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.960324885
Short name T360
Test name
Test status
Simulation time 21755201199 ps
CPU time 101.93 seconds
Started Jan 17 03:30:59 PM PST 24
Finished Jan 17 03:32:42 PM PST 24
Peak memory 217592 kb
Host smart-c6186567-2aa7-4ec3-8fe7-ae32a7152ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960324885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.960324885
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2704850710
Short name T1578
Test name
Test status
Simulation time 23969230993 ps
CPU time 19.5 seconds
Started Jan 17 03:30:58 PM PST 24
Finished Jan 17 03:31:18 PM PST 24
Peak memory 217200 kb
Host smart-31e68b75-aab0-4bfb-a028-bbaf003a17b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704850710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2704850710
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.616137333
Short name T1277
Test name
Test status
Simulation time 169005753 ps
CPU time 4.97 seconds
Started Jan 17 03:31:04 PM PST 24
Finished Jan 17 03:31:09 PM PST 24
Peak memory 217176 kb
Host smart-ce25d369-f1a9-4c12-a179-e5313f7f046f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616137333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.616137333
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1607421297
Short name T972
Test name
Test status
Simulation time 127706811 ps
CPU time 0.86 seconds
Started Jan 17 03:30:59 PM PST 24
Finished Jan 17 03:31:00 PM PST 24
Peak memory 207288 kb
Host smart-ce6dc6e5-7eb9-43b0-95e3-ca2ff5deea1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607421297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1607421297
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_txrx.2934166528
Short name T60
Test name
Test status
Simulation time 31043084538 ps
CPU time 281.2 seconds
Started Jan 17 03:30:54 PM PST 24
Finished Jan 17 03:35:38 PM PST 24
Peak memory 297352 kb
Host smart-27943105-2d16-4090-a5d8-e566f79776a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934166528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_txrx.2934166528
Directory /workspace/13.spi_device_txrx/latest

Test location /workspace/coverage/default/13.spi_device_upload.2990918696
Short name T570
Test name
Test status
Simulation time 7086406170 ps
CPU time 26.13 seconds
Started Jan 17 03:31:00 PM PST 24
Finished Jan 17 03:31:27 PM PST 24
Peak memory 246096 kb
Host smart-2f118f08-3676-4a2a-ae91-2cf2aeeebca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990918696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2990918696
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_abort.184817370
Short name T1594
Test name
Test status
Simulation time 74755005 ps
CPU time 0.74 seconds
Started Jan 17 03:31:18 PM PST 24
Finished Jan 17 03:31:25 PM PST 24
Peak memory 206980 kb
Host smart-58bcb0ea-de1f-4f0e-b45f-fbbb6ce74729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184817370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_abort.184817370
Directory /workspace/14.spi_device_abort/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.107729532
Short name T732
Test name
Test status
Simulation time 44340977 ps
CPU time 0.72 seconds
Started Jan 17 03:31:12 PM PST 24
Finished Jan 17 03:31:14 PM PST 24
Peak memory 206812 kb
Host smart-a6386d70-484a-432a-8df6-61705be6c346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107729532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.107729532
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_bit_transfer.9848920
Short name T1157
Test name
Test status
Simulation time 361257101 ps
CPU time 2.08 seconds
Started Jan 17 03:31:17 PM PST 24
Finished Jan 17 03:31:26 PM PST 24
Peak memory 217156 kb
Host smart-062980e3-e4ec-42a0-be0d-28eb12f1589b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9848920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_bit_transfer.9848920
Directory /workspace/14.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/14.spi_device_byte_transfer.4151722744
Short name T1011
Test name
Test status
Simulation time 1890499199 ps
CPU time 2.52 seconds
Started Jan 17 03:31:04 PM PST 24
Finished Jan 17 03:31:07 PM PST 24
Peak memory 217128 kb
Host smart-eb7417fb-5b6e-434a-8cd2-b3bfc2b3d601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151722744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_byte_transfer.4151722744
Directory /workspace/14.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2985592972
Short name T316
Test name
Test status
Simulation time 748272586 ps
CPU time 5.5 seconds
Started Jan 17 03:31:14 PM PST 24
Finished Jan 17 03:31:21 PM PST 24
Peak memory 239828 kb
Host smart-6e5efbc2-1825-406b-ac75-dc3260e7b55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985592972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2985592972
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.517558565
Short name T1686
Test name
Test status
Simulation time 61656715 ps
CPU time 0.8 seconds
Started Jan 17 03:31:05 PM PST 24
Finished Jan 17 03:31:07 PM PST 24
Peak memory 207876 kb
Host smart-0170b09a-e7de-4f9e-9c49-78dece8cfb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517558565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.517558565
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_dummy_item_extra_dly.3264323284
Short name T1601
Test name
Test status
Simulation time 23312013648 ps
CPU time 289.15 seconds
Started Jan 17 03:31:01 PM PST 24
Finished Jan 17 03:35:52 PM PST 24
Peak memory 273724 kb
Host smart-15448e5f-d7f1-4417-8412-a15e935c862c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264323284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_dummy_item_extra_dly.3264323284
Directory /workspace/14.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/14.spi_device_extreme_fifo_size.672188634
Short name T1548
Test name
Test status
Simulation time 72454168730 ps
CPU time 646.21 seconds
Started Jan 17 03:31:10 PM PST 24
Finished Jan 17 03:41:57 PM PST 24
Peak memory 217188 kb
Host smart-2b822e5e-dbe4-411a-8c52-b40add9e4fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672188634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_extreme_fifo_size.672188634
Directory /workspace/14.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/14.spi_device_fifo_full.1422458585
Short name T1763
Test name
Test status
Simulation time 36114787173 ps
CPU time 1037.81 seconds
Started Jan 17 03:31:03 PM PST 24
Finished Jan 17 03:48:22 PM PST 24
Peak memory 263328 kb
Host smart-3edc91a9-b63b-4694-af69-6803c1a39bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422458585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_fifo_full.1422458585
Directory /workspace/14.spi_device_fifo_full/latest

Test location /workspace/coverage/default/14.spi_device_fifo_underflow_overflow.3295963607
Short name T1043
Test name
Test status
Simulation time 233918139100 ps
CPU time 422.44 seconds
Started Jan 17 03:31:05 PM PST 24
Finished Jan 17 03:38:08 PM PST 24
Peak memory 302728 kb
Host smart-ce5c459b-681b-4b21-9739-86d659a6fc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295963607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_fifo_underflow_overf
low.3295963607
Directory /workspace/14.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3379533645
Short name T1210
Test name
Test status
Simulation time 6321822958 ps
CPU time 33.5 seconds
Started Jan 17 03:31:14 PM PST 24
Finished Jan 17 03:31:49 PM PST 24
Peak memory 258148 kb
Host smart-9f8fcff0-3819-4a7e-b340-88d4ce220d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379533645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3379533645
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.4159028845
Short name T300
Test name
Test status
Simulation time 77039207033 ps
CPU time 440.05 seconds
Started Jan 17 03:31:14 PM PST 24
Finished Jan 17 03:38:36 PM PST 24
Peak memory 269760 kb
Host smart-2caee651-88d7-4dd9-8794-935f18474fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159028845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.4159028845
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2823497434
Short name T1320
Test name
Test status
Simulation time 6223966329 ps
CPU time 84.59 seconds
Started Jan 17 03:31:11 PM PST 24
Finished Jan 17 03:32:37 PM PST 24
Peak memory 255448 kb
Host smart-a8ea14fd-a866-4ad3-af9e-e4f47650dd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823497434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2823497434
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1727647389
Short name T1606
Test name
Test status
Simulation time 1370006669 ps
CPU time 12.06 seconds
Started Jan 17 03:31:15 PM PST 24
Finished Jan 17 03:31:28 PM PST 24
Peak memory 253972 kb
Host smart-f1be3754-aeb1-415d-9325-4550d07df4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727647389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1727647389
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2934028677
Short name T1457
Test name
Test status
Simulation time 5989901646 ps
CPU time 6.87 seconds
Started Jan 17 03:31:10 PM PST 24
Finished Jan 17 03:31:17 PM PST 24
Peak memory 218676 kb
Host smart-2fe880ea-7f41-4470-80f4-44eedbf6610b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934028677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2934028677
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_intr.2427299614
Short name T884
Test name
Test status
Simulation time 3359473145 ps
CPU time 17.23 seconds
Started Jan 17 03:31:10 PM PST 24
Finished Jan 17 03:31:28 PM PST 24
Peak memory 225240 kb
Host smart-04424745-425d-4e23-9056-36371bb905a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427299614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intr.2427299614
Directory /workspace/14.spi_device_intr/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2674250891
Short name T1173
Test name
Test status
Simulation time 244734529 ps
CPU time 2.34 seconds
Started Jan 17 03:31:15 PM PST 24
Finished Jan 17 03:31:19 PM PST 24
Peak memory 219388 kb
Host smart-13341a59-e96b-40b9-838b-ad7f2b893c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674250891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2674250891
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.577864964
Short name T1435
Test name
Test status
Simulation time 43921199 ps
CPU time 1.12 seconds
Started Jan 17 03:31:06 PM PST 24
Finished Jan 17 03:31:08 PM PST 24
Peak memory 219156 kb
Host smart-fd6529b5-0b2d-4282-aca4-463dc5d4b8a5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577864964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.577864964
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1555133852
Short name T12
Test name
Test status
Simulation time 2362653211 ps
CPU time 7.4 seconds
Started Jan 17 03:31:14 PM PST 24
Finished Jan 17 03:31:23 PM PST 24
Peak memory 241824 kb
Host smart-b8302e03-650a-4111-be54-ddcf0c3671b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555133852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1555133852
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1792574863
Short name T933
Test name
Test status
Simulation time 444265345 ps
CPU time 6.1 seconds
Started Jan 17 03:31:11 PM PST 24
Finished Jan 17 03:31:19 PM PST 24
Peak memory 220348 kb
Host smart-044ed809-cbbc-44be-8df1-56f299f36e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792574863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1792574863
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_perf.1020566968
Short name T1409
Test name
Test status
Simulation time 30590761071 ps
CPU time 656.32 seconds
Started Jan 17 03:31:18 PM PST 24
Finished Jan 17 03:42:20 PM PST 24
Peak memory 299176 kb
Host smart-e9d75e99-a19c-401f-8e9a-9b396d3232dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020566968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_perf.1020566968
Directory /workspace/14.spi_device_perf/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.706326587
Short name T1227
Test name
Test status
Simulation time 35216072 ps
CPU time 0.72 seconds
Started Jan 17 03:31:18 PM PST 24
Finished Jan 17 03:31:25 PM PST 24
Peak memory 217056 kb
Host smart-6ab35c75-a7e3-43ac-8613-c27c7038e876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706326587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.706326587
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3100950673
Short name T521
Test name
Test status
Simulation time 73200037 ps
CPU time 3.63 seconds
Started Jan 17 03:31:11 PM PST 24
Finished Jan 17 03:31:16 PM PST 24
Peak memory 234772 kb
Host smart-e61285d7-176e-4b49-a700-c10867b15db0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3100950673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3100950673
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_rx_async_fifo_reset.3708904907
Short name T779
Test name
Test status
Simulation time 125378767 ps
CPU time 0.86 seconds
Started Jan 17 03:31:18 PM PST 24
Finished Jan 17 03:31:25 PM PST 24
Peak memory 208768 kb
Host smart-8f553149-2ade-4168-b6c6-2302ce6b1561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708904907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_rx_async_fifo_reset.3708904907
Directory /workspace/14.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/14.spi_device_rx_timeout.4201207940
Short name T812
Test name
Test status
Simulation time 378425508 ps
CPU time 4.42 seconds
Started Jan 17 03:31:05 PM PST 24
Finished Jan 17 03:31:10 PM PST 24
Peak memory 217020 kb
Host smart-609b5c3f-23cb-42ae-8212-c8f1ccd94eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201207940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_rx_timeout.4201207940
Directory /workspace/14.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/14.spi_device_smoke.1949553472
Short name T1369
Test name
Test status
Simulation time 61196598 ps
CPU time 1.05 seconds
Started Jan 17 03:31:04 PM PST 24
Finished Jan 17 03:31:06 PM PST 24
Peak memory 216888 kb
Host smart-3e1d7069-3acb-43ec-8d24-22feda4848a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949553472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_smoke.1949553472
Directory /workspace/14.spi_device_smoke/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1084316079
Short name T1591
Test name
Test status
Simulation time 8456443698 ps
CPU time 133.27 seconds
Started Jan 17 03:31:10 PM PST 24
Finished Jan 17 03:33:24 PM PST 24
Peak memory 217376 kb
Host smart-649522e4-8945-45ba-90f8-a582669f3bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084316079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1084316079
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.231187676
Short name T684
Test name
Test status
Simulation time 2799227776 ps
CPU time 10.62 seconds
Started Jan 17 03:31:18 PM PST 24
Finished Jan 17 03:31:35 PM PST 24
Peak memory 217208 kb
Host smart-d685e716-3791-446e-9846-49dcbd089e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231187676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.231187676
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1714346319
Short name T1310
Test name
Test status
Simulation time 35864364 ps
CPU time 1.23 seconds
Started Jan 17 03:31:14 PM PST 24
Finished Jan 17 03:31:17 PM PST 24
Peak memory 208724 kb
Host smart-68d0bdee-8fab-4abb-b72e-0e6f042c8c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714346319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1714346319
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1363591908
Short name T1289
Test name
Test status
Simulation time 399472618 ps
CPU time 1.01 seconds
Started Jan 17 03:31:12 PM PST 24
Finished Jan 17 03:31:14 PM PST 24
Peak memory 207220 kb
Host smart-11c62eab-6dad-4e3d-8677-67b170b38a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363591908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1363591908
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_tx_async_fifo_reset.3244676801
Short name T703
Test name
Test status
Simulation time 61040647 ps
CPU time 0.78 seconds
Started Jan 17 03:31:07 PM PST 24
Finished Jan 17 03:31:09 PM PST 24
Peak memory 208772 kb
Host smart-d2593d22-8c9e-4032-a00c-5bd10cd17068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244676801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tx_async_fifo_reset.3244676801
Directory /workspace/14.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/14.spi_device_txrx.3194043349
Short name T1155
Test name
Test status
Simulation time 32625544559 ps
CPU time 288.86 seconds
Started Jan 17 03:31:01 PM PST 24
Finished Jan 17 03:35:50 PM PST 24
Peak memory 268620 kb
Host smart-fc5d61b8-a367-4d5d-896c-69a501074f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194043349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_txrx.3194043349
Directory /workspace/14.spi_device_txrx/latest

Test location /workspace/coverage/default/14.spi_device_upload.2905491459
Short name T1451
Test name
Test status
Simulation time 9382644997 ps
CPU time 17.82 seconds
Started Jan 17 03:31:09 PM PST 24
Finished Jan 17 03:31:28 PM PST 24
Peak memory 248036 kb
Host smart-6a5794d6-401f-4949-abbd-1eef7a8ad54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905491459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2905491459
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_abort.67930332
Short name T768
Test name
Test status
Simulation time 47312469 ps
CPU time 0.75 seconds
Started Jan 17 03:31:22 PM PST 24
Finished Jan 17 03:31:25 PM PST 24
Peak memory 206976 kb
Host smart-906dc654-807f-4d8f-9928-aa4c0bb7d24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67930332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_abort.67930332
Directory /workspace/15.spi_device_abort/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1510643312
Short name T737
Test name
Test status
Simulation time 13895807 ps
CPU time 0.76 seconds
Started Jan 17 03:31:30 PM PST 24
Finished Jan 17 03:31:32 PM PST 24
Peak memory 206732 kb
Host smart-3130acb4-17d6-4dfa-9236-f57dc11df8b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510643312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1510643312
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_bit_transfer.3881754178
Short name T1107
Test name
Test status
Simulation time 211636194 ps
CPU time 2.26 seconds
Started Jan 17 03:31:15 PM PST 24
Finished Jan 17 03:31:19 PM PST 24
Peak memory 217132 kb
Host smart-5e2ef901-21f4-4790-9949-610af2137e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881754178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_bit_transfer.3881754178
Directory /workspace/15.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/15.spi_device_byte_transfer.2199896986
Short name T770
Test name
Test status
Simulation time 475712217 ps
CPU time 3.17 seconds
Started Jan 17 03:31:12 PM PST 24
Finished Jan 17 03:31:18 PM PST 24
Peak memory 217076 kb
Host smart-f7c51c75-3128-42e9-9b7a-27ed4bfa23f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199896986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_byte_transfer.2199896986
Directory /workspace/15.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4049474292
Short name T277
Test name
Test status
Simulation time 2643398560 ps
CPU time 5.43 seconds
Started Jan 17 03:31:26 PM PST 24
Finished Jan 17 03:31:32 PM PST 24
Peak memory 238852 kb
Host smart-41bd0458-fe4b-451c-9a7b-9920aa922b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049474292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4049474292
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1724178249
Short name T1315
Test name
Test status
Simulation time 27843963 ps
CPU time 0.81 seconds
Started Jan 17 03:31:14 PM PST 24
Finished Jan 17 03:31:17 PM PST 24
Peak memory 207924 kb
Host smart-c4cb981c-f6c5-49e2-b732-f28a684a0fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724178249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1724178249
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_dummy_item_extra_dly.42142179
Short name T1226
Test name
Test status
Simulation time 24643891441 ps
CPU time 89.38 seconds
Started Jan 17 03:31:15 PM PST 24
Finished Jan 17 03:32:45 PM PST 24
Peak memory 235260 kb
Host smart-d0612ae1-384a-43ab-a2e7-8eaa2534d778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42142179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_dummy_item_extra_dly.42142179
Directory /workspace/15.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/15.spi_device_extreme_fifo_size.1391097621
Short name T268
Test name
Test status
Simulation time 60669827995 ps
CPU time 600.4 seconds
Started Jan 17 03:31:13 PM PST 24
Finished Jan 17 03:41:16 PM PST 24
Peak memory 219244 kb
Host smart-44c128d9-fa11-41b2-a424-e8f9de605168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391097621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_extreme_fifo_size.1391097621
Directory /workspace/15.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/15.spi_device_fifo_full.1346190213
Short name T886
Test name
Test status
Simulation time 40976034105 ps
CPU time 565.9 seconds
Started Jan 17 03:31:12 PM PST 24
Finished Jan 17 03:40:39 PM PST 24
Peak memory 257488 kb
Host smart-43624ed7-2244-43a4-90e5-9a06ea436f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346190213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_fifo_full.1346190213
Directory /workspace/15.spi_device_fifo_full/latest

Test location /workspace/coverage/default/15.spi_device_fifo_underflow_overflow.1013439462
Short name T1508
Test name
Test status
Simulation time 146965027323 ps
CPU time 343.14 seconds
Started Jan 17 03:31:15 PM PST 24
Finished Jan 17 03:36:59 PM PST 24
Peak memory 344836 kb
Host smart-7d583c02-d96a-4b84-a0e6-302f6c107ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013439462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_fifo_underflow_overf
low.1013439462
Directory /workspace/15.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.577306700
Short name T219
Test name
Test status
Simulation time 99625443177 ps
CPU time 677.69 seconds
Started Jan 17 03:31:24 PM PST 24
Finished Jan 17 03:42:43 PM PST 24
Peak memory 266972 kb
Host smart-701870aa-28ef-48fa-aa2d-7bf37d874403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577306700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.577306700
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3078736261
Short name T1140
Test name
Test status
Simulation time 115324860431 ps
CPU time 248.21 seconds
Started Jan 17 03:31:28 PM PST 24
Finished Jan 17 03:35:37 PM PST 24
Peak memory 254836 kb
Host smart-2499d53c-5cfe-4bfe-ad10-9a1668de9aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078736261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3078736261
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3945061211
Short name T1344
Test name
Test status
Simulation time 845166092 ps
CPU time 3.93 seconds
Started Jan 17 03:31:18 PM PST 24
Finished Jan 17 03:31:28 PM PST 24
Peak memory 238860 kb
Host smart-e65e0f3f-8e62-409a-bae0-6de75a048059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945061211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3945061211
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_intr.3164502
Short name T588
Test name
Test status
Simulation time 5568821114 ps
CPU time 19.68 seconds
Started Jan 17 03:31:11 PM PST 24
Finished Jan 17 03:31:32 PM PST 24
Peak memory 225372 kb
Host smart-c10a81c5-6159-444f-bda7-132383bd7e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intr.3164502
Directory /workspace/15.spi_device_intr/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.410211628
Short name T1057
Test name
Test status
Simulation time 18776134127 ps
CPU time 29.33 seconds
Started Jan 17 03:31:27 PM PST 24
Finished Jan 17 03:31:58 PM PST 24
Peak memory 254220 kb
Host smart-20289aa9-4557-4823-89e9-934bc579c81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410211628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.410211628
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1685136094
Short name T43
Test name
Test status
Simulation time 117454894 ps
CPU time 1.08 seconds
Started Jan 17 03:31:14 PM PST 24
Finished Jan 17 03:31:17 PM PST 24
Peak memory 219080 kb
Host smart-aac954af-e29f-4019-bda5-48a0d54815db
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685136094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1685136094
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2426296769
Short name T650
Test name
Test status
Simulation time 7169707973 ps
CPU time 21.6 seconds
Started Jan 17 03:31:13 PM PST 24
Finished Jan 17 03:31:37 PM PST 24
Peak memory 228828 kb
Host smart-2d06dd88-9cbb-464f-9e15-2ac3cf7b5811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426296769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2426296769
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3635194300
Short name T1477
Test name
Test status
Simulation time 703451386 ps
CPU time 8.77 seconds
Started Jan 17 03:31:14 PM PST 24
Finished Jan 17 03:31:25 PM PST 24
Peak memory 241320 kb
Host smart-b5ec12ba-af84-4724-857b-fad095ec3bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635194300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3635194300
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_perf.3153616512
Short name T1643
Test name
Test status
Simulation time 69734983917 ps
CPU time 588.85 seconds
Started Jan 17 03:31:15 PM PST 24
Finished Jan 17 03:41:05 PM PST 24
Peak memory 265704 kb
Host smart-fb8a9be8-a298-4f28-a3b9-fb4a7a94192a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153616512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_perf.3153616512
Directory /workspace/15.spi_device_perf/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.466774026
Short name T168
Test name
Test status
Simulation time 1202748076 ps
CPU time 6.41 seconds
Started Jan 17 03:31:23 PM PST 24
Finished Jan 17 03:31:31 PM PST 24
Peak memory 234768 kb
Host smart-86a9917b-e676-4632-a1fd-1691286f4cb3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=466774026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.466774026
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_rx_async_fifo_reset.632483943
Short name T817
Test name
Test status
Simulation time 47001333 ps
CPU time 0.96 seconds
Started Jan 17 03:31:26 PM PST 24
Finished Jan 17 03:31:28 PM PST 24
Peak memory 208752 kb
Host smart-4920ae74-7e25-4e42-a024-d60de4e7cc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632483943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_rx_async_fifo_reset.632483943
Directory /workspace/15.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/15.spi_device_rx_timeout.2930571276
Short name T1132
Test name
Test status
Simulation time 1695192255 ps
CPU time 4.9 seconds
Started Jan 17 03:31:11 PM PST 24
Finished Jan 17 03:31:17 PM PST 24
Peak memory 217052 kb
Host smart-b76365cd-bf40-43e1-819e-8c66ca687ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930571276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_rx_timeout.2930571276
Directory /workspace/15.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/15.spi_device_smoke.1908561239
Short name T1384
Test name
Test status
Simulation time 19436298 ps
CPU time 1.03 seconds
Started Jan 17 03:31:12 PM PST 24
Finished Jan 17 03:31:14 PM PST 24
Peak memory 216928 kb
Host smart-47af154a-4b5b-4af8-8947-e701fcbcf8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908561239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_smoke.1908561239
Directory /workspace/15.spi_device_smoke/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.282463142
Short name T1064
Test name
Test status
Simulation time 19390711984 ps
CPU time 28.28 seconds
Started Jan 17 03:31:21 PM PST 24
Finished Jan 17 03:31:52 PM PST 24
Peak memory 217384 kb
Host smart-b63795bd-54db-40e0-8d1f-3d84679fa70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282463142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.282463142
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.358377907
Short name T818
Test name
Test status
Simulation time 7834074309 ps
CPU time 15.34 seconds
Started Jan 17 03:31:15 PM PST 24
Finished Jan 17 03:31:32 PM PST 24
Peak memory 217228 kb
Host smart-ac4cac70-1b79-4303-8cbd-5fad86b69a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358377907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.358377907
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3442016786
Short name T1774
Test name
Test status
Simulation time 292411567 ps
CPU time 1.43 seconds
Started Jan 17 03:31:15 PM PST 24
Finished Jan 17 03:31:17 PM PST 24
Peak memory 208972 kb
Host smart-02f299ee-3432-4cb7-a6be-85e76fb4a668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442016786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3442016786
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2935677089
Short name T61
Test name
Test status
Simulation time 1496910713 ps
CPU time 1.15 seconds
Started Jan 17 03:31:14 PM PST 24
Finished Jan 17 03:31:17 PM PST 24
Peak memory 208308 kb
Host smart-7e54545e-fbdf-4e8d-996d-563f487797df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935677089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2935677089
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_tx_async_fifo_reset.506681741
Short name T706
Test name
Test status
Simulation time 16574576 ps
CPU time 0.8 seconds
Started Jan 17 03:31:14 PM PST 24
Finished Jan 17 03:31:17 PM PST 24
Peak memory 208728 kb
Host smart-8c2b07c7-f6f5-4d26-9df5-3f595d8bf540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506681741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tx_async_fifo_reset.506681741
Directory /workspace/15.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/15.spi_device_txrx.2493148349
Short name T829
Test name
Test status
Simulation time 66408293916 ps
CPU time 194.74 seconds
Started Jan 17 03:31:10 PM PST 24
Finished Jan 17 03:34:26 PM PST 24
Peak memory 296592 kb
Host smart-28ae9547-27c9-446d-9c3e-1197860b3aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493148349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_txrx.2493148349
Directory /workspace/15.spi_device_txrx/latest

Test location /workspace/coverage/default/15.spi_device_upload.111717225
Short name T637
Test name
Test status
Simulation time 8110582429 ps
CPU time 22.18 seconds
Started Jan 17 03:31:32 PM PST 24
Finished Jan 17 03:31:55 PM PST 24
Peak memory 241332 kb
Host smart-372861a1-cdfe-4fc5-8daf-f07be0c0498e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111717225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.111717225
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_abort.3759856312
Short name T1183
Test name
Test status
Simulation time 13127220 ps
CPU time 0.75 seconds
Started Jan 17 03:31:32 PM PST 24
Finished Jan 17 03:31:33 PM PST 24
Peak memory 206948 kb
Host smart-547e8266-65c8-4597-b850-c5bd68b7ecdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759856312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_abort.3759856312
Directory /workspace/16.spi_device_abort/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1656615174
Short name T1008
Test name
Test status
Simulation time 40122442 ps
CPU time 0.73 seconds
Started Jan 17 03:31:42 PM PST 24
Finished Jan 17 03:31:46 PM PST 24
Peak memory 206780 kb
Host smart-d9d80e65-f1da-4de2-a70b-62c57d9d9887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656615174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1656615174
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_bit_transfer.2377034221
Short name T1697
Test name
Test status
Simulation time 329234594 ps
CPU time 2.1 seconds
Started Jan 17 03:31:31 PM PST 24
Finished Jan 17 03:31:34 PM PST 24
Peak memory 217108 kb
Host smart-b50cae8b-6917-43b3-a329-9d2c21a0b83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377034221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_bit_transfer.2377034221
Directory /workspace/16.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2721935052
Short name T824
Test name
Test status
Simulation time 294359221 ps
CPU time 2.62 seconds
Started Jan 17 03:31:40 PM PST 24
Finished Jan 17 03:31:46 PM PST 24
Peak memory 218856 kb
Host smart-1fa5b345-2ff9-4aa4-ac05-efb72512bad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721935052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2721935052
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.56454171
Short name T1029
Test name
Test status
Simulation time 22593125 ps
CPU time 0.78 seconds
Started Jan 17 03:31:31 PM PST 24
Finished Jan 17 03:31:33 PM PST 24
Peak memory 207952 kb
Host smart-88c401c9-3802-4104-ada1-07527e1c58fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56454171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.56454171
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_extreme_fifo_size.3457499600
Short name T207
Test name
Test status
Simulation time 39138951469 ps
CPU time 486.7 seconds
Started Jan 17 03:31:28 PM PST 24
Finished Jan 17 03:39:36 PM PST 24
Peak memory 222380 kb
Host smart-a208fb15-2405-44a8-86fb-3d19d0b5de5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457499600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_extreme_fifo_size.3457499600
Directory /workspace/16.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/16.spi_device_fifo_full.4288259003
Short name T687
Test name
Test status
Simulation time 36012082739 ps
CPU time 771.47 seconds
Started Jan 17 03:31:24 PM PST 24
Finished Jan 17 03:44:17 PM PST 24
Peak memory 274172 kb
Host smart-5a836761-7565-4d9b-a736-79a0b7e0d98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288259003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_fifo_full.4288259003
Directory /workspace/16.spi_device_fifo_full/latest

Test location /workspace/coverage/default/16.spi_device_fifo_underflow_overflow.2721620260
Short name T1228
Test name
Test status
Simulation time 67075189091 ps
CPU time 539.26 seconds
Started Jan 17 03:31:28 PM PST 24
Finished Jan 17 03:40:28 PM PST 24
Peak memory 495436 kb
Host smart-83846277-dee3-4af6-af74-7190fdbc62e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721620260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_fifo_underflow_overf
low.2721620260
Directory /workspace/16.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2351982127
Short name T331
Test name
Test status
Simulation time 170740069333 ps
CPU time 378.6 seconds
Started Jan 17 03:31:34 PM PST 24
Finished Jan 17 03:37:56 PM PST 24
Peak memory 263968 kb
Host smart-3dc44c3c-d1c0-4112-bf03-8107437d04db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351982127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2351982127
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.782245605
Short name T793
Test name
Test status
Simulation time 30157847627 ps
CPU time 94.28 seconds
Started Jan 17 03:31:35 PM PST 24
Finished Jan 17 03:33:13 PM PST 24
Peak memory 266468 kb
Host smart-be55835e-c7af-450e-bd88-c04df8f2604e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782245605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.782245605
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1488411134
Short name T1472
Test name
Test status
Simulation time 1944291098 ps
CPU time 9.06 seconds
Started Jan 17 03:31:34 PM PST 24
Finished Jan 17 03:31:47 PM PST 24
Peak memory 232016 kb
Host smart-1e2d37d0-6da2-47fe-b852-98f37c768c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488411134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1488411134
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2391636259
Short name T710
Test name
Test status
Simulation time 898408448 ps
CPU time 3.58 seconds
Started Jan 17 03:31:31 PM PST 24
Finished Jan 17 03:31:36 PM PST 24
Peak memory 225424 kb
Host smart-4983210f-e1ba-4329-aa03-28c9a472e429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391636259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2391636259
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_intr.577919540
Short name T940
Test name
Test status
Simulation time 53409705159 ps
CPU time 28.35 seconds
Started Jan 17 03:31:31 PM PST 24
Finished Jan 17 03:32:00 PM PST 24
Peak memory 222200 kb
Host smart-0952ce28-4d9b-4d62-912a-e0df8dae16ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577919540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intr.577919540
Directory /workspace/16.spi_device_intr/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.201171251
Short name T259
Test name
Test status
Simulation time 6196811953 ps
CPU time 23.09 seconds
Started Jan 17 03:31:34 PM PST 24
Finished Jan 17 03:31:58 PM PST 24
Peak memory 241196 kb
Host smart-07c7eb50-b8ff-4075-9375-ae4b015f0cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201171251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.201171251
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.967380685
Short name T1595
Test name
Test status
Simulation time 17851773 ps
CPU time 1.04 seconds
Started Jan 17 03:31:32 PM PST 24
Finished Jan 17 03:31:33 PM PST 24
Peak memory 219124 kb
Host smart-ef45a395-33f2-4ab1-afa4-e32fea1feddb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967380685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.967380685
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2394516639
Short name T292
Test name
Test status
Simulation time 810371347 ps
CPU time 12.63 seconds
Started Jan 17 03:31:32 PM PST 24
Finished Jan 17 03:31:45 PM PST 24
Peak memory 241460 kb
Host smart-ff307df3-bcc1-4cd4-b9e0-56161a11007e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394516639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2394516639
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3759119913
Short name T232
Test name
Test status
Simulation time 1325180475 ps
CPU time 10.26 seconds
Started Jan 17 03:31:30 PM PST 24
Finished Jan 17 03:31:41 PM PST 24
Peak memory 238344 kb
Host smart-37b7ceed-3ee0-469b-9d59-4416628dca1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759119913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3759119913
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_perf.901992689
Short name T14
Test name
Test status
Simulation time 17552846288 ps
CPU time 519 seconds
Started Jan 17 03:31:28 PM PST 24
Finished Jan 17 03:40:08 PM PST 24
Peak memory 283300 kb
Host smart-074ceb96-0d24-4275-88cc-a122a8e3cef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901992689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_perf.901992689
Directory /workspace/16.spi_device_perf/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.2639473283
Short name T659
Test name
Test status
Simulation time 33012045 ps
CPU time 0.72 seconds
Started Jan 17 03:31:31 PM PST 24
Finished Jan 17 03:31:32 PM PST 24
Peak memory 217076 kb
Host smart-d964e33b-f22c-429c-beb6-bf584c5aefc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639473283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.2639473283
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.4194720316
Short name T1211
Test name
Test status
Simulation time 1636979526 ps
CPU time 5.87 seconds
Started Jan 17 03:31:37 PM PST 24
Finished Jan 17 03:31:48 PM PST 24
Peak memory 236260 kb
Host smart-d62ddc96-3b31-4b11-9bb8-15cd688e251b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4194720316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.4194720316
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_rx_async_fifo_reset.2049518382
Short name T1269
Test name
Test status
Simulation time 117507810 ps
CPU time 0.93 seconds
Started Jan 17 03:31:34 PM PST 24
Finished Jan 17 03:31:39 PM PST 24
Peak memory 208808 kb
Host smart-027ce844-98c1-418f-8ab0-80572ee229ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049518382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_rx_async_fifo_reset.2049518382
Directory /workspace/16.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/16.spi_device_rx_timeout.2509543882
Short name T975
Test name
Test status
Simulation time 2693604167 ps
CPU time 5.41 seconds
Started Jan 17 03:31:31 PM PST 24
Finished Jan 17 03:31:37 PM PST 24
Peak memory 217260 kb
Host smart-33a180b1-a45c-4650-bc45-94dd815c0a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509543882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_rx_timeout.2509543882
Directory /workspace/16.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/16.spi_device_smoke.1927470902
Short name T810
Test name
Test status
Simulation time 203603913 ps
CPU time 0.96 seconds
Started Jan 17 03:31:23 PM PST 24
Finished Jan 17 03:31:25 PM PST 24
Peak memory 208436 kb
Host smart-fa7c7117-775d-439a-9ded-511825ad3ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927470902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_smoke.1927470902
Directory /workspace/16.spi_device_smoke/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3791406253
Short name T1014
Test name
Test status
Simulation time 423658744906 ps
CPU time 4422.4 seconds
Started Jan 17 03:31:33 PM PST 24
Finished Jan 17 04:45:16 PM PST 24
Peak memory 731256 kb
Host smart-f406a81d-df31-41de-92ce-b40c53385cc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791406253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3791406253
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1205607684
Short name T823
Test name
Test status
Simulation time 30772099074 ps
CPU time 109.71 seconds
Started Jan 17 03:31:28 PM PST 24
Finished Jan 17 03:33:19 PM PST 24
Peak memory 221056 kb
Host smart-2ef98097-b0a5-4a67-984f-4a19f95bf2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205607684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1205607684
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2775856971
Short name T1661
Test name
Test status
Simulation time 5962416257 ps
CPU time 9.69 seconds
Started Jan 17 03:31:32 PM PST 24
Finished Jan 17 03:31:42 PM PST 24
Peak memory 217164 kb
Host smart-6aafd56a-1c43-4ab7-9e94-d1349713ed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775856971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2775856971
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.4275051875
Short name T789
Test name
Test status
Simulation time 75432138 ps
CPU time 2.6 seconds
Started Jan 17 03:31:33 PM PST 24
Finished Jan 17 03:31:36 PM PST 24
Peak memory 217120 kb
Host smart-fbb08b5d-933c-49ec-807e-111c9d5f1434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275051875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.4275051875
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3233596727
Short name T516
Test name
Test status
Simulation time 332545029 ps
CPU time 0.85 seconds
Started Jan 17 03:31:40 PM PST 24
Finished Jan 17 03:31:45 PM PST 24
Peak memory 207256 kb
Host smart-47cfe7f7-a7f1-4685-b3c5-d28df3be2531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233596727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3233596727
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_tx_async_fifo_reset.2284874089
Short name T814
Test name
Test status
Simulation time 46058728 ps
CPU time 0.79 seconds
Started Jan 17 03:31:28 PM PST 24
Finished Jan 17 03:31:30 PM PST 24
Peak memory 208776 kb
Host smart-53118cb9-b83a-4f72-86df-e7032f75a235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284874089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tx_async_fifo_reset.2284874089
Directory /workspace/16.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/16.spi_device_txrx.3146023539
Short name T1255
Test name
Test status
Simulation time 26064492636 ps
CPU time 271.54 seconds
Started Jan 17 03:31:28 PM PST 24
Finished Jan 17 03:36:01 PM PST 24
Peak memory 300008 kb
Host smart-3108806b-cd74-40b1-956f-a326df084db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146023539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_txrx.3146023539
Directory /workspace/16.spi_device_txrx/latest

Test location /workspace/coverage/default/16.spi_device_upload.3965307866
Short name T1301
Test name
Test status
Simulation time 291384810 ps
CPU time 3.61 seconds
Started Jan 17 03:31:34 PM PST 24
Finished Jan 17 03:31:41 PM PST 24
Peak memory 226752 kb
Host smart-db3cc8ac-73c0-43c0-bd0c-27a43c5d55f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965307866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3965307866
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3659759712
Short name T1026
Test name
Test status
Simulation time 14984896 ps
CPU time 0.7 seconds
Started Jan 17 03:31:41 PM PST 24
Finished Jan 17 03:31:45 PM PST 24
Peak memory 206824 kb
Host smart-bbc599cd-2f25-421b-8b50-d3f3c826dac9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659759712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3659759712
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_bit_transfer.1519793687
Short name T1733
Test name
Test status
Simulation time 568967700 ps
CPU time 2.5 seconds
Started Jan 17 03:31:39 PM PST 24
Finished Jan 17 03:31:46 PM PST 24
Peak memory 217120 kb
Host smart-d7348ef0-204e-4589-bf16-fae9da4c47b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519793687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_bit_transfer.1519793687
Directory /workspace/17.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/17.spi_device_byte_transfer.4292280759
Short name T1545
Test name
Test status
Simulation time 370759063 ps
CPU time 3.01 seconds
Started Jan 17 03:31:37 PM PST 24
Finished Jan 17 03:31:45 PM PST 24
Peak memory 217144 kb
Host smart-fa1a42db-7c04-460b-a2e9-ed51f1faff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292280759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_byte_transfer.4292280759
Directory /workspace/17.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.914798066
Short name T273
Test name
Test status
Simulation time 303530308 ps
CPU time 5.02 seconds
Started Jan 17 03:31:48 PM PST 24
Finished Jan 17 03:31:54 PM PST 24
Peak memory 225444 kb
Host smart-6b779023-1f4f-4788-a158-b48cfeff2882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914798066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.914798066
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2219212590
Short name T1154
Test name
Test status
Simulation time 125765152 ps
CPU time 0.8 seconds
Started Jan 17 03:31:38 PM PST 24
Finished Jan 17 03:31:44 PM PST 24
Peak memory 207928 kb
Host smart-430e726c-c879-41aa-af7c-e927789c3871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219212590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2219212590
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_extreme_fifo_size.3550669828
Short name T269
Test name
Test status
Simulation time 320692220664 ps
CPU time 3247.5 seconds
Started Jan 17 03:31:36 PM PST 24
Finished Jan 17 04:25:48 PM PST 24
Peak memory 221376 kb
Host smart-05bf613e-578f-44e4-893a-30ff9e6cdd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550669828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_extreme_fifo_size.3550669828
Directory /workspace/17.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/17.spi_device_fifo_full.3687138900
Short name T709
Test name
Test status
Simulation time 46301987180 ps
CPU time 206.65 seconds
Started Jan 17 03:31:36 PM PST 24
Finished Jan 17 03:35:08 PM PST 24
Peak memory 265504 kb
Host smart-adf90a34-76dc-4d7b-8af2-1524905e1af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687138900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_fifo_full.3687138900
Directory /workspace/17.spi_device_fifo_full/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.548245495
Short name T244
Test name
Test status
Simulation time 4202187945 ps
CPU time 54.12 seconds
Started Jan 17 03:31:42 PM PST 24
Finished Jan 17 03:32:39 PM PST 24
Peak memory 254780 kb
Host smart-2e8aee15-ef2b-4868-8284-e7dee0c314f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548245495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.548245495
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1775805113
Short name T19
Test name
Test status
Simulation time 63625254622 ps
CPU time 219.03 seconds
Started Jan 17 03:31:45 PM PST 24
Finished Jan 17 03:35:26 PM PST 24
Peak memory 250088 kb
Host smart-e1c540b3-a1fe-4025-b478-85449ea7fec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775805113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1775805113
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2171650750
Short name T1133
Test name
Test status
Simulation time 440085334 ps
CPU time 12.45 seconds
Started Jan 17 03:31:43 PM PST 24
Finished Jan 17 03:31:58 PM PST 24
Peak memory 232768 kb
Host smart-4609e4f5-954b-4186-a8fe-453052f16a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171650750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2171650750
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3183575097
Short name T245
Test name
Test status
Simulation time 893850426 ps
CPU time 4.3 seconds
Started Jan 17 03:31:41 PM PST 24
Finished Jan 17 03:31:49 PM PST 24
Peak memory 241624 kb
Host smart-0508fd42-3691-4a8f-811d-6aabcac031f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183575097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3183575097
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_intr.1927523229
Short name T716
Test name
Test status
Simulation time 5119858133 ps
CPU time 27.97 seconds
Started Jan 17 03:31:39 PM PST 24
Finished Jan 17 03:32:11 PM PST 24
Peak memory 222892 kb
Host smart-5320800d-fda5-49cb-8c3a-fe905e40e30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927523229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intr.1927523229
Directory /workspace/17.spi_device_intr/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.33703860
Short name T21
Test name
Test status
Simulation time 1504479911 ps
CPU time 14.55 seconds
Started Jan 17 03:31:45 PM PST 24
Finished Jan 17 03:32:01 PM PST 24
Peak memory 248996 kb
Host smart-287076ac-ce24-45fe-b92f-467c558a7ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33703860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.33703860
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2284743156
Short name T1283
Test name
Test status
Simulation time 30478279 ps
CPU time 1.02 seconds
Started Jan 17 03:31:46 PM PST 24
Finished Jan 17 03:31:49 PM PST 24
Peak memory 219056 kb
Host smart-af82e56b-b7ea-427d-96a8-23c860ed3422
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284743156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2284743156
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.832143511
Short name T312
Test name
Test status
Simulation time 2281386213 ps
CPU time 10.41 seconds
Started Jan 17 03:31:47 PM PST 24
Finished Jan 17 03:31:58 PM PST 24
Peak memory 241248 kb
Host smart-e41369d6-864a-4b16-a858-febc7514e9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832143511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.832143511
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1516028617
Short name T1191
Test name
Test status
Simulation time 12836385980 ps
CPU time 12.8 seconds
Started Jan 17 03:31:51 PM PST 24
Finished Jan 17 03:32:06 PM PST 24
Peak memory 225496 kb
Host smart-68e166dd-d340-4eef-b488-982ae479cb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516028617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1516028617
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_perf.1255858849
Short name T1651
Test name
Test status
Simulation time 13541917664 ps
CPU time 61.84 seconds
Started Jan 17 03:31:46 PM PST 24
Finished Jan 17 03:32:50 PM PST 24
Peak memory 239976 kb
Host smart-c911bbc9-9803-4805-a238-45c5cec458c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255858849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_perf.1255858849
Directory /workspace/17.spi_device_perf/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.3371205995
Short name T760
Test name
Test status
Simulation time 46587068 ps
CPU time 0.72 seconds
Started Jan 17 03:31:37 PM PST 24
Finished Jan 17 03:31:43 PM PST 24
Peak memory 217020 kb
Host smart-9961e011-d281-46db-8d9b-cb5533d6bf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371205995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.3371205995
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.228164739
Short name T1081
Test name
Test status
Simulation time 5700074348 ps
CPU time 4.2 seconds
Started Jan 17 03:31:47 PM PST 24
Finished Jan 17 03:31:52 PM PST 24
Peak memory 218548 kb
Host smart-e4fb0bcf-4851-4793-a609-98f4ed4614af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=228164739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.228164739
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_rx_async_fifo_reset.1221995170
Short name T620
Test name
Test status
Simulation time 21115029 ps
CPU time 0.93 seconds
Started Jan 17 03:31:45 PM PST 24
Finished Jan 17 03:31:47 PM PST 24
Peak memory 208752 kb
Host smart-098c7d6c-1198-46e0-a1e3-1b0f3f216656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221995170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_rx_async_fifo_reset.1221995170
Directory /workspace/17.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/17.spi_device_rx_timeout.697850788
Short name T1311
Test name
Test status
Simulation time 2208855920 ps
CPU time 6.04 seconds
Started Jan 17 03:31:45 PM PST 24
Finished Jan 17 03:31:52 PM PST 24
Peak memory 217148 kb
Host smart-dda3d715-7daa-4ca8-ab17-a7f664c73dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697850788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_rx_timeout.697850788
Directory /workspace/17.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/17.spi_device_smoke.3880642197
Short name T681
Test name
Test status
Simulation time 293383990 ps
CPU time 1.08 seconds
Started Jan 17 03:31:46 PM PST 24
Finished Jan 17 03:31:48 PM PST 24
Peak memory 216892 kb
Host smart-8e42a971-3de9-4ae8-a0e2-e886e13210f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880642197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_smoke.3880642197
Directory /workspace/17.spi_device_smoke/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4114693019
Short name T1586
Test name
Test status
Simulation time 873417270 ps
CPU time 7.41 seconds
Started Jan 17 03:31:39 PM PST 24
Finished Jan 17 03:31:51 PM PST 24
Peak memory 217120 kb
Host smart-841feecb-76f1-46ec-bb80-c3669b5a16cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114693019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4114693019
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1306422358
Short name T962
Test name
Test status
Simulation time 9345185052 ps
CPU time 28.09 seconds
Started Jan 17 03:31:37 PM PST 24
Finished Jan 17 03:32:11 PM PST 24
Peak memory 217184 kb
Host smart-70cb1ae4-b799-437a-816b-e833b39b4600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306422358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1306422358
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1954052139
Short name T978
Test name
Test status
Simulation time 476576442 ps
CPU time 1.53 seconds
Started Jan 17 03:31:47 PM PST 24
Finished Jan 17 03:31:50 PM PST 24
Peak memory 217152 kb
Host smart-fa5e8b37-6b7a-4fd5-95fa-72e0fe39128f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954052139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1954052139
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3107441194
Short name T1371
Test name
Test status
Simulation time 124695162 ps
CPU time 0.86 seconds
Started Jan 17 03:31:44 PM PST 24
Finished Jan 17 03:31:47 PM PST 24
Peak memory 207292 kb
Host smart-298e5e0d-fe8e-49a3-80a5-514a4a62c527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107441194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3107441194
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_tx_async_fifo_reset.1692184176
Short name T1395
Test name
Test status
Simulation time 57568858 ps
CPU time 0.8 seconds
Started Jan 17 03:31:47 PM PST 24
Finished Jan 17 03:31:49 PM PST 24
Peak memory 208768 kb
Host smart-77846d06-fb73-4011-86e5-50b2def1d001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692184176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tx_async_fifo_reset.1692184176
Directory /workspace/17.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/17.spi_device_txrx.3617023968
Short name T907
Test name
Test status
Simulation time 188655150839 ps
CPU time 1019.02 seconds
Started Jan 17 03:31:40 PM PST 24
Finished Jan 17 03:48:43 PM PST 24
Peak memory 276476 kb
Host smart-abf99db0-b2a9-454c-b1e2-3b86fc144147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617023968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_txrx.3617023968
Directory /workspace/17.spi_device_txrx/latest

Test location /workspace/coverage/default/17.spi_device_upload.1882086926
Short name T1695
Test name
Test status
Simulation time 15658372346 ps
CPU time 32.64 seconds
Started Jan 17 03:31:47 PM PST 24
Finished Jan 17 03:32:21 PM PST 24
Peak memory 220768 kb
Host smart-17d6a84e-ec23-4edb-b831-3b6708aa7317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882086926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1882086926
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_abort.4108310456
Short name T899
Test name
Test status
Simulation time 14906088 ps
CPU time 0.8 seconds
Started Jan 17 03:31:48 PM PST 24
Finished Jan 17 03:31:51 PM PST 24
Peak memory 207048 kb
Host smart-06824f81-5326-4cde-a882-bf52468cbdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108310456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_abort.4108310456
Directory /workspace/18.spi_device_abort/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2141203358
Short name T509
Test name
Test status
Simulation time 27397281 ps
CPU time 0.78 seconds
Started Jan 17 03:31:53 PM PST 24
Finished Jan 17 03:31:54 PM PST 24
Peak memory 206824 kb
Host smart-4b3db49a-6154-41a8-9dec-d10b77792dbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141203358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2141203358
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_bit_transfer.363160303
Short name T1276
Test name
Test status
Simulation time 197884920 ps
CPU time 2.43 seconds
Started Jan 17 03:31:49 PM PST 24
Finished Jan 17 03:31:53 PM PST 24
Peak memory 217128 kb
Host smart-e9c1f324-bc4c-483b-8197-f0094c22fec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363160303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_bit_transfer.363160303
Directory /workspace/18.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/18.spi_device_byte_transfer.1849748414
Short name T1346
Test name
Test status
Simulation time 109008930 ps
CPU time 2.36 seconds
Started Jan 17 03:31:50 PM PST 24
Finished Jan 17 03:31:53 PM PST 24
Peak memory 217092 kb
Host smart-c0994ba7-1050-49c6-8911-4edaf846af24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849748414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_byte_transfer.1849748414
Directory /workspace/18.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.653498518
Short name T1188
Test name
Test status
Simulation time 4511310142 ps
CPU time 6.66 seconds
Started Jan 17 03:31:52 PM PST 24
Finished Jan 17 03:32:00 PM PST 24
Peak memory 241048 kb
Host smart-06fc314e-51d9-473b-a325-43f7e49ccc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653498518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.653498518
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.258413578
Short name T517
Test name
Test status
Simulation time 19403494 ps
CPU time 0.78 seconds
Started Jan 17 03:31:48 PM PST 24
Finished Jan 17 03:31:49 PM PST 24
Peak memory 206944 kb
Host smart-fb867644-a912-49bd-809d-6ccfa06267c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258413578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.258413578
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_dummy_item_extra_dly.2264126832
Short name T497
Test name
Test status
Simulation time 45583529784 ps
CPU time 292.15 seconds
Started Jan 17 03:31:48 PM PST 24
Finished Jan 17 03:36:41 PM PST 24
Peak memory 286668 kb
Host smart-b515b37b-a1c1-48db-b747-a1b952ec2f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264126832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_dummy_item_extra_dly.2264126832
Directory /workspace/18.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/18.spi_device_extreme_fifo_size.67711943
Short name T685
Test name
Test status
Simulation time 8927897613 ps
CPU time 57.97 seconds
Started Jan 17 03:31:47 PM PST 24
Finished Jan 17 03:32:46 PM PST 24
Peak memory 225360 kb
Host smart-9d86aee5-e772-4292-967d-01e0114eb393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67711943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_extreme_fifo_size.67711943
Directory /workspace/18.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/18.spi_device_fifo_full.1551693282
Short name T1637
Test name
Test status
Simulation time 111186383584 ps
CPU time 967.09 seconds
Started Jan 17 03:31:45 PM PST 24
Finished Jan 17 03:47:54 PM PST 24
Peak memory 269920 kb
Host smart-199ca511-610b-48ea-b7e2-1d0a570cbe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551693282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_fifo_full.1551693282
Directory /workspace/18.spi_device_fifo_full/latest

Test location /workspace/coverage/default/18.spi_device_fifo_underflow_overflow.1091954532
Short name T562
Test name
Test status
Simulation time 167506477281 ps
CPU time 462.23 seconds
Started Jan 17 03:31:47 PM PST 24
Finished Jan 17 03:39:30 PM PST 24
Peak memory 377992 kb
Host smart-eb4a2c4f-e334-4363-97ad-c800a4561216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091954532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_fifo_underflow_overf
low.1091954532
Directory /workspace/18.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1860642995
Short name T925
Test name
Test status
Simulation time 9838334534 ps
CPU time 51.79 seconds
Started Jan 17 03:32:20 PM PST 24
Finished Jan 17 03:33:14 PM PST 24
Peak memory 256260 kb
Host smart-be2b0393-9806-4a78-9d4c-2f6ce73c0777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860642995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1860642995
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3316515078
Short name T1165
Test name
Test status
Simulation time 67477382307 ps
CPU time 155.59 seconds
Started Jan 17 03:31:53 PM PST 24
Finished Jan 17 03:34:29 PM PST 24
Peak memory 274656 kb
Host smart-12f91d1d-daf7-4731-92ae-33258cb7e672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316515078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3316515078
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.419790374
Short name T1406
Test name
Test status
Simulation time 69920487180 ps
CPU time 558.48 seconds
Started Jan 17 03:32:20 PM PST 24
Finished Jan 17 03:41:40 PM PST 24
Peak memory 264456 kb
Host smart-58c40865-c461-486d-a4f8-0e6837cd6cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419790374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.419790374
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.988380296
Short name T352
Test name
Test status
Simulation time 2904196501 ps
CPU time 17.43 seconds
Started Jan 17 03:31:50 PM PST 24
Finished Jan 17 03:32:08 PM PST 24
Peak memory 248128 kb
Host smart-272287ed-2350-40a2-934f-2ff6f15e634f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988380296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.988380296
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2527605807
Short name T290
Test name
Test status
Simulation time 7791605550 ps
CPU time 6.87 seconds
Started Jan 17 03:31:50 PM PST 24
Finished Jan 17 03:31:58 PM PST 24
Peak memory 221228 kb
Host smart-13003a7d-006d-4133-a147-572c44e04b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527605807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2527605807
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_intr.931851459
Short name T1776
Test name
Test status
Simulation time 47337122154 ps
CPU time 51.2 seconds
Started Jan 17 03:31:50 PM PST 24
Finished Jan 17 03:32:42 PM PST 24
Peak memory 225472 kb
Host smart-99628f70-910d-43d4-9e0b-558e8debfd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931851459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intr.931851459
Directory /workspace/18.spi_device_intr/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2218152449
Short name T1078
Test name
Test status
Simulation time 2466257289 ps
CPU time 14.81 seconds
Started Jan 17 03:31:49 PM PST 24
Finished Jan 17 03:32:05 PM PST 24
Peak memory 241764 kb
Host smart-d5e0c19b-eeba-44e0-bc36-0473e99ca723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218152449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2218152449
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.216050531
Short name T42
Test name
Test status
Simulation time 53786030 ps
CPU time 1.04 seconds
Started Jan 17 03:31:47 PM PST 24
Finished Jan 17 03:31:49 PM PST 24
Peak memory 219156 kb
Host smart-6f5d82ce-2f2d-457a-90c1-38410498c061
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216050531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.216050531
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1467444573
Short name T348
Test name
Test status
Simulation time 147315079357 ps
CPU time 50.52 seconds
Started Jan 17 03:31:48 PM PST 24
Finished Jan 17 03:32:39 PM PST 24
Peak memory 252584 kb
Host smart-c393aa72-3e98-4da4-92a1-76f2d075883e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467444573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1467444573
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.4166852794
Short name T1445
Test name
Test status
Simulation time 383777174 ps
CPU time 3.47 seconds
Started Jan 17 03:31:53 PM PST 24
Finished Jan 17 03:31:57 PM PST 24
Peak memory 225368 kb
Host smart-e983e261-c687-41cf-a3fc-8997bd0c928c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166852794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.4166852794
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_perf.1977996971
Short name T901
Test name
Test status
Simulation time 22103651377 ps
CPU time 470.93 seconds
Started Jan 17 03:31:46 PM PST 24
Finished Jan 17 03:39:38 PM PST 24
Peak memory 266484 kb
Host smart-35dcc044-656d-429e-aaa9-e7ed5fc3d866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977996971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_perf.1977996971
Directory /workspace/18.spi_device_perf/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.470447351
Short name T1199
Test name
Test status
Simulation time 15751041 ps
CPU time 0.86 seconds
Started Jan 17 03:31:47 PM PST 24
Finished Jan 17 03:31:49 PM PST 24
Peak memory 217088 kb
Host smart-ae75b473-d73a-424d-abf0-7862761fb02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470447351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.470447351
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1589470917
Short name T822
Test name
Test status
Simulation time 636703142 ps
CPU time 4.88 seconds
Started Jan 17 03:31:55 PM PST 24
Finished Jan 17 03:32:02 PM PST 24
Peak memory 220944 kb
Host smart-33a4bebd-1bba-49da-81f4-2cf34d25b729
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1589470917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1589470917
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_rx_async_fifo_reset.984509459
Short name T1172
Test name
Test status
Simulation time 18448445 ps
CPU time 0.86 seconds
Started Jan 17 03:31:46 PM PST 24
Finished Jan 17 03:31:49 PM PST 24
Peak memory 208764 kb
Host smart-ad4be4d6-86e2-4edc-896a-15811da08c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984509459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_rx_async_fifo_reset.984509459
Directory /workspace/18.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/18.spi_device_rx_timeout.4026094025
Short name T1645
Test name
Test status
Simulation time 751812452 ps
CPU time 6.95 seconds
Started Jan 17 03:31:48 PM PST 24
Finished Jan 17 03:31:56 PM PST 24
Peak memory 217132 kb
Host smart-6d0a759a-c544-4d6d-bd68-b1d8ab9fbed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026094025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_rx_timeout.4026094025
Directory /workspace/18.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/18.spi_device_smoke.2609686142
Short name T882
Test name
Test status
Simulation time 94255825 ps
CPU time 0.94 seconds
Started Jan 17 03:31:47 PM PST 24
Finished Jan 17 03:31:49 PM PST 24
Peak memory 208228 kb
Host smart-23666609-a49c-4047-b179-5cc6a5a696bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609686142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_smoke.2609686142
Directory /workspace/18.spi_device_smoke/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.848153802
Short name T1101
Test name
Test status
Simulation time 7042431885 ps
CPU time 14.04 seconds
Started Jan 17 03:31:49 PM PST 24
Finished Jan 17 03:32:04 PM PST 24
Peak memory 217160 kb
Host smart-fd496994-b3be-45d7-aed7-431403539c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848153802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.848153802
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2900939956
Short name T1020
Test name
Test status
Simulation time 409885204 ps
CPU time 2.46 seconds
Started Jan 17 03:31:46 PM PST 24
Finished Jan 17 03:31:50 PM PST 24
Peak memory 217216 kb
Host smart-f2b6273d-f993-4b02-b36e-7bfa51c37828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900939956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2900939956
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3763040420
Short name T1069
Test name
Test status
Simulation time 284638290 ps
CPU time 1.07 seconds
Started Jan 17 03:31:50 PM PST 24
Finished Jan 17 03:31:52 PM PST 24
Peak memory 208232 kb
Host smart-b63d822f-7540-4392-bc43-61f02f539056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763040420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3763040420
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.546967648
Short name T1485
Test name
Test status
Simulation time 74369812 ps
CPU time 0.74 seconds
Started Jan 17 03:31:47 PM PST 24
Finished Jan 17 03:31:49 PM PST 24
Peak memory 207228 kb
Host smart-6730d1b1-704a-47f1-91e7-73844129bce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546967648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.546967648
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_tx_async_fifo_reset.132285699
Short name T1555
Test name
Test status
Simulation time 29543770 ps
CPU time 0.8 seconds
Started Jan 17 03:31:45 PM PST 24
Finished Jan 17 03:31:47 PM PST 24
Peak memory 208756 kb
Host smart-b6aa0e1b-e373-4e6e-86c8-b7b067b32fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132285699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tx_async_fifo_reset.132285699
Directory /workspace/18.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/18.spi_device_txrx.1664923175
Short name T1388
Test name
Test status
Simulation time 37644071595 ps
CPU time 375.9 seconds
Started Jan 17 03:31:47 PM PST 24
Finished Jan 17 03:38:04 PM PST 24
Peak memory 310168 kb
Host smart-149bbae9-089a-4142-9bd5-693720ba4d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664923175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_txrx.1664923175
Directory /workspace/18.spi_device_txrx/latest

Test location /workspace/coverage/default/18.spi_device_upload.3636280194
Short name T247
Test name
Test status
Simulation time 1220515896 ps
CPU time 9.07 seconds
Started Jan 17 03:31:52 PM PST 24
Finished Jan 17 03:32:02 PM PST 24
Peak memory 221240 kb
Host smart-ad47df0a-0f42-4c1b-918c-3db9304ce0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636280194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3636280194
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_abort.1408106959
Short name T1125
Test name
Test status
Simulation time 47475184 ps
CPU time 0.73 seconds
Started Jan 17 03:32:08 PM PST 24
Finished Jan 17 03:32:09 PM PST 24
Peak memory 207016 kb
Host smart-8c569447-6c99-4b69-921f-29281421799e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408106959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_abort.1408106959
Directory /workspace/19.spi_device_abort/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3375188343
Short name T523
Test name
Test status
Simulation time 15099713 ps
CPU time 0.81 seconds
Started Jan 17 03:32:08 PM PST 24
Finished Jan 17 03:32:10 PM PST 24
Peak memory 206772 kb
Host smart-2f51160b-6c30-41db-a157-810dc07c135d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375188343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3375188343
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_bit_transfer.1850944417
Short name T1375
Test name
Test status
Simulation time 1214655286 ps
CPU time 2.36 seconds
Started Jan 17 03:32:12 PM PST 24
Finished Jan 17 03:32:15 PM PST 24
Peak memory 217136 kb
Host smart-6cd19cda-1e67-4097-8cde-0e0ae56b9252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850944417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_bit_transfer.1850944417
Directory /workspace/19.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/19.spi_device_byte_transfer.3970185171
Short name T1002
Test name
Test status
Simulation time 249024217 ps
CPU time 3.32 seconds
Started Jan 17 03:32:08 PM PST 24
Finished Jan 17 03:32:12 PM PST 24
Peak memory 217152 kb
Host smart-e0991162-051e-42e0-8c55-aa4f658358d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970185171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_byte_transfer.3970185171
Directory /workspace/19.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.626714425
Short name T311
Test name
Test status
Simulation time 1367900592 ps
CPU time 3.74 seconds
Started Jan 17 03:32:02 PM PST 24
Finished Jan 17 03:32:11 PM PST 24
Peak memory 218704 kb
Host smart-ffd166bf-b9a9-4736-8cf6-19d96047ceb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626714425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.626714425
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2352135944
Short name T647
Test name
Test status
Simulation time 17636295 ps
CPU time 0.78 seconds
Started Jan 17 03:32:00 PM PST 24
Finished Jan 17 03:32:02 PM PST 24
Peak memory 207980 kb
Host smart-5d27205e-3314-4faf-8897-aafbdd5b4789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352135944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2352135944
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_dummy_item_extra_dly.1297592326
Short name T771
Test name
Test status
Simulation time 30818269971 ps
CPU time 497.89 seconds
Started Jan 17 03:32:05 PM PST 24
Finished Jan 17 03:40:25 PM PST 24
Peak memory 264372 kb
Host smart-ae28f2d8-79ae-438e-b991-4ab0c92cc6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297592326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_dummy_item_extra_dly.1297592326
Directory /workspace/19.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/19.spi_device_extreme_fifo_size.2715343454
Short name T625
Test name
Test status
Simulation time 82481236587 ps
CPU time 3694.19 seconds
Started Jan 17 03:31:53 PM PST 24
Finished Jan 17 04:33:28 PM PST 24
Peak memory 221568 kb
Host smart-51ace1ca-c3cd-40ba-bff4-45a5c2ba28b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715343454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_extreme_fifo_size.2715343454
Directory /workspace/19.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/19.spi_device_fifo_full.2536636146
Short name T606
Test name
Test status
Simulation time 127591527932 ps
CPU time 249.09 seconds
Started Jan 17 03:31:55 PM PST 24
Finished Jan 17 03:36:07 PM PST 24
Peak memory 272180 kb
Host smart-965c886a-55d9-4195-b93c-11b17eb6907a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536636146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_fifo_full.2536636146
Directory /workspace/19.spi_device_fifo_full/latest

Test location /workspace/coverage/default/19.spi_device_fifo_underflow_overflow.3671744834
Short name T573
Test name
Test status
Simulation time 105009232816 ps
CPU time 720.9 seconds
Started Jan 17 03:31:57 PM PST 24
Finished Jan 17 03:44:01 PM PST 24
Peak memory 548192 kb
Host smart-b6282f80-5f4d-4f96-a21d-25ed3b8e257d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671744834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_fifo_underflow_overf
low.3671744834
Directory /workspace/19.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1055987571
Short name T675
Test name
Test status
Simulation time 12820969600 ps
CPU time 62.58 seconds
Started Jan 17 03:32:08 PM PST 24
Finished Jan 17 03:33:11 PM PST 24
Peak memory 250160 kb
Host smart-56713921-55e1-4ec0-a13f-644875586882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055987571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1055987571
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1312588608
Short name T252
Test name
Test status
Simulation time 33703492161 ps
CPU time 67.25 seconds
Started Jan 17 03:32:09 PM PST 24
Finished Jan 17 03:33:17 PM PST 24
Peak memory 258420 kb
Host smart-3df2d654-a810-4f95-8270-3d30714faa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312588608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1312588608
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.561218536
Short name T1772
Test name
Test status
Simulation time 3630805792 ps
CPU time 13.75 seconds
Started Jan 17 03:32:09 PM PST 24
Finished Jan 17 03:32:23 PM PST 24
Peak memory 222712 kb
Host smart-f43c40c1-a01d-4b30-be0e-ac38f356f37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561218536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.561218536
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.693889454
Short name T256
Test name
Test status
Simulation time 417021650 ps
CPU time 3.43 seconds
Started Jan 17 03:32:08 PM PST 24
Finished Jan 17 03:32:12 PM PST 24
Peak memory 218896 kb
Host smart-6c8b3660-5254-408c-8f43-81cf90023622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693889454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.693889454
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_intr.1339876178
Short name T1142
Test name
Test status
Simulation time 56924178896 ps
CPU time 45.18 seconds
Started Jan 17 03:31:56 PM PST 24
Finished Jan 17 03:32:44 PM PST 24
Peak memory 225128 kb
Host smart-de9df569-27a7-4889-8b24-8834e0cf6e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339876178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intr.1339876178
Directory /workspace/19.spi_device_intr/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1201709432
Short name T1631
Test name
Test status
Simulation time 11037093988 ps
CPU time 22.65 seconds
Started Jan 17 03:32:12 PM PST 24
Finished Jan 17 03:32:35 PM PST 24
Peak memory 241488 kb
Host smart-4a92bc95-fd6e-43c0-bf63-d26423d6b241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201709432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1201709432
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2828032144
Short name T990
Test name
Test status
Simulation time 59259708 ps
CPU time 1.05 seconds
Started Jan 17 03:32:06 PM PST 24
Finished Jan 17 03:32:08 PM PST 24
Peak memory 219268 kb
Host smart-d53458a3-1b8b-4e6f-9592-82886e7b0980
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828032144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2828032144
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3127744558
Short name T914
Test name
Test status
Simulation time 42374693953 ps
CPU time 8.08 seconds
Started Jan 17 03:32:12 PM PST 24
Finished Jan 17 03:32:21 PM PST 24
Peak memory 223552 kb
Host smart-742c8571-8fce-49ec-a9c0-b7a37d719f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127744558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3127744558
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3851421099
Short name T1605
Test name
Test status
Simulation time 15881728639 ps
CPU time 12.88 seconds
Started Jan 17 03:32:11 PM PST 24
Finished Jan 17 03:32:25 PM PST 24
Peak memory 220308 kb
Host smart-b45ba693-9c46-4f62-96ab-05e784961807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851421099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3851421099
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_perf.3555191058
Short name T1432
Test name
Test status
Simulation time 24109185800 ps
CPU time 1532.12 seconds
Started Jan 17 03:32:08 PM PST 24
Finished Jan 17 03:57:42 PM PST 24
Peak memory 257824 kb
Host smart-b3e0cab8-6ca9-40c4-b2f1-493343f00920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555191058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_perf.3555191058
Directory /workspace/19.spi_device_perf/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.769849335
Short name T1692
Test name
Test status
Simulation time 32645342 ps
CPU time 0.72 seconds
Started Jan 17 03:32:07 PM PST 24
Finished Jan 17 03:32:09 PM PST 24
Peak memory 216992 kb
Host smart-9f3e5d39-b56f-4e33-9b36-6bc84a6b856e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769849335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.769849335
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4093333422
Short name T776
Test name
Test status
Simulation time 100556586 ps
CPU time 3.57 seconds
Started Jan 17 03:32:07 PM PST 24
Finished Jan 17 03:32:11 PM PST 24
Peak memory 219272 kb
Host smart-950e6b9c-5cd3-406d-8688-c92bb2e67d01
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4093333422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4093333422
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_rx_async_fifo_reset.1946914724
Short name T1757
Test name
Test status
Simulation time 19912771 ps
CPU time 0.87 seconds
Started Jan 17 03:32:19 PM PST 24
Finished Jan 17 03:32:22 PM PST 24
Peak memory 208796 kb
Host smart-7b5fd902-87e6-4a7a-8d95-08e717dd7d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946914724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_rx_async_fifo_reset.1946914724
Directory /workspace/19.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/19.spi_device_rx_timeout.4254978741
Short name T1717
Test name
Test status
Simulation time 723451464 ps
CPU time 5.45 seconds
Started Jan 17 03:32:08 PM PST 24
Finished Jan 17 03:32:14 PM PST 24
Peak memory 217120 kb
Host smart-70ccae40-7af3-446c-a6eb-9ce1f1f4a9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254978741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_rx_timeout.4254978741
Directory /workspace/19.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/19.spi_device_smoke.2534774085
Short name T1621
Test name
Test status
Simulation time 43557357 ps
CPU time 1.19 seconds
Started Jan 17 03:32:19 PM PST 24
Finished Jan 17 03:32:22 PM PST 24
Peak memory 217112 kb
Host smart-a3d741aa-0114-44a2-8531-91e87be3668f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534774085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_smoke.2534774085
Directory /workspace/19.spi_device_smoke/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3716005213
Short name T228
Test name
Test status
Simulation time 1154086547570 ps
CPU time 2377.03 seconds
Started Jan 17 03:32:09 PM PST 24
Finished Jan 17 04:11:47 PM PST 24
Peak memory 340156 kb
Host smart-e50fad4e-f169-4549-b289-1bb45477c730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716005213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3716005213
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3830473348
Short name T807
Test name
Test status
Simulation time 1522221515 ps
CPU time 21.52 seconds
Started Jan 17 03:32:07 PM PST 24
Finished Jan 17 03:32:29 PM PST 24
Peak memory 220240 kb
Host smart-a078f948-b629-4553-8c8c-cb2cb69aaffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830473348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3830473348
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2941881352
Short name T1284
Test name
Test status
Simulation time 1702344846 ps
CPU time 9.98 seconds
Started Jan 17 03:32:09 PM PST 24
Finished Jan 17 03:32:20 PM PST 24
Peak memory 217136 kb
Host smart-48f1551a-e1d4-4d9b-bb97-0e31380ba8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941881352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2941881352
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2866931937
Short name T747
Test name
Test status
Simulation time 2435931383 ps
CPU time 15.02 seconds
Started Jan 17 03:32:09 PM PST 24
Finished Jan 17 03:32:25 PM PST 24
Peak memory 217136 kb
Host smart-834b3d93-3ce9-4afc-bb1b-1ac7443fa6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866931937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2866931937
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4051604549
Short name T646
Test name
Test status
Simulation time 30203112 ps
CPU time 0.9 seconds
Started Jan 17 03:32:08 PM PST 24
Finished Jan 17 03:32:09 PM PST 24
Peak memory 208432 kb
Host smart-98a76e85-da5e-42db-babf-a7a0c9874340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051604549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4051604549
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_tx_async_fifo_reset.2666979675
Short name T1519
Test name
Test status
Simulation time 16022828 ps
CPU time 0.76 seconds
Started Jan 17 03:31:59 PM PST 24
Finished Jan 17 03:32:02 PM PST 24
Peak memory 208764 kb
Host smart-4431f5d5-4753-4b90-8ada-03f0e30923de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666979675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tx_async_fifo_reset.2666979675
Directory /workspace/19.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/19.spi_device_txrx.2365498779
Short name T1415
Test name
Test status
Simulation time 75276640467 ps
CPU time 126.77 seconds
Started Jan 17 03:31:55 PM PST 24
Finished Jan 17 03:34:04 PM PST 24
Peak memory 261452 kb
Host smart-c2f331a3-de32-486a-a804-c7494385f798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365498779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_txrx.2365498779
Directory /workspace/19.spi_device_txrx/latest

Test location /workspace/coverage/default/19.spi_device_upload.658235992
Short name T1426
Test name
Test status
Simulation time 13291003244 ps
CPU time 17.11 seconds
Started Jan 17 03:32:08 PM PST 24
Finished Jan 17 03:32:25 PM PST 24
Peak memory 250240 kb
Host smart-7fce86ff-0f9a-44dd-97ad-5c46f1671d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658235992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.658235992
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_abort.4122929356
Short name T1561
Test name
Test status
Simulation time 55138963 ps
CPU time 0.76 seconds
Started Jan 17 03:28:56 PM PST 24
Finished Jan 17 03:28:57 PM PST 24
Peak memory 207016 kb
Host smart-e528ccf6-8186-4b46-a368-d833a819d148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122929356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_abort.4122929356
Directory /workspace/2.spi_device_abort/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2636007384
Short name T1126
Test name
Test status
Simulation time 28997384 ps
CPU time 0.76 seconds
Started Jan 17 03:28:56 PM PST 24
Finished Jan 17 03:28:57 PM PST 24
Peak memory 206800 kb
Host smart-88c71303-1b75-405e-b235-e2405013fa39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636007384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
636007384
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_bit_transfer.171944336
Short name T1373
Test name
Test status
Simulation time 3186744714 ps
CPU time 4.24 seconds
Started Jan 17 03:28:51 PM PST 24
Finished Jan 17 03:28:57 PM PST 24
Peak memory 217196 kb
Host smart-1c83e0b7-32d3-427e-86dc-4acf46b4791d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171944336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_bit_transfer.171944336
Directory /workspace/2.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/2.spi_device_byte_transfer.2997431692
Short name T1055
Test name
Test status
Simulation time 165092476 ps
CPU time 3.25 seconds
Started Jan 17 03:28:56 PM PST 24
Finished Jan 17 03:29:00 PM PST 24
Peak memory 217184 kb
Host smart-ed2cf3c4-5323-4b14-bd1a-8fc5e848ec67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997431692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_byte_transfer.2997431692
Directory /workspace/2.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1036627717
Short name T1205
Test name
Test status
Simulation time 263930068 ps
CPU time 4.64 seconds
Started Jan 17 03:28:57 PM PST 24
Finished Jan 17 03:29:09 PM PST 24
Peak memory 241768 kb
Host smart-67f2daee-7c96-4b04-9d48-8b75bd10fd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036627717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1036627717
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3058880429
Short name T916
Test name
Test status
Simulation time 28403532 ps
CPU time 0.76 seconds
Started Jan 17 03:28:59 PM PST 24
Finished Jan 17 03:29:05 PM PST 24
Peak memory 206908 kb
Host smart-685fb21f-8448-44bc-8fce-2ff25758ef94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058880429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3058880429
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_dummy_item_extra_dly.795994514
Short name T944
Test name
Test status
Simulation time 244765758735 ps
CPU time 576.95 seconds
Started Jan 17 03:28:49 PM PST 24
Finished Jan 17 03:38:27 PM PST 24
Peak memory 266244 kb
Host smart-ce2129df-31df-492f-b6a1-72c2144a7e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795994514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_dummy_item_extra_dly.795994514
Directory /workspace/2.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/2.spi_device_extreme_fifo_size.106104774
Short name T179
Test name
Test status
Simulation time 56389447895 ps
CPU time 2613.95 seconds
Started Jan 17 03:28:47 PM PST 24
Finished Jan 17 04:12:21 PM PST 24
Peak memory 218460 kb
Host smart-68dd6424-2b76-4d45-8449-3408c2df4d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106104774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_extreme_fifo_size.106104774
Directory /workspace/2.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/2.spi_device_fifo_full.4123035816
Short name T1376
Test name
Test status
Simulation time 52554208363 ps
CPU time 2990.73 seconds
Started Jan 17 03:28:45 PM PST 24
Finished Jan 17 04:18:36 PM PST 24
Peak memory 256440 kb
Host smart-7af2a6a4-fbfb-4fd0-bcaf-0390a49ba119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123035816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_fifo_full.4123035816
Directory /workspace/2.spi_device_fifo_full/latest

Test location /workspace/coverage/default/2.spi_device_fifo_underflow_overflow.2174139659
Short name T1094
Test name
Test status
Simulation time 23752051029 ps
CPU time 319.61 seconds
Started Jan 17 03:28:48 PM PST 24
Finished Jan 17 03:34:08 PM PST 24
Peak memory 383864 kb
Host smart-3540dff7-1394-448a-9edf-4b65fb0111f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174139659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_fifo_underflow_overfl
ow.2174139659
Directory /workspace/2.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1788600793
Short name T795
Test name
Test status
Simulation time 74369664189 ps
CPU time 94.31 seconds
Started Jan 17 03:28:56 PM PST 24
Finished Jan 17 03:30:38 PM PST 24
Peak memory 252324 kb
Host smart-1b2f9f12-a986-444b-865e-0fcdc56abffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788600793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1788600793
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1147034198
Short name T885
Test name
Test status
Simulation time 9082076244 ps
CPU time 48.1 seconds
Started Jan 17 03:28:55 PM PST 24
Finished Jan 17 03:29:45 PM PST 24
Peak memory 251248 kb
Host smart-17f95c39-c92c-4816-9d89-da9ded47a5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147034198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1147034198
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.4028678441
Short name T836
Test name
Test status
Simulation time 2419677837 ps
CPU time 10.72 seconds
Started Jan 17 03:29:00 PM PST 24
Finished Jan 17 03:29:15 PM PST 24
Peak memory 222348 kb
Host smart-03d66b51-5f62-40d0-b427-62a33492f9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028678441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.4028678441
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3229578629
Short name T1769
Test name
Test status
Simulation time 8587733318 ps
CPU time 24.4 seconds
Started Jan 17 03:28:57 PM PST 24
Finished Jan 17 03:29:29 PM PST 24
Peak memory 224932 kb
Host smart-f8c01694-4204-49f7-ad0e-b415298e57ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229578629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3229578629
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1889275317
Short name T581
Test name
Test status
Simulation time 64836896 ps
CPU time 1 seconds
Started Jan 17 03:28:53 PM PST 24
Finished Jan 17 03:28:56 PM PST 24
Peak memory 219228 kb
Host smart-8cde455e-4387-43be-8d1a-b0b56cbaa85e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889275317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1889275317
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3947080602
Short name T13
Test name
Test status
Simulation time 15862952597 ps
CPU time 15.28 seconds
Started Jan 17 03:28:58 PM PST 24
Finished Jan 17 03:29:20 PM PST 24
Peak memory 219816 kb
Host smart-d6840d29-2833-4e5f-9af9-e2cf7f63e843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947080602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3947080602
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3986902340
Short name T976
Test name
Test status
Simulation time 3273224547 ps
CPU time 9.95 seconds
Started Jan 17 03:29:00 PM PST 24
Finished Jan 17 03:29:14 PM PST 24
Peak memory 239500 kb
Host smart-1aeb11be-8af2-4c9d-ab2e-59fdd1aaa1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986902340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3986902340
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_perf.3417198983
Short name T1182
Test name
Test status
Simulation time 21648375498 ps
CPU time 243.5 seconds
Started Jan 17 03:28:56 PM PST 24
Finished Jan 17 03:33:00 PM PST 24
Peak memory 254660 kb
Host smart-e89b684b-c7df-411d-8fc8-ca2bdefaab88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417198983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_perf.3417198983
Directory /workspace/2.spi_device_perf/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.1037356909
Short name T1474
Test name
Test status
Simulation time 25297063 ps
CPU time 0.72 seconds
Started Jan 17 03:28:50 PM PST 24
Finished Jan 17 03:28:52 PM PST 24
Peak memory 217052 kb
Host smart-75c68289-83f2-4538-a3b6-762a9e58c8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037356909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.1037356909
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3799469269
Short name T164
Test name
Test status
Simulation time 826195729 ps
CPU time 5.97 seconds
Started Jan 17 03:28:58 PM PST 24
Finished Jan 17 03:29:10 PM PST 24
Peak memory 234688 kb
Host smart-8c6cf8bf-ef21-401f-92fa-715eb1590e89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3799469269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3799469269
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_rx_async_fifo_reset.700455735
Short name T1196
Test name
Test status
Simulation time 19532616 ps
CPU time 0.86 seconds
Started Jan 17 03:28:51 PM PST 24
Finished Jan 17 03:28:53 PM PST 24
Peak memory 208760 kb
Host smart-415e53b1-f82c-4cdd-8d34-d0ba0d926505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700455735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_rx_async_fifo_reset.700455735
Directory /workspace/2.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/2.spi_device_rx_timeout.2420671313
Short name T953
Test name
Test status
Simulation time 10930791434 ps
CPU time 5.47 seconds
Started Jan 17 03:28:53 PM PST 24
Finished Jan 17 03:29:01 PM PST 24
Peak memory 217204 kb
Host smart-a374decd-c3ff-4828-84f3-d7098270c122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420671313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_rx_timeout.2420671313
Directory /workspace/2.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.594272942
Short name T91
Test name
Test status
Simulation time 167294523 ps
CPU time 0.99 seconds
Started Jan 17 03:28:57 PM PST 24
Finished Jan 17 03:29:05 PM PST 24
Peak memory 235992 kb
Host smart-bd0a204f-3435-4b3d-a78b-948c34661e5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594272942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.594272942
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_smoke.3704305792
Short name T602
Test name
Test status
Simulation time 37680995 ps
CPU time 1.1 seconds
Started Jan 17 03:28:53 PM PST 24
Finished Jan 17 03:28:56 PM PST 24
Peak memory 216944 kb
Host smart-fdaa36dd-ff81-4223-9755-6adedfe35088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704305792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_smoke.3704305792
Directory /workspace/2.spi_device_smoke/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.642657350
Short name T1321
Test name
Test status
Simulation time 540516982 ps
CPU time 4.66 seconds
Started Jan 17 03:28:59 PM PST 24
Finished Jan 17 03:29:09 PM PST 24
Peak memory 221056 kb
Host smart-2e725055-1da7-40eb-b89f-c05f120d7b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642657350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.642657350
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2287417692
Short name T1465
Test name
Test status
Simulation time 766186652 ps
CPU time 3.5 seconds
Started Jan 17 03:28:51 PM PST 24
Finished Jan 17 03:28:55 PM PST 24
Peak memory 217116 kb
Host smart-770fade4-3aab-4452-b265-9f97e5db90f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287417692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2287417692
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2729522095
Short name T6
Test name
Test status
Simulation time 1251135887 ps
CPU time 4.8 seconds
Started Jan 17 03:28:57 PM PST 24
Finished Jan 17 03:29:09 PM PST 24
Peak memory 217192 kb
Host smart-a5c0001a-2c1b-4032-8fdc-45bb173d36af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729522095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2729522095
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.4099230853
Short name T890
Test name
Test status
Simulation time 44918893 ps
CPU time 0.82 seconds
Started Jan 17 03:28:57 PM PST 24
Finished Jan 17 03:29:05 PM PST 24
Peak memory 207268 kb
Host smart-7e8bdad4-a4f9-4190-8799-0c343a251e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099230853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4099230853
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_tx_async_fifo_reset.698720751
Short name T707
Test name
Test status
Simulation time 13998198 ps
CPU time 0.78 seconds
Started Jan 17 03:28:56 PM PST 24
Finished Jan 17 03:28:57 PM PST 24
Peak memory 208784 kb
Host smart-81ad1a6c-514e-4401-a473-dce5bc4c85e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698720751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tx_async_fifo_reset.698720751
Directory /workspace/2.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/2.spi_device_txrx.1754878228
Short name T1731
Test name
Test status
Simulation time 45240846242 ps
CPU time 134.12 seconds
Started Jan 17 03:28:46 PM PST 24
Finished Jan 17 03:31:01 PM PST 24
Peak memory 266364 kb
Host smart-8eca03b8-e357-413a-a18c-5d2f12e7862d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754878228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_txrx.1754878228
Directory /workspace/2.spi_device_txrx/latest

Test location /workspace/coverage/default/2.spi_device_upload.1646947571
Short name T310
Test name
Test status
Simulation time 1814269971 ps
CPU time 11.68 seconds
Started Jan 17 03:28:56 PM PST 24
Finished Jan 17 03:29:15 PM PST 24
Peak memory 252428 kb
Host smart-804ce55b-4df2-418c-85a6-1538fc15f4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646947571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1646947571
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_abort.1231083602
Short name T1747
Test name
Test status
Simulation time 22911970 ps
CPU time 0.74 seconds
Started Jan 17 03:32:17 PM PST 24
Finished Jan 17 03:32:19 PM PST 24
Peak memory 206936 kb
Host smart-a23395de-dd5c-4280-9a21-e874cc1518e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231083602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_abort.1231083602
Directory /workspace/20.spi_device_abort/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3125866642
Short name T498
Test name
Test status
Simulation time 13452345 ps
CPU time 0.72 seconds
Started Jan 17 03:32:23 PM PST 24
Finished Jan 17 03:32:25 PM PST 24
Peak memory 206780 kb
Host smart-9be38be3-b3ce-49a1-9c02-00836a6f0d85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125866642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3125866642
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_bit_transfer.3818535143
Short name T1706
Test name
Test status
Simulation time 225901200 ps
CPU time 2.13 seconds
Started Jan 17 03:32:13 PM PST 24
Finished Jan 17 03:32:15 PM PST 24
Peak memory 216060 kb
Host smart-39447d14-1d81-4f51-9a2a-77fc8e146750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818535143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_bit_transfer.3818535143
Directory /workspace/20.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/20.spi_device_byte_transfer.3642992617
Short name T1765
Test name
Test status
Simulation time 146733143 ps
CPU time 3.02 seconds
Started Jan 17 03:32:10 PM PST 24
Finished Jan 17 03:32:14 PM PST 24
Peak memory 217028 kb
Host smart-9024a2d1-1b71-4b6f-b376-f2c52e5da336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642992617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_byte_transfer.3642992617
Directory /workspace/20.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2264552422
Short name T1592
Test name
Test status
Simulation time 166333607 ps
CPU time 3.91 seconds
Started Jan 17 03:32:18 PM PST 24
Finished Jan 17 03:32:25 PM PST 24
Peak memory 240228 kb
Host smart-7bb2224a-931a-4438-adf4-700d0eeb2797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264552422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2264552422
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1236997134
Short name T1518
Test name
Test status
Simulation time 46599655 ps
CPU time 0.78 seconds
Started Jan 17 03:32:11 PM PST 24
Finished Jan 17 03:32:13 PM PST 24
Peak memory 207972 kb
Host smart-59b8e511-e2e3-4223-9441-f31247d5470a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236997134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1236997134
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_dummy_item_extra_dly.1058840777
Short name T1274
Test name
Test status
Simulation time 34535292413 ps
CPU time 459.36 seconds
Started Jan 17 03:32:07 PM PST 24
Finished Jan 17 03:39:47 PM PST 24
Peak memory 283864 kb
Host smart-0b47ea96-fdea-41e6-b2f9-ee7717805d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058840777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_dummy_item_extra_dly.1058840777
Directory /workspace/20.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/20.spi_device_extreme_fifo_size.44293102
Short name T1286
Test name
Test status
Simulation time 267964950420 ps
CPU time 864.67 seconds
Started Jan 17 03:32:12 PM PST 24
Finished Jan 17 03:46:38 PM PST 24
Peak memory 225364 kb
Host smart-6c834637-1059-4206-b361-7348492e8ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44293102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_extreme_fifo_size.44293102
Directory /workspace/20.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/20.spi_device_fifo_full.3889426806
Short name T1023
Test name
Test status
Simulation time 38877848885 ps
CPU time 2303.64 seconds
Started Jan 17 03:32:07 PM PST 24
Finished Jan 17 04:10:31 PM PST 24
Peak memory 288940 kb
Host smart-e5cd1ea9-9db0-46b7-8f79-e6923f3ca61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889426806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_fifo_full.3889426806
Directory /workspace/20.spi_device_fifo_full/latest

Test location /workspace/coverage/default/20.spi_device_fifo_underflow_overflow.3163174120
Short name T626
Test name
Test status
Simulation time 34608463487 ps
CPU time 395.91 seconds
Started Jan 17 03:32:11 PM PST 24
Finished Jan 17 03:38:47 PM PST 24
Peak memory 397516 kb
Host smart-8b2f42af-0320-4963-914f-5e05fb25c5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163174120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_fifo_underflow_overf
low.3163174120
Directory /workspace/20.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2577498458
Short name T534
Test name
Test status
Simulation time 114551357078 ps
CPU time 140.99 seconds
Started Jan 17 03:32:11 PM PST 24
Finished Jan 17 03:34:33 PM PST 24
Peak memory 250080 kb
Host smart-2422a63f-4fdd-4e47-971b-9084b4d7dced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577498458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2577498458
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.275454225
Short name T1504
Test name
Test status
Simulation time 9090835359 ps
CPU time 64.07 seconds
Started Jan 17 03:32:15 PM PST 24
Finished Jan 17 03:33:20 PM PST 24
Peak memory 239228 kb
Host smart-d7e5a531-741f-4f6f-a597-4016eb1afd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275454225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.275454225
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3371968612
Short name T880
Test name
Test status
Simulation time 4395047565 ps
CPU time 27.65 seconds
Started Jan 17 03:32:25 PM PST 24
Finished Jan 17 03:32:53 PM PST 24
Peak memory 247900 kb
Host smart-e9822192-8c22-40fc-8a7b-f2166d803297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371968612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3371968612
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3043611401
Short name T1083
Test name
Test status
Simulation time 564928662 ps
CPU time 4.18 seconds
Started Jan 17 03:32:15 PM PST 24
Finished Jan 17 03:32:19 PM PST 24
Peak memory 238624 kb
Host smart-5353d6bf-b6f6-4257-9913-ed015f53e3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043611401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3043611401
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_intr.1727089541
Short name T1141
Test name
Test status
Simulation time 4743128856 ps
CPU time 33.54 seconds
Started Jan 17 03:32:08 PM PST 24
Finished Jan 17 03:32:42 PM PST 24
Peak memory 233660 kb
Host smart-1664991e-2ca5-40aa-847b-6425ab45ac30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727089541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intr.1727089541
Directory /workspace/20.spi_device_intr/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1709198020
Short name T595
Test name
Test status
Simulation time 12179575287 ps
CPU time 13.46 seconds
Started Jan 17 03:32:17 PM PST 24
Finished Jan 17 03:32:31 PM PST 24
Peak memory 248220 kb
Host smart-dc07cd74-b6ec-4f5e-b834-84b467d23f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709198020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1709198020
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1728970195
Short name T1687
Test name
Test status
Simulation time 26369970388 ps
CPU time 17.67 seconds
Started Jan 17 03:32:09 PM PST 24
Finished Jan 17 03:32:28 PM PST 24
Peak memory 221784 kb
Host smart-af9ab590-6474-4eb9-8c3d-4433ac73c927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728970195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1728970195
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.620038213
Short name T1258
Test name
Test status
Simulation time 20079672292 ps
CPU time 11.56 seconds
Started Jan 17 03:32:11 PM PST 24
Finished Jan 17 03:32:23 PM PST 24
Peak memory 230248 kb
Host smart-dcbb3978-71ab-4f63-9219-c6e145a792bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620038213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.620038213
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_perf.1625782701
Short name T1773
Test name
Test status
Simulation time 36185612047 ps
CPU time 266.83 seconds
Started Jan 17 03:32:13 PM PST 24
Finished Jan 17 03:36:40 PM PST 24
Peak memory 248932 kb
Host smart-c1b18f81-63c6-4ed2-86fe-2a6ff2c174a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625782701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_perf.1625782701
Directory /workspace/20.spi_device_perf/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.357930539
Short name T1044
Test name
Test status
Simulation time 4691581350 ps
CPU time 6.46 seconds
Started Jan 17 03:32:16 PM PST 24
Finished Jan 17 03:32:24 PM PST 24
Peak memory 219200 kb
Host smart-c7a5e6cf-75bc-4170-a0cf-0a07eeca3eac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=357930539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.357930539
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_rx_async_fifo_reset.2127613556
Short name T1377
Test name
Test status
Simulation time 19818358 ps
CPU time 0.86 seconds
Started Jan 17 03:32:17 PM PST 24
Finished Jan 17 03:32:19 PM PST 24
Peak memory 208732 kb
Host smart-496c19fd-b441-4cd0-a517-885c453ad273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127613556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_rx_async_fifo_reset.2127613556
Directory /workspace/20.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/20.spi_device_rx_timeout.3433336300
Short name T564
Test name
Test status
Simulation time 491969651 ps
CPU time 4.96 seconds
Started Jan 17 03:32:13 PM PST 24
Finished Jan 17 03:32:19 PM PST 24
Peak memory 217120 kb
Host smart-f53eec77-e630-4504-9d2b-ab288515d864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433336300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_rx_timeout.3433336300
Directory /workspace/20.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/20.spi_device_smoke.2532457442
Short name T927
Test name
Test status
Simulation time 33055337 ps
CPU time 1.12 seconds
Started Jan 17 03:32:09 PM PST 24
Finished Jan 17 03:32:11 PM PST 24
Peak memory 216936 kb
Host smart-da0d5470-1b6c-4055-9d15-43009ef06068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532457442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_smoke.2532457442
Directory /workspace/20.spi_device_smoke/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.850206958
Short name T129
Test name
Test status
Simulation time 106056406959 ps
CPU time 647.93 seconds
Started Jan 17 03:32:25 PM PST 24
Finished Jan 17 03:43:14 PM PST 24
Peak memory 338756 kb
Host smart-f01ae232-57d6-4bcd-bedf-0c9dd10f9628
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850206958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.850206958
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2527474284
Short name T1672
Test name
Test status
Simulation time 1687060022 ps
CPU time 9.86 seconds
Started Jan 17 03:32:12 PM PST 24
Finished Jan 17 03:32:23 PM PST 24
Peak memory 217432 kb
Host smart-2c693875-5155-4a68-9eaf-67f82618609d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527474284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2527474284
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.574089165
Short name T492
Test name
Test status
Simulation time 1258507585 ps
CPU time 2.93 seconds
Started Jan 17 03:32:14 PM PST 24
Finished Jan 17 03:32:17 PM PST 24
Peak memory 217140 kb
Host smart-8e81636b-32ac-48e1-8572-88a684ad6b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574089165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.574089165
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3333072040
Short name T968
Test name
Test status
Simulation time 437655809 ps
CPU time 2.13 seconds
Started Jan 17 03:32:12 PM PST 24
Finished Jan 17 03:32:15 PM PST 24
Peak memory 217116 kb
Host smart-f836cbc4-8a06-4b39-8fb3-6cb5c9d16263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333072040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3333072040
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2709136551
Short name T870
Test name
Test status
Simulation time 26027762 ps
CPU time 0.77 seconds
Started Jan 17 03:32:17 PM PST 24
Finished Jan 17 03:32:19 PM PST 24
Peak memory 207208 kb
Host smart-ed083ad5-6d88-428b-9a9e-72c8cb5d19e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709136551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2709136551
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_tx_async_fifo_reset.437664808
Short name T660
Test name
Test status
Simulation time 15864389 ps
CPU time 0.81 seconds
Started Jan 17 03:32:15 PM PST 24
Finished Jan 17 03:32:17 PM PST 24
Peak memory 208784 kb
Host smart-ac14d4f2-f9da-40fe-8ae3-b37e65131206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437664808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tx_async_fifo_reset.437664808
Directory /workspace/20.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/20.spi_device_txrx.3208123204
Short name T1541
Test name
Test status
Simulation time 88317338552 ps
CPU time 476.6 seconds
Started Jan 17 03:32:02 PM PST 24
Finished Jan 17 03:40:04 PM PST 24
Peak memory 259184 kb
Host smart-5f8ff392-72f9-4484-a90e-94b59db9a422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208123204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_txrx.3208123204
Directory /workspace/20.spi_device_txrx/latest

Test location /workspace/coverage/default/20.spi_device_upload.310241359
Short name T918
Test name
Test status
Simulation time 625627919 ps
CPU time 7.4 seconds
Started Jan 17 03:32:16 PM PST 24
Finished Jan 17 03:32:25 PM PST 24
Peak memory 238140 kb
Host smart-4b2b9365-7538-4ef4-bdcb-7940dbd57d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310241359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.310241359
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_abort.3394625315
Short name T1759
Test name
Test status
Simulation time 16066878 ps
CPU time 0.76 seconds
Started Jan 17 03:32:24 PM PST 24
Finished Jan 17 03:32:25 PM PST 24
Peak memory 207016 kb
Host smart-8fb6679d-bc33-4b7b-add3-85407739a217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394625315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_abort.3394625315
Directory /workspace/21.spi_device_abort/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.587503815
Short name T627
Test name
Test status
Simulation time 54035394 ps
CPU time 0.77 seconds
Started Jan 17 03:32:35 PM PST 24
Finished Jan 17 03:32:38 PM PST 24
Peak memory 206768 kb
Host smart-59fda973-66ac-41a7-8360-3f0efdab7be6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587503815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.587503815
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_bit_transfer.2848613761
Short name T1459
Test name
Test status
Simulation time 206940816 ps
CPU time 2.22 seconds
Started Jan 17 03:32:19 PM PST 24
Finished Jan 17 03:32:24 PM PST 24
Peak memory 217104 kb
Host smart-bf10389b-379e-49c2-96f7-36a2a4c78d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848613761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_bit_transfer.2848613761
Directory /workspace/21.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/21.spi_device_byte_transfer.621697961
Short name T480
Test name
Test status
Simulation time 329850855 ps
CPU time 4.61 seconds
Started Jan 17 03:32:22 PM PST 24
Finished Jan 17 03:32:28 PM PST 24
Peak memory 217116 kb
Host smart-1405b07f-95cc-414d-8155-b781b8fa7beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621697961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_byte_transfer.621697961
Directory /workspace/21.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.968586968
Short name T1272
Test name
Test status
Simulation time 111036004 ps
CPU time 2.75 seconds
Started Jan 17 03:32:25 PM PST 24
Finished Jan 17 03:32:28 PM PST 24
Peak memory 238928 kb
Host smart-ef0f03bc-e44c-4a41-b0af-229338d098a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968586968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.968586968
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2990370591
Short name T1150
Test name
Test status
Simulation time 17948714 ps
CPU time 0.75 seconds
Started Jan 17 03:32:21 PM PST 24
Finished Jan 17 03:32:23 PM PST 24
Peak memory 206884 kb
Host smart-cc7bd2f5-9b5e-4b5a-8d67-2e586dc955a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990370591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2990370591
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_dummy_item_extra_dly.900417084
Short name T1639
Test name
Test status
Simulation time 569502621764 ps
CPU time 285.48 seconds
Started Jan 17 03:32:22 PM PST 24
Finished Jan 17 03:37:09 PM PST 24
Peak memory 304452 kb
Host smart-25512d04-adbf-4adc-8b81-c6ccbe5b5433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900417084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_dummy_item_extra_dly.900417084
Directory /workspace/21.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/21.spi_device_fifo_full.2722330443
Short name T1480
Test name
Test status
Simulation time 35029595999 ps
CPU time 930.19 seconds
Started Jan 17 03:32:17 PM PST 24
Finished Jan 17 03:47:49 PM PST 24
Peak memory 281248 kb
Host smart-5e35862f-097e-4f04-be4e-f5c08c36003d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722330443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_fifo_full.2722330443
Directory /workspace/21.spi_device_fifo_full/latest

Test location /workspace/coverage/default/21.spi_device_fifo_underflow_overflow.214829897
Short name T591
Test name
Test status
Simulation time 321627861283 ps
CPU time 748.24 seconds
Started Jan 17 03:32:15 PM PST 24
Finished Jan 17 03:44:44 PM PST 24
Peak memory 652256 kb
Host smart-8a3a6419-a848-471b-831e-cc8f000c9ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214829897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_fifo_underflow_overfl
ow.214829897
Directory /workspace/21.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1181118967
Short name T1624
Test name
Test status
Simulation time 18062880169 ps
CPU time 48.64 seconds
Started Jan 17 03:32:24 PM PST 24
Finished Jan 17 03:33:14 PM PST 24
Peak memory 241796 kb
Host smart-ae2a23f9-f144-4e95-aa21-c050a3624b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181118967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1181118967
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.65706514
Short name T939
Test name
Test status
Simulation time 27748139244 ps
CPU time 78.2 seconds
Started Jan 17 03:32:35 PM PST 24
Finished Jan 17 03:33:55 PM PST 24
Peak memory 256920 kb
Host smart-5842c523-6449-434e-ab87-c004d9c2ddc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65706514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.65706514
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.4119842298
Short name T1531
Test name
Test status
Simulation time 1912743161 ps
CPU time 23.79 seconds
Started Jan 17 03:32:26 PM PST 24
Finished Jan 17 03:32:50 PM PST 24
Peak memory 249832 kb
Host smart-16ad24b8-427f-4528-b559-2300dfe50b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119842298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.4119842298
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1381779059
Short name T313
Test name
Test status
Simulation time 212772173 ps
CPU time 4.3 seconds
Started Jan 17 03:32:27 PM PST 24
Finished Jan 17 03:32:32 PM PST 24
Peak memory 225340 kb
Host smart-914c2d70-2d17-4777-b05b-c49c021353cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381779059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1381779059
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_intr.823972550
Short name T1245
Test name
Test status
Simulation time 34165162842 ps
CPU time 30.34 seconds
Started Jan 17 03:32:25 PM PST 24
Finished Jan 17 03:32:56 PM PST 24
Peak memory 225216 kb
Host smart-f9a928cd-5c7d-4bf4-826a-496f76ec0506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823972550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intr.823972550
Directory /workspace/21.spi_device_intr/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1251717943
Short name T943
Test name
Test status
Simulation time 672818757 ps
CPU time 11.03 seconds
Started Jan 17 03:32:27 PM PST 24
Finished Jan 17 03:32:39 PM PST 24
Peak memory 240712 kb
Host smart-ea83c0f1-f5fc-4fc5-b92f-cdbb2c735de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251717943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1251717943
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.972890265
Short name T1327
Test name
Test status
Simulation time 1348777197 ps
CPU time 4.71 seconds
Started Jan 17 03:32:29 PM PST 24
Finished Jan 17 03:32:34 PM PST 24
Peak memory 241732 kb
Host smart-fef2f5f4-ce38-4dcc-8bbf-ef72b97d9e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972890265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.972890265
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.595696993
Short name T16
Test name
Test status
Simulation time 836416725 ps
CPU time 6.51 seconds
Started Jan 17 03:32:24 PM PST 24
Finished Jan 17 03:32:31 PM PST 24
Peak memory 223148 kb
Host smart-62629e9d-6f8f-42de-8793-956dd2cac062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595696993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.595696993
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_perf.2781414014
Short name T785
Test name
Test status
Simulation time 19083570192 ps
CPU time 690.43 seconds
Started Jan 17 03:32:20 PM PST 24
Finished Jan 17 03:43:52 PM PST 24
Peak memory 287500 kb
Host smart-66468d09-7280-4ddb-a718-f6295b336f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781414014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_perf.2781414014
Directory /workspace/21.spi_device_perf/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3151618376
Short name T1024
Test name
Test status
Simulation time 475574708 ps
CPU time 4.84 seconds
Started Jan 17 03:32:23 PM PST 24
Finished Jan 17 03:32:29 PM PST 24
Peak memory 234976 kb
Host smart-62ef03b1-fb81-48fc-84ea-3ddd66340305
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3151618376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3151618376
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_rx_async_fifo_reset.914661966
Short name T1152
Test name
Test status
Simulation time 60495644 ps
CPU time 0.82 seconds
Started Jan 17 03:32:19 PM PST 24
Finished Jan 17 03:32:22 PM PST 24
Peak memory 208764 kb
Host smart-fe5250e4-ae52-4bd4-8611-4b6a4282bf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914661966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_rx_async_fifo_reset.914661966
Directory /workspace/21.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/21.spi_device_rx_timeout.2428181246
Short name T97
Test name
Test status
Simulation time 631595172 ps
CPU time 5.71 seconds
Started Jan 17 03:32:22 PM PST 24
Finished Jan 17 03:32:29 PM PST 24
Peak memory 217180 kb
Host smart-8adfab5e-eda9-496f-b047-c8e5b6d2dad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428181246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_rx_timeout.2428181246
Directory /workspace/21.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/21.spi_device_smoke.1715271535
Short name T997
Test name
Test status
Simulation time 70509398 ps
CPU time 0.97 seconds
Started Jan 17 03:32:22 PM PST 24
Finished Jan 17 03:32:23 PM PST 24
Peak memory 208340 kb
Host smart-c29c466e-9852-4c6b-bea7-ba5872d62c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715271535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_smoke.1715271535
Directory /workspace/21.spi_device_smoke/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3874859205
Short name T186
Test name
Test status
Simulation time 39401539853 ps
CPU time 520.8 seconds
Started Jan 17 03:32:33 PM PST 24
Finished Jan 17 03:41:17 PM PST 24
Peak memory 339892 kb
Host smart-a8f5fb95-04f5-41ef-a9db-41d9b75c4662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874859205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3874859205
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.64703006
Short name T1570
Test name
Test status
Simulation time 27365959806 ps
CPU time 94.24 seconds
Started Jan 17 03:32:21 PM PST 24
Finished Jan 17 03:33:56 PM PST 24
Peak memory 217344 kb
Host smart-5e078d3a-df10-4736-810b-f269564be876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64703006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.64703006
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2493147174
Short name T1444
Test name
Test status
Simulation time 1208936147 ps
CPU time 4.04 seconds
Started Jan 17 03:32:20 PM PST 24
Finished Jan 17 03:32:26 PM PST 24
Peak memory 217152 kb
Host smart-2e72d3ac-2c36-4e63-afb6-557edff3e681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493147174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2493147174
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.749253683
Short name T1617
Test name
Test status
Simulation time 143952343 ps
CPU time 5.55 seconds
Started Jan 17 03:32:20 PM PST 24
Finished Jan 17 03:32:27 PM PST 24
Peak memory 217112 kb
Host smart-9f0476d1-61b2-4f2b-8e42-8464a14a149d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749253683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.749253683
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1039760820
Short name T1058
Test name
Test status
Simulation time 31535059 ps
CPU time 0.78 seconds
Started Jan 17 03:32:24 PM PST 24
Finished Jan 17 03:32:25 PM PST 24
Peak memory 207288 kb
Host smart-292b0423-c416-4a77-a98d-c230f4bed4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039760820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1039760820
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_tx_async_fifo_reset.2108214924
Short name T46
Test name
Test status
Simulation time 49007521 ps
CPU time 0.8 seconds
Started Jan 17 03:32:22 PM PST 24
Finished Jan 17 03:32:25 PM PST 24
Peak memory 208680 kb
Host smart-c1da6027-bdae-481c-bf4d-9e8c637d70f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108214924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tx_async_fifo_reset.2108214924
Directory /workspace/21.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/21.spi_device_txrx.3434401272
Short name T1381
Test name
Test status
Simulation time 377012742764 ps
CPU time 257.78 seconds
Started Jan 17 03:32:18 PM PST 24
Finished Jan 17 03:36:37 PM PST 24
Peak memory 295900 kb
Host smart-8ffa82f0-87da-4605-a413-08280694b1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434401272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_txrx.3434401272
Directory /workspace/21.spi_device_txrx/latest

Test location /workspace/coverage/default/21.spi_device_upload.3439540727
Short name T1598
Test name
Test status
Simulation time 114616575694 ps
CPU time 56.74 seconds
Started Jan 17 03:32:26 PM PST 24
Finished Jan 17 03:33:24 PM PST 24
Peak memory 233668 kb
Host smart-7476ab63-ce78-4dff-b34d-c239ed8b3c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439540727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3439540727
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_abort.486476337
Short name T677
Test name
Test status
Simulation time 26897504 ps
CPU time 0.75 seconds
Started Jan 17 03:32:41 PM PST 24
Finished Jan 17 03:32:45 PM PST 24
Peak memory 206984 kb
Host smart-253edd45-1188-447b-b832-207a29d798ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486476337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_abort.486476337
Directory /workspace/22.spi_device_abort/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2691390480
Short name T37
Test name
Test status
Simulation time 14745098 ps
CPU time 0.73 seconds
Started Jan 17 03:32:48 PM PST 24
Finished Jan 17 03:32:49 PM PST 24
Peak memory 206812 kb
Host smart-5d0071ea-83ac-4b5d-a4c6-7998b7728d3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691390480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2691390480
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_bit_transfer.2443550512
Short name T544
Test name
Test status
Simulation time 503591979 ps
CPU time 2.52 seconds
Started Jan 17 03:32:39 PM PST 24
Finished Jan 17 03:32:46 PM PST 24
Peak memory 217108 kb
Host smart-836bd7fd-b194-43b8-a657-a772f868674d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443550512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_bit_transfer.2443550512
Directory /workspace/22.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/22.spi_device_byte_transfer.161994387
Short name T1000
Test name
Test status
Simulation time 371343218 ps
CPU time 3.09 seconds
Started Jan 17 03:32:38 PM PST 24
Finished Jan 17 03:32:47 PM PST 24
Peak memory 217136 kb
Host smart-367f0ae9-9085-457f-b189-338c54aed7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161994387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_byte_transfer.161994387
Directory /workspace/22.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.308312437
Short name T1353
Test name
Test status
Simulation time 270959759 ps
CPU time 3.29 seconds
Started Jan 17 03:32:43 PM PST 24
Finished Jan 17 03:32:47 PM PST 24
Peak memory 241264 kb
Host smart-c6c504f3-7afa-4c8b-b87c-e2a2356f694f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308312437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.308312437
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1137716822
Short name T484
Test name
Test status
Simulation time 22223435 ps
CPU time 0.82 seconds
Started Jan 17 03:32:37 PM PST 24
Finished Jan 17 03:32:44 PM PST 24
Peak memory 207952 kb
Host smart-94600327-13d8-4afd-ae50-1fca8711583f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137716822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1137716822
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_dummy_item_extra_dly.1015201199
Short name T1337
Test name
Test status
Simulation time 97586988829 ps
CPU time 2261.83 seconds
Started Jan 17 03:32:33 PM PST 24
Finished Jan 17 04:10:18 PM PST 24
Peak memory 284340 kb
Host smart-c1eae635-95a9-4379-8bfb-1de162793381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015201199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_dummy_item_extra_dly.1015201199
Directory /workspace/22.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/22.spi_device_extreme_fifo_size.1096999723
Short name T1229
Test name
Test status
Simulation time 184291884799 ps
CPU time 1657.43 seconds
Started Jan 17 03:32:35 PM PST 24
Finished Jan 17 04:00:15 PM PST 24
Peak memory 218292 kb
Host smart-4d6acbc2-9f52-4dbb-851e-267dc47480dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096999723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_extreme_fifo_size.1096999723
Directory /workspace/22.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/22.spi_device_fifo_full.3409226191
Short name T1189
Test name
Test status
Simulation time 28823451282 ps
CPU time 624.25 seconds
Started Jan 17 03:32:32 PM PST 24
Finished Jan 17 03:42:58 PM PST 24
Peak memory 266404 kb
Host smart-03e4c50f-92c3-4457-86f4-aa5505d96e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409226191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_fifo_full.3409226191
Directory /workspace/22.spi_device_fifo_full/latest

Test location /workspace/coverage/default/22.spi_device_fifo_underflow_overflow.665678265
Short name T575
Test name
Test status
Simulation time 380605113132 ps
CPU time 331.64 seconds
Started Jan 17 03:32:33 PM PST 24
Finished Jan 17 03:38:08 PM PST 24
Peak memory 321652 kb
Host smart-bb3da4b5-ef02-4ac9-bc54-776afec8076a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665678265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_fifo_underflow_overfl
ow.665678265
Directory /workspace/22.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1861414558
Short name T1462
Test name
Test status
Simulation time 147308403103 ps
CPU time 107.07 seconds
Started Jan 17 03:32:42 PM PST 24
Finished Jan 17 03:34:31 PM PST 24
Peak memory 250064 kb
Host smart-6012e6b7-b44e-4f6f-b396-9e6c8a59b601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861414558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1861414558
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.516123288
Short name T1576
Test name
Test status
Simulation time 22664611851 ps
CPU time 269.5 seconds
Started Jan 17 03:32:44 PM PST 24
Finished Jan 17 03:37:14 PM PST 24
Peak memory 282916 kb
Host smart-da2b6c8e-28d9-46c3-bfae-e31f047d37cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516123288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.516123288
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2309045387
Short name T1100
Test name
Test status
Simulation time 26214981020 ps
CPU time 47.18 seconds
Started Jan 17 03:32:40 PM PST 24
Finished Jan 17 03:33:31 PM PST 24
Peak memory 257300 kb
Host smart-258476ad-dd95-4675-8b20-ed6706507f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309045387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2309045387
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intr.1739138292
Short name T693
Test name
Test status
Simulation time 42200153390 ps
CPU time 15.56 seconds
Started Jan 17 03:32:33 PM PST 24
Finished Jan 17 03:32:51 PM PST 24
Peak memory 225320 kb
Host smart-3be420fc-64cb-4b92-8a2b-0d0c46c56361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739138292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intr.1739138292
Directory /workspace/22.spi_device_intr/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.853745142
Short name T979
Test name
Test status
Simulation time 94910911038 ps
CPU time 52.92 seconds
Started Jan 17 03:32:43 PM PST 24
Finished Jan 17 03:33:37 PM PST 24
Peak memory 246948 kb
Host smart-2a1d0f5e-413e-4d6f-ab2d-2536aee3aa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853745142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.853745142
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2993553438
Short name T658
Test name
Test status
Simulation time 4181598490 ps
CPU time 14.94 seconds
Started Jan 17 03:32:40 PM PST 24
Finished Jan 17 03:32:59 PM PST 24
Peak memory 250028 kb
Host smart-0d4e8393-a445-4cbe-a4ef-f47a6f44f52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993553438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2993553438
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3229434826
Short name T1523
Test name
Test status
Simulation time 16976526162 ps
CPU time 35.42 seconds
Started Jan 17 03:32:45 PM PST 24
Finished Jan 17 03:33:21 PM PST 24
Peak memory 238428 kb
Host smart-4d6fe01d-e17f-41a6-b898-cc38ce8974c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229434826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3229434826
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_perf.3652343449
Short name T271
Test name
Test status
Simulation time 13688151492 ps
CPU time 349.08 seconds
Started Jan 17 03:32:36 PM PST 24
Finished Jan 17 03:38:26 PM PST 24
Peak memory 288472 kb
Host smart-5dfd3298-74de-4f9b-87f1-07298efc07d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652343449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_perf.3652343449
Directory /workspace/22.spi_device_perf/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2595604562
Short name T714
Test name
Test status
Simulation time 3068938304 ps
CPU time 5.07 seconds
Started Jan 17 03:32:45 PM PST 24
Finished Jan 17 03:32:50 PM PST 24
Peak memory 220924 kb
Host smart-3d1427d8-5d55-45dc-aea2-ebcffdff93cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2595604562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2595604562
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_rx_async_fifo_reset.3712917269
Short name T1674
Test name
Test status
Simulation time 44246185 ps
CPU time 0.99 seconds
Started Jan 17 03:32:39 PM PST 24
Finished Jan 17 03:32:45 PM PST 24
Peak memory 208776 kb
Host smart-9e940715-5aea-4f86-a508-6f39fafdc226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712917269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_rx_async_fifo_reset.3712917269
Directory /workspace/22.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/22.spi_device_rx_timeout.4274380251
Short name T704
Test name
Test status
Simulation time 886262506 ps
CPU time 6.77 seconds
Started Jan 17 03:32:36 PM PST 24
Finished Jan 17 03:32:44 PM PST 24
Peak memory 217184 kb
Host smart-81099a13-fe37-4489-9eb9-45e356316605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274380251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_rx_timeout.4274380251
Directory /workspace/22.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/22.spi_device_smoke.3830516291
Short name T553
Test name
Test status
Simulation time 123456882 ps
CPU time 1.23 seconds
Started Jan 17 03:32:32 PM PST 24
Finished Jan 17 03:32:35 PM PST 24
Peak memory 216972 kb
Host smart-1385bc63-758c-4ac8-9c10-de1d01a89a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830516291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_smoke.3830516291
Directory /workspace/22.spi_device_smoke/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.363468891
Short name T1394
Test name
Test status
Simulation time 77334769496 ps
CPU time 340.98 seconds
Started Jan 17 03:32:42 PM PST 24
Finished Jan 17 03:38:25 PM PST 24
Peak memory 307492 kb
Host smart-522cf90c-8a38-42ad-994b-a5194608cb9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363468891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.363468891
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4040161268
Short name T618
Test name
Test status
Simulation time 189430867 ps
CPU time 2.88 seconds
Started Jan 17 03:32:37 PM PST 24
Finished Jan 17 03:32:46 PM PST 24
Peak memory 217164 kb
Host smart-c7471533-6ac1-49cd-8756-845750fd6f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040161268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4040161268
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1634815533
Short name T1600
Test name
Test status
Simulation time 1406831149 ps
CPU time 4.03 seconds
Started Jan 17 03:32:37 PM PST 24
Finished Jan 17 03:32:42 PM PST 24
Peak memory 217032 kb
Host smart-82ead7f1-cbe4-438f-9203-1d717011690e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634815533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1634815533
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1838074160
Short name T746
Test name
Test status
Simulation time 144642587 ps
CPU time 1.91 seconds
Started Jan 17 03:32:44 PM PST 24
Finished Jan 17 03:32:46 PM PST 24
Peak memory 217104 kb
Host smart-6878bbb2-f5af-4eba-9ca7-5b1c3e1c02ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838074160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1838074160
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3501428956
Short name T1314
Test name
Test status
Simulation time 29521496 ps
CPU time 0.72 seconds
Started Jan 17 03:32:45 PM PST 24
Finished Jan 17 03:32:46 PM PST 24
Peak memory 207296 kb
Host smart-98bca34e-7440-4739-890e-818454faac9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501428956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3501428956
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_tx_async_fifo_reset.137037211
Short name T1560
Test name
Test status
Simulation time 68743715 ps
CPU time 0.78 seconds
Started Jan 17 03:32:35 PM PST 24
Finished Jan 17 03:32:38 PM PST 24
Peak memory 208776 kb
Host smart-991faf30-a088-4a44-b355-74bf89853dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137037211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tx_async_fifo_reset.137037211
Directory /workspace/22.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/22.spi_device_txrx.4190344613
Short name T1448
Test name
Test status
Simulation time 43849393333 ps
CPU time 550.08 seconds
Started Jan 17 03:32:34 PM PST 24
Finished Jan 17 03:41:46 PM PST 24
Peak memory 249688 kb
Host smart-e023d030-5b06-4561-8ea1-70bc9a6d320f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190344613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_txrx.4190344613
Directory /workspace/22.spi_device_txrx/latest

Test location /workspace/coverage/default/22.spi_device_upload.1966505676
Short name T1529
Test name
Test status
Simulation time 30407777917 ps
CPU time 20.92 seconds
Started Jan 17 03:32:40 PM PST 24
Finished Jan 17 03:33:05 PM PST 24
Peak memory 237752 kb
Host smart-a371f11c-33a3-4432-8974-b4fbcb15f04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966505676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1966505676
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_abort.766776451
Short name T1493
Test name
Test status
Simulation time 15084945 ps
CPU time 0.74 seconds
Started Jan 17 03:32:56 PM PST 24
Finished Jan 17 03:32:58 PM PST 24
Peak memory 207012 kb
Host smart-245bc896-324d-42dc-9291-f1e6674c7bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766776451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_abort.766776451
Directory /workspace/23.spi_device_abort/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2719606854
Short name T1039
Test name
Test status
Simulation time 11109095 ps
CPU time 0.72 seconds
Started Jan 17 03:32:57 PM PST 24
Finished Jan 17 03:32:59 PM PST 24
Peak memory 206776 kb
Host smart-13fe83dd-71e8-4fa0-820a-9797e8033268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719606854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2719606854
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_byte_transfer.1281281376
Short name T1287
Test name
Test status
Simulation time 125163319 ps
CPU time 2.7 seconds
Started Jan 17 03:32:45 PM PST 24
Finished Jan 17 03:32:48 PM PST 24
Peak memory 217104 kb
Host smart-caa19ba2-d589-4510-b49b-8492113c3d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281281376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_byte_transfer.1281281376
Directory /workspace/23.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3085222642
Short name T1436
Test name
Test status
Simulation time 111000738 ps
CPU time 3.06 seconds
Started Jan 17 03:32:51 PM PST 24
Finished Jan 17 03:32:55 PM PST 24
Peak memory 241056 kb
Host smart-e09cadf8-2690-4926-9fd1-cf1367bbd9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085222642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3085222642
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3672015786
Short name T757
Test name
Test status
Simulation time 150747663 ps
CPU time 0.81 seconds
Started Jan 17 03:32:49 PM PST 24
Finished Jan 17 03:32:50 PM PST 24
Peak memory 207964 kb
Host smart-c74f4774-eb47-4c3c-aa4a-ddff6c28b36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672015786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3672015786
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_dummy_item_extra_dly.548512476
Short name T586
Test name
Test status
Simulation time 258542819207 ps
CPU time 506.87 seconds
Started Jan 17 03:32:41 PM PST 24
Finished Jan 17 03:41:11 PM PST 24
Peak memory 266096 kb
Host smart-40f1016c-6c74-43a0-a07a-75c7feea02e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548512476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_dummy_item_extra_dly.548512476
Directory /workspace/23.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/23.spi_device_extreme_fifo_size.255084314
Short name T594
Test name
Test status
Simulation time 212154241389 ps
CPU time 2398.05 seconds
Started Jan 17 03:32:43 PM PST 24
Finished Jan 17 04:12:42 PM PST 24
Peak memory 225404 kb
Host smart-858e8792-5049-401b-8f59-7cd0233bd986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255084314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_extreme_fifo_size.255084314
Directory /workspace/23.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/23.spi_device_fifo_full.576213505
Short name T1113
Test name
Test status
Simulation time 108467973879 ps
CPU time 904.74 seconds
Started Jan 17 03:32:42 PM PST 24
Finished Jan 17 03:47:49 PM PST 24
Peak memory 286492 kb
Host smart-f8f2e979-f9b8-4bca-89aa-54f68f3829ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576213505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_fifo_full.576213505
Directory /workspace/23.spi_device_fifo_full/latest

Test location /workspace/coverage/default/23.spi_device_fifo_underflow_overflow.2978574907
Short name T1380
Test name
Test status
Simulation time 56446197584 ps
CPU time 214.84 seconds
Started Jan 17 03:32:49 PM PST 24
Finished Jan 17 03:36:24 PM PST 24
Peak memory 393868 kb
Host smart-3d9b2f32-eab6-4446-a6d4-91c5c1969d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978574907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_fifo_underflow_overf
low.2978574907
Directory /workspace/23.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.478922852
Short name T1278
Test name
Test status
Simulation time 19204210746 ps
CPU time 29.87 seconds
Started Jan 17 03:32:54 PM PST 24
Finished Jan 17 03:33:27 PM PST 24
Peak memory 240740 kb
Host smart-4791466b-b4f3-4e84-97af-a4a1fa76fc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478922852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.478922852
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1457166899
Short name T1293
Test name
Test status
Simulation time 12986809838 ps
CPU time 133.31 seconds
Started Jan 17 03:32:50 PM PST 24
Finished Jan 17 03:35:04 PM PST 24
Peak memory 255792 kb
Host smart-ea88f64a-f805-4ecd-ae8d-9e53f6ed65b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457166899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1457166899
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3505586935
Short name T1079
Test name
Test status
Simulation time 1086629881 ps
CPU time 6.48 seconds
Started Jan 17 03:32:51 PM PST 24
Finished Jan 17 03:32:58 PM PST 24
Peak memory 238404 kb
Host smart-aab515cf-338c-4386-9a86-cfca47d68ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505586935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3505586935
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_intr.3920440447
Short name T617
Test name
Test status
Simulation time 66198354910 ps
CPU time 19.74 seconds
Started Jan 17 03:32:41 PM PST 24
Finished Jan 17 03:33:04 PM PST 24
Peak memory 219332 kb
Host smart-ec7745d1-399a-4d02-8aa0-16fb908fa270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920440447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intr.3920440447
Directory /workspace/23.spi_device_intr/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2154749147
Short name T1678
Test name
Test status
Simulation time 2881545221 ps
CPU time 11.7 seconds
Started Jan 17 03:32:54 PM PST 24
Finished Jan 17 03:33:09 PM PST 24
Peak memory 247524 kb
Host smart-5b844073-2364-4ac7-af57-630a01438b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154749147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2154749147
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2686656023
Short name T775
Test name
Test status
Simulation time 5062190463 ps
CPU time 10.66 seconds
Started Jan 17 03:32:51 PM PST 24
Finished Jan 17 03:33:02 PM PST 24
Peak memory 225464 kb
Host smart-11d2e242-781f-42cd-b5e0-60538f43a72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686656023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2686656023
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1545190982
Short name T1450
Test name
Test status
Simulation time 4195723066 ps
CPU time 7.83 seconds
Started Jan 17 03:32:51 PM PST 24
Finished Jan 17 03:33:00 PM PST 24
Peak memory 218560 kb
Host smart-2ebcaf7f-45f1-4e95-b38a-c30cdbccb9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545190982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1545190982
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_perf.1915269502
Short name T519
Test name
Test status
Simulation time 6235797418 ps
CPU time 493.91 seconds
Started Jan 17 03:32:49 PM PST 24
Finished Jan 17 03:41:04 PM PST 24
Peak memory 287676 kb
Host smart-1df4aa5f-b4f6-4dbe-af5d-280a212dcb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915269502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_perf.1915269502
Directory /workspace/23.spi_device_perf/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2177208680
Short name T1524
Test name
Test status
Simulation time 2089672558 ps
CPU time 6.53 seconds
Started Jan 17 03:32:51 PM PST 24
Finished Jan 17 03:32:58 PM PST 24
Peak memory 234856 kb
Host smart-fd50a102-506b-4e76-9afd-2f627aa6d330
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2177208680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2177208680
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_rx_async_fifo_reset.2225994974
Short name T1076
Test name
Test status
Simulation time 50582565 ps
CPU time 0.99 seconds
Started Jan 17 03:32:51 PM PST 24
Finished Jan 17 03:32:53 PM PST 24
Peak memory 208708 kb
Host smart-2b3d1a72-1727-4745-b376-28fb277aeb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225994974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_rx_async_fifo_reset.2225994974
Directory /workspace/23.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/23.spi_device_rx_timeout.1194336537
Short name T819
Test name
Test status
Simulation time 9111445352 ps
CPU time 6.88 seconds
Started Jan 17 03:32:40 PM PST 24
Finished Jan 17 03:32:51 PM PST 24
Peak memory 217240 kb
Host smart-e4960ea5-59a3-4429-8077-6a3704b6e79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194336537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_rx_timeout.1194336537
Directory /workspace/23.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/23.spi_device_smoke.577494548
Short name T1059
Test name
Test status
Simulation time 30952799 ps
CPU time 1.07 seconds
Started Jan 17 03:32:43 PM PST 24
Finished Jan 17 03:32:45 PM PST 24
Peak memory 208728 kb
Host smart-27c1fd81-45cb-404d-9f03-8e7f7086f3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577494548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_smoke.577494548
Directory /workspace/23.spi_device_smoke/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1879348549
Short name T1673
Test name
Test status
Simulation time 200891973289 ps
CPU time 653.51 seconds
Started Jan 17 03:32:56 PM PST 24
Finished Jan 17 03:43:51 PM PST 24
Peak memory 289360 kb
Host smart-a82030a3-4181-41e8-83b4-ad4138878c91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879348549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1879348549
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.4222196550
Short name T1326
Test name
Test status
Simulation time 6806324068 ps
CPU time 48.21 seconds
Started Jan 17 03:32:47 PM PST 24
Finished Jan 17 03:33:36 PM PST 24
Peak memory 217244 kb
Host smart-f3935741-5f93-48e1-a9e2-45e6f8bf70db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222196550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4222196550
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.847318514
Short name T541
Test name
Test status
Simulation time 1992651402 ps
CPU time 5.15 seconds
Started Jan 17 03:32:49 PM PST 24
Finished Jan 17 03:32:55 PM PST 24
Peak memory 217056 kb
Host smart-9feafb21-4a98-4068-8505-170b65ae74ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847318514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.847318514
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3149756597
Short name T959
Test name
Test status
Simulation time 153681395 ps
CPU time 5.42 seconds
Started Jan 17 03:32:49 PM PST 24
Finished Jan 17 03:32:55 PM PST 24
Peak memory 217164 kb
Host smart-eb77c347-6542-44c7-8963-ab383dadd7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149756597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3149756597
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2676831090
Short name T558
Test name
Test status
Simulation time 40697727 ps
CPU time 0.92 seconds
Started Jan 17 03:32:56 PM PST 24
Finished Jan 17 03:32:59 PM PST 24
Peak memory 208440 kb
Host smart-1baf3e55-7fde-4694-9bf6-7c7f622d4200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676831090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2676831090
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_tx_async_fifo_reset.3214119633
Short name T79
Test name
Test status
Simulation time 17764945 ps
CPU time 0.78 seconds
Started Jan 17 03:32:50 PM PST 24
Finished Jan 17 03:32:52 PM PST 24
Peak memory 208764 kb
Host smart-eca1ad39-2017-4d3e-9038-e255504819d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214119633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tx_async_fifo_reset.3214119633
Directory /workspace/23.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/23.spi_device_txrx.113707245
Short name T1167
Test name
Test status
Simulation time 32437848438 ps
CPU time 226.05 seconds
Started Jan 17 03:32:43 PM PST 24
Finished Jan 17 03:36:30 PM PST 24
Peak memory 266404 kb
Host smart-2a53015c-125e-4493-acb3-b99c0164a9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113707245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_txrx.113707245
Directory /workspace/23.spi_device_txrx/latest

Test location /workspace/coverage/default/23.spi_device_upload.982056165
Short name T315
Test name
Test status
Simulation time 6367755381 ps
CPU time 7.93 seconds
Started Jan 17 03:32:49 PM PST 24
Finished Jan 17 03:32:57 PM PST 24
Peak memory 219312 kb
Host smart-881fe559-c888-4f54-be30-09c4bd194058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982056165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.982056165
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_abort.1878838625
Short name T1390
Test name
Test status
Simulation time 22485727 ps
CPU time 0.74 seconds
Started Jan 17 03:32:58 PM PST 24
Finished Jan 17 03:33:00 PM PST 24
Peak memory 206964 kb
Host smart-c76bc8d5-b30e-41af-a1a5-1a14c12588ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878838625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_abort.1878838625
Directory /workspace/24.spi_device_abort/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2422962808
Short name T540
Test name
Test status
Simulation time 23581926 ps
CPU time 0.73 seconds
Started Jan 17 03:33:07 PM PST 24
Finished Jan 17 03:33:08 PM PST 24
Peak memory 206784 kb
Host smart-a9bc738a-384f-4385-8fdc-45119d3dde83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422962808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2422962808
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_bit_transfer.716832094
Short name T504
Test name
Test status
Simulation time 361654717 ps
CPU time 2.43 seconds
Started Jan 17 03:32:55 PM PST 24
Finished Jan 17 03:33:00 PM PST 24
Peak memory 217072 kb
Host smart-71a01266-a0d2-42ab-9ffe-bafc1937e38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716832094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_bit_transfer.716832094
Directory /workspace/24.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/24.spi_device_byte_transfer.1525000058
Short name T728
Test name
Test status
Simulation time 671447248 ps
CPU time 4.14 seconds
Started Jan 17 03:32:57 PM PST 24
Finished Jan 17 03:33:02 PM PST 24
Peak memory 217168 kb
Host smart-0e5045aa-e139-45b5-8b47-59631a537d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525000058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_byte_transfer.1525000058
Directory /workspace/24.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1406678216
Short name T1734
Test name
Test status
Simulation time 1079902693 ps
CPU time 5.28 seconds
Started Jan 17 03:33:00 PM PST 24
Finished Jan 17 03:33:06 PM PST 24
Peak memory 219224 kb
Host smart-7a7e61ae-de28-4c02-8530-7e12fc9f54a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406678216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1406678216
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2258837357
Short name T715
Test name
Test status
Simulation time 17552709 ps
CPU time 0.76 seconds
Started Jan 17 03:32:56 PM PST 24
Finished Jan 17 03:32:59 PM PST 24
Peak memory 207972 kb
Host smart-0f5b7951-0983-4670-abe2-1579303d01b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258837357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2258837357
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_dummy_item_extra_dly.30502453
Short name T35
Test name
Test status
Simulation time 177154025665 ps
CPU time 417.11 seconds
Started Jan 17 03:32:54 PM PST 24
Finished Jan 17 03:39:53 PM PST 24
Peak memory 249696 kb
Host smart-1e75aa6b-7890-431c-a2bf-8b2eb7c9317e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30502453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_dummy_item_extra_dly.30502453
Directory /workspace/24.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/24.spi_device_extreme_fifo_size.3260694433
Short name T533
Test name
Test status
Simulation time 49414838943 ps
CPU time 803.63 seconds
Started Jan 17 03:32:51 PM PST 24
Finished Jan 17 03:46:15 PM PST 24
Peak memory 219172 kb
Host smart-67a82efb-e154-4433-9553-06d6333995ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260694433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_extreme_fifo_size.3260694433
Directory /workspace/24.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/24.spi_device_fifo_full.376129146
Short name T590
Test name
Test status
Simulation time 78958617969 ps
CPU time 454.24 seconds
Started Jan 17 03:32:57 PM PST 24
Finished Jan 17 03:40:32 PM PST 24
Peak memory 266032 kb
Host smart-390cdc28-7de2-4896-9b4a-a8e7fffe8ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376129146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_fifo_full.376129146
Directory /workspace/24.spi_device_fifo_full/latest

Test location /workspace/coverage/default/24.spi_device_fifo_underflow_overflow.2922239392
Short name T183
Test name
Test status
Simulation time 14406497089 ps
CPU time 128.78 seconds
Started Jan 17 03:32:58 PM PST 24
Finished Jan 17 03:35:08 PM PST 24
Peak memory 297560 kb
Host smart-b9e81684-bbaa-447b-b241-bc522082d63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922239392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_fifo_underflow_overf
low.2922239392
Directory /workspace/24.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1075900993
Short name T197
Test name
Test status
Simulation time 31606489921 ps
CPU time 106.72 seconds
Started Jan 17 03:32:58 PM PST 24
Finished Jan 17 03:34:46 PM PST 24
Peak memory 266468 kb
Host smart-8df67278-1cc0-4a1d-b332-2f4e5cb04e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075900993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1075900993
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1796669766
Short name T1365
Test name
Test status
Simulation time 31897921307 ps
CPU time 169.73 seconds
Started Jan 17 03:33:03 PM PST 24
Finished Jan 17 03:35:53 PM PST 24
Peak memory 251048 kb
Host smart-a5685f7c-43fb-44c1-9e06-0f83bcf5918c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796669766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1796669766
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2988001457
Short name T1387
Test name
Test status
Simulation time 854633731 ps
CPU time 9.1 seconds
Started Jan 17 03:32:59 PM PST 24
Finished Jan 17 03:33:08 PM PST 24
Peak memory 230468 kb
Host smart-de304a0b-26ae-457f-a7d0-5150c0ec7539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988001457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2988001457
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.778447142
Short name T554
Test name
Test status
Simulation time 1268805577 ps
CPU time 4.77 seconds
Started Jan 17 03:33:01 PM PST 24
Finished Jan 17 03:33:06 PM PST 24
Peak memory 220360 kb
Host smart-70504ac3-22af-4110-9a9d-9a29a27e08fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778447142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.778447142
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_intr.1188732531
Short name T1736
Test name
Test status
Simulation time 24202306669 ps
CPU time 22.74 seconds
Started Jan 17 03:32:54 PM PST 24
Finished Jan 17 03:33:20 PM PST 24
Peak memory 225444 kb
Host smart-738fa4e8-2494-4eba-8fca-5e7d3de6ec76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188732531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intr.1188732531
Directory /workspace/24.spi_device_intr/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3248030709
Short name T1177
Test name
Test status
Simulation time 2273488253 ps
CPU time 12.03 seconds
Started Jan 17 03:33:04 PM PST 24
Finished Jan 17 03:33:16 PM PST 24
Peak memory 233680 kb
Host smart-e3e80c97-c4ff-4f5b-a089-8b6658d7c05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248030709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3248030709
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1310303798
Short name T340
Test name
Test status
Simulation time 332335323 ps
CPU time 4.59 seconds
Started Jan 17 03:33:02 PM PST 24
Finished Jan 17 03:33:07 PM PST 24
Peak memory 220644 kb
Host smart-f6dd01f9-c76e-4178-8a02-c5c052be64d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310303798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1310303798
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3145986074
Short name T700
Test name
Test status
Simulation time 93067072141 ps
CPU time 56.5 seconds
Started Jan 17 03:33:03 PM PST 24
Finished Jan 17 03:34:00 PM PST 24
Peak memory 257980 kb
Host smart-6d42ac7d-8963-453f-a5c9-59449f39a97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145986074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3145986074
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_perf.1383414682
Short name T1164
Test name
Test status
Simulation time 15167325072 ps
CPU time 403.06 seconds
Started Jan 17 03:32:54 PM PST 24
Finished Jan 17 03:39:40 PM PST 24
Peak memory 265712 kb
Host smart-c036c6bd-d9ff-4a95-b758-0a445f0fe10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383414682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_perf.1383414682
Directory /workspace/24.spi_device_perf/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3297555376
Short name T1349
Test name
Test status
Simulation time 1023024595 ps
CPU time 4.76 seconds
Started Jan 17 03:33:03 PM PST 24
Finished Jan 17 03:33:08 PM PST 24
Peak memory 234704 kb
Host smart-91a24640-5686-42f5-b82a-974b374eb346
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3297555376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3297555376
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_rx_async_fifo_reset.186518574
Short name T572
Test name
Test status
Simulation time 92984710 ps
CPU time 0.85 seconds
Started Jan 17 03:33:00 PM PST 24
Finished Jan 17 03:33:01 PM PST 24
Peak memory 208724 kb
Host smart-dc03c7fa-62fe-4bc1-a934-600e06b99bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186518574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_rx_async_fifo_reset.186518574
Directory /workspace/24.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/24.spi_device_rx_timeout.1662863771
Short name T985
Test name
Test status
Simulation time 9036552144 ps
CPU time 4.9 seconds
Started Jan 17 03:32:57 PM PST 24
Finished Jan 17 03:33:03 PM PST 24
Peak memory 217304 kb
Host smart-6a7c189c-0005-411f-b295-f4b59eea12a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662863771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_rx_timeout.1662863771
Directory /workspace/24.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/24.spi_device_smoke.1232077832
Short name T798
Test name
Test status
Simulation time 72650700 ps
CPU time 0.95 seconds
Started Jan 17 03:32:55 PM PST 24
Finished Jan 17 03:32:59 PM PST 24
Peak memory 208372 kb
Host smart-00252be8-66f6-4c85-9330-71e83afbd389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232077832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_smoke.1232077832
Directory /workspace/24.spi_device_smoke/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3063722989
Short name T635
Test name
Test status
Simulation time 10374280583 ps
CPU time 46.35 seconds
Started Jan 17 03:32:55 PM PST 24
Finished Jan 17 03:33:44 PM PST 24
Peak memory 217320 kb
Host smart-f83410a4-b69a-4094-87fc-6d5a6dd2ef4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063722989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3063722989
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4084663626
Short name T1361
Test name
Test status
Simulation time 7571793882 ps
CPU time 3.76 seconds
Started Jan 17 03:32:58 PM PST 24
Finished Jan 17 03:33:03 PM PST 24
Peak memory 217212 kb
Host smart-b3bf8c91-bd90-4396-bb1f-3e27369cd5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084663626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4084663626
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3912651993
Short name T1305
Test name
Test status
Simulation time 197502737 ps
CPU time 1.63 seconds
Started Jan 17 03:33:00 PM PST 24
Finished Jan 17 03:33:02 PM PST 24
Peak memory 217032 kb
Host smart-ba35ff51-3af8-47b5-a455-c1ebff32700f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912651993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3912651993
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.391480209
Short name T1214
Test name
Test status
Simulation time 160672770 ps
CPU time 0.85 seconds
Started Jan 17 03:33:00 PM PST 24
Finished Jan 17 03:33:02 PM PST 24
Peak memory 207292 kb
Host smart-8056193a-4ec2-4c51-ba22-4a18491f8ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391480209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.391480209
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_tx_async_fifo_reset.3562765931
Short name T949
Test name
Test status
Simulation time 27824618 ps
CPU time 0.79 seconds
Started Jan 17 03:32:57 PM PST 24
Finished Jan 17 03:32:59 PM PST 24
Peak memory 208756 kb
Host smart-f4f65352-fece-4d2a-9eac-65d60d5a776e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562765931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tx_async_fifo_reset.3562765931
Directory /workspace/24.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/24.spi_device_txrx.3329792482
Short name T1683
Test name
Test status
Simulation time 213129430217 ps
CPU time 239.31 seconds
Started Jan 17 03:32:58 PM PST 24
Finished Jan 17 03:36:58 PM PST 24
Peak memory 304380 kb
Host smart-77a4ac51-2733-4b65-88f2-6d5ad1d1efd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329792482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_txrx.3329792482
Directory /workspace/24.spi_device_txrx/latest

Test location /workspace/coverage/default/24.spi_device_upload.499133709
Short name T260
Test name
Test status
Simulation time 1864240702 ps
CPU time 12.96 seconds
Started Jan 17 03:33:00 PM PST 24
Finished Jan 17 03:33:14 PM PST 24
Peak memory 241744 kb
Host smart-4a6dbfa9-b768-4f7f-8528-3b03433b2cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499133709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.499133709
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_abort.3563143200
Short name T804
Test name
Test status
Simulation time 27085126 ps
CPU time 0.77 seconds
Started Jan 17 03:33:11 PM PST 24
Finished Jan 17 03:33:13 PM PST 24
Peak memory 207252 kb
Host smart-6aa10a47-5199-4d7e-b88f-a811ce1cd7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563143200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_abort.3563143200
Directory /workspace/25.spi_device_abort/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.343357715
Short name T493
Test name
Test status
Simulation time 15457176 ps
CPU time 0.74 seconds
Started Jan 17 03:33:12 PM PST 24
Finished Jan 17 03:33:13 PM PST 24
Peak memory 206768 kb
Host smart-974d604e-7fa9-4d2e-bdd7-2fbd3f610772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343357715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.343357715
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_bit_transfer.3999366706
Short name T1382
Test name
Test status
Simulation time 534251252 ps
CPU time 3.06 seconds
Started Jan 17 03:33:06 PM PST 24
Finished Jan 17 03:33:09 PM PST 24
Peak memory 217128 kb
Host smart-fcb75bf4-71ae-41d2-b85b-3634faa085f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999366706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_bit_transfer.3999366706
Directory /workspace/25.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/25.spi_device_byte_transfer.2861870154
Short name T1640
Test name
Test status
Simulation time 735624010 ps
CPU time 3.11 seconds
Started Jan 17 03:33:07 PM PST 24
Finished Jan 17 03:33:10 PM PST 24
Peak memory 217192 kb
Host smart-9532e37f-d5ae-4632-a5bb-2010b4440675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861870154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_byte_transfer.2861870154
Directory /workspace/25.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1792206029
Short name T1654
Test name
Test status
Simulation time 257824428 ps
CPU time 3.23 seconds
Started Jan 17 03:33:10 PM PST 24
Finished Jan 17 03:33:15 PM PST 24
Peak memory 219764 kb
Host smart-c9171e53-440e-4c46-81ce-5f4a9b2d236f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792206029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1792206029
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.924197003
Short name T1264
Test name
Test status
Simulation time 14982037 ps
CPU time 0.86 seconds
Started Jan 17 03:33:05 PM PST 24
Finished Jan 17 03:33:07 PM PST 24
Peak memory 207956 kb
Host smart-df2073f6-c1a1-447f-9312-1a8957d71589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924197003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.924197003
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_dummy_item_extra_dly.943059717
Short name T1458
Test name
Test status
Simulation time 59495637285 ps
CPU time 502.76 seconds
Started Jan 17 03:33:03 PM PST 24
Finished Jan 17 03:41:27 PM PST 24
Peak memory 256308 kb
Host smart-56b72abd-a27f-42fc-882b-d8fc42353ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943059717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_dummy_item_extra_dly.943059717
Directory /workspace/25.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/25.spi_device_extreme_fifo_size.3345592929
Short name T1449
Test name
Test status
Simulation time 5453869166 ps
CPU time 29.89 seconds
Started Jan 17 03:33:06 PM PST 24
Finished Jan 17 03:33:36 PM PST 24
Peak memory 241112 kb
Host smart-86922016-40cc-48b6-9464-2272af02de08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345592929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_extreme_fifo_size.3345592929
Directory /workspace/25.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/25.spi_device_fifo_full.1968705724
Short name T1130
Test name
Test status
Simulation time 49782204751 ps
CPU time 493.92 seconds
Started Jan 17 03:33:04 PM PST 24
Finished Jan 17 03:41:20 PM PST 24
Peak memory 249984 kb
Host smart-6215cec5-6fad-465f-9b1c-a7c44d5ae2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968705724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_fifo_full.1968705724
Directory /workspace/25.spi_device_fifo_full/latest

Test location /workspace/coverage/default/25.spi_device_fifo_underflow_overflow.2978086671
Short name T1739
Test name
Test status
Simulation time 60107303682 ps
CPU time 516.18 seconds
Started Jan 17 03:33:04 PM PST 24
Finished Jan 17 03:41:41 PM PST 24
Peak memory 528852 kb
Host smart-34afc948-e336-4cc0-aedc-a36a65d6d89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978086671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_fifo_underflow_overf
low.2978086671
Directory /workspace/25.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.4070084282
Short name T297
Test name
Test status
Simulation time 75352745150 ps
CPU time 153.24 seconds
Started Jan 17 03:33:13 PM PST 24
Finished Jan 17 03:35:53 PM PST 24
Peak memory 252844 kb
Host smart-703f44b9-9dbe-47ba-904f-59285e0d516f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070084282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.4070084282
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.822744933
Short name T246
Test name
Test status
Simulation time 246780360684 ps
CPU time 276.81 seconds
Started Jan 17 03:33:20 PM PST 24
Finished Jan 17 03:37:58 PM PST 24
Peak memory 253016 kb
Host smart-00a35754-9742-49ec-ab52-4cbf004b8042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822744933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.822744933
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.4058152129
Short name T720
Test name
Test status
Simulation time 5921324866 ps
CPU time 31.27 seconds
Started Jan 17 03:33:17 PM PST 24
Finished Jan 17 03:33:51 PM PST 24
Peak memory 238404 kb
Host smart-a84649a9-e240-40d8-93a0-afeb4d8c15ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058152129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4058152129
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2872895666
Short name T833
Test name
Test status
Simulation time 912060548 ps
CPU time 3.7 seconds
Started Jan 17 03:33:08 PM PST 24
Finished Jan 17 03:33:14 PM PST 24
Peak memory 233696 kb
Host smart-6125e2f0-bd4e-4397-983c-8ada321aefec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872895666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2872895666
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_intr.3034279498
Short name T1124
Test name
Test status
Simulation time 272204910843 ps
CPU time 96.24 seconds
Started Jan 17 03:33:06 PM PST 24
Finished Jan 17 03:34:43 PM PST 24
Peak memory 241124 kb
Host smart-86bba8a0-1648-4b17-87e4-003f20215bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034279498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intr.3034279498
Directory /workspace/25.spi_device_intr/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2414918596
Short name T220
Test name
Test status
Simulation time 13468236458 ps
CPU time 11.44 seconds
Started Jan 17 03:33:11 PM PST 24
Finished Jan 17 03:33:24 PM PST 24
Peak memory 221256 kb
Host smart-6fc9a77a-b718-4d45-b628-b567a93e91c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414918596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2414918596
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.274541406
Short name T1569
Test name
Test status
Simulation time 17319611186 ps
CPU time 21.64 seconds
Started Jan 17 03:33:13 PM PST 24
Finished Jan 17 03:33:41 PM PST 24
Peak memory 248192 kb
Host smart-0d8a106a-8bce-451c-be7f-a793ab50499d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274541406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.274541406
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.367579018
Short name T253
Test name
Test status
Simulation time 887387776 ps
CPU time 6.5 seconds
Started Jan 17 03:33:17 PM PST 24
Finished Jan 17 03:33:27 PM PST 24
Peak memory 248100 kb
Host smart-ebb18e18-e9e9-4d85-aad8-ca2d94ab5678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367579018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.367579018
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_perf.4123964371
Short name T1128
Test name
Test status
Simulation time 13797243527 ps
CPU time 275.57 seconds
Started Jan 17 03:33:06 PM PST 24
Finished Jan 17 03:37:42 PM PST 24
Peak memory 241668 kb
Host smart-ea01bca2-4e34-49c1-a100-8a4debae8222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123964371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_perf.4123964371
Directory /workspace/25.spi_device_perf/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2317347284
Short name T781
Test name
Test status
Simulation time 4565421979 ps
CPU time 5.82 seconds
Started Jan 17 03:33:15 PM PST 24
Finished Jan 17 03:33:25 PM PST 24
Peak memory 221156 kb
Host smart-cc195d6a-eae5-44eb-a584-de33bcdb4eaa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2317347284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2317347284
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_rx_async_fifo_reset.998227918
Short name T1512
Test name
Test status
Simulation time 67034916 ps
CPU time 0.91 seconds
Started Jan 17 03:33:11 PM PST 24
Finished Jan 17 03:33:13 PM PST 24
Peak memory 208784 kb
Host smart-4bbff8c2-47a8-4570-b3ee-0996d2e574ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998227918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_rx_async_fifo_reset.998227918
Directory /workspace/25.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/25.spi_device_rx_timeout.2524533715
Short name T774
Test name
Test status
Simulation time 729146648 ps
CPU time 6.83 seconds
Started Jan 17 03:33:06 PM PST 24
Finished Jan 17 03:33:14 PM PST 24
Peak memory 217040 kb
Host smart-419d25be-4065-462f-95f6-d89fb4c5309d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524533715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_rx_timeout.2524533715
Directory /workspace/25.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/25.spi_device_smoke.4048131265
Short name T1146
Test name
Test status
Simulation time 25890724 ps
CPU time 0.99 seconds
Started Jan 17 03:33:06 PM PST 24
Finished Jan 17 03:33:07 PM PST 24
Peak memory 208368 kb
Host smart-4d21ee1b-e04f-473a-b3b6-d3218c5c2a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048131265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_smoke.4048131265
Directory /workspace/25.spi_device_smoke/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2504260086
Short name T1647
Test name
Test status
Simulation time 2700335049 ps
CPU time 10.16 seconds
Started Jan 17 03:33:08 PM PST 24
Finished Jan 17 03:33:19 PM PST 24
Peak memory 217252 kb
Host smart-49e922b3-8eaf-499c-b860-959e4e6181c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504260086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2504260086
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.928482800
Short name T1307
Test name
Test status
Simulation time 2871932301 ps
CPU time 6.57 seconds
Started Jan 17 03:33:07 PM PST 24
Finished Jan 17 03:33:14 PM PST 24
Peak memory 217148 kb
Host smart-47c2b0ec-b34f-4c6b-8f33-45a80bc8dafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928482800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.928482800
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3068883276
Short name T930
Test name
Test status
Simulation time 347947257 ps
CPU time 11.86 seconds
Started Jan 17 03:33:17 PM PST 24
Finished Jan 17 03:33:32 PM PST 24
Peak memory 217088 kb
Host smart-e5a407bc-9fdc-4016-9499-6b07149eb090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068883276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3068883276
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1597664968
Short name T649
Test name
Test status
Simulation time 541950743 ps
CPU time 1.15 seconds
Started Jan 17 03:33:11 PM PST 24
Finished Jan 17 03:33:14 PM PST 24
Peak memory 208348 kb
Host smart-672c6a2f-3850-4278-b1d8-0b98c9e690f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597664968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1597664968
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_tx_async_fifo_reset.3713208330
Short name T1254
Test name
Test status
Simulation time 48543083 ps
CPU time 0.77 seconds
Started Jan 17 03:33:15 PM PST 24
Finished Jan 17 03:33:20 PM PST 24
Peak memory 208756 kb
Host smart-1002b452-9871-4712-b599-b1931b0ca834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713208330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tx_async_fifo_reset.3713208330
Directory /workspace/25.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/25.spi_device_txrx.1968453360
Short name T1121
Test name
Test status
Simulation time 114339165919 ps
CPU time 541.9 seconds
Started Jan 17 03:33:04 PM PST 24
Finished Jan 17 03:42:08 PM PST 24
Peak memory 299100 kb
Host smart-9f762bea-f931-47ae-8a13-47ef2b783662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968453360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_txrx.1968453360
Directory /workspace/25.spi_device_txrx/latest

Test location /workspace/coverage/default/25.spi_device_upload.3960255408
Short name T1583
Test name
Test status
Simulation time 185468663 ps
CPU time 4.37 seconds
Started Jan 17 03:33:12 PM PST 24
Finished Jan 17 03:33:17 PM PST 24
Peak memory 224356 kb
Host smart-8436f3d9-fcec-4291-b07c-7fa11c6e156c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960255408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3960255408
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_abort.923376944
Short name T567
Test name
Test status
Simulation time 49019349 ps
CPU time 0.76 seconds
Started Jan 17 03:33:29 PM PST 24
Finished Jan 17 03:33:31 PM PST 24
Peak memory 207252 kb
Host smart-9ca12c7b-e640-4acd-8b30-37584ffbebeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923376944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_abort.923376944
Directory /workspace/26.spi_device_abort/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2563632391
Short name T867
Test name
Test status
Simulation time 101819007 ps
CPU time 0.72 seconds
Started Jan 17 03:33:35 PM PST 24
Finished Jan 17 03:33:38 PM PST 24
Peak memory 206724 kb
Host smart-21570ca2-82ec-4677-8dac-eaff0c617935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563632391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2563632391
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_bit_transfer.287829352
Short name T1635
Test name
Test status
Simulation time 1254330423 ps
CPU time 3.14 seconds
Started Jan 17 03:33:27 PM PST 24
Finished Jan 17 03:33:30 PM PST 24
Peak memory 217120 kb
Host smart-bae9faaf-aa40-4ecc-96ee-0a103d2d858a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287829352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_bit_transfer.287829352
Directory /workspace/26.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/26.spi_device_byte_transfer.690910832
Short name T1323
Test name
Test status
Simulation time 1159834495 ps
CPU time 3.59 seconds
Started Jan 17 03:33:21 PM PST 24
Finished Jan 17 03:33:25 PM PST 24
Peak memory 217128 kb
Host smart-9905c460-b369-49e0-adaa-36aad8ea649b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690910832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_byte_transfer.690910832
Directory /workspace/26.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2757239678
Short name T314
Test name
Test status
Simulation time 521860316 ps
CPU time 4.44 seconds
Started Jan 17 03:33:35 PM PST 24
Finished Jan 17 03:33:41 PM PST 24
Peak memory 238808 kb
Host smart-7cdca29d-41ae-4f1b-896b-aa3a66e47123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757239678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2757239678
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1408337723
Short name T811
Test name
Test status
Simulation time 32268071 ps
CPU time 0.79 seconds
Started Jan 17 03:33:17 PM PST 24
Finished Jan 17 03:33:21 PM PST 24
Peak memory 207964 kb
Host smart-5f3de586-997d-4800-a89b-0a89fea2a8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408337723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1408337723
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_dummy_item_extra_dly.706518453
Short name T948
Test name
Test status
Simulation time 18541446140 ps
CPU time 286.31 seconds
Started Jan 17 03:33:12 PM PST 24
Finished Jan 17 03:37:59 PM PST 24
Peak memory 250040 kb
Host smart-a211711d-b820-4647-bfad-36de7650d30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706518453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_dummy_item_extra_dly.706518453
Directory /workspace/26.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/26.spi_device_extreme_fifo_size.3679000530
Short name T1676
Test name
Test status
Simulation time 15207100431 ps
CPU time 27.8 seconds
Started Jan 17 03:33:14 PM PST 24
Finished Jan 17 03:33:47 PM PST 24
Peak memory 224908 kb
Host smart-9fa2d155-6d81-4020-930c-41e859c34686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679000530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_extreme_fifo_size.3679000530
Directory /workspace/26.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/26.spi_device_fifo_full.977218211
Short name T1271
Test name
Test status
Simulation time 36569651010 ps
CPU time 315.7 seconds
Started Jan 17 03:33:12 PM PST 24
Finished Jan 17 03:38:28 PM PST 24
Peak memory 267500 kb
Host smart-9edd10ee-f56a-4642-9327-87badac952a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977218211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_fifo_full.977218211
Directory /workspace/26.spi_device_fifo_full/latest

Test location /workspace/coverage/default/26.spi_device_fifo_underflow_overflow.1738679519
Short name T50
Test name
Test status
Simulation time 103993473601 ps
CPU time 542.34 seconds
Started Jan 17 03:33:17 PM PST 24
Finished Jan 17 03:42:22 PM PST 24
Peak memory 431432 kb
Host smart-33103863-53a1-4da7-99f4-d314521b200a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738679519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_fifo_underflow_overf
low.1738679519
Directory /workspace/26.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3499946224
Short name T678
Test name
Test status
Simulation time 14251681420 ps
CPU time 20.55 seconds
Started Jan 17 03:33:36 PM PST 24
Finished Jan 17 03:33:58 PM PST 24
Peak memory 220616 kb
Host smart-c6265cd8-a959-4a0d-88b2-53666c7d3ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499946224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3499946224
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2104408225
Short name T608
Test name
Test status
Simulation time 16367046543 ps
CPU time 20.07 seconds
Started Jan 17 03:33:36 PM PST 24
Finished Jan 17 03:33:57 PM PST 24
Peak memory 233720 kb
Host smart-301fd222-3300-4851-817f-25af0a1393d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104408225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2104408225
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2674033548
Short name T1222
Test name
Test status
Simulation time 384936114 ps
CPU time 2.89 seconds
Started Jan 17 03:33:37 PM PST 24
Finished Jan 17 03:33:46 PM PST 24
Peak memory 225296 kb
Host smart-b7ffaaff-6846-4018-ae8c-d18085bd8199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674033548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2674033548
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_intr.3164890886
Short name T511
Test name
Test status
Simulation time 8920468158 ps
CPU time 35.54 seconds
Started Jan 17 03:33:24 PM PST 24
Finished Jan 17 03:34:00 PM PST 24
Peak memory 233400 kb
Host smart-32cc4a17-b808-403a-8d15-e81ac7aefcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164890886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intr.3164890886
Directory /workspace/26.spi_device_intr/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1240745294
Short name T1193
Test name
Test status
Simulation time 148327389 ps
CPU time 2.99 seconds
Started Jan 17 03:33:35 PM PST 24
Finished Jan 17 03:33:40 PM PST 24
Peak memory 218500 kb
Host smart-430b0b62-53d6-4ed4-a174-5fc5dce3cb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240745294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1240745294
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.652323620
Short name T1521
Test name
Test status
Simulation time 3222378444 ps
CPU time 10.44 seconds
Started Jan 17 03:33:27 PM PST 24
Finished Jan 17 03:33:38 PM PST 24
Peak memory 239528 kb
Host smart-a27a462e-6e58-4bfa-80fe-8a4e99148740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652323620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.652323620
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.686200114
Short name T257
Test name
Test status
Simulation time 14900210916 ps
CPU time 12.2 seconds
Started Jan 17 03:33:29 PM PST 24
Finished Jan 17 03:33:42 PM PST 24
Peak memory 219880 kb
Host smart-83eb5342-6c67-4e9b-9155-fb8a2fdba3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686200114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.686200114
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_perf.3916233662
Short name T1037
Test name
Test status
Simulation time 77316626457 ps
CPU time 244.11 seconds
Started Jan 17 03:33:21 PM PST 24
Finished Jan 17 03:37:26 PM PST 24
Peak memory 284800 kb
Host smart-a2020df8-b18d-476e-909b-d315c1326790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916233662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_perf.3916233662
Directory /workspace/26.spi_device_perf/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1265253725
Short name T1206
Test name
Test status
Simulation time 691283449 ps
CPU time 5.06 seconds
Started Jan 17 03:33:38 PM PST 24
Finished Jan 17 03:33:48 PM PST 24
Peak memory 220232 kb
Host smart-666c2a58-02a6-461a-ba9b-f64482900cf2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1265253725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1265253725
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_rx_async_fifo_reset.1784330777
Short name T1410
Test name
Test status
Simulation time 39367978 ps
CPU time 0.88 seconds
Started Jan 17 03:33:34 PM PST 24
Finished Jan 17 03:33:36 PM PST 24
Peak memory 208796 kb
Host smart-c424eae9-389c-4568-9850-677552437442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784330777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_rx_async_fifo_reset.1784330777
Directory /workspace/26.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/26.spi_device_rx_timeout.2667208722
Short name T1280
Test name
Test status
Simulation time 1250755724 ps
CPU time 5.88 seconds
Started Jan 17 03:33:17 PM PST 24
Finished Jan 17 03:33:26 PM PST 24
Peak memory 217184 kb
Host smart-3788c05f-b8b7-4101-b5bc-374adf5a3dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667208722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_rx_timeout.2667208722
Directory /workspace/26.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/26.spi_device_smoke.2069473527
Short name T1689
Test name
Test status
Simulation time 17565424 ps
CPU time 0.88 seconds
Started Jan 17 03:33:21 PM PST 24
Finished Jan 17 03:33:22 PM PST 24
Peak memory 208328 kb
Host smart-9307997f-819a-41c5-afe4-742b7586e715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069473527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_smoke.2069473527
Directory /workspace/26.spi_device_smoke/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1291221420
Short name T126
Test name
Test status
Simulation time 74560215614 ps
CPU time 988.54 seconds
Started Jan 17 03:33:33 PM PST 24
Finished Jan 17 03:50:03 PM PST 24
Peak memory 425332 kb
Host smart-235bd4dd-a8ea-4ded-ab3b-74e8677ad474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291221420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1291221420
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3988881704
Short name T736
Test name
Test status
Simulation time 19651773042 ps
CPU time 87.72 seconds
Started Jan 17 03:33:21 PM PST 24
Finished Jan 17 03:34:49 PM PST 24
Peak memory 217188 kb
Host smart-72223a50-34a5-4ba8-9c5b-5b7b77a24f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988881704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3988881704
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.903444541
Short name T1086
Test name
Test status
Simulation time 7476026269 ps
CPU time 12.32 seconds
Started Jan 17 03:33:19 PM PST 24
Finished Jan 17 03:33:33 PM PST 24
Peak memory 217092 kb
Host smart-538d571f-0310-42e8-889c-ee1b5e980d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903444541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.903444541
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2503566828
Short name T565
Test name
Test status
Simulation time 49297620 ps
CPU time 1.01 seconds
Started Jan 17 03:33:34 PM PST 24
Finished Jan 17 03:33:36 PM PST 24
Peak memory 208000 kb
Host smart-eb5b78b5-d255-4c74-8947-aefaf76a676e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503566828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2503566828
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.4157588075
Short name T503
Test name
Test status
Simulation time 52289957 ps
CPU time 0.89 seconds
Started Jan 17 03:33:31 PM PST 24
Finished Jan 17 03:33:33 PM PST 24
Peak memory 207248 kb
Host smart-238db77d-3a2a-4ae5-a8a9-7562ba5ffe65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157588075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4157588075
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_tx_async_fifo_reset.1311297542
Short name T1025
Test name
Test status
Simulation time 53245117 ps
CPU time 0.76 seconds
Started Jan 17 03:33:29 PM PST 24
Finished Jan 17 03:33:31 PM PST 24
Peak memory 208764 kb
Host smart-8f9e99c4-fc38-4b98-8352-847e2a006dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311297542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tx_async_fifo_reset.1311297542
Directory /workspace/26.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/26.spi_device_txrx.2571852752
Short name T1198
Test name
Test status
Simulation time 346197997731 ps
CPU time 337.54 seconds
Started Jan 17 03:33:21 PM PST 24
Finished Jan 17 03:38:59 PM PST 24
Peak memory 306000 kb
Host smart-cd8c9c76-cae4-48a4-80c1-d7489a67b4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571852752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_txrx.2571852752
Directory /workspace/26.spi_device_txrx/latest

Test location /workspace/coverage/default/26.spi_device_upload.1544782770
Short name T1290
Test name
Test status
Simulation time 1052192642 ps
CPU time 5.38 seconds
Started Jan 17 03:33:34 PM PST 24
Finished Jan 17 03:33:41 PM PST 24
Peak memory 218552 kb
Host smart-a6c73a06-3ed6-4ebf-9d46-f7d3ea12f056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544782770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1544782770
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_abort.2119286587
Short name T1330
Test name
Test status
Simulation time 41112351 ps
CPU time 0.73 seconds
Started Jan 17 03:33:40 PM PST 24
Finished Jan 17 03:33:44 PM PST 24
Peak memory 206936 kb
Host smart-d2db9234-8951-4c23-9af3-151ae5126e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119286587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_abort.2119286587
Directory /workspace/27.spi_device_abort/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1490897375
Short name T966
Test name
Test status
Simulation time 15145509 ps
CPU time 0.71 seconds
Started Jan 17 03:34:01 PM PST 24
Finished Jan 17 03:34:02 PM PST 24
Peak memory 206816 kb
Host smart-9990aade-4e0f-40e4-82e2-462a93730477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490897375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1490897375
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_bit_transfer.605748194
Short name T657
Test name
Test status
Simulation time 218939070 ps
CPU time 2.49 seconds
Started Jan 17 03:33:39 PM PST 24
Finished Jan 17 03:33:46 PM PST 24
Peak memory 217008 kb
Host smart-3e130fc0-585d-43c2-a67d-853abdd025e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605748194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_bit_transfer.605748194
Directory /workspace/27.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/27.spi_device_byte_transfer.2095942379
Short name T670
Test name
Test status
Simulation time 449114586 ps
CPU time 2.95 seconds
Started Jan 17 03:33:39 PM PST 24
Finished Jan 17 03:33:46 PM PST 24
Peak memory 217144 kb
Host smart-3344b019-e0a3-42ba-afe0-b1a1d62c0f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095942379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_byte_transfer.2095942379
Directory /workspace/27.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1974392566
Short name T1627
Test name
Test status
Simulation time 60545042 ps
CPU time 2.76 seconds
Started Jan 17 03:33:37 PM PST 24
Finished Jan 17 03:33:45 PM PST 24
Peak memory 238852 kb
Host smart-5a2963e8-99d4-4a15-8487-c5a2931a3510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974392566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1974392566
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2312325513
Short name T963
Test name
Test status
Simulation time 20386484 ps
CPU time 0.79 seconds
Started Jan 17 03:33:38 PM PST 24
Finished Jan 17 03:33:44 PM PST 24
Peak memory 206956 kb
Host smart-6aae8c07-71cc-4d96-926c-710a04eeefd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312325513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2312325513
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_dummy_item_extra_dly.109292435
Short name T934
Test name
Test status
Simulation time 89900838097 ps
CPU time 317.31 seconds
Started Jan 17 03:33:37 PM PST 24
Finished Jan 17 03:38:59 PM PST 24
Peak memory 264416 kb
Host smart-3c315432-1f40-4b95-b282-f14626537d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109292435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_dummy_item_extra_dly.109292435
Directory /workspace/27.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/27.spi_device_extreme_fifo_size.1249017221
Short name T531
Test name
Test status
Simulation time 129896723599 ps
CPU time 718.94 seconds
Started Jan 17 03:33:36 PM PST 24
Finished Jan 17 03:45:36 PM PST 24
Peak memory 219312 kb
Host smart-1a19f784-180b-466f-a742-cf803058b58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249017221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_extreme_fifo_size.1249017221
Directory /workspace/27.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/27.spi_device_fifo_full.1526273107
Short name T860
Test name
Test status
Simulation time 57548202768 ps
CPU time 1649.37 seconds
Started Jan 17 03:33:36 PM PST 24
Finished Jan 17 04:01:07 PM PST 24
Peak memory 312832 kb
Host smart-f62b2a86-b2f8-4b60-aa00-eec4aa2c8b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526273107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_fifo_full.1526273107
Directory /workspace/27.spi_device_fifo_full/latest

Test location /workspace/coverage/default/27.spi_device_fifo_underflow_overflow.1980817347
Short name T808
Test name
Test status
Simulation time 89331129905 ps
CPU time 512.16 seconds
Started Jan 17 03:33:36 PM PST 24
Finished Jan 17 03:42:09 PM PST 24
Peak memory 388140 kb
Host smart-791496b6-c8e4-429a-8f45-8a2c0448f562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980817347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_fifo_underflow_overf
low.1980817347
Directory /workspace/27.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2497561470
Short name T1454
Test name
Test status
Simulation time 1390479464 ps
CPU time 12.44 seconds
Started Jan 17 03:33:36 PM PST 24
Finished Jan 17 03:33:50 PM PST 24
Peak memory 239496 kb
Host smart-5504f7b6-82b7-42c2-91cf-c1d95ec7c742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497561470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2497561470
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3307910563
Short name T262
Test name
Test status
Simulation time 24129984772 ps
CPU time 119.16 seconds
Started Jan 17 03:34:02 PM PST 24
Finished Jan 17 03:36:02 PM PST 24
Peak memory 258284 kb
Host smart-91ec592f-0b5e-44f2-8078-bb596d57e3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307910563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3307910563
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2939766278
Short name T1766
Test name
Test status
Simulation time 2089921418 ps
CPU time 50.12 seconds
Started Jan 17 03:33:38 PM PST 24
Finished Jan 17 03:34:33 PM PST 24
Peak memory 261436 kb
Host smart-d0feebe9-c0af-4586-b072-e80131578fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939766278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2939766278
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.4172209528
Short name T1027
Test name
Test status
Simulation time 84437258859 ps
CPU time 97.57 seconds
Started Jan 17 03:33:37 PM PST 24
Finished Jan 17 03:35:15 PM PST 24
Peak memory 267236 kb
Host smart-57e7883b-b75a-49f1-8006-c6923352e6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172209528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.4172209528
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3621693194
Short name T23
Test name
Test status
Simulation time 815103230 ps
CPU time 6.33 seconds
Started Jan 17 03:33:38 PM PST 24
Finished Jan 17 03:33:50 PM PST 24
Peak memory 241612 kb
Host smart-7593a6ae-4015-4933-9d09-55c97055a4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621693194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3621693194
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_intr.3772919667
Short name T1303
Test name
Test status
Simulation time 34418549401 ps
CPU time 47.99 seconds
Started Jan 17 03:33:39 PM PST 24
Finished Jan 17 03:34:31 PM PST 24
Peak memory 236928 kb
Host smart-28397557-1d0b-488a-9dcf-ecf9adbe0b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772919667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intr.3772919667
Directory /workspace/27.spi_device_intr/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1711266847
Short name T1754
Test name
Test status
Simulation time 206011565 ps
CPU time 3.22 seconds
Started Jan 17 03:33:38 PM PST 24
Finished Jan 17 03:33:46 PM PST 24
Peak memory 226368 kb
Host smart-5e615acb-0e01-422e-b045-34ea2bf95445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711266847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1711266847
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.565730284
Short name T1616
Test name
Test status
Simulation time 7221150886 ps
CPU time 23.58 seconds
Started Jan 17 03:33:37 PM PST 24
Finished Jan 17 03:34:06 PM PST 24
Peak memory 228676 kb
Host smart-3b08a6e7-416a-4c37-9752-b38918e040a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565730284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.565730284
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1660666079
Short name T844
Test name
Test status
Simulation time 299864593 ps
CPU time 3.32 seconds
Started Jan 17 03:33:39 PM PST 24
Finished Jan 17 03:33:47 PM PST 24
Peak memory 241728 kb
Host smart-f99d2f9f-03ce-4618-9cc4-0bd625a1f843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660666079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1660666079
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_perf.4067153312
Short name T1577
Test name
Test status
Simulation time 6022335387 ps
CPU time 176.95 seconds
Started Jan 17 03:33:38 PM PST 24
Finished Jan 17 03:36:40 PM PST 24
Peak memory 255340 kb
Host smart-e72098d9-843f-4f20-ae4a-1a2ada797d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067153312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_perf.4067153312
Directory /workspace/27.spi_device_perf/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2526812377
Short name T532
Test name
Test status
Simulation time 5332307250 ps
CPU time 7.2 seconds
Started Jan 17 03:33:35 PM PST 24
Finished Jan 17 03:33:44 PM PST 24
Peak memory 237388 kb
Host smart-ced9d50d-139d-4158-9a3c-f281a08e6b80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2526812377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2526812377
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_rx_async_fifo_reset.749740098
Short name T1515
Test name
Test status
Simulation time 28194100 ps
CPU time 0.83 seconds
Started Jan 17 03:34:02 PM PST 24
Finished Jan 17 03:34:03 PM PST 24
Peak memory 208808 kb
Host smart-cba11acc-6f5e-4117-9c80-81fce8fa305e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749740098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_rx_async_fifo_reset.749740098
Directory /workspace/27.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/27.spi_device_rx_timeout.494198907
Short name T645
Test name
Test status
Simulation time 836930249 ps
CPU time 5.89 seconds
Started Jan 17 03:33:41 PM PST 24
Finished Jan 17 03:33:49 PM PST 24
Peak memory 216524 kb
Host smart-82f184b0-a92b-43d7-bdf5-c4c659f3aeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494198907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_rx_timeout.494198907
Directory /workspace/27.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/27.spi_device_smoke.2648555094
Short name T772
Test name
Test status
Simulation time 66520140 ps
CPU time 1.24 seconds
Started Jan 17 03:33:38 PM PST 24
Finished Jan 17 03:33:44 PM PST 24
Peak memory 217056 kb
Host smart-d805a498-79e6-402c-adcf-b24204e86b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648555094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_smoke.2648555094
Directory /workspace/27.spi_device_smoke/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1935393968
Short name T123
Test name
Test status
Simulation time 551272740079 ps
CPU time 2280.83 seconds
Started Jan 17 03:34:01 PM PST 24
Finished Jan 17 04:12:03 PM PST 24
Peak memory 631700 kb
Host smart-44f408c0-1c29-402f-a073-bd324d3fc35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935393968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1935393968
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.4257149373
Short name T1719
Test name
Test status
Simulation time 14256934618 ps
CPU time 84.5 seconds
Started Jan 17 03:33:40 PM PST 24
Finished Jan 17 03:35:08 PM PST 24
Peak memory 221220 kb
Host smart-df6ead44-89de-44d3-b99a-d33821501f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257149373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4257149373
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.343774462
Short name T1648
Test name
Test status
Simulation time 55275087617 ps
CPU time 31.02 seconds
Started Jan 17 03:33:39 PM PST 24
Finished Jan 17 03:34:14 PM PST 24
Peak memory 217132 kb
Host smart-c4d56cbd-089c-4b68-bfdd-2cb4167e7238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343774462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.343774462
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3943274254
Short name T1539
Test name
Test status
Simulation time 82782893 ps
CPU time 1.36 seconds
Started Jan 17 03:33:35 PM PST 24
Finished Jan 17 03:33:38 PM PST 24
Peak memory 217120 kb
Host smart-ac30cce8-50a9-4e0f-a7ce-da092b774399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943274254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3943274254
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2035304718
Short name T923
Test name
Test status
Simulation time 446167616 ps
CPU time 1.1 seconds
Started Jan 17 03:34:02 PM PST 24
Finished Jan 17 03:34:03 PM PST 24
Peak memory 208388 kb
Host smart-f747b624-cedb-40b9-8413-50a04ea9a4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035304718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2035304718
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_tx_async_fifo_reset.923210003
Short name T1642
Test name
Test status
Simulation time 52050901 ps
CPU time 0.78 seconds
Started Jan 17 03:33:38 PM PST 24
Finished Jan 17 03:33:44 PM PST 24
Peak memory 208724 kb
Host smart-24558d53-61e2-4a63-a661-67a49cedfc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923210003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tx_async_fifo_reset.923210003
Directory /workspace/27.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/27.spi_device_txrx.2739742659
Short name T527
Test name
Test status
Simulation time 464047704219 ps
CPU time 610.88 seconds
Started Jan 17 03:33:35 PM PST 24
Finished Jan 17 03:43:48 PM PST 24
Peak memory 276724 kb
Host smart-971a5b9d-b042-480a-bf27-8437f1fca943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739742659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_txrx.2739742659
Directory /workspace/27.spi_device_txrx/latest

Test location /workspace/coverage/default/27.spi_device_upload.3713607084
Short name T783
Test name
Test status
Simulation time 9254163286 ps
CPU time 9.76 seconds
Started Jan 17 03:33:38 PM PST 24
Finished Jan 17 03:33:53 PM PST 24
Peak memory 220048 kb
Host smart-27b10d90-5ebd-4621-8ced-c86642202ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713607084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3713607084
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_abort.1025975528
Short name T1581
Test name
Test status
Simulation time 123648759 ps
CPU time 0.74 seconds
Started Jan 17 03:33:44 PM PST 24
Finished Jan 17 03:33:45 PM PST 24
Peak memory 207012 kb
Host smart-0f5dfe3f-b5e4-40c1-b950-6f1f0d69fd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025975528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_abort.1025975528
Directory /workspace/28.spi_device_abort/latest

Test location /workspace/coverage/default/28.spi_device_bit_transfer.3561710437
Short name T1053
Test name
Test status
Simulation time 181549724 ps
CPU time 2.52 seconds
Started Jan 17 03:33:43 PM PST 24
Finished Jan 17 03:33:46 PM PST 24
Peak memory 217128 kb
Host smart-282a9777-1fdf-4e4e-ae2f-37c668166e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561710437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_bit_transfer.3561710437
Directory /workspace/28.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/28.spi_device_byte_transfer.667217940
Short name T1533
Test name
Test status
Simulation time 2521843672 ps
CPU time 2.84 seconds
Started Jan 17 03:33:44 PM PST 24
Finished Jan 17 03:33:48 PM PST 24
Peak memory 217188 kb
Host smart-4993c37c-1369-4696-92d5-85dd50a5f594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667217940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_byte_transfer.667217940
Directory /workspace/28.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3488078932
Short name T96
Test name
Test status
Simulation time 798469340 ps
CPU time 4.22 seconds
Started Jan 17 03:33:54 PM PST 24
Finished Jan 17 03:34:01 PM PST 24
Peak memory 220952 kb
Host smart-e216c848-f355-422f-987d-801d0a9350b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488078932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3488078932
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.609859618
Short name T1082
Test name
Test status
Simulation time 16531881 ps
CPU time 0.78 seconds
Started Jan 17 03:33:43 PM PST 24
Finished Jan 17 03:33:44 PM PST 24
Peak memory 206948 kb
Host smart-cb544c86-6922-494d-83de-c77468ed8877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609859618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.609859618
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_extreme_fifo_size.4230738948
Short name T1488
Test name
Test status
Simulation time 34480034663 ps
CPU time 1584.07 seconds
Started Jan 17 03:34:01 PM PST 24
Finished Jan 17 04:00:26 PM PST 24
Peak memory 218316 kb
Host smart-ffe21c0f-8fbf-4f7e-9673-b6e9cbe48b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230738948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_extreme_fifo_size.4230738948
Directory /workspace/28.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/28.spi_device_fifo_full.1170282836
Short name T574
Test name
Test status
Simulation time 13166902811 ps
CPU time 270.82 seconds
Started Jan 17 03:33:37 PM PST 24
Finished Jan 17 03:38:08 PM PST 24
Peak memory 275256 kb
Host smart-ad4082fe-ed7d-453b-bc05-9f288c4a35cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170282836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_fifo_full.1170282836
Directory /workspace/28.spi_device_fifo_full/latest

Test location /workspace/coverage/default/28.spi_device_fifo_underflow_overflow.2191254039
Short name T1408
Test name
Test status
Simulation time 61378018983 ps
CPU time 149.12 seconds
Started Jan 17 03:34:01 PM PST 24
Finished Jan 17 03:36:31 PM PST 24
Peak memory 329472 kb
Host smart-6a13d042-773a-4d64-97fd-3acf82e233d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191254039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_fifo_underflow_overf
low.2191254039
Directory /workspace/28.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3532668036
Short name T1253
Test name
Test status
Simulation time 1487220394 ps
CPU time 29.93 seconds
Started Jan 17 03:33:53 PM PST 24
Finished Jan 17 03:34:26 PM PST 24
Peak memory 241820 kb
Host smart-ef653747-7a6c-4982-bc4e-7e1064bb044c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532668036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3532668036
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.323621157
Short name T321
Test name
Test status
Simulation time 67665687148 ps
CPU time 119.78 seconds
Started Jan 17 03:33:56 PM PST 24
Finished Jan 17 03:35:57 PM PST 24
Peak memory 256252 kb
Host smart-7e16a7b2-fe89-45a5-be75-789a4107439d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323621157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.323621157
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3540138911
Short name T41
Test name
Test status
Simulation time 453694748 ps
CPU time 12.52 seconds
Started Jan 17 03:33:51 PM PST 24
Finished Jan 17 03:34:04 PM PST 24
Peak memory 246388 kb
Host smart-65d11136-068c-4bb7-87d6-59d0edecda18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540138911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3540138911
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1666033358
Short name T672
Test name
Test status
Simulation time 11751406090 ps
CPU time 12.49 seconds
Started Jan 17 03:33:44 PM PST 24
Finished Jan 17 03:33:57 PM PST 24
Peak memory 221756 kb
Host smart-60b5dd59-e5b8-4dad-9d31-b5f8be2b5d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666033358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1666033358
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_intr.1336719671
Short name T956
Test name
Test status
Simulation time 44762266984 ps
CPU time 46.1 seconds
Started Jan 17 03:33:45 PM PST 24
Finished Jan 17 03:34:32 PM PST 24
Peak memory 232936 kb
Host smart-6b7c6ee9-59be-4054-a962-96d3df5b82c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336719671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intr.1336719671
Directory /workspace/28.spi_device_intr/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.4279561685
Short name T305
Test name
Test status
Simulation time 3201425444 ps
CPU time 15.27 seconds
Started Jan 17 03:33:44 PM PST 24
Finished Jan 17 03:34:00 PM PST 24
Peak memory 239864 kb
Host smart-ffb3c941-b52b-4290-8443-bcf0ade07f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279561685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4279561685
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1932126761
Short name T298
Test name
Test status
Simulation time 313954931 ps
CPU time 5.45 seconds
Started Jan 17 03:33:44 PM PST 24
Finished Jan 17 03:33:50 PM PST 24
Peak memory 220492 kb
Host smart-8105eff3-be68-45db-9835-bbf9648cf9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932126761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1932126761
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2316002252
Short name T900
Test name
Test status
Simulation time 3279769521 ps
CPU time 5.85 seconds
Started Jan 17 03:33:56 PM PST 24
Finished Jan 17 03:34:04 PM PST 24
Peak memory 235328 kb
Host smart-d3827360-74cf-4d8b-aab1-0de69112c531
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2316002252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2316002252
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_rx_async_fifo_reset.2235965511
Short name T891
Test name
Test status
Simulation time 214061816 ps
CPU time 0.84 seconds
Started Jan 17 03:33:46 PM PST 24
Finished Jan 17 03:33:48 PM PST 24
Peak memory 208804 kb
Host smart-322d84bf-3395-4a9c-b0ee-cd2cf302d832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235965511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_rx_async_fifo_reset.2235965511
Directory /workspace/28.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/28.spi_device_rx_timeout.3495208259
Short name T862
Test name
Test status
Simulation time 448408365 ps
CPU time 5.28 seconds
Started Jan 17 03:33:44 PM PST 24
Finished Jan 17 03:33:50 PM PST 24
Peak memory 217180 kb
Host smart-bbae44a5-5a5c-4aa9-ac74-278f6d90a800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495208259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_rx_timeout.3495208259
Directory /workspace/28.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/28.spi_device_smoke.1592089141
Short name T1116
Test name
Test status
Simulation time 27051166 ps
CPU time 0.87 seconds
Started Jan 17 03:34:02 PM PST 24
Finished Jan 17 03:34:04 PM PST 24
Peak memory 208172 kb
Host smart-a6d8d768-a79f-4842-bf3a-6ba2d6c4f524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592089141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_smoke.1592089141
Directory /workspace/28.spi_device_smoke/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1740666008
Short name T72
Test name
Test status
Simulation time 10289519978 ps
CPU time 56.57 seconds
Started Jan 17 03:33:56 PM PST 24
Finished Jan 17 03:34:54 PM PST 24
Peak memory 256548 kb
Host smart-1d0ddf31-4d0d-42a9-ac3d-4ee4bdfbe9d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740666008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1740666008
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3319215514
Short name T361
Test name
Test status
Simulation time 959909693 ps
CPU time 13.46 seconds
Started Jan 17 03:33:51 PM PST 24
Finished Jan 17 03:34:05 PM PST 24
Peak memory 217096 kb
Host smart-77a5ccaa-557f-4c4a-ab37-e667330ffa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319215514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3319215514
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3317146530
Short name T1650
Test name
Test status
Simulation time 26121873142 ps
CPU time 11.01 seconds
Started Jan 17 03:33:46 PM PST 24
Finished Jan 17 03:33:58 PM PST 24
Peak memory 217252 kb
Host smart-c01dad49-ac2c-4386-b08f-2c890c6faaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317146530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3317146530
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.4098218115
Short name T1619
Test name
Test status
Simulation time 316493835 ps
CPU time 2.59 seconds
Started Jan 17 03:33:53 PM PST 24
Finished Jan 17 03:33:59 PM PST 24
Peak memory 217188 kb
Host smart-f4346099-a386-48fb-afaa-e16ce731bc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098218115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4098218115
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1150709486
Short name T967
Test name
Test status
Simulation time 219089289 ps
CPU time 1 seconds
Started Jan 17 03:33:51 PM PST 24
Finished Jan 17 03:33:52 PM PST 24
Peak memory 207288 kb
Host smart-725aa840-fc45-4a19-92bb-a064b634f017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150709486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1150709486
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_tx_async_fifo_reset.1378633955
Short name T1694
Test name
Test status
Simulation time 22559041 ps
CPU time 0.79 seconds
Started Jan 17 03:33:51 PM PST 24
Finished Jan 17 03:33:52 PM PST 24
Peak memory 208764 kb
Host smart-203fe54e-3e05-460a-bbea-39d26b2d6195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378633955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tx_async_fifo_reset.1378633955
Directory /workspace/28.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/28.spi_device_txrx.176043823
Short name T1016
Test name
Test status
Simulation time 20212471232 ps
CPU time 192.89 seconds
Started Jan 17 03:33:39 PM PST 24
Finished Jan 17 03:36:56 PM PST 24
Peak memory 284192 kb
Host smart-60cf9fa4-b731-44a8-bca2-d08a70e6f41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176043823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_txrx.176043823
Directory /workspace/28.spi_device_txrx/latest

Test location /workspace/coverage/default/28.spi_device_upload.4174157915
Short name T1582
Test name
Test status
Simulation time 109685257 ps
CPU time 3.91 seconds
Started Jan 17 03:34:02 PM PST 24
Finished Jan 17 03:34:07 PM PST 24
Peak memory 238096 kb
Host smart-3d2e9fd8-edda-4c22-b13f-965494adfc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174157915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.4174157915
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_abort.3816304642
Short name T639
Test name
Test status
Simulation time 63884967 ps
CPU time 0.79 seconds
Started Jan 17 03:33:59 PM PST 24
Finished Jan 17 03:34:01 PM PST 24
Peak memory 206972 kb
Host smart-0fde593e-b92a-466f-a41b-210abe989656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816304642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_abort.3816304642
Directory /workspace/29.spi_device_abort/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2538553683
Short name T850
Test name
Test status
Simulation time 22423788 ps
CPU time 0.73 seconds
Started Jan 17 03:34:14 PM PST 24
Finished Jan 17 03:34:22 PM PST 24
Peak memory 206816 kb
Host smart-ad251e1e-3dd3-4677-9b75-f312f25cfe85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538553683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2538553683
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_bit_transfer.3833685036
Short name T1762
Test name
Test status
Simulation time 671889874 ps
CPU time 2.49 seconds
Started Jan 17 03:33:58 PM PST 24
Finished Jan 17 03:34:01 PM PST 24
Peak memory 217116 kb
Host smart-dca372fd-b5de-4f2b-a412-c26fb4fbf728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833685036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_bit_transfer.3833685036
Directory /workspace/29.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/29.spi_device_byte_transfer.3479473090
Short name T1275
Test name
Test status
Simulation time 82868065 ps
CPU time 3.28 seconds
Started Jan 17 03:33:55 PM PST 24
Finished Jan 17 03:34:00 PM PST 24
Peak memory 217008 kb
Host smart-1c131b3e-d9f3-402d-ac60-239a36a64eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479473090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_byte_transfer.3479473090
Directory /workspace/29.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1209327135
Short name T898
Test name
Test status
Simulation time 760145469 ps
CPU time 4.68 seconds
Started Jan 17 03:34:13 PM PST 24
Finished Jan 17 03:34:20 PM PST 24
Peak memory 218556 kb
Host smart-a957378c-6814-4af1-9d28-c18eb32ebcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209327135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1209327135
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.122904290
Short name T887
Test name
Test status
Simulation time 37689881 ps
CPU time 0.77 seconds
Started Jan 17 03:33:56 PM PST 24
Finished Jan 17 03:33:58 PM PST 24
Peak memory 207980 kb
Host smart-43a5e768-c042-45e2-b6ee-4b223c0dc3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122904290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.122904290
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_dummy_item_extra_dly.3567781928
Short name T719
Test name
Test status
Simulation time 29036446175 ps
CPU time 100.22 seconds
Started Jan 17 03:33:55 PM PST 24
Finished Jan 17 03:35:38 PM PST 24
Peak memory 238664 kb
Host smart-41edd004-fb44-4c8c-bcb5-f9683e7d76e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567781928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_dummy_item_extra_dly.3567781928
Directory /workspace/29.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/29.spi_device_extreme_fifo_size.3834697888
Short name T1585
Test name
Test status
Simulation time 179038906478 ps
CPU time 471.99 seconds
Started Jan 17 03:33:56 PM PST 24
Finished Jan 17 03:41:50 PM PST 24
Peak memory 218216 kb
Host smart-2ff249b9-a7f0-49c7-93c3-7f2203314d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834697888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_extreme_fifo_size.3834697888
Directory /workspace/29.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/29.spi_device_fifo_full.4055843406
Short name T748
Test name
Test status
Simulation time 46665036842 ps
CPU time 1007.98 seconds
Started Jan 17 03:33:53 PM PST 24
Finished Jan 17 03:50:44 PM PST 24
Peak memory 315492 kb
Host smart-373d2c01-f18e-4315-a335-94a8c778a583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055843406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_fifo_full.4055843406
Directory /workspace/29.spi_device_fifo_full/latest

Test location /workspace/coverage/default/29.spi_device_fifo_underflow_overflow.2550712391
Short name T593
Test name
Test status
Simulation time 16878703723 ps
CPU time 299.69 seconds
Started Jan 17 03:33:57 PM PST 24
Finished Jan 17 03:38:58 PM PST 24
Peak memory 357436 kb
Host smart-a5e71976-143d-4fa9-9003-1cd9d5bcdf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550712391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_fifo_underflow_overf
low.2550712391
Directory /workspace/29.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.222882808
Short name T1411
Test name
Test status
Simulation time 75287114262 ps
CPU time 161.14 seconds
Started Jan 17 03:34:05 PM PST 24
Finished Jan 17 03:36:47 PM PST 24
Peak memory 252152 kb
Host smart-357c9bfd-889e-4a40-ae88-19fef95d17f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222882808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.222882808
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1901349724
Short name T1417
Test name
Test status
Simulation time 5232807540 ps
CPU time 90.19 seconds
Started Jan 17 03:34:09 PM PST 24
Finished Jan 17 03:35:41 PM PST 24
Peak memory 253368 kb
Host smart-433f8404-49d3-41d8-839e-900ce1b7d92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901349724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1901349724
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.63285094
Short name T1236
Test name
Test status
Simulation time 1701344533 ps
CPU time 18.73 seconds
Started Jan 17 03:34:06 PM PST 24
Finished Jan 17 03:34:26 PM PST 24
Peak memory 258372 kb
Host smart-a25f753c-71bc-4326-853d-1e6b6200e61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63285094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.63285094
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.634846351
Short name T1536
Test name
Test status
Simulation time 1048746405 ps
CPU time 5.59 seconds
Started Jan 17 03:33:56 PM PST 24
Finished Jan 17 03:34:03 PM PST 24
Peak memory 221784 kb
Host smart-d236346b-56d0-4d66-a996-a3bd146252bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634846351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.634846351
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_intr.4096430651
Short name T1737
Test name
Test status
Simulation time 97694955257 ps
CPU time 34 seconds
Started Jan 17 03:33:56 PM PST 24
Finished Jan 17 03:34:32 PM PST 24
Peak memory 233604 kb
Host smart-a064e9ce-7eb7-4bbc-b418-e973c398aa18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096430651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intr.4096430651
Directory /workspace/29.spi_device_intr/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2755247595
Short name T250
Test name
Test status
Simulation time 3955303945 ps
CPU time 22.79 seconds
Started Jan 17 03:34:08 PM PST 24
Finished Jan 17 03:34:31 PM PST 24
Peak memory 256996 kb
Host smart-c6122852-d7bc-4c97-8f21-fc4c6c960b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755247595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2755247595
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.534604955
Short name T293
Test name
Test status
Simulation time 635253281 ps
CPU time 10.3 seconds
Started Jan 17 03:34:00 PM PST 24
Finished Jan 17 03:34:11 PM PST 24
Peak memory 253396 kb
Host smart-f765ac5c-ef49-4193-865e-c82a639f7353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534604955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.534604955
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1487249434
Short name T873
Test name
Test status
Simulation time 13630380877 ps
CPU time 42.71 seconds
Started Jan 17 03:33:59 PM PST 24
Finished Jan 17 03:34:43 PM PST 24
Peak memory 250968 kb
Host smart-99a48ef8-bbe7-4ad4-b29e-139a3f8d8576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487249434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1487249434
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_perf.1728324335
Short name T1176
Test name
Test status
Simulation time 6940865285 ps
CPU time 81.46 seconds
Started Jan 17 03:33:55 PM PST 24
Finished Jan 17 03:35:19 PM PST 24
Peak memory 254032 kb
Host smart-a336512b-690c-4e6b-83e0-513ee17fe9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728324335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_perf.1728324335
Directory /workspace/29.spi_device_perf/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.4123674967
Short name T1423
Test name
Test status
Simulation time 365622239 ps
CPU time 4.68 seconds
Started Jan 17 03:34:12 PM PST 24
Finished Jan 17 03:34:19 PM PST 24
Peak memory 219728 kb
Host smart-6a1659dd-3a78-48c5-adb1-92869486f4c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4123674967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.4123674967
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_rx_async_fifo_reset.2701602548
Short name T124
Test name
Test status
Simulation time 71679452 ps
CPU time 0.91 seconds
Started Jan 17 03:33:59 PM PST 24
Finished Jan 17 03:34:00 PM PST 24
Peak memory 208752 kb
Host smart-452dbcae-eda7-43ad-8498-0161b4b75b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701602548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_rx_async_fifo_reset.2701602548
Directory /workspace/29.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/29.spi_device_rx_timeout.1346034966
Short name T661
Test name
Test status
Simulation time 3420702667 ps
CPU time 4.84 seconds
Started Jan 17 03:33:56 PM PST 24
Finished Jan 17 03:34:02 PM PST 24
Peak memory 217188 kb
Host smart-bf52bba7-73eb-44d9-bb17-4d5c61b0651a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346034966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_rx_timeout.1346034966
Directory /workspace/29.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/29.spi_device_smoke.2487800057
Short name T917
Test name
Test status
Simulation time 124800668 ps
CPU time 1.02 seconds
Started Jan 17 03:33:53 PM PST 24
Finished Jan 17 03:33:57 PM PST 24
Peak memory 208364 kb
Host smart-670b38b1-0f31-4139-83a5-bacc2a02a652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487800057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_smoke.2487800057
Directory /workspace/29.spi_device_smoke/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.210918667
Short name T31
Test name
Test status
Simulation time 4407748758 ps
CPU time 23.52 seconds
Started Jan 17 03:33:59 PM PST 24
Finished Jan 17 03:34:24 PM PST 24
Peak memory 221648 kb
Host smart-abace618-66d9-487d-96d7-909a51773fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210918667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.210918667
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2779578290
Short name T848
Test name
Test status
Simulation time 8258751546 ps
CPU time 12.66 seconds
Started Jan 17 03:33:59 PM PST 24
Finished Jan 17 03:34:12 PM PST 24
Peak memory 217228 kb
Host smart-8defc8de-6f39-4d54-88a4-d19f511e4241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779578290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2779578290
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1188407107
Short name T529
Test name
Test status
Simulation time 245740362 ps
CPU time 1.53 seconds
Started Jan 17 03:33:55 PM PST 24
Finished Jan 17 03:33:59 PM PST 24
Peak memory 217092 kb
Host smart-230a29dd-44c5-4633-86c2-de050258dbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188407107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1188407107
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1782660309
Short name T1699
Test name
Test status
Simulation time 234570193 ps
CPU time 1.02 seconds
Started Jan 17 03:33:55 PM PST 24
Finished Jan 17 03:33:58 PM PST 24
Peak memory 207248 kb
Host smart-4994f26b-34f1-4abf-9c57-1d0a5ca5ff69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782660309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1782660309
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_tx_async_fifo_reset.359148837
Short name T958
Test name
Test status
Simulation time 57252175 ps
CPU time 0.76 seconds
Started Jan 17 03:33:58 PM PST 24
Finished Jan 17 03:34:00 PM PST 24
Peak memory 208792 kb
Host smart-0de91797-0608-4bcb-9f3d-a57618c273db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359148837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tx_async_fifo_reset.359148837
Directory /workspace/29.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/29.spi_device_txrx.1955000375
Short name T1656
Test name
Test status
Simulation time 86776347275 ps
CPU time 149.75 seconds
Started Jan 17 03:33:52 PM PST 24
Finished Jan 17 03:36:24 PM PST 24
Peak memory 258200 kb
Host smart-c29ae70a-ad26-4501-bb47-0c8edf838a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955000375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_txrx.1955000375
Directory /workspace/29.spi_device_txrx/latest

Test location /workspace/coverage/default/29.spi_device_upload.2002958571
Short name T751
Test name
Test status
Simulation time 11306507415 ps
CPU time 16.01 seconds
Started Jan 17 03:34:07 PM PST 24
Finished Jan 17 03:34:23 PM PST 24
Peak memory 225412 kb
Host smart-c6d3759f-c2a3-4b66-8a03-131f764bbbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002958571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2002958571
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_abort.2574259880
Short name T3
Test name
Test status
Simulation time 24959557 ps
CPU time 0.74 seconds
Started Jan 17 03:29:04 PM PST 24
Finished Jan 17 03:29:06 PM PST 24
Peak memory 206964 kb
Host smart-2933fc23-9009-49ff-acc4-b453d41e90bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574259880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_abort.2574259880
Directory /workspace/3.spi_device_abort/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.906017291
Short name T1104
Test name
Test status
Simulation time 16455679 ps
CPU time 0.73 seconds
Started Jan 17 03:29:14 PM PST 24
Finished Jan 17 03:29:16 PM PST 24
Peak memory 206792 kb
Host smart-7ce85559-e322-4d55-bd6a-3404e2fef4eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906017291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.906017291
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_bit_transfer.3986277714
Short name T1118
Test name
Test status
Simulation time 425378525 ps
CPU time 2.2 seconds
Started Jan 17 03:29:06 PM PST 24
Finished Jan 17 03:29:08 PM PST 24
Peak memory 217188 kb
Host smart-ca89e07c-ee87-4603-89ec-77a4707ca22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986277714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_bit_transfer.3986277714
Directory /workspace/3.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/3.spi_device_byte_transfer.3493702513
Short name T77
Test name
Test status
Simulation time 928183511 ps
CPU time 3.3 seconds
Started Jan 17 03:29:04 PM PST 24
Finished Jan 17 03:29:09 PM PST 24
Peak memory 217204 kb
Host smart-cb7d6376-be96-41fa-93c1-79e1da234eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493702513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_byte_transfer.3493702513
Directory /workspace/3.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3612517611
Short name T1316
Test name
Test status
Simulation time 565782636 ps
CPU time 4.67 seconds
Started Jan 17 03:29:12 PM PST 24
Finished Jan 17 03:29:17 PM PST 24
Peak memory 238932 kb
Host smart-341f5bf1-e50c-47d3-b2b2-7eca2d4d7886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612517611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3612517611
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2052837440
Short name T1260
Test name
Test status
Simulation time 15965661 ps
CPU time 0.8 seconds
Started Jan 17 03:29:06 PM PST 24
Finished Jan 17 03:29:07 PM PST 24
Peak memory 207976 kb
Host smart-2f7bba0e-bf75-4226-b44f-48f43560e6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052837440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2052837440
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_dummy_item_extra_dly.2646355613
Short name T477
Test name
Test status
Simulation time 63943010743 ps
CPU time 593.53 seconds
Started Jan 17 03:29:03 PM PST 24
Finished Jan 17 03:38:58 PM PST 24
Peak memory 250052 kb
Host smart-653f5683-c018-4c94-91da-040e2a88df06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646355613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_dummy_item_extra_dly.2646355613
Directory /workspace/3.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/3.spi_device_extreme_fifo_size.660191977
Short name T264
Test name
Test status
Simulation time 275663351279 ps
CPU time 3340.99 seconds
Started Jan 17 03:29:05 PM PST 24
Finished Jan 17 04:24:47 PM PST 24
Peak memory 222428 kb
Host smart-0611d0d6-caaf-4421-a075-4d741b89bd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660191977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_extreme_fifo_size.660191977
Directory /workspace/3.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/3.spi_device_fifo_full.1247355564
Short name T762
Test name
Test status
Simulation time 35347578284 ps
CPU time 211.56 seconds
Started Jan 17 03:29:04 PM PST 24
Finished Jan 17 03:32:37 PM PST 24
Peak memory 281328 kb
Host smart-2ee21174-7494-4814-972a-b5861bf36cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247355564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_fifo_full.1247355564
Directory /workspace/3.spi_device_fifo_full/latest

Test location /workspace/coverage/default/3.spi_device_fifo_underflow_overflow.764890310
Short name T209
Test name
Test status
Simulation time 289758463573 ps
CPU time 1380.85 seconds
Started Jan 17 03:29:04 PM PST 24
Finished Jan 17 03:52:06 PM PST 24
Peak memory 681584 kb
Host smart-64bd7a67-6d81-40d3-9fe6-b2e161a7bb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764890310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_fifo_underflow_overflo
w.764890310
Directory /workspace/3.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2750110036
Short name T296
Test name
Test status
Simulation time 2772029202 ps
CPU time 13.87 seconds
Started Jan 17 03:29:16 PM PST 24
Finished Jan 17 03:29:32 PM PST 24
Peak memory 241020 kb
Host smart-659b9ff7-9298-4c61-b863-8401ebb115d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750110036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2750110036
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3902306493
Short name T198
Test name
Test status
Simulation time 112721900531 ps
CPU time 207.51 seconds
Started Jan 17 03:29:17 PM PST 24
Finished Jan 17 03:32:46 PM PST 24
Peak memory 266068 kb
Host smart-9799ffdc-6f0e-4859-957d-af1ef8ae58e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902306493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3902306493
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2428071889
Short name T1068
Test name
Test status
Simulation time 2463053840 ps
CPU time 18.15 seconds
Started Jan 17 03:29:12 PM PST 24
Finished Jan 17 03:29:31 PM PST 24
Peak memory 257724 kb
Host smart-57e2daf4-66fa-44e6-a929-12e60914de19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428071889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2428071889
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.4282507845
Short name T1575
Test name
Test status
Simulation time 6439963460 ps
CPU time 11.22 seconds
Started Jan 17 03:29:12 PM PST 24
Finished Jan 17 03:29:24 PM PST 24
Peak memory 225500 kb
Host smart-f2996842-56f2-4c41-804d-c5d49f9041d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282507845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.4282507845
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_intr.343137134
Short name T1122
Test name
Test status
Simulation time 58943475028 ps
CPU time 51.83 seconds
Started Jan 17 03:29:04 PM PST 24
Finished Jan 17 03:29:57 PM PST 24
Peak memory 223844 kb
Host smart-8dd2c98a-07f5-4d19-9e17-3edcf4f4ad87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343137134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intr.343137134
Directory /workspace/3.spi_device_intr/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2233812453
Short name T852
Test name
Test status
Simulation time 209890801 ps
CPU time 4.7 seconds
Started Jan 17 03:29:13 PM PST 24
Finished Jan 17 03:29:19 PM PST 24
Peak memory 218788 kb
Host smart-93be6cde-84c3-45ce-9e44-cb0f286998e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233812453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2233812453
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2130157114
Short name T1537
Test name
Test status
Simulation time 119317244 ps
CPU time 1.15 seconds
Started Jan 17 03:29:03 PM PST 24
Finished Jan 17 03:29:06 PM PST 24
Peak memory 219184 kb
Host smart-b33d811b-e6ee-463a-a361-724f49c11ee6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130157114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2130157114
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.899325797
Short name T1425
Test name
Test status
Simulation time 4448213915 ps
CPU time 9.52 seconds
Started Jan 17 03:29:11 PM PST 24
Finished Jan 17 03:29:21 PM PST 24
Peak memory 249608 kb
Host smart-3016a10d-8c74-4e43-b8c1-3e3524423f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899325797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
899325797
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.65725733
Short name T1728
Test name
Test status
Simulation time 131854271 ps
CPU time 3.19 seconds
Started Jan 17 03:29:10 PM PST 24
Finished Jan 17 03:29:13 PM PST 24
Peak memory 238632 kb
Host smart-3e0738aa-04bd-4471-abd6-3637e99f6f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65725733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.65725733
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_perf.693183990
Short name T1270
Test name
Test status
Simulation time 403076849395 ps
CPU time 762.18 seconds
Started Jan 17 03:29:07 PM PST 24
Finished Jan 17 03:41:50 PM PST 24
Peak memory 275752 kb
Host smart-0557d421-2101-4fd0-9d26-e5ed1ba2d268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693183990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_perf.693183990
Directory /workspace/3.spi_device_perf/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.799097593
Short name T1761
Test name
Test status
Simulation time 26915039 ps
CPU time 0.74 seconds
Started Jan 17 03:29:04 PM PST 24
Finished Jan 17 03:29:06 PM PST 24
Peak memory 217044 kb
Host smart-55232cae-a04d-45f0-8495-7d895c113969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799097593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.799097593
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2281089224
Short name T1760
Test name
Test status
Simulation time 1480368412 ps
CPU time 6.02 seconds
Started Jan 17 03:29:12 PM PST 24
Finished Jan 17 03:29:18 PM PST 24
Peak memory 234760 kb
Host smart-62f0ceaf-afa6-4821-bed9-e7a33dd6888e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2281089224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2281089224
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_rx_async_fifo_reset.1583707105
Short name T1566
Test name
Test status
Simulation time 45952909 ps
CPU time 0.94 seconds
Started Jan 17 03:29:03 PM PST 24
Finished Jan 17 03:29:05 PM PST 24
Peak memory 208804 kb
Host smart-a4dc06bf-eecd-4e3a-9e0e-4f8eb7bf9044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583707105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_rx_async_fifo_reset.1583707105
Directory /workspace/3.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/3.spi_device_rx_timeout.1727981561
Short name T1195
Test name
Test status
Simulation time 3082845480 ps
CPU time 5.98 seconds
Started Jan 17 03:29:03 PM PST 24
Finished Jan 17 03:29:11 PM PST 24
Peak memory 217484 kb
Host smart-4e082642-b65c-4152-af59-f2ab0e607e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727981561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_rx_timeout.1727981561
Directory /workspace/3.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3513755944
Short name T93
Test name
Test status
Simulation time 541989723 ps
CPU time 1.24 seconds
Started Jan 17 03:29:16 PM PST 24
Finished Jan 17 03:29:19 PM PST 24
Peak memory 238284 kb
Host smart-9fd2e1a8-cb60-44c7-9fc2-665882f69ef7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513755944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3513755944
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_smoke.2659160588
Short name T1268
Test name
Test status
Simulation time 221516966 ps
CPU time 1.19 seconds
Started Jan 17 03:29:07 PM PST 24
Finished Jan 17 03:29:09 PM PST 24
Peak memory 216936 kb
Host smart-01c6a284-a96f-4aed-9e15-bbb1c0d1242d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659160588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_smoke.2659160588
Directory /workspace/3.spi_device_smoke/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.254737506
Short name T317
Test name
Test status
Simulation time 46079557724 ps
CPU time 468.38 seconds
Started Jan 17 03:29:12 PM PST 24
Finished Jan 17 03:37:01 PM PST 24
Peak memory 290096 kb
Host smart-eb61f0ac-6217-48a6-bd76-2f9e872ca1be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254737506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.254737506
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.943942604
Short name T881
Test name
Test status
Simulation time 17561739660 ps
CPU time 35.43 seconds
Started Jan 17 03:29:03 PM PST 24
Finished Jan 17 03:29:40 PM PST 24
Peak memory 221396 kb
Host smart-1a088422-73bb-48c8-b5bf-c47163e90956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943942604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.943942604
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2360885823
Short name T1414
Test name
Test status
Simulation time 1620363103 ps
CPU time 3.54 seconds
Started Jan 17 03:29:03 PM PST 24
Finished Jan 17 03:29:08 PM PST 24
Peak memory 216888 kb
Host smart-34d210fd-b4f5-4683-ac20-53554c9918f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360885823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2360885823
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3934862778
Short name T630
Test name
Test status
Simulation time 518498581 ps
CPU time 1.68 seconds
Started Jan 17 03:29:10 PM PST 24
Finished Jan 17 03:29:13 PM PST 24
Peak memory 217132 kb
Host smart-0bc753e5-65c6-4961-869e-2999a3928315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934862778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3934862778
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3880121367
Short name T1171
Test name
Test status
Simulation time 153110682 ps
CPU time 0.95 seconds
Started Jan 17 03:29:10 PM PST 24
Finished Jan 17 03:29:11 PM PST 24
Peak memory 207312 kb
Host smart-b80101af-ed80-4eed-aed4-75ac09c94c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880121367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3880121367
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_tx_async_fifo_reset.23198268
Short name T705
Test name
Test status
Simulation time 47127506 ps
CPU time 0.75 seconds
Started Jan 17 03:29:04 PM PST 24
Finished Jan 17 03:29:06 PM PST 24
Peak memory 208728 kb
Host smart-f41594b3-5350-43b0-8286-aaa556ca7ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23198268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tx_async_fifo_reset.23198268
Directory /workspace/3.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/3.spi_device_txrx.3412655513
Short name T1147
Test name
Test status
Simulation time 104588398306 ps
CPU time 507.28 seconds
Started Jan 17 03:29:04 PM PST 24
Finished Jan 17 03:37:32 PM PST 24
Peak memory 258188 kb
Host smart-c2e29b4a-b504-488d-a317-5fdf751f55bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412655513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_txrx.3412655513
Directory /workspace/3.spi_device_txrx/latest

Test location /workspace/coverage/default/3.spi_device_upload.955705555
Short name T790
Test name
Test status
Simulation time 2753560546 ps
CPU time 15.26 seconds
Started Jan 17 03:29:15 PM PST 24
Finished Jan 17 03:29:31 PM PST 24
Peak memory 240060 kb
Host smart-57729743-532d-435e-b274-a131ed191641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955705555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.955705555
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_abort.3759279177
Short name T666
Test name
Test status
Simulation time 22668024 ps
CPU time 0.8 seconds
Started Jan 17 03:34:09 PM PST 24
Finished Jan 17 03:34:11 PM PST 24
Peak memory 207024 kb
Host smart-cb2527c4-0cbd-4434-9522-d7b6d42c83dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759279177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_abort.3759279177
Directory /workspace/30.spi_device_abort/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.574891856
Short name T543
Test name
Test status
Simulation time 48762325 ps
CPU time 0.76 seconds
Started Jan 17 03:34:14 PM PST 24
Finished Jan 17 03:34:22 PM PST 24
Peak memory 207052 kb
Host smart-456b632c-d6b9-4dd7-82f7-7b2f68d67866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574891856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.574891856
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_bit_transfer.1334572222
Short name T756
Test name
Test status
Simulation time 114768681 ps
CPU time 2.83 seconds
Started Jan 17 03:34:14 PM PST 24
Finished Jan 17 03:34:18 PM PST 24
Peak memory 217164 kb
Host smart-100b2360-1925-41fe-b964-f2c68e53fca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334572222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_bit_transfer.1334572222
Directory /workspace/30.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/30.spi_device_byte_transfer.458293611
Short name T834
Test name
Test status
Simulation time 205245696 ps
CPU time 2.77 seconds
Started Jan 17 03:34:20 PM PST 24
Finished Jan 17 03:34:25 PM PST 24
Peak memory 217092 kb
Host smart-29db0141-e1c2-485f-97d7-eaea399b9605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458293611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_byte_transfer.458293611
Directory /workspace/30.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1753858397
Short name T849
Test name
Test status
Simulation time 822729693 ps
CPU time 3.58 seconds
Started Jan 17 03:34:11 PM PST 24
Finished Jan 17 03:34:16 PM PST 24
Peak memory 233648 kb
Host smart-cb1e3ba8-321b-4103-864a-24c95f33aee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753858397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1753858397
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1719125197
Short name T1471
Test name
Test status
Simulation time 14732285 ps
CPU time 0.79 seconds
Started Jan 17 03:34:05 PM PST 24
Finished Jan 17 03:34:06 PM PST 24
Peak memory 207880 kb
Host smart-f420e6df-ee52-46ea-b1ba-745e65274244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719125197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1719125197
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_dummy_item_extra_dly.1674404651
Short name T1677
Test name
Test status
Simulation time 108556814637 ps
CPU time 488.8 seconds
Started Jan 17 03:34:18 PM PST 24
Finished Jan 17 03:42:31 PM PST 24
Peak memory 304440 kb
Host smart-29d05af7-57a4-4b3f-bd32-d8ac51e67b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674404651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_dummy_item_extra_dly.1674404651
Directory /workspace/30.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/30.spi_device_extreme_fifo_size.1131358278
Short name T1709
Test name
Test status
Simulation time 3597700011 ps
CPU time 32.63 seconds
Started Jan 17 03:34:10 PM PST 24
Finished Jan 17 03:34:45 PM PST 24
Peak memory 233636 kb
Host smart-4f48ed07-bc76-4604-b47d-8a7a2215ed03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131358278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_extreme_fifo_size.1131358278
Directory /workspace/30.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/30.spi_device_fifo_full.193227707
Short name T612
Test name
Test status
Simulation time 22736991687 ps
CPU time 342.18 seconds
Started Jan 17 03:34:10 PM PST 24
Finished Jan 17 03:39:55 PM PST 24
Peak memory 272064 kb
Host smart-f343249d-c560-46e0-9bf5-aea2eccb208d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193227707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_fifo_full.193227707
Directory /workspace/30.spi_device_fifo_full/latest

Test location /workspace/coverage/default/30.spi_device_fifo_underflow_overflow.88138181
Short name T758
Test name
Test status
Simulation time 137442817333 ps
CPU time 469.66 seconds
Started Jan 17 03:34:09 PM PST 24
Finished Jan 17 03:42:00 PM PST 24
Peak memory 428660 kb
Host smart-c7086601-d588-4706-8f70-09e07eb25151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88138181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_fifo_underflow_overflo
w.88138181
Directory /workspace/30.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2384958973
Short name T961
Test name
Test status
Simulation time 3197862737 ps
CPU time 79.67 seconds
Started Jan 17 03:34:27 PM PST 24
Finished Jan 17 03:35:47 PM PST 24
Peak memory 262796 kb
Host smart-be1b7f81-2ba5-4b40-8f61-90aa04132a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384958973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2384958973
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2806774206
Short name T281
Test name
Test status
Simulation time 38876770001 ps
CPU time 39.78 seconds
Started Jan 17 03:34:23 PM PST 24
Finished Jan 17 03:35:03 PM PST 24
Peak memory 251084 kb
Host smart-08bf0d61-8c64-4cb3-8416-5db8f32db7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806774206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2806774206
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3051947749
Short name T1336
Test name
Test status
Simulation time 869044918 ps
CPU time 15.05 seconds
Started Jan 17 03:34:27 PM PST 24
Finished Jan 17 03:34:43 PM PST 24
Peak memory 238436 kb
Host smart-0a3e042a-c08a-4d47-a5b5-9498644dc6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051947749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3051947749
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.4074381214
Short name T279
Test name
Test status
Simulation time 4030343287 ps
CPU time 15.27 seconds
Started Jan 17 03:34:15 PM PST 24
Finished Jan 17 03:34:37 PM PST 24
Peak memory 237336 kb
Host smart-aa2d6985-3363-4d57-b0fa-939ae34195fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074381214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.4074381214
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_intr.518401592
Short name T741
Test name
Test status
Simulation time 2521549158 ps
CPU time 10.72 seconds
Started Jan 17 03:34:23 PM PST 24
Finished Jan 17 03:34:34 PM PST 24
Peak memory 223748 kb
Host smart-2336b5b6-cbf5-4b36-9a8d-74984cc1a0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518401592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intr.518401592
Directory /workspace/30.spi_device_intr/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2429786913
Short name T223
Test name
Test status
Simulation time 4012260114 ps
CPU time 12.15 seconds
Started Jan 17 03:34:14 PM PST 24
Finished Jan 17 03:34:34 PM PST 24
Peak memory 256772 kb
Host smart-257152ed-14c1-41c2-afc5-fb684716fa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429786913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2429786913
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3942585004
Short name T1383
Test name
Test status
Simulation time 343161550 ps
CPU time 5.09 seconds
Started Jan 17 03:34:11 PM PST 24
Finished Jan 17 03:34:19 PM PST 24
Peak memory 238512 kb
Host smart-50c0fe60-0693-46ad-a800-6b05e17e5b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942585004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3942585004
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.386659247
Short name T904
Test name
Test status
Simulation time 6900061237 ps
CPU time 9.05 seconds
Started Jan 17 03:34:09 PM PST 24
Finished Jan 17 03:34:20 PM PST 24
Peak memory 249808 kb
Host smart-36ada211-e2cb-490a-b8fe-9977be85c4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386659247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.386659247
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_perf.2337124439
Short name T611
Test name
Test status
Simulation time 33546198283 ps
CPU time 193.94 seconds
Started Jan 17 03:34:26 PM PST 24
Finished Jan 17 03:37:40 PM PST 24
Peak memory 250060 kb
Host smart-5d5bc00f-9ea2-402f-86ea-8f8d0ee03161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337124439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_perf.2337124439
Directory /workspace/30.spi_device_perf/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.433324221
Short name T1615
Test name
Test status
Simulation time 880503552 ps
CPU time 5.7 seconds
Started Jan 17 03:34:24 PM PST 24
Finished Jan 17 03:34:30 PM PST 24
Peak memory 234860 kb
Host smart-3c5e5b82-a809-4dd6-951c-606c6b59db0b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=433324221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.433324221
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_rx_async_fifo_reset.1520440433
Short name T1440
Test name
Test status
Simulation time 37494579 ps
CPU time 0.84 seconds
Started Jan 17 03:34:10 PM PST 24
Finished Jan 17 03:34:14 PM PST 24
Peak memory 208796 kb
Host smart-ba479348-ce8e-4aa5-be76-ebd783c8e4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520440433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_rx_async_fifo_reset.1520440433
Directory /workspace/30.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/30.spi_device_rx_timeout.3387164700
Short name T1771
Test name
Test status
Simulation time 918136808 ps
CPU time 6.71 seconds
Started Jan 17 03:34:21 PM PST 24
Finished Jan 17 03:34:29 PM PST 24
Peak memory 217032 kb
Host smart-ecb690d3-8827-46ee-b8c1-78c588f1d8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387164700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_rx_timeout.3387164700
Directory /workspace/30.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/30.spi_device_smoke.201755663
Short name T1517
Test name
Test status
Simulation time 40317973 ps
CPU time 1.08 seconds
Started Jan 17 03:34:09 PM PST 24
Finished Jan 17 03:34:12 PM PST 24
Peak memory 208508 kb
Host smart-48dc1f26-0364-4b29-8548-07564abbd892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201755663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_smoke.201755663
Directory /workspace/30.spi_device_smoke/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1685971967
Short name T1341
Test name
Test status
Simulation time 788057435 ps
CPU time 8 seconds
Started Jan 17 03:34:26 PM PST 24
Finished Jan 17 03:34:35 PM PST 24
Peak memory 217336 kb
Host smart-42347aa3-68be-4d71-98a0-a044b127e222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685971967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1685971967
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3828328343
Short name T1748
Test name
Test status
Simulation time 14915526656 ps
CPU time 19.75 seconds
Started Jan 17 03:34:19 PM PST 24
Finished Jan 17 03:34:42 PM PST 24
Peak memory 217172 kb
Host smart-4b2850a3-577c-4dca-8408-a032d6fc87c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828328343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3828328343
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.576543643
Short name T1507
Test name
Test status
Simulation time 1599454349 ps
CPU time 4.46 seconds
Started Jan 17 03:34:13 PM PST 24
Finished Jan 17 03:34:20 PM PST 24
Peak memory 216916 kb
Host smart-7d3716c8-c32b-434e-8916-7fe335ba0165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576543643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.576543643
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1307824951
Short name T505
Test name
Test status
Simulation time 139640523 ps
CPU time 1 seconds
Started Jan 17 03:34:10 PM PST 24
Finished Jan 17 03:34:14 PM PST 24
Peak memory 207252 kb
Host smart-6cecd352-73e9-416e-b378-b4804d4090de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307824951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1307824951
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_tx_async_fifo_reset.900218588
Short name T664
Test name
Test status
Simulation time 53811004 ps
CPU time 0.82 seconds
Started Jan 17 03:34:14 PM PST 24
Finished Jan 17 03:34:22 PM PST 24
Peak memory 208756 kb
Host smart-1172bca8-ce05-4410-b3c5-b5fed3de76d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900218588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tx_async_fifo_reset.900218588
Directory /workspace/30.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/30.spi_device_txrx.292430894
Short name T1036
Test name
Test status
Simulation time 199808924873 ps
CPU time 633.49 seconds
Started Jan 17 03:34:10 PM PST 24
Finished Jan 17 03:44:45 PM PST 24
Peak memory 306324 kb
Host smart-8f4fa20b-5e64-4397-bf03-d26eb870cd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292430894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_txrx.292430894
Directory /workspace/30.spi_device_txrx/latest

Test location /workspace/coverage/default/30.spi_device_upload.2173818414
Short name T1325
Test name
Test status
Simulation time 6014725100 ps
CPU time 9.34 seconds
Started Jan 17 03:34:11 PM PST 24
Finished Jan 17 03:34:23 PM PST 24
Peak memory 250568 kb
Host smart-1e506ad7-8771-4658-bc55-416151105afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173818414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2173818414
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_abort.753000789
Short name T764
Test name
Test status
Simulation time 42084249 ps
CPU time 0.8 seconds
Started Jan 17 03:34:24 PM PST 24
Finished Jan 17 03:34:26 PM PST 24
Peak memory 207040 kb
Host smart-b7dded54-e2b4-4511-82b7-d35add65aa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753000789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_abort.753000789
Directory /workspace/31.spi_device_abort/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1351034356
Short name T1109
Test name
Test status
Simulation time 29840445 ps
CPU time 0.79 seconds
Started Jan 17 03:34:32 PM PST 24
Finished Jan 17 03:34:33 PM PST 24
Peak memory 206764 kb
Host smart-6b1672e0-2fec-43f9-aded-0504b2b784ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351034356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1351034356
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_bit_transfer.1249265301
Short name T669
Test name
Test status
Simulation time 142237717 ps
CPU time 2.91 seconds
Started Jan 17 03:34:27 PM PST 24
Finished Jan 17 03:34:30 PM PST 24
Peak memory 217148 kb
Host smart-7a3363bc-0b0d-48f5-9c44-c56d3546c574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249265301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_bit_transfer.1249265301
Directory /workspace/31.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.152359180
Short name T1066
Test name
Test status
Simulation time 295434274 ps
CPU time 3.11 seconds
Started Jan 17 03:34:33 PM PST 24
Finished Jan 17 03:34:38 PM PST 24
Peak memory 233636 kb
Host smart-ff9c6347-9e85-4ec0-b542-d035a5982386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152359180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.152359180
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3722229351
Short name T1490
Test name
Test status
Simulation time 33264192 ps
CPU time 0.88 seconds
Started Jan 17 03:34:26 PM PST 24
Finished Jan 17 03:34:28 PM PST 24
Peak memory 207964 kb
Host smart-e081562d-ff9f-494e-806d-fe57136d4d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722229351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3722229351
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_dummy_item_extra_dly.1970104574
Short name T1208
Test name
Test status
Simulation time 52719927349 ps
CPU time 1030.77 seconds
Started Jan 17 03:34:25 PM PST 24
Finished Jan 17 03:51:37 PM PST 24
Peak memory 266412 kb
Host smart-5044ca0a-501d-49fc-8915-98ff36f936d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970104574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_dummy_item_extra_dly.1970104574
Directory /workspace/31.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/31.spi_device_extreme_fifo_size.2865282779
Short name T613
Test name
Test status
Simulation time 137488592582 ps
CPU time 1368.31 seconds
Started Jan 17 03:34:27 PM PST 24
Finished Jan 17 03:57:16 PM PST 24
Peak memory 217216 kb
Host smart-306de506-3cc8-4782-892f-662c999d234e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865282779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_extreme_fifo_size.2865282779
Directory /workspace/31.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/31.spi_device_fifo_full.2057198082
Short name T683
Test name
Test status
Simulation time 14272261597 ps
CPU time 346.29 seconds
Started Jan 17 03:34:13 PM PST 24
Finished Jan 17 03:40:00 PM PST 24
Peak memory 281964 kb
Host smart-f0bb2a78-9f4e-4bac-aa9d-ef96980407c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057198082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_fifo_full.2057198082
Directory /workspace/31.spi_device_fifo_full/latest

Test location /workspace/coverage/default/31.spi_device_fifo_underflow_overflow.2121888461
Short name T1088
Test name
Test status
Simulation time 459033574293 ps
CPU time 259.16 seconds
Started Jan 17 03:34:19 PM PST 24
Finished Jan 17 03:38:41 PM PST 24
Peak memory 331932 kb
Host smart-971b9a3d-6f8a-401c-950b-1f8c1017e6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121888461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_fifo_underflow_overf
low.2121888461
Directory /workspace/31.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2836076133
Short name T1168
Test name
Test status
Simulation time 106458177343 ps
CPU time 138.3 seconds
Started Jan 17 03:34:31 PM PST 24
Finished Jan 17 03:36:50 PM PST 24
Peak memory 256888 kb
Host smart-032346ae-0fa4-43ba-9193-c9a00c18c2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836076133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2836076133
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2617428124
Short name T1156
Test name
Test status
Simulation time 6572441971 ps
CPU time 62.32 seconds
Started Jan 17 03:34:30 PM PST 24
Finished Jan 17 03:35:33 PM PST 24
Peak memory 241888 kb
Host smart-256bb99d-b1a1-4f80-939b-1211a6edfc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617428124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2617428124
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3814882743
Short name T213
Test name
Test status
Simulation time 16544080551 ps
CPU time 50.01 seconds
Started Jan 17 03:34:29 PM PST 24
Finished Jan 17 03:35:20 PM PST 24
Peak memory 250152 kb
Host smart-6f09283b-8430-4f3c-aa17-390ba5ce0520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814882743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3814882743
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2131931482
Short name T951
Test name
Test status
Simulation time 5791598118 ps
CPU time 29.41 seconds
Started Jan 17 03:34:29 PM PST 24
Finished Jan 17 03:34:59 PM PST 24
Peak memory 234748 kb
Host smart-4ec57210-691b-49e8-8755-f960f264c1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131931482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2131931482
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1822684563
Short name T237
Test name
Test status
Simulation time 1717276314 ps
CPU time 4.59 seconds
Started Jan 17 03:34:27 PM PST 24
Finished Jan 17 03:34:32 PM PST 24
Peak memory 225384 kb
Host smart-0ff1f470-7414-4c7c-9cfe-1bba00df5d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822684563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1822684563
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_intr.2918133757
Short name T1187
Test name
Test status
Simulation time 4663469587 ps
CPU time 28.32 seconds
Started Jan 17 03:34:25 PM PST 24
Finished Jan 17 03:34:54 PM PST 24
Peak memory 232772 kb
Host smart-3e215ee2-0e52-434c-8aa0-26ca94165137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918133757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intr.2918133757
Directory /workspace/31.spi_device_intr/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.681469606
Short name T233
Test name
Test status
Simulation time 1390435693 ps
CPU time 15.96 seconds
Started Jan 17 03:34:23 PM PST 24
Finished Jan 17 03:34:40 PM PST 24
Peak memory 256672 kb
Host smart-d893687f-0ae1-4696-a026-452fbbcc2ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681469606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.681469606
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3872821831
Short name T1667
Test name
Test status
Simulation time 1889607578 ps
CPU time 12.95 seconds
Started Jan 17 03:34:27 PM PST 24
Finished Jan 17 03:34:40 PM PST 24
Peak memory 241680 kb
Host smart-e6f05c94-be1d-458c-978d-2a1e8aa5a8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872821831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3872821831
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1547271317
Short name T1367
Test name
Test status
Simulation time 2880073583 ps
CPU time 9.86 seconds
Started Jan 17 03:34:34 PM PST 24
Finished Jan 17 03:34:47 PM PST 24
Peak memory 219192 kb
Host smart-6d87da63-7b59-4b98-b79d-119e5f13352b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547271317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1547271317
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_perf.1182090907
Short name T668
Test name
Test status
Simulation time 185394465434 ps
CPU time 588.86 seconds
Started Jan 17 03:34:25 PM PST 24
Finished Jan 17 03:44:15 PM PST 24
Peak memory 259648 kb
Host smart-870a5999-104a-4392-8945-f2c4aa10ecd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182090907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_perf.1182090907
Directory /workspace/31.spi_device_perf/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3087071435
Short name T1192
Test name
Test status
Simulation time 607208773 ps
CPU time 4.27 seconds
Started Jan 17 03:34:31 PM PST 24
Finished Jan 17 03:34:36 PM PST 24
Peak memory 220312 kb
Host smart-5b399e00-08a0-4cb7-9a04-42c3b51d0d03
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3087071435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3087071435
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_rx_async_fifo_reset.2928361632
Short name T15
Test name
Test status
Simulation time 54515606 ps
CPU time 0.85 seconds
Started Jan 17 03:34:25 PM PST 24
Finished Jan 17 03:34:27 PM PST 24
Peak memory 208784 kb
Host smart-1444670b-e28b-4aba-9865-da6a95485b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928361632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_rx_async_fifo_reset.2928361632
Directory /workspace/31.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/31.spi_device_rx_timeout.3994178333
Short name T806
Test name
Test status
Simulation time 2016370435 ps
CPU time 5.4 seconds
Started Jan 17 03:34:28 PM PST 24
Finished Jan 17 03:34:34 PM PST 24
Peak memory 217124 kb
Host smart-63d11e1d-8044-499c-b7f9-01baf75b6a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994178333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_rx_timeout.3994178333
Directory /workspace/31.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/31.spi_device_smoke.444782704
Short name T1481
Test name
Test status
Simulation time 30300818 ps
CPU time 1.02 seconds
Started Jan 17 03:34:26 PM PST 24
Finished Jan 17 03:34:28 PM PST 24
Peak memory 208776 kb
Host smart-c6034216-da53-4715-a3c8-425c4b025a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444782704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_smoke.444782704
Directory /workspace/31.spi_device_smoke/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.321269867
Short name T1003
Test name
Test status
Simulation time 11422039408 ps
CPU time 43.79 seconds
Started Jan 17 03:34:26 PM PST 24
Finished Jan 17 03:35:11 PM PST 24
Peak memory 217252 kb
Host smart-41907861-b023-491e-b52e-ad9bcaa40fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321269867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.321269867
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3811508376
Short name T546
Test name
Test status
Simulation time 1524339141 ps
CPU time 8.91 seconds
Started Jan 17 03:34:23 PM PST 24
Finished Jan 17 03:34:33 PM PST 24
Peak memory 217136 kb
Host smart-f72a7f4f-7df8-44a4-b9d6-2ab09627fc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811508376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3811508376
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2580179099
Short name T680
Test name
Test status
Simulation time 22589579 ps
CPU time 1.02 seconds
Started Jan 17 03:34:25 PM PST 24
Finished Jan 17 03:34:27 PM PST 24
Peak memory 208480 kb
Host smart-a9def2e4-259a-4c11-8104-e1014dc6b74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580179099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2580179099
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.259523005
Short name T103
Test name
Test status
Simulation time 46645339 ps
CPU time 0.86 seconds
Started Jan 17 03:34:24 PM PST 24
Finished Jan 17 03:34:26 PM PST 24
Peak memory 207240 kb
Host smart-9be7cb9c-6b9c-4ed1-b0b2-61d0d0513431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259523005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.259523005
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_tx_async_fifo_reset.1869218281
Short name T1530
Test name
Test status
Simulation time 52094998 ps
CPU time 0.75 seconds
Started Jan 17 03:34:27 PM PST 24
Finished Jan 17 03:34:29 PM PST 24
Peak memory 208724 kb
Host smart-1484a833-0fe0-4b65-a4b4-cf74fd632d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869218281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tx_async_fifo_reset.1869218281
Directory /workspace/31.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/31.spi_device_txrx.3521190437
Short name T1135
Test name
Test status
Simulation time 44715977855 ps
CPU time 175.1 seconds
Started Jan 17 03:34:26 PM PST 24
Finished Jan 17 03:37:22 PM PST 24
Peak memory 266008 kb
Host smart-7b4c7aca-0cf9-4a0d-bffa-2968de84a97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521190437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_txrx.3521190437
Directory /workspace/31.spi_device_txrx/latest

Test location /workspace/coverage/default/31.spi_device_upload.310484803
Short name T1714
Test name
Test status
Simulation time 991099470 ps
CPU time 6.11 seconds
Started Jan 17 03:34:34 PM PST 24
Finished Jan 17 03:34:43 PM PST 24
Peak memory 218816 kb
Host smart-879d76ed-5c59-429c-8464-07221fe1bf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310484803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.310484803
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_abort.3564120496
Short name T1434
Test name
Test status
Simulation time 16771353 ps
CPU time 0.79 seconds
Started Jan 17 03:34:41 PM PST 24
Finished Jan 17 03:34:47 PM PST 24
Peak memory 206948 kb
Host smart-117f8661-f9ad-4af8-abf8-b0410e82a185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564120496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_abort.3564120496
Directory /workspace/32.spi_device_abort/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.749806712
Short name T857
Test name
Test status
Simulation time 20870841 ps
CPU time 0.73 seconds
Started Jan 17 03:34:45 PM PST 24
Finished Jan 17 03:34:47 PM PST 24
Peak memory 206780 kb
Host smart-01adbee9-67ea-42ea-a500-6d3df155ed8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749806712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.749806712
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_bit_transfer.2456796264
Short name T1209
Test name
Test status
Simulation time 1292649740 ps
CPU time 3.16 seconds
Started Jan 17 03:34:36 PM PST 24
Finished Jan 17 03:34:41 PM PST 24
Peak memory 217044 kb
Host smart-36935f9e-124f-452f-9047-460fee5fe4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456796264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_bit_transfer.2456796264
Directory /workspace/32.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/32.spi_device_byte_transfer.596268941
Short name T1240
Test name
Test status
Simulation time 65962038 ps
CPU time 2.56 seconds
Started Jan 17 03:34:31 PM PST 24
Finished Jan 17 03:34:34 PM PST 24
Peak memory 217116 kb
Host smart-ef289de6-f6be-4cf7-b79e-83efe8539111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596268941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_byte_transfer.596268941
Directory /workspace/32.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2230908027
Short name T559
Test name
Test status
Simulation time 89533626 ps
CPU time 2.57 seconds
Started Jan 17 03:34:46 PM PST 24
Finished Jan 17 03:34:49 PM PST 24
Peak memory 218708 kb
Host smart-23ace7b7-ea63-4196-b7e2-73cc7af09487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230908027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2230908027
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1323393370
Short name T1095
Test name
Test status
Simulation time 32475702 ps
CPU time 0.82 seconds
Started Jan 17 03:34:36 PM PST 24
Finished Jan 17 03:34:40 PM PST 24
Peak memory 208020 kb
Host smart-ec581844-df54-4421-84d7-25b6589ad790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323393370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1323393370
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_dummy_item_extra_dly.3538387054
Short name T1456
Test name
Test status
Simulation time 41769502189 ps
CPU time 569.59 seconds
Started Jan 17 03:34:35 PM PST 24
Finished Jan 17 03:44:08 PM PST 24
Peak memory 295664 kb
Host smart-92fd678d-730d-4ec8-9cb6-26aa41db8965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538387054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_dummy_item_extra_dly.3538387054
Directory /workspace/32.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/32.spi_device_extreme_fifo_size.2428316033
Short name T56
Test name
Test status
Simulation time 56582199071 ps
CPU time 892.59 seconds
Started Jan 17 03:34:33 PM PST 24
Finished Jan 17 03:49:26 PM PST 24
Peak memory 219304 kb
Host smart-da8ebbef-d3e3-4663-9481-6d0fe652fbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428316033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_extreme_fifo_size.2428316033
Directory /workspace/32.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/32.spi_device_fifo_full.3518626004
Short name T1629
Test name
Test status
Simulation time 14068063830 ps
CPU time 433.84 seconds
Started Jan 17 03:34:33 PM PST 24
Finished Jan 17 03:41:47 PM PST 24
Peak memory 273924 kb
Host smart-f23d8cbd-64f1-442f-9e8b-947868f65c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518626004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_fifo_full.3518626004
Directory /workspace/32.spi_device_fifo_full/latest

Test location /workspace/coverage/default/32.spi_device_fifo_underflow_overflow.1106056669
Short name T699
Test name
Test status
Simulation time 53475928763 ps
CPU time 303.88 seconds
Started Jan 17 03:34:35 PM PST 24
Finished Jan 17 03:39:41 PM PST 24
Peak memory 382992 kb
Host smart-65f2b1fe-c90f-48e1-8f35-2554ee124fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106056669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_fifo_underflow_overf
low.1106056669
Directory /workspace/32.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2398586064
Short name T26
Test name
Test status
Simulation time 48072360591 ps
CPU time 140.8 seconds
Started Jan 17 03:34:48 PM PST 24
Finished Jan 17 03:37:09 PM PST 24
Peak memory 265888 kb
Host smart-12d5dbe2-db46-4ab3-8586-3eb9f61a8847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398586064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2398586064
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3440035306
Short name T302
Test name
Test status
Simulation time 84842387428 ps
CPU time 416.05 seconds
Started Jan 17 03:34:46 PM PST 24
Finished Jan 17 03:41:43 PM PST 24
Peak memory 283380 kb
Host smart-2da4900e-9153-4054-9940-6ea77520fd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440035306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3440035306
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1779372157
Short name T215
Test name
Test status
Simulation time 14517975560 ps
CPU time 124.09 seconds
Started Jan 17 03:34:48 PM PST 24
Finished Jan 17 03:36:53 PM PST 24
Peak memory 266524 kb
Host smart-eb0403cd-34e4-49fc-ae61-27aa18ff31d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779372157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1779372157
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2966704906
Short name T1106
Test name
Test status
Simulation time 268230256 ps
CPU time 7.81 seconds
Started Jan 17 03:34:47 PM PST 24
Finished Jan 17 03:34:56 PM PST 24
Peak memory 250064 kb
Host smart-c16aa9b2-edcd-463c-ac0a-b504c03acfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966704906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2966704906
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.59757435
Short name T1223
Test name
Test status
Simulation time 663627559 ps
CPU time 6.73 seconds
Started Jan 17 03:34:41 PM PST 24
Finished Jan 17 03:34:53 PM PST 24
Peak memory 220732 kb
Host smart-63e7e157-9570-4fee-92f7-680bcb9f89cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59757435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.59757435
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_intr.2310784665
Short name T1317
Test name
Test status
Simulation time 36139855826 ps
CPU time 50.5 seconds
Started Jan 17 03:34:36 PM PST 24
Finished Jan 17 03:35:29 PM PST 24
Peak memory 232416 kb
Host smart-cf9c2bc6-f9be-4000-826a-0fca405f7502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310784665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intr.2310784665
Directory /workspace/32.spi_device_intr/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1914960967
Short name T243
Test name
Test status
Simulation time 1737223704 ps
CPU time 4.69 seconds
Started Jan 17 03:34:41 PM PST 24
Finished Jan 17 03:34:51 PM PST 24
Peak memory 238364 kb
Host smart-59d27332-2f47-47fa-8e7c-1972f1f74838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914960967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1914960967
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1833160286
Short name T1117
Test name
Test status
Simulation time 6748490335 ps
CPU time 24.74 seconds
Started Jan 17 03:34:40 PM PST 24
Finished Jan 17 03:35:11 PM PST 24
Peak memory 249956 kb
Host smart-e8f81063-d421-4dd1-8ef6-13b008808fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833160286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1833160286
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1119721709
Short name T892
Test name
Test status
Simulation time 719253383 ps
CPU time 3.51 seconds
Started Jan 17 03:34:36 PM PST 24
Finished Jan 17 03:34:42 PM PST 24
Peak memory 238540 kb
Host smart-088ed4f4-8362-4905-8925-effab959ecf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119721709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1119721709
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_perf.347261115
Short name T655
Test name
Test status
Simulation time 41090108841 ps
CPU time 158.11 seconds
Started Jan 17 03:34:36 PM PST 24
Finished Jan 17 03:37:17 PM PST 24
Peak memory 248788 kb
Host smart-d8f532f7-d91c-4de9-a5de-2d3fe759227d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347261115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_perf.347261115
Directory /workspace/32.spi_device_perf/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3675205865
Short name T928
Test name
Test status
Simulation time 153366308 ps
CPU time 3.55 seconds
Started Jan 17 03:34:45 PM PST 24
Finished Jan 17 03:34:50 PM PST 24
Peak memory 218872 kb
Host smart-e39fce9d-c173-4a31-9115-d50364a902cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3675205865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3675205865
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_rx_async_fifo_reset.118298294
Short name T1162
Test name
Test status
Simulation time 18395861 ps
CPU time 0.9 seconds
Started Jan 17 03:34:41 PM PST 24
Finished Jan 17 03:34:47 PM PST 24
Peak memory 208792 kb
Host smart-b5a2d7e9-3ded-471e-9721-8af3bc1bec4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118298294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_rx_async_fifo_reset.118298294
Directory /workspace/32.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/32.spi_device_rx_timeout.1937108077
Short name T718
Test name
Test status
Simulation time 690520437 ps
CPU time 5.93 seconds
Started Jan 17 03:34:33 PM PST 24
Finished Jan 17 03:34:39 PM PST 24
Peak memory 217092 kb
Host smart-85fc681b-de5b-4b74-a34a-073cae2abaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937108077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_rx_timeout.1937108077
Directory /workspace/32.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/32.spi_device_smoke.362289390
Short name T638
Test name
Test status
Simulation time 77136282 ps
CPU time 1.18 seconds
Started Jan 17 03:34:31 PM PST 24
Finished Jan 17 03:34:33 PM PST 24
Peak memory 217080 kb
Host smart-e32bba7d-484c-4a12-9eea-ec6ee1bc83db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362289390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_smoke.362289390
Directory /workspace/32.spi_device_smoke/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3855707290
Short name T106
Test name
Test status
Simulation time 1167338266 ps
CPU time 2.89 seconds
Started Jan 17 03:34:36 PM PST 24
Finished Jan 17 03:34:41 PM PST 24
Peak memory 217188 kb
Host smart-972ba1d4-5f79-4175-a569-427a57e510d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855707290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3855707290
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3095991809
Short name T631
Test name
Test status
Simulation time 1594437058 ps
CPU time 1.77 seconds
Started Jan 17 03:34:36 PM PST 24
Finished Jan 17 03:34:41 PM PST 24
Peak memory 208736 kb
Host smart-16bc2b55-141b-453a-b204-d2de3d6b79e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095991809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3095991809
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3821011555
Short name T4
Test name
Test status
Simulation time 64754362 ps
CPU time 1.95 seconds
Started Jan 17 03:34:36 PM PST 24
Finished Jan 17 03:34:41 PM PST 24
Peak memory 217124 kb
Host smart-48571263-9f47-406e-accf-1da1fdf283fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821011555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3821011555
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2478249734
Short name T1328
Test name
Test status
Simulation time 401566615 ps
CPU time 1.02 seconds
Started Jan 17 03:34:39 PM PST 24
Finished Jan 17 03:34:41 PM PST 24
Peak memory 208360 kb
Host smart-68b44f45-4878-4075-910c-562e7485f02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478249734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2478249734
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_tx_async_fifo_reset.693156568
Short name T1495
Test name
Test status
Simulation time 17089544 ps
CPU time 0.79 seconds
Started Jan 17 03:34:42 PM PST 24
Finished Jan 17 03:34:47 PM PST 24
Peak memory 208744 kb
Host smart-03340cd2-f21f-4058-a04b-bb62d2952402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693156568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tx_async_fifo_reset.693156568
Directory /workspace/32.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/32.spi_device_txrx.1608170180
Short name T1184
Test name
Test status
Simulation time 20379811561 ps
CPU time 217.56 seconds
Started Jan 17 03:34:28 PM PST 24
Finished Jan 17 03:38:06 PM PST 24
Peak memory 248284 kb
Host smart-3305488f-93b0-40dd-9c4d-04009ebb4e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608170180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_txrx.1608170180
Directory /workspace/32.spi_device_txrx/latest

Test location /workspace/coverage/default/32.spi_device_upload.3925668538
Short name T278
Test name
Test status
Simulation time 293503560 ps
CPU time 7.26 seconds
Started Jan 17 03:34:39 PM PST 24
Finished Jan 17 03:34:47 PM PST 24
Peak memory 246440 kb
Host smart-cdcdcbaf-99eb-45fb-84ba-6719f3786b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925668538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3925668538
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_abort.4180511963
Short name T869
Test name
Test status
Simulation time 37010550 ps
CPU time 0.77 seconds
Started Jan 17 03:34:53 PM PST 24
Finished Jan 17 03:34:56 PM PST 24
Peak memory 207016 kb
Host smart-71561915-9c40-4fc5-ad47-2055a6a2c4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180511963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_abort.4180511963
Directory /workspace/33.spi_device_abort/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.926079158
Short name T1389
Test name
Test status
Simulation time 61504009 ps
CPU time 0.76 seconds
Started Jan 17 03:35:03 PM PST 24
Finished Jan 17 03:35:04 PM PST 24
Peak memory 206776 kb
Host smart-281b123c-91a9-4454-9cbe-e12e4d7892c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926079158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.926079158
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_bit_transfer.1152509563
Short name T743
Test name
Test status
Simulation time 356779563 ps
CPU time 2.22 seconds
Started Jan 17 03:34:50 PM PST 24
Finished Jan 17 03:34:53 PM PST 24
Peak memory 217140 kb
Host smart-37f2e38f-f817-49b7-ab43-5a8cb7686e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152509563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_bit_transfer.1152509563
Directory /workspace/33.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/33.spi_device_byte_transfer.322775452
Short name T555
Test name
Test status
Simulation time 1460232636 ps
CPU time 3.74 seconds
Started Jan 17 03:34:50 PM PST 24
Finished Jan 17 03:34:54 PM PST 24
Peak memory 217124 kb
Host smart-d6a43f61-6a6b-4053-b77b-9804157d20cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322775452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_byte_transfer.322775452
Directory /workspace/33.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3443339717
Short name T1048
Test name
Test status
Simulation time 963990731 ps
CPU time 5.67 seconds
Started Jan 17 03:34:50 PM PST 24
Finished Jan 17 03:34:57 PM PST 24
Peak memory 238996 kb
Host smart-7de191ba-e28f-42d6-8d25-d49821ba7ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443339717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3443339717
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3927626335
Short name T475
Test name
Test status
Simulation time 46952646 ps
CPU time 0.79 seconds
Started Jan 17 03:34:46 PM PST 24
Finished Jan 17 03:34:48 PM PST 24
Peak memory 207932 kb
Host smart-0ceaf983-96f0-40d5-b545-6b9438d202f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927626335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3927626335
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_dummy_item_extra_dly.3039657341
Short name T1018
Test name
Test status
Simulation time 125289440840 ps
CPU time 237.39 seconds
Started Jan 17 03:34:49 PM PST 24
Finished Jan 17 03:38:47 PM PST 24
Peak memory 265188 kb
Host smart-9ebc6dcf-50f0-4f12-ac85-df1cd95d3b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039657341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_dummy_item_extra_dly.3039657341
Directory /workspace/33.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/33.spi_device_extreme_fifo_size.3921246001
Short name T265
Test name
Test status
Simulation time 24452222155 ps
CPU time 35.63 seconds
Started Jan 17 03:34:42 PM PST 24
Finished Jan 17 03:35:22 PM PST 24
Peak memory 232588 kb
Host smart-47bd0e5a-8512-461d-af37-1f777852a969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921246001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_extreme_fifo_size.3921246001
Directory /workspace/33.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/33.spi_device_fifo_full.2790270021
Short name T1740
Test name
Test status
Simulation time 51886231545 ps
CPU time 3076.41 seconds
Started Jan 17 03:34:45 PM PST 24
Finished Jan 17 04:26:03 PM PST 24
Peak memory 266800 kb
Host smart-ff8f3118-9a20-479b-af55-c0afe55e5783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790270021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_fifo_full.2790270021
Directory /workspace/33.spi_device_fifo_full/latest

Test location /workspace/coverage/default/33.spi_device_fifo_underflow_overflow.2723758745
Short name T1705
Test name
Test status
Simulation time 78783228513 ps
CPU time 276.92 seconds
Started Jan 17 03:34:48 PM PST 24
Finished Jan 17 03:39:25 PM PST 24
Peak memory 458144 kb
Host smart-f08a9287-dca3-452a-913c-258c054d84a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723758745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_fifo_underflow_overf
low.2723758745
Directory /workspace/33.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2799077599
Short name T319
Test name
Test status
Simulation time 143208687463 ps
CPU time 115.2 seconds
Started Jan 17 03:34:48 PM PST 24
Finished Jan 17 03:36:44 PM PST 24
Peak memory 265880 kb
Host smart-ded25c92-f19a-4209-95e0-18d909d9b9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799077599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2799077599
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.100011237
Short name T328
Test name
Test status
Simulation time 128039173915 ps
CPU time 409.59 seconds
Started Jan 17 03:34:51 PM PST 24
Finished Jan 17 03:41:42 PM PST 24
Peak memory 273412 kb
Host smart-72a0253e-d20e-414b-9bad-ea79188d89ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100011237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.100011237
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3734022157
Short name T1478
Test name
Test status
Simulation time 1158028849 ps
CPU time 9.45 seconds
Started Jan 17 03:34:53 PM PST 24
Finished Jan 17 03:35:04 PM PST 24
Peak memory 233300 kb
Host smart-e31e3eb1-a9ec-48d5-b3b5-3eaffee8a65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734022157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3734022157
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1236455424
Short name T861
Test name
Test status
Simulation time 26993742870 ps
CPU time 15.36 seconds
Started Jan 17 03:34:56 PM PST 24
Finished Jan 17 03:35:13 PM PST 24
Peak memory 221500 kb
Host smart-7428aa9e-7cb7-40b8-a8a9-a7360e5bcb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236455424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1236455424
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_intr.4101972701
Short name T765
Test name
Test status
Simulation time 29669237532 ps
CPU time 26.03 seconds
Started Jan 17 03:34:52 PM PST 24
Finished Jan 17 03:35:19 PM PST 24
Peak memory 221328 kb
Host smart-8cb9c0d3-44d3-40e0-a393-d28e15475ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101972701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intr.4101972701
Directory /workspace/33.spi_device_intr/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.4100916683
Short name T1482
Test name
Test status
Simulation time 7595750946 ps
CPU time 26.58 seconds
Started Jan 17 03:34:53 PM PST 24
Finished Jan 17 03:35:21 PM PST 24
Peak memory 247824 kb
Host smart-9999fda7-44ba-468b-bf9c-23e03aa7a9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100916683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.4100916683
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.119599589
Short name T1340
Test name
Test status
Simulation time 6809859895 ps
CPU time 21.45 seconds
Started Jan 17 03:34:50 PM PST 24
Finished Jan 17 03:35:12 PM PST 24
Peak memory 239384 kb
Host smart-30f3f694-f623-409d-b020-07c2b1a33223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119599589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.119599589
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3626531916
Short name T1028
Test name
Test status
Simulation time 134190742092 ps
CPU time 67.65 seconds
Started Jan 17 03:34:48 PM PST 24
Finished Jan 17 03:35:56 PM PST 24
Peak memory 257644 kb
Host smart-e48d74b8-254c-46fd-b384-096bf21e1828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626531916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3626531916
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_perf.2119945549
Short name T1040
Test name
Test status
Simulation time 81817406176 ps
CPU time 1316.85 seconds
Started Jan 17 03:34:46 PM PST 24
Finished Jan 17 03:56:44 PM PST 24
Peak memory 257004 kb
Host smart-5432258f-813f-4619-bfe2-97654de9c5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119945549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_perf.2119945549
Directory /workspace/33.spi_device_perf/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.597208811
Short name T38
Test name
Test status
Simulation time 323868619 ps
CPU time 4.3 seconds
Started Jan 17 03:34:50 PM PST 24
Finished Jan 17 03:34:55 PM PST 24
Peak memory 236208 kb
Host smart-68ea9574-3947-42fc-a7c6-85fc77bf614c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=597208811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.597208811
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_rx_async_fifo_reset.2763537418
Short name T1590
Test name
Test status
Simulation time 183946619 ps
CPU time 0.9 seconds
Started Jan 17 03:34:49 PM PST 24
Finished Jan 17 03:34:51 PM PST 24
Peak memory 208764 kb
Host smart-d607863d-8067-45fd-bc33-2a599c917511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763537418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_rx_async_fifo_reset.2763537418
Directory /workspace/33.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/33.spi_device_rx_timeout.2717723603
Short name T1540
Test name
Test status
Simulation time 3048737457 ps
CPU time 4.77 seconds
Started Jan 17 03:34:47 PM PST 24
Finished Jan 17 03:34:53 PM PST 24
Peak memory 217180 kb
Host smart-84493fdd-67bb-4b1e-a1d9-8477fe932551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717723603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_rx_timeout.2717723603
Directory /workspace/33.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/33.spi_device_smoke.2984313720
Short name T1203
Test name
Test status
Simulation time 76551936 ps
CPU time 1.09 seconds
Started Jan 17 03:34:48 PM PST 24
Finished Jan 17 03:34:50 PM PST 24
Peak memory 216944 kb
Host smart-0b2c00df-722a-427b-9fbd-2f031b1d7188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984313720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_smoke.2984313720
Directory /workspace/33.spi_device_smoke/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3811805292
Short name T334
Test name
Test status
Simulation time 22100412248 ps
CPU time 185.21 seconds
Started Jan 17 03:34:57 PM PST 24
Finished Jan 17 03:38:04 PM PST 24
Peak memory 282860 kb
Host smart-e6b1dd86-e99d-4e24-abd9-39626dddeef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811805292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3811805292
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.587084693
Short name T727
Test name
Test status
Simulation time 8679087222 ps
CPU time 63.59 seconds
Started Jan 17 03:34:54 PM PST 24
Finished Jan 17 03:36:00 PM PST 24
Peak memory 217296 kb
Host smart-7c5e7c60-54d6-459e-bcaf-4e0d22a0ff17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587084693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.587084693
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1441316298
Short name T1243
Test name
Test status
Simulation time 4614823120 ps
CPU time 4.03 seconds
Started Jan 17 03:34:43 PM PST 24
Finished Jan 17 03:34:51 PM PST 24
Peak memory 217024 kb
Host smart-973a91e4-4518-4621-a171-31804d28a46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441316298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1441316298
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.4137206746
Short name T1056
Test name
Test status
Simulation time 69753134 ps
CPU time 1.85 seconds
Started Jan 17 03:34:53 PM PST 24
Finished Jan 17 03:34:56 PM PST 24
Peak memory 217032 kb
Host smart-6a3b27d0-0cdd-4eb9-bcde-b5594ff9b0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137206746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.4137206746
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3321817776
Short name T556
Test name
Test status
Simulation time 32613070 ps
CPU time 0.77 seconds
Started Jan 17 03:34:57 PM PST 24
Finished Jan 17 03:34:59 PM PST 24
Peak memory 207248 kb
Host smart-dfeda3e2-b501-47a2-b063-79f815d36f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321817776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3321817776
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_tx_async_fifo_reset.2783166367
Short name T745
Test name
Test status
Simulation time 18139489 ps
CPU time 0.81 seconds
Started Jan 17 03:34:50 PM PST 24
Finished Jan 17 03:34:51 PM PST 24
Peak memory 208780 kb
Host smart-713bb461-093f-4caf-8132-b87c4819457f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783166367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tx_async_fifo_reset.2783166367
Directory /workspace/33.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/33.spi_device_txrx.2195387287
Short name T723
Test name
Test status
Simulation time 93537824525 ps
CPU time 280.91 seconds
Started Jan 17 03:34:46 PM PST 24
Finished Jan 17 03:39:28 PM PST 24
Peak memory 302796 kb
Host smart-cd756f16-8644-4498-9df3-a8b5229f6420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195387287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_txrx.2195387287
Directory /workspace/33.spi_device_txrx/latest

Test location /workspace/coverage/default/34.spi_device_abort.2277977203
Short name T610
Test name
Test status
Simulation time 91551875 ps
CPU time 0.79 seconds
Started Jan 17 03:35:06 PM PST 24
Finished Jan 17 03:35:07 PM PST 24
Peak memory 207008 kb
Host smart-bf257ed5-3fa8-410e-b2e0-c939a2ebc64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277977203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_abort.2277977203
Directory /workspace/34.spi_device_abort/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.818351511
Short name T689
Test name
Test status
Simulation time 11917708 ps
CPU time 0.71 seconds
Started Jan 17 03:35:07 PM PST 24
Finished Jan 17 03:35:09 PM PST 24
Peak memory 207060 kb
Host smart-c2116237-4ebb-40b1-89f6-a0d2592cae18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818351511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.818351511
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_bit_transfer.2225096651
Short name T1136
Test name
Test status
Simulation time 83772015 ps
CPU time 2.51 seconds
Started Jan 17 03:34:58 PM PST 24
Finished Jan 17 03:35:01 PM PST 24
Peak memory 217120 kb
Host smart-c1e56d6c-163e-4b55-9b2c-1c765e4f0fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225096651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_bit_transfer.2225096651
Directory /workspace/34.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/34.spi_device_byte_transfer.559736814
Short name T490
Test name
Test status
Simulation time 336351715 ps
CPU time 3.56 seconds
Started Jan 17 03:34:58 PM PST 24
Finished Jan 17 03:35:02 PM PST 24
Peak memory 217100 kb
Host smart-abd7dd57-9fbc-47ec-97eb-f3b009c4cb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559736814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_byte_transfer.559736814
Directory /workspace/34.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1851899475
Short name T701
Test name
Test status
Simulation time 614857091 ps
CPU time 5.56 seconds
Started Jan 17 03:35:05 PM PST 24
Finished Jan 17 03:35:11 PM PST 24
Peak memory 223376 kb
Host smart-3c14134c-3dc7-4738-bb9e-09040eae14d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851899475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1851899475
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.4171678723
Short name T1420
Test name
Test status
Simulation time 48694759 ps
CPU time 0.8 seconds
Started Jan 17 03:34:59 PM PST 24
Finished Jan 17 03:35:00 PM PST 24
Peak memory 207956 kb
Host smart-8d041c64-1445-4e6c-ad2a-e5fc9db4148d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171678723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.4171678723
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_dummy_item_extra_dly.2103537319
Short name T1663
Test name
Test status
Simulation time 51150260252 ps
CPU time 135.06 seconds
Started Jan 17 03:34:58 PM PST 24
Finished Jan 17 03:37:14 PM PST 24
Peak memory 274484 kb
Host smart-d29a73b3-c44c-4be3-9e8e-6ee63098f90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103537319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_dummy_item_extra_dly.2103537319
Directory /workspace/34.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/34.spi_device_extreme_fifo_size.1863292811
Short name T476
Test name
Test status
Simulation time 92477600494 ps
CPU time 107.27 seconds
Started Jan 17 03:34:58 PM PST 24
Finished Jan 17 03:36:46 PM PST 24
Peak memory 233796 kb
Host smart-522d0bac-2e87-44e5-b0f8-a6b3db0463c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863292811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_extreme_fifo_size.1863292811
Directory /workspace/34.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/34.spi_device_fifo_full.2859670762
Short name T815
Test name
Test status
Simulation time 116595051841 ps
CPU time 993.28 seconds
Started Jan 17 03:35:00 PM PST 24
Finished Jan 17 03:51:34 PM PST 24
Peak memory 250060 kb
Host smart-a576f6cd-f2d9-4abe-8a17-bf3e6c6d9862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859670762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_fifo_full.2859670762
Directory /workspace/34.spi_device_fifo_full/latest

Test location /workspace/coverage/default/34.spi_device_fifo_underflow_overflow.69491957
Short name T786
Test name
Test status
Simulation time 135584963586 ps
CPU time 764.2 seconds
Started Jan 17 03:35:00 PM PST 24
Finished Jan 17 03:47:45 PM PST 24
Peak memory 533344 kb
Host smart-e2cf2018-105f-4aa6-8be3-64ce734b0cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69491957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_fifo_underflow_overflo
w.69491957
Directory /workspace/34.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1608303339
Short name T322
Test name
Test status
Simulation time 66923336424 ps
CPU time 95.5 seconds
Started Jan 17 03:35:07 PM PST 24
Finished Jan 17 03:36:42 PM PST 24
Peak memory 263348 kb
Host smart-784b30e4-7cbf-4627-8f83-68a81bc2cef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608303339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1608303339
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1677738134
Short name T212
Test name
Test status
Simulation time 44958219000 ps
CPU time 127.71 seconds
Started Jan 17 03:35:09 PM PST 24
Finished Jan 17 03:37:19 PM PST 24
Peak memory 233708 kb
Host smart-b851380c-a029-4563-a3f8-88aa84cd8672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677738134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1677738134
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.4020570508
Short name T1302
Test name
Test status
Simulation time 2008270018 ps
CPU time 12.85 seconds
Started Jan 17 03:35:11 PM PST 24
Finished Jan 17 03:35:25 PM PST 24
Peak memory 233536 kb
Host smart-31dda557-d065-4ba9-a3aa-fe605f210e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020570508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.4020570508
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2881589183
Short name T1553
Test name
Test status
Simulation time 4425253487 ps
CPU time 8.29 seconds
Started Jan 17 03:35:05 PM PST 24
Finished Jan 17 03:35:14 PM PST 24
Peak memory 239460 kb
Host smart-00f2944a-6604-4d9e-8294-053ca2b4e017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881589183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2881589183
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_intr.159691287
Short name T1703
Test name
Test status
Simulation time 32476650098 ps
CPU time 30.36 seconds
Started Jan 17 03:34:57 PM PST 24
Finished Jan 17 03:35:29 PM PST 24
Peak memory 221732 kb
Host smart-0a15a66f-d7c8-40d2-8d0d-92b5a4ce7cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159691287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intr.159691287
Directory /workspace/34.spi_device_intr/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3442559598
Short name T1509
Test name
Test status
Simulation time 2557079758 ps
CPU time 14.56 seconds
Started Jan 17 03:35:04 PM PST 24
Finished Jan 17 03:35:20 PM PST 24
Peak memory 249088 kb
Host smart-128e7a29-94f2-472a-8aad-7c254f3b2e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442559598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3442559598
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2123839244
Short name T996
Test name
Test status
Simulation time 158513514 ps
CPU time 3.37 seconds
Started Jan 17 03:35:06 PM PST 24
Finished Jan 17 03:35:10 PM PST 24
Peak memory 238116 kb
Host smart-2bcb5f7a-27e0-4988-946a-044ba34b418d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123839244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2123839244
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2114860820
Short name T1559
Test name
Test status
Simulation time 73780803455 ps
CPU time 46.54 seconds
Started Jan 17 03:35:06 PM PST 24
Finished Jan 17 03:35:53 PM PST 24
Peak memory 250036 kb
Host smart-8aa29f52-6b93-43ea-bff6-1c8477fec176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114860820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2114860820
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_perf.4220971200
Short name T871
Test name
Test status
Simulation time 4940441817 ps
CPU time 336.79 seconds
Started Jan 17 03:34:57 PM PST 24
Finished Jan 17 03:40:36 PM PST 24
Peak memory 257560 kb
Host smart-f5124e39-6381-4b02-9ce8-01d41fe21e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220971200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_perf.4220971200
Directory /workspace/34.spi_device_perf/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.878834815
Short name T1573
Test name
Test status
Simulation time 1239931989 ps
CPU time 6.44 seconds
Started Jan 17 03:35:11 PM PST 24
Finished Jan 17 03:35:19 PM PST 24
Peak memory 220216 kb
Host smart-1b3d78a8-7bbe-4d41-adef-875b81e94cca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=878834815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.878834815
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_rx_async_fifo_reset.11341663
Short name T735
Test name
Test status
Simulation time 20968097 ps
CPU time 0.84 seconds
Started Jan 17 03:34:58 PM PST 24
Finished Jan 17 03:35:00 PM PST 24
Peak memory 208816 kb
Host smart-d50b5ed4-205c-422d-a4ce-266a69bbdf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11341663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_rx_async_fifo_reset.11341663
Directory /workspace/34.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/34.spi_device_rx_timeout.1935279721
Short name T1665
Test name
Test status
Simulation time 616961589 ps
CPU time 5.33 seconds
Started Jan 17 03:34:59 PM PST 24
Finished Jan 17 03:35:05 PM PST 24
Peak memory 217136 kb
Host smart-1544895e-adfa-458b-a3ff-69834419323a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935279721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_rx_timeout.1935279721
Directory /workspace/34.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/34.spi_device_smoke.231558112
Short name T1292
Test name
Test status
Simulation time 88862780 ps
CPU time 1.21 seconds
Started Jan 17 03:34:59 PM PST 24
Finished Jan 17 03:35:01 PM PST 24
Peak memory 216916 kb
Host smart-3b374e32-9d3d-4075-aacc-cd350ce3509a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231558112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_smoke.231558112
Directory /workspace/34.spi_device_smoke/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3078579303
Short name T73
Test name
Test status
Simulation time 123235407145 ps
CPU time 6426.08 seconds
Started Jan 17 03:35:11 PM PST 24
Finished Jan 17 05:22:19 PM PST 24
Peak memory 380340 kb
Host smart-26aec27e-e9b7-4450-8f5d-8622bdb94f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078579303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3078579303
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3749843276
Short name T1597
Test name
Test status
Simulation time 55689876466 ps
CPU time 207.59 seconds
Started Jan 17 03:35:00 PM PST 24
Finished Jan 17 03:38:29 PM PST 24
Peak memory 217252 kb
Host smart-26375d9d-91d5-461b-9270-1b10028f048c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749843276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3749843276
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1657997484
Short name T1062
Test name
Test status
Simulation time 26698645167 ps
CPU time 25.78 seconds
Started Jan 17 03:35:04 PM PST 24
Finished Jan 17 03:35:31 PM PST 24
Peak memory 217252 kb
Host smart-5b8fd6de-7932-472e-938a-a691e67649dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657997484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1657997484
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1685451155
Short name T1251
Test name
Test status
Simulation time 349444570 ps
CPU time 2.79 seconds
Started Jan 17 03:35:02 PM PST 24
Finished Jan 17 03:35:06 PM PST 24
Peak memory 217104 kb
Host smart-7db2ca26-25ce-462c-aa2b-d02a1d888b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685451155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1685451155
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2336722062
Short name T1225
Test name
Test status
Simulation time 313326425 ps
CPU time 0.89 seconds
Started Jan 17 03:35:00 PM PST 24
Finished Jan 17 03:35:02 PM PST 24
Peak memory 207240 kb
Host smart-ad487872-3484-4278-b536-b236f2edac59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336722062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2336722062
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_tx_async_fifo_reset.2423593036
Short name T711
Test name
Test status
Simulation time 16831359 ps
CPU time 0.78 seconds
Started Jan 17 03:35:01 PM PST 24
Finished Jan 17 03:35:02 PM PST 24
Peak memory 208740 kb
Host smart-e4a49dc2-c37c-4aca-bef7-71b798e041e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423593036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tx_async_fifo_reset.2423593036
Directory /workspace/34.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/34.spi_device_txrx.1829408150
Short name T1589
Test name
Test status
Simulation time 42427757770 ps
CPU time 479.66 seconds
Started Jan 17 03:35:01 PM PST 24
Finished Jan 17 03:43:01 PM PST 24
Peak memory 241760 kb
Host smart-00650a2a-3f5a-4892-b931-27364c9b45da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829408150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_txrx.1829408150
Directory /workspace/34.spi_device_txrx/latest

Test location /workspace/coverage/default/34.spi_device_upload.486136753
Short name T932
Test name
Test status
Simulation time 2299595295 ps
CPU time 10.81 seconds
Started Jan 17 03:35:07 PM PST 24
Finished Jan 17 03:35:18 PM PST 24
Peak memory 219984 kb
Host smart-f68dc3b0-2c90-4fd6-9ea7-4b0a13647292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486136753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.486136753
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_abort.1557389243
Short name T600
Test name
Test status
Simulation time 58580384 ps
CPU time 0.8 seconds
Started Jan 17 03:35:16 PM PST 24
Finished Jan 17 03:35:19 PM PST 24
Peak memory 207004 kb
Host smart-dda8cc83-3a3d-464e-8647-91d37af934b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557389243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_abort.1557389243
Directory /workspace/35.spi_device_abort/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.4071744201
Short name T1099
Test name
Test status
Simulation time 44295311 ps
CPU time 0.72 seconds
Started Jan 17 03:35:23 PM PST 24
Finished Jan 17 03:35:24 PM PST 24
Peak memory 206804 kb
Host smart-77fede44-d584-44f2-a9ad-d04fa6e0cbe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071744201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
4071744201
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_bit_transfer.3861684777
Short name T566
Test name
Test status
Simulation time 1778306425 ps
CPU time 2.77 seconds
Started Jan 17 03:35:15 PM PST 24
Finished Jan 17 03:35:21 PM PST 24
Peak memory 217148 kb
Host smart-b1edb33d-06ff-4739-a00b-bf403294ce22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861684777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_bit_transfer.3861684777
Directory /workspace/35.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/35.spi_device_byte_transfer.210745883
Short name T1030
Test name
Test status
Simulation time 1646141180 ps
CPU time 3.08 seconds
Started Jan 17 03:35:13 PM PST 24
Finished Jan 17 03:35:21 PM PST 24
Peak memory 217044 kb
Host smart-6f7a9782-eb09-4129-8181-736efe58b41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210745883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_byte_transfer.210745883
Directory /workspace/35.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2527103859
Short name T1599
Test name
Test status
Simulation time 2163667316 ps
CPU time 5.94 seconds
Started Jan 17 03:35:26 PM PST 24
Finished Jan 17 03:35:33 PM PST 24
Peak memory 241788 kb
Host smart-ae31177c-32ad-41bd-8d47-70e94afa5b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527103859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2527103859
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.4205778382
Short name T1634
Test name
Test status
Simulation time 21319740 ps
CPU time 0.81 seconds
Started Jan 17 03:35:15 PM PST 24
Finished Jan 17 03:35:19 PM PST 24
Peak memory 207928 kb
Host smart-18a7e875-da4e-439e-8c06-00d2c2039b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205778382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.4205778382
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_dummy_item_extra_dly.3362264004
Short name T499
Test name
Test status
Simulation time 57314120481 ps
CPU time 322.49 seconds
Started Jan 17 03:35:08 PM PST 24
Finished Jan 17 03:40:32 PM PST 24
Peak memory 284748 kb
Host smart-152c447a-16f0-4224-ab01-399b22109ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362264004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_dummy_item_extra_dly.3362264004
Directory /workspace/35.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/35.spi_device_extreme_fifo_size.574518457
Short name T1148
Test name
Test status
Simulation time 149323320324 ps
CPU time 1373.25 seconds
Started Jan 17 03:35:06 PM PST 24
Finished Jan 17 03:58:00 PM PST 24
Peak memory 218308 kb
Host smart-93e09086-5515-4861-9b00-6a4eda2d6310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574518457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_extreme_fifo_size.574518457
Directory /workspace/35.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/35.spi_device_fifo_full.2635213570
Short name T1535
Test name
Test status
Simulation time 466671269971 ps
CPU time 911.88 seconds
Started Jan 17 03:35:11 PM PST 24
Finished Jan 17 03:50:25 PM PST 24
Peak memory 259308 kb
Host smart-9eb784f5-a8df-44e2-a9f6-458866306eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635213570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_fifo_full.2635213570
Directory /workspace/35.spi_device_fifo_full/latest

Test location /workspace/coverage/default/35.spi_device_fifo_underflow_overflow.2675392044
Short name T51
Test name
Test status
Simulation time 310181187117 ps
CPU time 774.18 seconds
Started Jan 17 03:35:07 PM PST 24
Finished Jan 17 03:48:03 PM PST 24
Peak memory 641100 kb
Host smart-eca03577-1714-4511-bd82-bfe31623376c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675392044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_fifo_underflow_overf
low.2675392044
Directory /workspace/35.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1634571527
Short name T1110
Test name
Test status
Simulation time 2733950108 ps
CPU time 52.75 seconds
Started Jan 17 03:35:23 PM PST 24
Finished Jan 17 03:36:16 PM PST 24
Peak memory 255164 kb
Host smart-1c1727ec-7b26-4a94-8c8e-f418dda98b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634571527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1634571527
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.4286969293
Short name T229
Test name
Test status
Simulation time 12884082731 ps
CPU time 154.73 seconds
Started Jan 17 03:35:25 PM PST 24
Finished Jan 17 03:38:00 PM PST 24
Peak memory 268836 kb
Host smart-22ab58a8-47c2-46da-80c7-f8f26a6b30fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286969293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.4286969293
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3921343026
Short name T1424
Test name
Test status
Simulation time 24224275718 ps
CPU time 82.62 seconds
Started Jan 17 03:35:25 PM PST 24
Finished Jan 17 03:36:48 PM PST 24
Peak memory 265872 kb
Host smart-4b6de7ab-0b33-4896-911a-420515528f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921343026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3921343026
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3574136883
Short name T354
Test name
Test status
Simulation time 2750312763 ps
CPU time 13.22 seconds
Started Jan 17 03:35:25 PM PST 24
Finished Jan 17 03:35:39 PM PST 24
Peak memory 225436 kb
Host smart-2a571e60-31d0-437d-8c87-7b86a036496c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574136883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3574136883
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.4091749432
Short name T1479
Test name
Test status
Simulation time 2859679141 ps
CPU time 10.99 seconds
Started Jan 17 03:35:16 PM PST 24
Finished Jan 17 03:35:30 PM PST 24
Peak memory 221984 kb
Host smart-0899386e-3a71-40f3-8af1-f66c76cbadf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091749432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.4091749432
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_intr.3215449435
Short name T1646
Test name
Test status
Simulation time 14497879760 ps
CPU time 27.12 seconds
Started Jan 17 03:35:08 PM PST 24
Finished Jan 17 03:35:36 PM PST 24
Peak memory 240024 kb
Host smart-a351a9a5-06a0-4266-bce2-2234c9d7a73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215449435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intr.3215449435
Directory /workspace/35.spi_device_intr/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1629664785
Short name T241
Test name
Test status
Simulation time 30310098676 ps
CPU time 39.55 seconds
Started Jan 17 03:35:15 PM PST 24
Finished Jan 17 03:35:58 PM PST 24
Peak memory 233580 kb
Host smart-45d18983-5602-4dde-84c7-35c2e2e7c34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629664785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1629664785
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.663481563
Short name T501
Test name
Test status
Simulation time 490214714 ps
CPU time 3.94 seconds
Started Jan 17 03:35:16 PM PST 24
Finished Jan 17 03:35:23 PM PST 24
Peak memory 219232 kb
Host smart-d176e3b6-2695-49a8-b622-831bf9de1e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663481563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.663481563
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.4094202298
Short name T1446
Test name
Test status
Simulation time 1918371793 ps
CPU time 7.38 seconds
Started Jan 17 03:35:18 PM PST 24
Finished Jan 17 03:35:27 PM PST 24
Peak memory 247800 kb
Host smart-b61e6d8f-df4e-4829-9c96-3bc25173bbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094202298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.4094202298
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_perf.2347003914
Short name T1342
Test name
Test status
Simulation time 164514586182 ps
CPU time 2619.02 seconds
Started Jan 17 03:35:06 PM PST 24
Finished Jan 17 04:18:45 PM PST 24
Peak memory 291084 kb
Host smart-199ea018-1c2b-4392-a5b0-61bd12e03099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347003914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_perf.2347003914
Directory /workspace/35.spi_device_perf/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1609894020
Short name T7
Test name
Test status
Simulation time 666576530 ps
CPU time 3.57 seconds
Started Jan 17 03:35:25 PM PST 24
Finished Jan 17 03:35:29 PM PST 24
Peak memory 219224 kb
Host smart-a75baa8d-4e61-43ce-ac05-43866a1d6419
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1609894020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1609894020
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_rx_async_fifo_reset.1312269705
Short name T1723
Test name
Test status
Simulation time 20147153 ps
CPU time 0.87 seconds
Started Jan 17 03:35:17 PM PST 24
Finished Jan 17 03:35:20 PM PST 24
Peak memory 209040 kb
Host smart-20e6f29d-7431-428d-b1e3-3838a12542b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312269705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_rx_async_fifo_reset.1312269705
Directory /workspace/35.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/35.spi_device_rx_timeout.272156917
Short name T1438
Test name
Test status
Simulation time 1183928789 ps
CPU time 5.02 seconds
Started Jan 17 03:35:14 PM PST 24
Finished Jan 17 03:35:24 PM PST 24
Peak memory 217188 kb
Host smart-d24b74c3-d644-4c0f-acc6-26a563a1b007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272156917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_rx_timeout.272156917
Directory /workspace/35.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/35.spi_device_smoke.1554269941
Short name T1700
Test name
Test status
Simulation time 47177938 ps
CPU time 1.17 seconds
Started Jan 17 03:35:10 PM PST 24
Finished Jan 17 03:35:13 PM PST 24
Peak memory 217076 kb
Host smart-62f108a7-1970-41f4-bc7f-c61710379db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554269941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_smoke.1554269941
Directory /workspace/35.spi_device_smoke/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.706536429
Short name T1295
Test name
Test status
Simulation time 172282361092 ps
CPU time 890.52 seconds
Started Jan 17 03:35:22 PM PST 24
Finished Jan 17 03:50:13 PM PST 24
Peak memory 300856 kb
Host smart-a4032d58-7723-4da3-a6ff-53bfb6f7f85e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706536429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.706536429
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.222933364
Short name T623
Test name
Test status
Simulation time 818963629 ps
CPU time 9.72 seconds
Started Jan 17 03:35:14 PM PST 24
Finished Jan 17 03:35:28 PM PST 24
Peak memory 217264 kb
Host smart-7d232a10-3712-488b-b728-84faee4680f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222933364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.222933364
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2476008229
Short name T673
Test name
Test status
Simulation time 8406448490 ps
CPU time 15.94 seconds
Started Jan 17 03:35:14 PM PST 24
Finished Jan 17 03:35:35 PM PST 24
Peak memory 217168 kb
Host smart-5b3f5bc2-eafc-4da9-8982-c80f6dfaaa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476008229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2476008229
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3380652999
Short name T1572
Test name
Test status
Simulation time 141022850 ps
CPU time 4.97 seconds
Started Jan 17 03:35:17 PM PST 24
Finished Jan 17 03:35:24 PM PST 24
Peak memory 217200 kb
Host smart-f20c8def-c7e7-4005-affe-f24cd984b11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380652999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3380652999
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2296784069
Short name T1356
Test name
Test status
Simulation time 102929929 ps
CPU time 0.9 seconds
Started Jan 17 03:35:14 PM PST 24
Finished Jan 17 03:35:20 PM PST 24
Peak memory 207264 kb
Host smart-be56ce1e-8466-4e20-81ae-4c4730829be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296784069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2296784069
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_tx_async_fifo_reset.1368886030
Short name T580
Test name
Test status
Simulation time 16469311 ps
CPU time 0.82 seconds
Started Jan 17 03:35:16 PM PST 24
Finished Jan 17 03:35:19 PM PST 24
Peak memory 208716 kb
Host smart-b59384bd-918a-4d6a-a808-6838ce86befb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368886030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tx_async_fifo_reset.1368886030
Directory /workspace/35.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/35.spi_device_txrx.1517386843
Short name T489
Test name
Test status
Simulation time 9822193081 ps
CPU time 139.17 seconds
Started Jan 17 03:35:08 PM PST 24
Finished Jan 17 03:37:28 PM PST 24
Peak memory 241804 kb
Host smart-05605c7d-b1e8-4c39-b5cb-312782f08a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517386843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_txrx.1517386843
Directory /workspace/35.spi_device_txrx/latest

Test location /workspace/coverage/default/35.spi_device_upload.2138512984
Short name T952
Test name
Test status
Simulation time 39069842120 ps
CPU time 20.12 seconds
Started Jan 17 03:35:22 PM PST 24
Finished Jan 17 03:35:43 PM PST 24
Peak memory 244968 kb
Host smart-707e3a82-d00a-45e2-928b-78dcf90cea3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138512984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2138512984
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_abort.3774148130
Short name T991
Test name
Test status
Simulation time 43375701 ps
CPU time 0.76 seconds
Started Jan 17 03:35:46 PM PST 24
Finished Jan 17 03:35:48 PM PST 24
Peak memory 206996 kb
Host smart-49ac7b45-0d59-42e6-a9fc-3a020fd91d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774148130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_abort.3774148130
Directory /workspace/36.spi_device_abort/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2603542368
Short name T876
Test name
Test status
Simulation time 13974851 ps
CPU time 0.75 seconds
Started Jan 17 03:35:45 PM PST 24
Finished Jan 17 03:35:48 PM PST 24
Peak memory 206808 kb
Host smart-5c29609a-6cc3-49ee-9856-80ac85a404f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603542368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2603542368
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_bit_transfer.1716579576
Short name T644
Test name
Test status
Simulation time 202672271 ps
CPU time 2.69 seconds
Started Jan 17 03:35:48 PM PST 24
Finished Jan 17 03:35:52 PM PST 24
Peak memory 217100 kb
Host smart-ae0e65b0-b6c6-4596-8d34-f6deab4ff72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716579576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_bit_transfer.1716579576
Directory /workspace/36.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/36.spi_device_byte_transfer.4147188997
Short name T1491
Test name
Test status
Simulation time 421378085 ps
CPU time 2.87 seconds
Started Jan 17 03:35:29 PM PST 24
Finished Jan 17 03:35:33 PM PST 24
Peak memory 217124 kb
Host smart-7fa67110-d99b-46dc-87a3-b0cd997b0e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147188997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_byte_transfer.4147188997
Directory /workspace/36.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.4004349845
Short name T309
Test name
Test status
Simulation time 6292407712 ps
CPU time 11 seconds
Started Jan 17 03:35:50 PM PST 24
Finished Jan 17 03:36:04 PM PST 24
Peak memory 221024 kb
Host smart-106018aa-88c6-47d2-96f4-7ca80242ecc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004349845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.4004349845
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1094794358
Short name T1347
Test name
Test status
Simulation time 15340530 ps
CPU time 0.78 seconds
Started Jan 17 03:35:31 PM PST 24
Finished Jan 17 03:35:32 PM PST 24
Peak memory 207896 kb
Host smart-a814e3e2-e1e7-415d-8f3e-5934d27b8208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094794358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1094794358
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_dummy_item_extra_dly.3022491165
Short name T648
Test name
Test status
Simulation time 159848706584 ps
CPU time 458.36 seconds
Started Jan 17 03:35:25 PM PST 24
Finished Jan 17 03:43:04 PM PST 24
Peak memory 283868 kb
Host smart-a0031c62-5630-4f78-bcae-ef4ccccba32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022491165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_dummy_item_extra_dly.3022491165
Directory /workspace/36.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/36.spi_device_extreme_fifo_size.2731506432
Short name T846
Test name
Test status
Simulation time 46957869129 ps
CPU time 334.55 seconds
Started Jan 17 03:35:27 PM PST 24
Finished Jan 17 03:41:02 PM PST 24
Peak memory 225400 kb
Host smart-5abb1a72-901a-42c1-abfb-deb932a68c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731506432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_extreme_fifo_size.2731506432
Directory /workspace/36.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/36.spi_device_fifo_underflow_overflow.2399682565
Short name T1622
Test name
Test status
Simulation time 72556261247 ps
CPU time 181.34 seconds
Started Jan 17 03:35:29 PM PST 24
Finished Jan 17 03:38:31 PM PST 24
Peak memory 358476 kb
Host smart-7e60f367-e7f4-43ee-99ab-11bbc76eff57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399682565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_fifo_underflow_overf
low.2399682565
Directory /workspace/36.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1589161752
Short name T1503
Test name
Test status
Simulation time 10293096831 ps
CPU time 46.03 seconds
Started Jan 17 03:35:49 PM PST 24
Finished Jan 17 03:36:36 PM PST 24
Peak memory 258280 kb
Host smart-7f2c3460-3d40-4991-8c7b-041179d4f966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589161752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1589161752
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1484192986
Short name T324
Test name
Test status
Simulation time 104234307032 ps
CPU time 366.89 seconds
Started Jan 17 03:35:46 PM PST 24
Finished Jan 17 03:41:54 PM PST 24
Peak memory 250192 kb
Host smart-745c7ae9-5b99-4ef7-88ab-d29f79b49bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484192986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1484192986
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2288503300
Short name T1609
Test name
Test status
Simulation time 5721350207 ps
CPU time 7.07 seconds
Started Jan 17 03:35:50 PM PST 24
Finished Jan 17 03:36:00 PM PST 24
Peak memory 225412 kb
Host smart-48d88b1f-a8e0-47ef-b5dd-ab680ee22401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288503300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2288503300
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_intr.1576461842
Short name T1710
Test name
Test status
Simulation time 6743492284 ps
CPU time 48.3 seconds
Started Jan 17 03:35:32 PM PST 24
Finished Jan 17 03:36:21 PM PST 24
Peak memory 240832 kb
Host smart-6d8e3a52-8f90-42cd-9e8e-4c7e6f565711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576461842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intr.1576461842
Directory /workspace/36.spi_device_intr/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.496620906
Short name T1318
Test name
Test status
Simulation time 3838549750 ps
CPU time 19.03 seconds
Started Jan 17 03:35:45 PM PST 24
Finished Jan 17 03:36:05 PM PST 24
Peak memory 236776 kb
Host smart-10506844-9f7b-47cd-9119-3720c8196ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496620906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.496620906
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.495491825
Short name T1402
Test name
Test status
Simulation time 2293555630 ps
CPU time 4.83 seconds
Started Jan 17 03:35:49 PM PST 24
Finished Jan 17 03:35:55 PM PST 24
Peak memory 220040 kb
Host smart-d84d7c57-7c1f-408a-9ee2-dc13ec52208e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495491825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.495491825
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1589668456
Short name T1407
Test name
Test status
Simulation time 1178567318 ps
CPU time 8.54 seconds
Started Jan 17 03:35:46 PM PST 24
Finished Jan 17 03:35:56 PM PST 24
Peak memory 248636 kb
Host smart-876a1fd1-efba-4a94-863e-daf8fab776ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589668456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1589668456
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_perf.661361786
Short name T270
Test name
Test status
Simulation time 61605967710 ps
CPU time 793.96 seconds
Started Jan 17 03:35:31 PM PST 24
Finished Jan 17 03:48:46 PM PST 24
Peak memory 283792 kb
Host smart-3e1ed976-32a6-41e1-bd25-e9210cff5f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661361786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_perf.661361786
Directory /workspace/36.spi_device_perf/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3821015848
Short name T552
Test name
Test status
Simulation time 3409563308 ps
CPU time 5.31 seconds
Started Jan 17 03:35:49 PM PST 24
Finished Jan 17 03:35:55 PM PST 24
Peak memory 235924 kb
Host smart-05fa1ed4-4179-40b4-bae4-a70e2ffe5a7f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3821015848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3821015848
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_rx_async_fifo_reset.4212458803
Short name T1087
Test name
Test status
Simulation time 233861535 ps
CPU time 0.9 seconds
Started Jan 17 03:35:45 PM PST 24
Finished Jan 17 03:35:47 PM PST 24
Peak memory 208792 kb
Host smart-e245785f-4ccb-4b46-982f-aa102cab2800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212458803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_rx_async_fifo_reset.4212458803
Directory /workspace/36.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/36.spi_device_rx_timeout.2530623661
Short name T1160
Test name
Test status
Simulation time 572126813 ps
CPU time 5.88 seconds
Started Jan 17 03:35:34 PM PST 24
Finished Jan 17 03:35:40 PM PST 24
Peak memory 217172 kb
Host smart-fdf35c71-19d8-43de-a899-daf77a77e8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530623661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_rx_timeout.2530623661
Directory /workspace/36.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/36.spi_device_smoke.974015850
Short name T858
Test name
Test status
Simulation time 17425929 ps
CPU time 1.11 seconds
Started Jan 17 03:35:22 PM PST 24
Finished Jan 17 03:35:23 PM PST 24
Peak memory 216968 kb
Host smart-cc4a145d-35f9-4cff-a8f4-61d815d33c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974015850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_smoke.974015850
Directory /workspace/36.spi_device_smoke/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.4125069143
Short name T187
Test name
Test status
Simulation time 215364346999 ps
CPU time 2346.68 seconds
Started Jan 17 03:35:46 PM PST 24
Finished Jan 17 04:14:54 PM PST 24
Peak memory 709864 kb
Host smart-bc6d7353-1048-436f-8ffe-bb604d1efac4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125069143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.4125069143
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.738695811
Short name T1237
Test name
Test status
Simulation time 5267453773 ps
CPU time 100.73 seconds
Started Jan 17 03:35:45 PM PST 24
Finished Jan 17 03:37:28 PM PST 24
Peak memory 217264 kb
Host smart-a5d2c203-78ca-42bf-bb9a-d015652d8c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738695811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.738695811
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3799672000
Short name T1200
Test name
Test status
Simulation time 268809186 ps
CPU time 1.53 seconds
Started Jan 17 03:35:29 PM PST 24
Finished Jan 17 03:35:31 PM PST 24
Peak memory 208744 kb
Host smart-71435fbb-bc84-4704-98f1-305fd7762fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799672000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3799672000
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.370413368
Short name T1102
Test name
Test status
Simulation time 428504954 ps
CPU time 2.51 seconds
Started Jan 17 03:35:47 PM PST 24
Finished Jan 17 03:35:51 PM PST 24
Peak memory 217096 kb
Host smart-ca85767a-4fa9-499c-ae23-8aa2ead0b936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370413368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.370413368
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2952402041
Short name T99
Test name
Test status
Simulation time 94239403 ps
CPU time 0.89 seconds
Started Jan 17 03:35:44 PM PST 24
Finished Jan 17 03:35:46 PM PST 24
Peak memory 207292 kb
Host smart-63fbecdb-78bc-43b4-91a4-4898231012a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952402041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2952402041
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_tx_async_fifo_reset.2851658929
Short name T78
Test name
Test status
Simulation time 23012208 ps
CPU time 0.78 seconds
Started Jan 17 03:35:48 PM PST 24
Finished Jan 17 03:35:50 PM PST 24
Peak memory 208808 kb
Host smart-ba5e7e8f-424f-4ecf-b9be-f54e3be26422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851658929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tx_async_fifo_reset.2851658929
Directory /workspace/36.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/36.spi_device_txrx.67380624
Short name T910
Test name
Test status
Simulation time 63496445152 ps
CPU time 401.65 seconds
Started Jan 17 03:35:22 PM PST 24
Finished Jan 17 03:42:04 PM PST 24
Peak memory 224920 kb
Host smart-2f783011-479a-4d99-980a-1bd32421bc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67380624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_txrx.67380624
Directory /workspace/36.spi_device_txrx/latest

Test location /workspace/coverage/default/36.spi_device_upload.3228530914
Short name T1721
Test name
Test status
Simulation time 6873150020 ps
CPU time 13.56 seconds
Started Jan 17 03:35:51 PM PST 24
Finished Jan 17 03:36:09 PM PST 24
Peak memory 253336 kb
Host smart-98a5c63d-ec23-4d9f-a037-e8863f81c098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228530914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3228530914
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_abort.556423312
Short name T1242
Test name
Test status
Simulation time 79890911 ps
CPU time 0.74 seconds
Started Jan 17 03:35:48 PM PST 24
Finished Jan 17 03:35:50 PM PST 24
Peak memory 207008 kb
Host smart-698c7a4d-c7b7-45d7-8cfe-063fd40151c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556423312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_abort.556423312
Directory /workspace/37.spi_device_abort/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2403322613
Short name T1012
Test name
Test status
Simulation time 12622053 ps
CPU time 0.73 seconds
Started Jan 17 03:35:55 PM PST 24
Finished Jan 17 03:35:57 PM PST 24
Peak memory 206812 kb
Host smart-ced92e7e-f24e-44cf-9b33-004d39adcfcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403322613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2403322613
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_bit_transfer.3525221964
Short name T1419
Test name
Test status
Simulation time 241862341 ps
CPU time 2.36 seconds
Started Jan 17 03:35:47 PM PST 24
Finished Jan 17 03:35:51 PM PST 24
Peak memory 217024 kb
Host smart-f62349c6-fcc8-400d-a023-9d13d26c3d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525221964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_bit_transfer.3525221964
Directory /workspace/37.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/37.spi_device_byte_transfer.1487297284
Short name T1032
Test name
Test status
Simulation time 252644605 ps
CPU time 3.01 seconds
Started Jan 17 03:35:49 PM PST 24
Finished Jan 17 03:35:53 PM PST 24
Peak memory 217196 kb
Host smart-3492da71-65e1-4573-adf4-b4c45a0ffa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487297284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_byte_transfer.1487297284
Directory /workspace/37.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.423908116
Short name T1181
Test name
Test status
Simulation time 39355430807 ps
CPU time 12.11 seconds
Started Jan 17 03:35:53 PM PST 24
Finished Jan 17 03:36:08 PM PST 24
Peak memory 221908 kb
Host smart-36fe1284-d17a-4b96-803d-dd0f665de54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423908116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.423908116
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.68210562
Short name T830
Test name
Test status
Simulation time 145967227 ps
CPU time 0.78 seconds
Started Jan 17 03:35:47 PM PST 24
Finished Jan 17 03:35:49 PM PST 24
Peak memory 207880 kb
Host smart-5560cd91-98a7-47c2-a70f-59efe5e11b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68210562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.68210562
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_dummy_item_extra_dly.370128408
Short name T820
Test name
Test status
Simulation time 100107754435 ps
CPU time 2430.81 seconds
Started Jan 17 03:35:47 PM PST 24
Finished Jan 17 04:16:19 PM PST 24
Peak memory 272556 kb
Host smart-c7135d96-a277-4603-befb-8e2f8a9214a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370128408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_dummy_item_extra_dly.370128408
Directory /workspace/37.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/37.spi_device_extreme_fifo_size.4293344420
Short name T1151
Test name
Test status
Simulation time 142360415905 ps
CPU time 1069.41 seconds
Started Jan 17 03:35:46 PM PST 24
Finished Jan 17 03:53:37 PM PST 24
Peak memory 218288 kb
Host smart-dc82df7f-4cb6-44bf-a3be-cf0e9595bb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293344420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_extreme_fifo_size.4293344420
Directory /workspace/37.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/37.spi_device_fifo_full.2052161626
Short name T619
Test name
Test status
Simulation time 112230078498 ps
CPU time 511.44 seconds
Started Jan 17 03:35:47 PM PST 24
Finished Jan 17 03:44:20 PM PST 24
Peak memory 265544 kb
Host smart-02052e2f-7425-42d3-b0e6-5032b1c121d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052161626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_fifo_full.2052161626
Directory /workspace/37.spi_device_fifo_full/latest

Test location /workspace/coverage/default/37.spi_device_fifo_underflow_overflow.1252304014
Short name T52
Test name
Test status
Simulation time 391913896970 ps
CPU time 1579.68 seconds
Started Jan 17 03:35:53 PM PST 24
Finished Jan 17 04:02:16 PM PST 24
Peak memory 534568 kb
Host smart-0c8e5fbd-e3a6-401c-b47f-762b41972ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252304014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_fifo_underflow_overf
low.1252304014
Directory /workspace/37.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1015325965
Short name T1571
Test name
Test status
Simulation time 58066680318 ps
CPU time 210.34 seconds
Started Jan 17 03:35:53 PM PST 24
Finished Jan 17 03:39:27 PM PST 24
Peak memory 266412 kb
Host smart-1bba6cbc-a4ed-492d-9908-b4057792a6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015325965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1015325965
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.311383002
Short name T8
Test name
Test status
Simulation time 54467264085 ps
CPU time 297.15 seconds
Started Jan 17 03:35:53 PM PST 24
Finished Jan 17 03:40:54 PM PST 24
Peak memory 266472 kb
Host smart-ba3af02b-1865-4638-92fb-26dfc9aead5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311383002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.311383002
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1223126420
Short name T107
Test name
Test status
Simulation time 31671991914 ps
CPU time 210.71 seconds
Started Jan 17 03:35:53 PM PST 24
Finished Jan 17 03:39:27 PM PST 24
Peak memory 251592 kb
Host smart-4c0ab2b4-2ac0-42ba-aeb8-1d358b4da3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223126420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1223126420
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3935583090
Short name T1743
Test name
Test status
Simulation time 70934839664 ps
CPU time 19.36 seconds
Started Jan 17 03:35:53 PM PST 24
Finished Jan 17 03:36:16 PM PST 24
Peak memory 236288 kb
Host smart-0e3cba70-0e69-472b-9090-fc2316471f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935583090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3935583090
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3893954054
Short name T1632
Test name
Test status
Simulation time 678637188 ps
CPU time 4.43 seconds
Started Jan 17 03:35:47 PM PST 24
Finished Jan 17 03:35:53 PM PST 24
Peak memory 219572 kb
Host smart-0bfae0a0-318b-4959-81c3-3721ac45cc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893954054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3893954054
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_intr.3614854503
Short name T1584
Test name
Test status
Simulation time 15215989191 ps
CPU time 49.38 seconds
Started Jan 17 03:35:49 PM PST 24
Finished Jan 17 03:36:40 PM PST 24
Peak memory 237480 kb
Host smart-b904750d-36ac-4866-9cc2-ad529717f422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614854503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intr.3614854503
Directory /workspace/37.spi_device_intr/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3436788836
Short name T1238
Test name
Test status
Simulation time 31409434258 ps
CPU time 26.34 seconds
Started Jan 17 03:35:55 PM PST 24
Finished Jan 17 03:36:23 PM PST 24
Peak memory 230008 kb
Host smart-6a32bd86-85ec-42c5-a176-3a3996a642ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436788836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3436788836
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.156742893
Short name T337
Test name
Test status
Simulation time 20582329756 ps
CPU time 33.31 seconds
Started Jan 17 03:35:51 PM PST 24
Finished Jan 17 03:36:28 PM PST 24
Peak memory 250068 kb
Host smart-a9fb4c38-fd70-4e8b-8573-611df7341a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156742893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.156742893
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.61008854
Short name T193
Test name
Test status
Simulation time 1530662714 ps
CPU time 4.09 seconds
Started Jan 17 03:35:49 PM PST 24
Finished Jan 17 03:35:54 PM PST 24
Peak memory 239200 kb
Host smart-bd4d1ecd-06a4-4e54-8b13-14486e714148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61008854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.61008854
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_perf.3629628831
Short name T582
Test name
Test status
Simulation time 119011705277 ps
CPU time 1289.77 seconds
Started Jan 17 03:35:46 PM PST 24
Finished Jan 17 03:57:17 PM PST 24
Peak memory 254680 kb
Host smart-8ff0ed93-498f-45cc-ae8c-2b7fd5999817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629628831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_perf.3629628831
Directory /workspace/37.spi_device_perf/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.461721375
Short name T576
Test name
Test status
Simulation time 104697982 ps
CPU time 3.6 seconds
Started Jan 17 03:35:54 PM PST 24
Finished Jan 17 03:36:00 PM PST 24
Peak memory 220100 kb
Host smart-1a01011c-85a7-4ae9-9b72-dfb260385734
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=461721375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.461721375
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_rx_async_fifo_reset.158286364
Short name T1744
Test name
Test status
Simulation time 35716243 ps
CPU time 1.04 seconds
Started Jan 17 03:35:49 PM PST 24
Finished Jan 17 03:35:51 PM PST 24
Peak memory 208760 kb
Host smart-6562837f-4969-4cb7-9d33-6d76cc17cc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158286364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_rx_async_fifo_reset.158286364
Directory /workspace/37.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/37.spi_device_rx_timeout.2417409915
Short name T1749
Test name
Test status
Simulation time 976945954 ps
CPU time 5.45 seconds
Started Jan 17 03:35:52 PM PST 24
Finished Jan 17 03:36:02 PM PST 24
Peak memory 217152 kb
Host smart-d5abfb33-5463-4f95-84df-c96e59ee0f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417409915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_rx_timeout.2417409915
Directory /workspace/37.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/37.spi_device_smoke.3548930492
Short name T1092
Test name
Test status
Simulation time 31090913 ps
CPU time 1.07 seconds
Started Jan 17 03:35:48 PM PST 24
Finished Jan 17 03:35:50 PM PST 24
Peak memory 216884 kb
Host smart-c88692d6-0382-4660-8960-40fcab214ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548930492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_smoke.3548930492
Directory /workspace/37.spi_device_smoke/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3863829406
Short name T1670
Test name
Test status
Simulation time 6317016153 ps
CPU time 54.77 seconds
Started Jan 17 03:35:48 PM PST 24
Finished Jan 17 03:36:44 PM PST 24
Peak memory 217152 kb
Host smart-c1b85e29-01ba-4fc6-a7f6-b343b1f0cae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863829406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3863829406
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3734665122
Short name T549
Test name
Test status
Simulation time 2419482220 ps
CPU time 9.42 seconds
Started Jan 17 03:35:52 PM PST 24
Finished Jan 17 03:36:06 PM PST 24
Peak memory 217220 kb
Host smart-17d621c0-3445-4153-be9f-c7602c277078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734665122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3734665122
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2681235467
Short name T1049
Test name
Test status
Simulation time 59530531 ps
CPU time 0.8 seconds
Started Jan 17 03:35:50 PM PST 24
Finished Jan 17 03:35:52 PM PST 24
Peak memory 207280 kb
Host smart-a5fcd779-1d18-47c4-b4a1-694415334a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681235467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2681235467
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1098726799
Short name T1333
Test name
Test status
Simulation time 288342896 ps
CPU time 0.95 seconds
Started Jan 17 03:35:51 PM PST 24
Finished Jan 17 03:35:56 PM PST 24
Peak memory 207292 kb
Host smart-b2f1abda-7264-49d4-9697-467eff2cc0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098726799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1098726799
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_tx_async_fifo_reset.139345779
Short name T942
Test name
Test status
Simulation time 15746774 ps
CPU time 0.78 seconds
Started Jan 17 03:35:48 PM PST 24
Finished Jan 17 03:35:50 PM PST 24
Peak memory 208736 kb
Host smart-16108fe9-c7f8-4dc8-aec2-115f7f9c15b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139345779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tx_async_fifo_reset.139345779
Directory /workspace/37.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/37.spi_device_txrx.3963701222
Short name T1362
Test name
Test status
Simulation time 10307549754 ps
CPU time 133.78 seconds
Started Jan 17 03:35:46 PM PST 24
Finished Jan 17 03:38:01 PM PST 24
Peak memory 278128 kb
Host smart-ffaf7043-99d0-4b60-83c4-571d647b6940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963701222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_txrx.3963701222
Directory /workspace/37.spi_device_txrx/latest

Test location /workspace/coverage/default/37.spi_device_upload.1121434797
Short name T194
Test name
Test status
Simulation time 3591787437 ps
CPU time 4.32 seconds
Started Jan 17 03:35:55 PM PST 24
Finished Jan 17 03:36:01 PM PST 24
Peak memory 239308 kb
Host smart-6bd20b06-b64f-40bd-9df3-54071b4ac60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121434797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1121434797
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_abort.4065563740
Short name T1204
Test name
Test status
Simulation time 53794350 ps
CPU time 0.74 seconds
Started Jan 17 03:35:58 PM PST 24
Finished Jan 17 03:35:59 PM PST 24
Peak memory 206948 kb
Host smart-608ae8da-dce1-405f-b330-a4d99c68a727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065563740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_abort.4065563740
Directory /workspace/38.spi_device_abort/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1688092132
Short name T695
Test name
Test status
Simulation time 142755632 ps
CPU time 0.74 seconds
Started Jan 17 03:36:01 PM PST 24
Finished Jan 17 03:36:03 PM PST 24
Peak memory 206824 kb
Host smart-d05ea30d-9fd5-42f4-8cee-1070c5228fa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688092132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1688092132
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_bit_transfer.1935987201
Short name T1308
Test name
Test status
Simulation time 306186398 ps
CPU time 2.86 seconds
Started Jan 17 03:35:59 PM PST 24
Finished Jan 17 03:36:02 PM PST 24
Peak memory 217204 kb
Host smart-d40b5a7c-d106-4986-a43c-4b6e4f459779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935987201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_bit_transfer.1935987201
Directory /workspace/38.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/38.spi_device_byte_transfer.3356700477
Short name T1659
Test name
Test status
Simulation time 2638760874 ps
CPU time 2.75 seconds
Started Jan 17 03:35:59 PM PST 24
Finished Jan 17 03:36:02 PM PST 24
Peak memory 217164 kb
Host smart-a2c7285a-0587-47b1-803f-d3dae24be67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356700477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_byte_transfer.3356700477
Directory /workspace/38.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.489250391
Short name T988
Test name
Test status
Simulation time 871505252 ps
CPU time 3.3 seconds
Started Jan 17 03:36:04 PM PST 24
Finished Jan 17 03:36:09 PM PST 24
Peak memory 238836 kb
Host smart-12a89c39-0017-4f58-88ff-43e57d3916b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489250391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.489250391
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1643366399
Short name T1413
Test name
Test status
Simulation time 52445809 ps
CPU time 0.78 seconds
Started Jan 17 03:35:56 PM PST 24
Finished Jan 17 03:35:58 PM PST 24
Peak memory 207960 kb
Host smart-00fcf3af-f934-4a6d-933a-3a4be109d0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643366399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1643366399
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_dummy_item_extra_dly.1965460787
Short name T568
Test name
Test status
Simulation time 180480033455 ps
CPU time 286.61 seconds
Started Jan 17 03:35:59 PM PST 24
Finished Jan 17 03:40:46 PM PST 24
Peak memory 288884 kb
Host smart-a8ab555c-6732-4c21-a5be-6f799e903c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965460787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_dummy_item_extra_dly.1965460787
Directory /workspace/38.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/38.spi_device_extreme_fifo_size.4004493513
Short name T1614
Test name
Test status
Simulation time 227254284494 ps
CPU time 2228.13 seconds
Started Jan 17 03:35:54 PM PST 24
Finished Jan 17 04:13:05 PM PST 24
Peak memory 218272 kb
Host smart-99325a7c-0968-4568-a21f-52c62764fa8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004493513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_extreme_fifo_size.4004493513
Directory /workspace/38.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/38.spi_device_fifo_full.305907061
Short name T1072
Test name
Test status
Simulation time 190745621634 ps
CPU time 474.23 seconds
Started Jan 17 03:35:54 PM PST 24
Finished Jan 17 03:43:51 PM PST 24
Peak memory 306748 kb
Host smart-73c2ef5e-3e09-4a80-805f-be9e77e0a957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305907061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_fifo_full.305907061
Directory /workspace/38.spi_device_fifo_full/latest

Test location /workspace/coverage/default/38.spi_device_fifo_underflow_overflow.1942074596
Short name T1194
Test name
Test status
Simulation time 26930584826 ps
CPU time 289.18 seconds
Started Jan 17 03:35:55 PM PST 24
Finished Jan 17 03:40:46 PM PST 24
Peak memory 419204 kb
Host smart-14f25f16-b6ce-4126-adab-bc150b26ee87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942074596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_fifo_underflow_overf
low.1942074596
Directory /workspace/38.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.694144649
Short name T1319
Test name
Test status
Simulation time 60556697954 ps
CPU time 142.11 seconds
Started Jan 17 03:36:04 PM PST 24
Finished Jan 17 03:38:26 PM PST 24
Peak memory 256544 kb
Host smart-bd4c8631-312a-4a94-a382-bdee8bedd889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694144649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.694144649
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.500824865
Short name T225
Test name
Test status
Simulation time 6923118348 ps
CPU time 81.22 seconds
Started Jan 17 03:36:04 PM PST 24
Finished Jan 17 03:37:27 PM PST 24
Peak memory 255056 kb
Host smart-e2455e8d-4a99-40bc-b0e7-ba26faa6571b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500824865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.500824865
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.90363621
Short name T903
Test name
Test status
Simulation time 592356805 ps
CPU time 12 seconds
Started Jan 17 03:36:04 PM PST 24
Finished Jan 17 03:36:18 PM PST 24
Peak memory 239584 kb
Host smart-2a6665c7-ae49-4a12-b28f-6662dadf5110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90363621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.90363621
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1398951765
Short name T1664
Test name
Test status
Simulation time 1540029122 ps
CPU time 3.17 seconds
Started Jan 17 03:36:04 PM PST 24
Finished Jan 17 03:36:09 PM PST 24
Peak memory 218644 kb
Host smart-092f56f1-a041-4d0f-9a70-e950e394bdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398951765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1398951765
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_intr.2708623406
Short name T1552
Test name
Test status
Simulation time 67810053668 ps
CPU time 69.46 seconds
Started Jan 17 03:35:57 PM PST 24
Finished Jan 17 03:37:07 PM PST 24
Peak memory 241384 kb
Host smart-a0495d02-b1ea-47cd-8014-4f81adc9d2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708623406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intr.2708623406
Directory /workspace/38.spi_device_intr/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4061443829
Short name T36
Test name
Test status
Simulation time 132650722409 ps
CPU time 23.92 seconds
Started Jan 17 03:36:04 PM PST 24
Finished Jan 17 03:36:29 PM PST 24
Peak memory 246772 kb
Host smart-a209de9b-a884-4bb6-aaf6-2556786e4e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061443829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4061443829
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.682356182
Short name T1732
Test name
Test status
Simulation time 19401098982 ps
CPU time 42.03 seconds
Started Jan 17 03:36:00 PM PST 24
Finished Jan 17 03:36:43 PM PST 24
Peak memory 231928 kb
Host smart-cc46ab7f-75a0-4c07-90f7-7698934db45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682356182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.682356182
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2240735306
Short name T1178
Test name
Test status
Simulation time 505099021 ps
CPU time 4.36 seconds
Started Jan 17 03:35:58 PM PST 24
Finished Jan 17 03:36:03 PM PST 24
Peak memory 219036 kb
Host smart-a715cb6e-d8a8-4bed-a7e2-659deb0ddc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240735306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2240735306
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_perf.1205964918
Short name T1005
Test name
Test status
Simulation time 4102672475 ps
CPU time 249.71 seconds
Started Jan 17 03:35:56 PM PST 24
Finished Jan 17 03:40:07 PM PST 24
Peak memory 254240 kb
Host smart-f53a1177-4db9-43cf-b185-029b08c4d020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205964918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_perf.1205964918
Directory /workspace/38.spi_device_perf/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3485793059
Short name T931
Test name
Test status
Simulation time 6942251790 ps
CPU time 6.27 seconds
Started Jan 17 03:36:03 PM PST 24
Finished Jan 17 03:36:10 PM PST 24
Peak memory 236776 kb
Host smart-9b72873b-fe03-47a1-b51d-327665469ead
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3485793059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3485793059
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_rx_async_fifo_reset.4055886789
Short name T1335
Test name
Test status
Simulation time 42037446 ps
CPU time 0.94 seconds
Started Jan 17 03:35:58 PM PST 24
Finished Jan 17 03:35:59 PM PST 24
Peak memory 208800 kb
Host smart-4c53dd02-8977-4b78-ad81-a3fb15600428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055886789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_rx_async_fifo_reset.4055886789
Directory /workspace/38.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/38.spi_device_rx_timeout.2711042286
Short name T1468
Test name
Test status
Simulation time 718705636 ps
CPU time 6.57 seconds
Started Jan 17 03:35:56 PM PST 24
Finished Jan 17 03:36:04 PM PST 24
Peak memory 217168 kb
Host smart-b4a1a983-1037-44e2-ae42-8a44e9a569a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711042286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_rx_timeout.2711042286
Directory /workspace/38.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/38.spi_device_smoke.4242853449
Short name T998
Test name
Test status
Simulation time 409518772 ps
CPU time 1.07 seconds
Started Jan 17 03:35:56 PM PST 24
Finished Jan 17 03:35:58 PM PST 24
Peak memory 216960 kb
Host smart-9cba71ea-0ef3-4440-8708-66b24bfdaa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242853449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_smoke.4242853449
Directory /workspace/38.spi_device_smoke/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3418585017
Short name T1546
Test name
Test status
Simulation time 462796245448 ps
CPU time 867.4 seconds
Started Jan 17 03:36:03 PM PST 24
Finished Jan 17 03:50:31 PM PST 24
Peak memory 526804 kb
Host smart-5bf34778-4ae9-4b80-b242-d3926bb66fe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418585017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3418585017
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2474220248
Short name T1304
Test name
Test status
Simulation time 1658037030 ps
CPU time 8.77 seconds
Started Jan 17 03:35:59 PM PST 24
Finished Jan 17 03:36:08 PM PST 24
Peak memory 217332 kb
Host smart-97aa33a9-832b-468e-ad26-442fa4f6c27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474220248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2474220248
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.766194838
Short name T1372
Test name
Test status
Simulation time 1363727597 ps
CPU time 9.52 seconds
Started Jan 17 03:35:59 PM PST 24
Finished Jan 17 03:36:09 PM PST 24
Peak memory 217092 kb
Host smart-76f0b2a4-6b99-4f13-bfe1-1bb8f5abd0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766194838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.766194838
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.233064470
Short name T483
Test name
Test status
Simulation time 483219905 ps
CPU time 5.91 seconds
Started Jan 17 03:36:04 PM PST 24
Finished Jan 17 03:36:12 PM PST 24
Peak memory 217040 kb
Host smart-90c6ff9c-b716-4186-8ea4-8dfacec4e487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233064470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.233064470
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3728771237
Short name T1653
Test name
Test status
Simulation time 113272774 ps
CPU time 1.08 seconds
Started Jan 17 03:36:04 PM PST 24
Finished Jan 17 03:36:07 PM PST 24
Peak memory 208336 kb
Host smart-ce3e721c-cc8c-4432-9bb5-8cdd16ee18e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728771237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3728771237
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_tx_async_fifo_reset.1933391678
Short name T132
Test name
Test status
Simulation time 32457694 ps
CPU time 0.8 seconds
Started Jan 17 03:35:58 PM PST 24
Finished Jan 17 03:36:00 PM PST 24
Peak memory 208712 kb
Host smart-7c08ccba-f4e5-452d-be2f-31dd7ee440da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933391678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tx_async_fifo_reset.1933391678
Directory /workspace/38.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/38.spi_device_txrx.1960353298
Short name T1161
Test name
Test status
Simulation time 41918522966 ps
CPU time 348.26 seconds
Started Jan 17 03:35:57 PM PST 24
Finished Jan 17 03:41:46 PM PST 24
Peak memory 262336 kb
Host smart-d193cdb1-5b20-4894-b1cf-a7b395d3f304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960353298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_txrx.1960353298
Directory /workspace/38.spi_device_txrx/latest

Test location /workspace/coverage/default/38.spi_device_upload.4181232545
Short name T211
Test name
Test status
Simulation time 6936876824 ps
CPU time 12.01 seconds
Started Jan 17 03:36:04 PM PST 24
Finished Jan 17 03:36:18 PM PST 24
Peak memory 247760 kb
Host smart-378462d1-2cff-49b6-a3bb-cc9ebfd111c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181232545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.4181232545
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_abort.3703077988
Short name T969
Test name
Test status
Simulation time 16274589 ps
CPU time 0.79 seconds
Started Jan 17 03:36:06 PM PST 24
Finished Jan 17 03:36:07 PM PST 24
Peak memory 206996 kb
Host smart-5ce7ebd9-cb90-4a64-848f-87bfa68226b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703077988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_abort.3703077988
Directory /workspace/39.spi_device_abort/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2195124842
Short name T1496
Test name
Test status
Simulation time 27586315 ps
CPU time 0.74 seconds
Started Jan 17 03:36:14 PM PST 24
Finished Jan 17 03:36:16 PM PST 24
Peak memory 206760 kb
Host smart-e08c3a3a-914c-4bb9-8c72-c95bd90a85c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195124842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2195124842
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_bit_transfer.1293125623
Short name T1730
Test name
Test status
Simulation time 1327999442 ps
CPU time 3.11 seconds
Started Jan 17 03:36:10 PM PST 24
Finished Jan 17 03:36:15 PM PST 24
Peak memory 217132 kb
Host smart-7dfe2171-6528-480b-bd92-a628d68d6599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293125623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_bit_transfer.1293125623
Directory /workspace/39.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/39.spi_device_byte_transfer.622118206
Short name T1702
Test name
Test status
Simulation time 200067899 ps
CPU time 2.79 seconds
Started Jan 17 03:36:07 PM PST 24
Finished Jan 17 03:36:10 PM PST 24
Peak memory 217200 kb
Host smart-45b4e1bd-39ec-488e-a1c3-582e9eff873b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622118206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_byte_transfer.622118206
Directory /workspace/39.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2330684362
Short name T866
Test name
Test status
Simulation time 301766316 ps
CPU time 3.76 seconds
Started Jan 17 03:36:11 PM PST 24
Finished Jan 17 03:36:16 PM PST 24
Peak memory 241660 kb
Host smart-26286aaa-3cad-4853-9f26-3ad79351afc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330684362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2330684362
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1617179879
Short name T510
Test name
Test status
Simulation time 75173017 ps
CPU time 0.77 seconds
Started Jan 17 03:36:08 PM PST 24
Finished Jan 17 03:36:10 PM PST 24
Peak memory 206936 kb
Host smart-f403c23b-776c-4384-b493-52f2caac84c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617179879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1617179879
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_dummy_item_extra_dly.1915651921
Short name T1613
Test name
Test status
Simulation time 68748490912 ps
CPU time 475.5 seconds
Started Jan 17 03:36:04 PM PST 24
Finished Jan 17 03:44:01 PM PST 24
Peak memory 311536 kb
Host smart-22f60971-2a31-4737-8fe5-77ab2407ce80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915651921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_dummy_item_extra_dly.1915651921
Directory /workspace/39.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/39.spi_device_extreme_fifo_size.1184164572
Short name T982
Test name
Test status
Simulation time 88045033078 ps
CPU time 1286.02 seconds
Started Jan 17 03:36:02 PM PST 24
Finished Jan 17 03:57:28 PM PST 24
Peak memory 221392 kb
Host smart-c8939e02-cf27-4763-8ff6-60c4407d6ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184164572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_extreme_fifo_size.1184164572
Directory /workspace/39.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/39.spi_device_fifo_full.1788489700
Short name T1067
Test name
Test status
Simulation time 81617184597 ps
CPU time 751.45 seconds
Started Jan 17 03:36:01 PM PST 24
Finished Jan 17 03:48:34 PM PST 24
Peak memory 268296 kb
Host smart-3e578277-6294-464d-a11f-59bcb88a38bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788489700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_fifo_full.1788489700
Directory /workspace/39.spi_device_fifo_full/latest

Test location /workspace/coverage/default/39.spi_device_fifo_underflow_overflow.3755466276
Short name T1497
Test name
Test status
Simulation time 94662827230 ps
CPU time 192.98 seconds
Started Jan 17 03:36:03 PM PST 24
Finished Jan 17 03:39:17 PM PST 24
Peak memory 318128 kb
Host smart-c92ccc22-baf6-4fc8-a212-534ef9ecbbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755466276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_fifo_underflow_overf
low.3755466276
Directory /workspace/39.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3811679899
Short name T216
Test name
Test status
Simulation time 41078170047 ps
CPU time 223.68 seconds
Started Jan 17 03:36:11 PM PST 24
Finished Jan 17 03:39:56 PM PST 24
Peak memory 257568 kb
Host smart-16dba2b6-5e51-4b05-bfaa-70098dba857c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811679899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3811679899
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.4234623713
Short name T1312
Test name
Test status
Simulation time 132578007183 ps
CPU time 524.02 seconds
Started Jan 17 03:36:14 PM PST 24
Finished Jan 17 03:44:59 PM PST 24
Peak memory 266056 kb
Host smart-5498f005-7067-4a74-b6fa-c89a24a16be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234623713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.4234623713
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.111370773
Short name T1359
Test name
Test status
Simulation time 6724383716 ps
CPU time 33.24 seconds
Started Jan 17 03:36:10 PM PST 24
Finished Jan 17 03:36:45 PM PST 24
Peak memory 240084 kb
Host smart-e475be4e-89bd-490d-89fa-aea174c51a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111370773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.111370773
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2628883147
Short name T1129
Test name
Test status
Simulation time 1297578066 ps
CPU time 5.83 seconds
Started Jan 17 03:36:12 PM PST 24
Finished Jan 17 03:36:20 PM PST 24
Peak memory 219776 kb
Host smart-783814ce-d1c1-488a-b485-ef6a99bed73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628883147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2628883147
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_intr.2313543592
Short name T571
Test name
Test status
Simulation time 22501658947 ps
CPU time 84.82 seconds
Started Jan 17 03:36:06 PM PST 24
Finished Jan 17 03:37:31 PM PST 24
Peak memory 236536 kb
Host smart-f9fbaa3b-e62c-4c22-8dbf-e91523c54805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313543592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intr.2313543592
Directory /workspace/39.spi_device_intr/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1659635848
Short name T663
Test name
Test status
Simulation time 453686527 ps
CPU time 10.08 seconds
Started Jan 17 03:36:11 PM PST 24
Finished Jan 17 03:36:23 PM PST 24
Peak memory 251304 kb
Host smart-2f877d06-1778-4f55-b9b5-97a0137f6637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659635848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1659635848
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3114472866
Short name T239
Test name
Test status
Simulation time 37085276609 ps
CPU time 27.47 seconds
Started Jan 17 03:36:13 PM PST 24
Finished Jan 17 03:36:42 PM PST 24
Peak memory 244508 kb
Host smart-c8152391-b2f5-4ac0-9454-8d25ea096741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114472866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3114472866
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3354399034
Short name T218
Test name
Test status
Simulation time 17809358482 ps
CPU time 24.71 seconds
Started Jan 17 03:36:14 PM PST 24
Finished Jan 17 03:36:40 PM PST 24
Peak memory 225460 kb
Host smart-0ccdf570-34cd-408a-83ad-c0a43634e170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354399034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3354399034
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_perf.1516617992
Short name T57
Test name
Test status
Simulation time 24454850079 ps
CPU time 779.34 seconds
Started Jan 17 03:36:07 PM PST 24
Finished Jan 17 03:49:07 PM PST 24
Peak memory 265952 kb
Host smart-029bf7cf-b01d-42e4-a6c5-8e8b4a3a03a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516617992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_perf.1516617992
Directory /workspace/39.spi_device_perf/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1240723321
Short name T1239
Test name
Test status
Simulation time 213388088 ps
CPU time 4.99 seconds
Started Jan 17 03:36:16 PM PST 24
Finished Jan 17 03:36:36 PM PST 24
Peak memory 236584 kb
Host smart-992a2d10-4ac4-43b9-b146-52ed3dbbcf48
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1240723321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1240723321
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_rx_async_fifo_reset.2801274347
Short name T122
Test name
Test status
Simulation time 69482238 ps
CPU time 0.95 seconds
Started Jan 17 03:36:03 PM PST 24
Finished Jan 17 03:36:04 PM PST 24
Peak memory 208824 kb
Host smart-cf02d43b-2712-4171-8468-ad7f9f68b9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801274347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_rx_async_fifo_reset.2801274347
Directory /workspace/39.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/39.spi_device_rx_timeout.2052923276
Short name T112
Test name
Test status
Simulation time 3056094916 ps
CPU time 5.58 seconds
Started Jan 17 03:36:06 PM PST 24
Finished Jan 17 03:36:12 PM PST 24
Peak memory 217228 kb
Host smart-aaf7a09b-7e8a-47c8-8d0e-fa367077a42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052923276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_rx_timeout.2052923276
Directory /workspace/39.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/39.spi_device_smoke.633707872
Short name T912
Test name
Test status
Simulation time 224418055 ps
CPU time 1.27 seconds
Started Jan 17 03:36:03 PM PST 24
Finished Jan 17 03:36:05 PM PST 24
Peak memory 217132 kb
Host smart-ae7bb5a9-72ac-434f-a91f-29cc7c5e9918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633707872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_smoke.633707872
Directory /workspace/39.spi_device_smoke/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2892069864
Short name T128
Test name
Test status
Simulation time 231073799434 ps
CPU time 573.22 seconds
Started Jan 17 03:36:12 PM PST 24
Finished Jan 17 03:45:47 PM PST 24
Peak memory 335764 kb
Host smart-a6ea4e45-16db-42f1-b039-24ae8e951654
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892069864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2892069864
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.398731656
Short name T1137
Test name
Test status
Simulation time 17709682571 ps
CPU time 35.36 seconds
Started Jan 17 03:36:08 PM PST 24
Finished Jan 17 03:36:43 PM PST 24
Peak memory 217312 kb
Host smart-393a70de-e671-42d5-9f99-38085c0a8943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398731656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.398731656
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2900485670
Short name T696
Test name
Test status
Simulation time 6467802883 ps
CPU time 11.3 seconds
Started Jan 17 03:36:07 PM PST 24
Finished Jan 17 03:36:18 PM PST 24
Peak memory 217208 kb
Host smart-b53cd79c-38ba-483c-808b-557d220aa2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900485670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2900485670
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.356841653
Short name T1727
Test name
Test status
Simulation time 77125409 ps
CPU time 1.61 seconds
Started Jan 17 03:36:08 PM PST 24
Finished Jan 17 03:36:10 PM PST 24
Peak memory 217440 kb
Host smart-14f9f48e-1d16-4685-a609-c74aeb53095f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356841653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.356841653
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1551591228
Short name T1306
Test name
Test status
Simulation time 173036725 ps
CPU time 1.07 seconds
Started Jan 17 03:36:08 PM PST 24
Finished Jan 17 03:36:10 PM PST 24
Peak memory 208388 kb
Host smart-24c505e6-6ff9-46c5-8267-500930ca07b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551591228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1551591228
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_tx_async_fifo_reset.1595407262
Short name T547
Test name
Test status
Simulation time 53730488 ps
CPU time 0.77 seconds
Started Jan 17 03:36:09 PM PST 24
Finished Jan 17 03:36:10 PM PST 24
Peak memory 208776 kb
Host smart-1c52c649-fe88-45fa-913a-e0d34aa43b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595407262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tx_async_fifo_reset.1595407262
Directory /workspace/39.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/39.spi_device_txrx.2716798206
Short name T1073
Test name
Test status
Simulation time 310151360113 ps
CPU time 2592.53 seconds
Started Jan 17 03:36:01 PM PST 24
Finished Jan 17 04:19:14 PM PST 24
Peak memory 273708 kb
Host smart-f8074702-2b53-495d-8377-12d356891bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716798206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_txrx.2716798206
Directory /workspace/39.spi_device_txrx/latest

Test location /workspace/coverage/default/39.spi_device_upload.2400757583
Short name T1724
Test name
Test status
Simulation time 6881249405 ps
CPU time 21.66 seconds
Started Jan 17 03:36:17 PM PST 24
Finished Jan 17 03:36:53 PM PST 24
Peak memory 241176 kb
Host smart-a5c1f7e3-9b8c-45c3-97c2-62cb6c65bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400757583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2400757583
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_abort.1921959795
Short name T801
Test name
Test status
Simulation time 45702987 ps
CPU time 0.77 seconds
Started Jan 17 03:29:19 PM PST 24
Finished Jan 17 03:29:21 PM PST 24
Peak memory 206944 kb
Host smart-519ea893-ec55-4e4c-a5f8-e1305587578a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921959795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_abort.1921959795
Directory /workspace/4.spi_device_abort/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.518112104
Short name T101
Test name
Test status
Simulation time 13731941 ps
CPU time 0.71 seconds
Started Jan 17 03:29:25 PM PST 24
Finished Jan 17 03:29:31 PM PST 24
Peak memory 206812 kb
Host smart-41442685-fc65-4f56-ad61-e00e0d802b4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518112104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.518112104
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_bit_transfer.3147470028
Short name T1166
Test name
Test status
Simulation time 1110109411 ps
CPU time 2.93 seconds
Started Jan 17 03:29:21 PM PST 24
Finished Jan 17 03:29:26 PM PST 24
Peak memory 217204 kb
Host smart-08c3b7e2-e8ca-4ad3-857b-45b94d88634b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147470028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_bit_transfer.3147470028
Directory /workspace/4.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/4.spi_device_byte_transfer.3682804765
Short name T1464
Test name
Test status
Simulation time 125305032 ps
CPU time 2.69 seconds
Started Jan 17 03:29:18 PM PST 24
Finished Jan 17 03:29:23 PM PST 24
Peak memory 217116 kb
Host smart-9710b9a6-c5ee-4996-8274-fd4b462b515a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682804765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_byte_transfer.3682804765
Directory /workspace/4.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3333413664
Short name T1091
Test name
Test status
Simulation time 395811209 ps
CPU time 3.77 seconds
Started Jan 17 03:29:20 PM PST 24
Finished Jan 17 03:29:26 PM PST 24
Peak memory 238336 kb
Host smart-52122612-7063-44ff-954f-5de0ad3c6579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333413664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3333413664
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.264478469
Short name T652
Test name
Test status
Simulation time 19161300 ps
CPU time 0.86 seconds
Started Jan 17 03:29:22 PM PST 24
Finished Jan 17 03:29:24 PM PST 24
Peak memory 207936 kb
Host smart-451a10ae-b39d-4587-8b1d-663c5b1e3800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264478469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.264478469
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_dummy_item_extra_dly.969808126
Short name T1437
Test name
Test status
Simulation time 43663943658 ps
CPU time 377.81 seconds
Started Jan 17 03:29:21 PM PST 24
Finished Jan 17 03:35:41 PM PST 24
Peak memory 232656 kb
Host smart-6d891098-a184-4f64-b3ff-b33e14391203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969808126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_dummy_item_extra_dly.969808126
Directory /workspace/4.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/4.spi_device_fifo_full.820494854
Short name T1084
Test name
Test status
Simulation time 209132357424 ps
CPU time 1113.08 seconds
Started Jan 17 03:29:11 PM PST 24
Finished Jan 17 03:47:45 PM PST 24
Peak memory 271560 kb
Host smart-63c15559-6ca2-4b59-9fea-e7f79f0ef5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820494854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_fifo_full.820494854
Directory /workspace/4.spi_device_fifo_full/latest

Test location /workspace/coverage/default/4.spi_device_fifo_underflow_overflow.2507913875
Short name T778
Test name
Test status
Simulation time 62892089536 ps
CPU time 343.61 seconds
Started Jan 17 03:29:20 PM PST 24
Finished Jan 17 03:35:05 PM PST 24
Peak memory 350664 kb
Host smart-049c3a2f-df6f-40ff-bbb7-6bb000c8f89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507913875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_fifo_underflow_overfl
ow.2507913875
Directory /workspace/4.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1369607657
Short name T1722
Test name
Test status
Simulation time 7993354194 ps
CPU time 137.92 seconds
Started Jan 17 03:29:23 PM PST 24
Finished Jan 17 03:31:42 PM PST 24
Peak memory 266452 kb
Host smart-100b54e0-5bc5-438d-8f27-49d4a2dc305d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369607657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1369607657
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1637249555
Short name T1527
Test name
Test status
Simulation time 3741920753 ps
CPU time 53.13 seconds
Started Jan 17 03:29:25 PM PST 24
Finished Jan 17 03:30:24 PM PST 24
Peak memory 253868 kb
Host smart-ac7b9a73-e9ee-42c6-b7df-172d3feeb0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637249555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1637249555
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3982676489
Short name T1386
Test name
Test status
Simulation time 23960069437 ps
CPU time 67.53 seconds
Started Jan 17 03:29:21 PM PST 24
Finished Jan 17 03:30:31 PM PST 24
Peak memory 258128 kb
Host smart-db849374-5617-4845-85ac-899743718c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982676489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3982676489
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.394450615
Short name T936
Test name
Test status
Simulation time 2023065471 ps
CPU time 10.48 seconds
Started Jan 17 03:29:20 PM PST 24
Finished Jan 17 03:29:32 PM PST 24
Peak memory 239172 kb
Host smart-4ac42efb-eea6-4e1d-927a-102fcafee6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394450615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.394450615
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_intr.307529787
Short name T859
Test name
Test status
Simulation time 19052764332 ps
CPU time 26.61 seconds
Started Jan 17 03:29:19 PM PST 24
Finished Jan 17 03:29:47 PM PST 24
Peak memory 232372 kb
Host smart-358d787f-3ca0-4b69-a509-def21a10030d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307529787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intr.307529787
Directory /workspace/4.spi_device_intr/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.430413028
Short name T919
Test name
Test status
Simulation time 6844236070 ps
CPU time 8.17 seconds
Started Jan 17 03:29:17 PM PST 24
Finished Jan 17 03:29:26 PM PST 24
Peak memory 230944 kb
Host smart-0300776a-246f-4024-85fa-f34ac3cd3456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430413028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.430413028
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3672026322
Short name T671
Test name
Test status
Simulation time 65333839 ps
CPU time 1.08 seconds
Started Jan 17 03:29:25 PM PST 24
Finished Jan 17 03:29:32 PM PST 24
Peak memory 219088 kb
Host smart-ccbd2935-a0f8-4455-ab42-1fe4e7370d62
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672026322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3672026322
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3174119190
Short name T333
Test name
Test status
Simulation time 7195747330 ps
CPU time 13.43 seconds
Started Jan 17 03:29:22 PM PST 24
Finished Jan 17 03:29:37 PM PST 24
Peak memory 221332 kb
Host smart-22d30545-7dab-41d5-8625-9efa648afc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174119190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3174119190
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2479111936
Short name T1004
Test name
Test status
Simulation time 229718213 ps
CPU time 3.02 seconds
Started Jan 17 03:29:22 PM PST 24
Finished Jan 17 03:29:26 PM PST 24
Peak memory 218888 kb
Host smart-9f554689-b596-40f1-ae0e-bc44c38ef6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479111936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2479111936
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_perf.2384683235
Short name T1603
Test name
Test status
Simulation time 12986795856 ps
CPU time 88.12 seconds
Started Jan 17 03:29:20 PM PST 24
Finished Jan 17 03:30:50 PM PST 24
Peak memory 253052 kb
Host smart-eceb103f-3dc4-4a47-b925-97a056ca0bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384683235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_perf.2384683235
Directory /workspace/4.spi_device_perf/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.315246701
Short name T89
Test name
Test status
Simulation time 20390170 ps
CPU time 0.77 seconds
Started Jan 17 03:29:21 PM PST 24
Finished Jan 17 03:29:23 PM PST 24
Peak memory 217044 kb
Host smart-999719b4-7c68-46be-96b9-a7189d65dcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315246701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.315246701
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1908917623
Short name T845
Test name
Test status
Simulation time 1027099089 ps
CPU time 3.87 seconds
Started Jan 17 03:29:23 PM PST 24
Finished Jan 17 03:29:33 PM PST 24
Peak memory 234456 kb
Host smart-623587e8-0e4f-4050-a5fe-bfa09f7782ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1908917623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1908917623
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_rx_async_fifo_reset.2404073604
Short name T1354
Test name
Test status
Simulation time 37057608 ps
CPU time 0.97 seconds
Started Jan 17 03:29:21 PM PST 24
Finished Jan 17 03:29:24 PM PST 24
Peak memory 208768 kb
Host smart-bdb8a384-6951-4e64-8d7a-b96d707e8da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404073604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_rx_async_fifo_reset.2404073604
Directory /workspace/4.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/4.spi_device_rx_timeout.1791653354
Short name T1097
Test name
Test status
Simulation time 1563459198 ps
CPU time 6.92 seconds
Started Jan 17 03:29:21 PM PST 24
Finished Jan 17 03:29:30 PM PST 24
Peak memory 217120 kb
Host smart-6c906e71-4b7a-4da0-90bf-0b6d3eb318ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791653354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_rx_timeout.1791653354
Directory /workspace/4.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.4182372035
Short name T94
Test name
Test status
Simulation time 137109912 ps
CPU time 0.99 seconds
Started Jan 17 03:29:28 PM PST 24
Finished Jan 17 03:29:32 PM PST 24
Peak memory 238284 kb
Host smart-0cdef786-6918-4ec8-8b8b-ef567b98f257
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182372035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.4182372035
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_smoke.2026358154
Short name T45
Test name
Test status
Simulation time 67744744 ps
CPU time 0.93 seconds
Started Jan 17 03:29:14 PM PST 24
Finished Jan 17 03:29:16 PM PST 24
Peak memory 208268 kb
Host smart-fc3e0a42-79de-41e9-ba08-18ce948a6895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026358154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_smoke.2026358154
Directory /workspace/4.spi_device_smoke/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.389134799
Short name T865
Test name
Test status
Simulation time 3605141396 ps
CPU time 17.53 seconds
Started Jan 17 03:29:18 PM PST 24
Finished Jan 17 03:29:37 PM PST 24
Peak memory 217484 kb
Host smart-b6b35ed0-d969-4490-a5a6-bb7e733b4e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389134799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.389134799
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1625788567
Short name T1726
Test name
Test status
Simulation time 18101176789 ps
CPU time 25.25 seconds
Started Jan 17 03:29:21 PM PST 24
Finished Jan 17 03:29:49 PM PST 24
Peak memory 217200 kb
Host smart-24416337-bef3-4571-842e-d4df739892d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625788567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1625788567
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1169389526
Short name T1704
Test name
Test status
Simulation time 67878444 ps
CPU time 1.44 seconds
Started Jan 17 03:29:19 PM PST 24
Finished Jan 17 03:29:22 PM PST 24
Peak memory 217088 kb
Host smart-7f2beef7-8802-429a-b02b-c25bdfc353d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169389526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1169389526
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3811928766
Short name T1175
Test name
Test status
Simulation time 22678343 ps
CPU time 0.71 seconds
Started Jan 17 03:29:21 PM PST 24
Finished Jan 17 03:29:24 PM PST 24
Peak memory 207276 kb
Host smart-5f182c0d-c789-441d-a8d5-2990e6928a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811928766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3811928766
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_tx_async_fifo_reset.4213382839
Short name T1080
Test name
Test status
Simulation time 81279433 ps
CPU time 0.79 seconds
Started Jan 17 03:29:20 PM PST 24
Finished Jan 17 03:29:23 PM PST 24
Peak memory 208804 kb
Host smart-241ac4a8-3b01-435c-8de2-dd1accb2f9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213382839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tx_async_fifo_reset.4213382839
Directory /workspace/4.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/4.spi_device_txrx.4055203901
Short name T1246
Test name
Test status
Simulation time 138859596504 ps
CPU time 295.93 seconds
Started Jan 17 03:29:15 PM PST 24
Finished Jan 17 03:34:12 PM PST 24
Peak memory 299064 kb
Host smart-845ade83-d57f-45d6-a53a-9270d02ba97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055203901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_txrx.4055203901
Directory /workspace/4.spi_device_txrx/latest

Test location /workspace/coverage/default/4.spi_device_upload.3137899825
Short name T1248
Test name
Test status
Simulation time 3707906509 ps
CPU time 13.95 seconds
Started Jan 17 03:29:23 PM PST 24
Finished Jan 17 03:29:44 PM PST 24
Peak memory 219144 kb
Host smart-b7fa3f6d-db7b-4b57-bca8-35d76ce0a0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137899825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3137899825
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_abort.2436730725
Short name T525
Test name
Test status
Simulation time 22470507 ps
CPU time 0.77 seconds
Started Jan 17 03:36:22 PM PST 24
Finished Jan 17 03:36:31 PM PST 24
Peak memory 207016 kb
Host smart-1b1244a0-4aa0-47af-b26f-871ea59fb2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436730725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_abort.2436730725
Directory /workspace/40.spi_device_abort/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3484510967
Short name T726
Test name
Test status
Simulation time 13252305 ps
CPU time 0.75 seconds
Started Jan 17 03:36:35 PM PST 24
Finished Jan 17 03:36:36 PM PST 24
Peak memory 206820 kb
Host smart-2311270c-70d5-4a20-a354-3c69cdd24fe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484510967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3484510967
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_bit_transfer.38529242
Short name T1522
Test name
Test status
Simulation time 1004755007 ps
CPU time 2.55 seconds
Started Jan 17 03:36:29 PM PST 24
Finished Jan 17 03:36:35 PM PST 24
Peak memory 217148 kb
Host smart-23973108-01b3-4f82-b454-11c8afe3676f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38529242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_bit_transfer.38529242
Directory /workspace/40.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/40.spi_device_byte_transfer.903829026
Short name T481
Test name
Test status
Simulation time 134198305 ps
CPU time 3.04 seconds
Started Jan 17 03:36:19 PM PST 24
Finished Jan 17 03:36:34 PM PST 24
Peak memory 217184 kb
Host smart-e45c0b82-ed23-4509-b18d-5699b8338065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903829026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_byte_transfer.903829026
Directory /workspace/40.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1737241853
Short name T1232
Test name
Test status
Simulation time 7365029304 ps
CPU time 4.26 seconds
Started Jan 17 03:36:19 PM PST 24
Finished Jan 17 03:36:35 PM PST 24
Peak memory 219736 kb
Host smart-75772ec8-6ed0-46d9-9f58-ce948bca189d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737241853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1737241853
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3218957413
Short name T992
Test name
Test status
Simulation time 27931317 ps
CPU time 0.76 seconds
Started Jan 17 03:36:24 PM PST 24
Finished Jan 17 03:36:32 PM PST 24
Peak memory 206880 kb
Host smart-03088c26-4861-4d6b-907f-76b454b58d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218957413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3218957413
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_dummy_item_extra_dly.2296460442
Short name T583
Test name
Test status
Simulation time 205175175130 ps
CPU time 464.7 seconds
Started Jan 17 03:36:20 PM PST 24
Finished Jan 17 03:44:15 PM PST 24
Peak memory 278764 kb
Host smart-326823fe-988b-4851-82bf-dd7ce364f45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296460442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_dummy_item_extra_dly.2296460442
Directory /workspace/40.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/40.spi_device_extreme_fifo_size.1702710445
Short name T1300
Test name
Test status
Simulation time 182141408480 ps
CPU time 586.04 seconds
Started Jan 17 03:36:17 PM PST 24
Finished Jan 17 03:46:17 PM PST 24
Peak memory 218328 kb
Host smart-ae4680a5-fe62-4c1a-89cf-3305d07556d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702710445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_extreme_fifo_size.1702710445
Directory /workspace/40.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/40.spi_device_fifo_full.3606910745
Short name T636
Test name
Test status
Simulation time 54602017714 ps
CPU time 810.13 seconds
Started Jan 17 03:36:22 PM PST 24
Finished Jan 17 03:50:01 PM PST 24
Peak memory 268532 kb
Host smart-2b02a332-82b2-442b-add2-a3e725660433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606910745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_fifo_full.3606910745
Directory /workspace/40.spi_device_fifo_full/latest

Test location /workspace/coverage/default/40.spi_device_fifo_underflow_overflow.618027307
Short name T667
Test name
Test status
Simulation time 14891693853 ps
CPU time 195.1 seconds
Started Jan 17 03:36:15 PM PST 24
Finished Jan 17 03:39:43 PM PST 24
Peak memory 334576 kb
Host smart-8fba9e81-8441-44b4-adfb-b303ee441230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618027307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_fifo_underflow_overfl
ow.618027307
Directory /workspace/40.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2017385937
Short name T274
Test name
Test status
Simulation time 12900701067 ps
CPU time 96.88 seconds
Started Jan 17 03:36:31 PM PST 24
Finished Jan 17 03:38:09 PM PST 24
Peak memory 267772 kb
Host smart-176ab4f5-ff4b-450e-bdba-7c2384fa2f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017385937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2017385937
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.4051354476
Short name T1528
Test name
Test status
Simulation time 107953705342 ps
CPU time 181.91 seconds
Started Jan 17 03:36:32 PM PST 24
Finished Jan 17 03:39:34 PM PST 24
Peak memory 251092 kb
Host smart-e575efc5-3c6f-4894-abaa-cd867eab8b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051354476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.4051354476
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2165521933
Short name T66
Test name
Test status
Simulation time 36407522538 ps
CPU time 164.52 seconds
Started Jan 17 03:36:31 PM PST 24
Finished Jan 17 03:39:17 PM PST 24
Peak memory 260360 kb
Host smart-617ce115-9695-46eb-abdc-fe6f40480bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165521933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2165521933
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3512159868
Short name T1366
Test name
Test status
Simulation time 3753415973 ps
CPU time 16.26 seconds
Started Jan 17 03:36:23 PM PST 24
Finished Jan 17 03:36:47 PM PST 24
Peak memory 249820 kb
Host smart-89fd695a-8af5-4ccd-a378-e28daaf79a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512159868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3512159868
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3267279465
Short name T615
Test name
Test status
Simulation time 3288132503 ps
CPU time 5.55 seconds
Started Jan 17 03:36:23 PM PST 24
Finished Jan 17 03:36:37 PM PST 24
Peak memory 239004 kb
Host smart-cf6e950c-80b2-4b3d-8f5f-e6c5c1a61288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267279465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3267279465
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_intr.4224197358
Short name T1241
Test name
Test status
Simulation time 29197246589 ps
CPU time 57.96 seconds
Started Jan 17 03:36:18 PM PST 24
Finished Jan 17 03:37:29 PM PST 24
Peak memory 239312 kb
Host smart-85eacb31-c99c-45b3-bd4f-95e1ee78b2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224197358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intr.4224197358
Directory /workspace/40.spi_device_intr/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.927374427
Short name T304
Test name
Test status
Simulation time 15626158050 ps
CPU time 15.49 seconds
Started Jan 17 03:36:24 PM PST 24
Finished Jan 17 03:36:46 PM PST 24
Peak memory 240652 kb
Host smart-43cc3115-39a4-4178-ac19-228a55a4e7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927374427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.927374427
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1828143858
Short name T100
Test name
Test status
Simulation time 2510145010 ps
CPU time 11.34 seconds
Started Jan 17 03:36:19 PM PST 24
Finished Jan 17 03:36:42 PM PST 24
Peak memory 219484 kb
Host smart-7de11c1a-7622-41a6-a64e-3f176626e63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828143858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1828143858
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1372860357
Short name T291
Test name
Test status
Simulation time 6328596625 ps
CPU time 11.03 seconds
Started Jan 17 03:36:21 PM PST 24
Finished Jan 17 03:36:42 PM PST 24
Peak memory 220672 kb
Host smart-b8ebdd45-78c5-4ee0-886a-57a33cc1f181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372860357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1372860357
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_perf.2355704091
Short name T1441
Test name
Test status
Simulation time 23595663312 ps
CPU time 483.04 seconds
Started Jan 17 03:36:13 PM PST 24
Finished Jan 17 03:44:18 PM PST 24
Peak memory 257536 kb
Host smart-204b495b-e0c0-4e4c-8f6f-722b00e7fb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355704091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_perf.2355704091
Directory /workspace/40.spi_device_perf/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1395758097
Short name T170
Test name
Test status
Simulation time 7827212446 ps
CPU time 5.19 seconds
Started Jan 17 03:36:20 PM PST 24
Finished Jan 17 03:36:36 PM PST 24
Peak memory 220404 kb
Host smart-f96bd617-961e-4518-a0ce-8cbb4df14323
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1395758097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1395758097
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_rx_async_fifo_reset.326207246
Short name T888
Test name
Test status
Simulation time 25109601 ps
CPU time 0.85 seconds
Started Jan 17 03:36:29 PM PST 24
Finished Jan 17 03:36:33 PM PST 24
Peak memory 208996 kb
Host smart-075df433-ef69-41ae-a4cc-000476cbfafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326207246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_rx_async_fifo_reset.326207246
Directory /workspace/40.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/40.spi_device_rx_timeout.3074732745
Short name T584
Test name
Test status
Simulation time 816778546 ps
CPU time 6.28 seconds
Started Jan 17 03:36:17 PM PST 24
Finished Jan 17 03:36:37 PM PST 24
Peak memory 217108 kb
Host smart-13558e9b-5ded-4ed1-a97f-71737fa112fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074732745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_rx_timeout.3074732745
Directory /workspace/40.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/40.spi_device_smoke.3452924875
Short name T1612
Test name
Test status
Simulation time 89429531 ps
CPU time 1.08 seconds
Started Jan 17 03:36:10 PM PST 24
Finished Jan 17 03:36:13 PM PST 24
Peak memory 208716 kb
Host smart-246af44e-4929-4c92-b046-a7ae847181c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452924875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_smoke.3452924875
Directory /workspace/40.spi_device_smoke/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3749575995
Short name T1511
Test name
Test status
Simulation time 1385244102 ps
CPU time 4.31 seconds
Started Jan 17 03:36:17 PM PST 24
Finished Jan 17 03:36:35 PM PST 24
Peak memory 217364 kb
Host smart-089090ce-63d7-47a9-9793-a02cac7cc914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749575995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3749575995
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3741760585
Short name T1564
Test name
Test status
Simulation time 8339562067 ps
CPU time 25.12 seconds
Started Jan 17 03:36:19 PM PST 24
Finished Jan 17 03:36:56 PM PST 24
Peak memory 217216 kb
Host smart-eea51e51-1067-4664-8eea-22d5cb5d1368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741760585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3741760585
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1266030726
Short name T1563
Test name
Test status
Simulation time 662954869 ps
CPU time 3.21 seconds
Started Jan 17 03:36:19 PM PST 24
Finished Jan 17 03:36:34 PM PST 24
Peak memory 217124 kb
Host smart-2882a264-b027-4418-a0db-7c96446638c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266030726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1266030726
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2821784351
Short name T1671
Test name
Test status
Simulation time 36419819 ps
CPU time 0.71 seconds
Started Jan 17 03:36:17 PM PST 24
Finished Jan 17 03:36:31 PM PST 24
Peak memory 207240 kb
Host smart-fee5c006-73d1-486f-940f-0534abc4c512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821784351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2821784351
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_tx_async_fifo_reset.3628441279
Short name T1085
Test name
Test status
Simulation time 22525154 ps
CPU time 0.8 seconds
Started Jan 17 03:36:19 PM PST 24
Finished Jan 17 03:36:31 PM PST 24
Peak memory 208804 kb
Host smart-a17ea0c1-77b2-4288-a3a3-ed1ccbc7704c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628441279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tx_async_fifo_reset.3628441279
Directory /workspace/40.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/40.spi_device_txrx.3288071218
Short name T1429
Test name
Test status
Simulation time 31942720218 ps
CPU time 259.89 seconds
Started Jan 17 03:36:16 PM PST 24
Finished Jan 17 03:40:51 PM PST 24
Peak memory 312188 kb
Host smart-0751acd8-8593-48ce-b9cc-beb9620c890b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288071218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_txrx.3288071218
Directory /workspace/40.spi_device_txrx/latest

Test location /workspace/coverage/default/40.spi_device_upload.1120642844
Short name T926
Test name
Test status
Simulation time 5364599951 ps
CPU time 19.45 seconds
Started Jan 17 03:36:26 PM PST 24
Finished Jan 17 03:36:50 PM PST 24
Peak memory 220264 kb
Host smart-11b4d280-423c-4425-a4de-906df6207110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120642844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1120642844
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_abort.876811698
Short name T1574
Test name
Test status
Simulation time 20184865 ps
CPU time 0.75 seconds
Started Jan 17 03:36:46 PM PST 24
Finished Jan 17 03:36:48 PM PST 24
Peak memory 207016 kb
Host smart-26b3e2fd-b37f-4d80-9875-1fa3290fcd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876811698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_abort.876811698
Directory /workspace/41.spi_device_abort/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3982184062
Short name T82
Test name
Test status
Simulation time 13812778 ps
CPU time 0.71 seconds
Started Jan 17 03:36:57 PM PST 24
Finished Jan 17 03:37:00 PM PST 24
Peak memory 206788 kb
Host smart-d43489ef-bebe-4665-81cf-5fd96091288a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982184062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3982184062
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_bit_transfer.2767500138
Short name T616
Test name
Test status
Simulation time 1129996982 ps
CPU time 2.14 seconds
Started Jan 17 03:36:33 PM PST 24
Finished Jan 17 03:36:36 PM PST 24
Peak memory 217160 kb
Host smart-2f4c4ad5-9e52-4bd4-89f7-8518ddac1460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767500138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_bit_transfer.2767500138
Directory /workspace/41.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/41.spi_device_byte_transfer.1853890823
Short name T563
Test name
Test status
Simulation time 630227048 ps
CPU time 2.75 seconds
Started Jan 17 03:36:32 PM PST 24
Finished Jan 17 03:36:35 PM PST 24
Peak memory 217068 kb
Host smart-7e4c9e3b-1226-4b27-baae-b3da641b113b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853890823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_byte_transfer.1853890823
Directory /workspace/41.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2922142893
Short name T731
Test name
Test status
Simulation time 186568408 ps
CPU time 2.83 seconds
Started Jan 17 03:36:51 PM PST 24
Finished Jan 17 03:37:00 PM PST 24
Peak memory 219172 kb
Host smart-bcc3c364-cf37-4b4f-92a0-594b643a45ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922142893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2922142893
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.862434429
Short name T513
Test name
Test status
Simulation time 21787823 ps
CPU time 0.79 seconds
Started Jan 17 03:36:34 PM PST 24
Finished Jan 17 03:36:35 PM PST 24
Peak memory 207880 kb
Host smart-acd6ff99-3069-4104-92de-5cf893b69bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862434429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.862434429
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_dummy_item_extra_dly.1944477123
Short name T1669
Test name
Test status
Simulation time 774918385986 ps
CPU time 1737.71 seconds
Started Jan 17 03:36:38 PM PST 24
Finished Jan 17 04:05:37 PM PST 24
Peak memory 284732 kb
Host smart-91c2c0bc-9d84-43f5-8314-0075f664b460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944477123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_dummy_item_extra_dly.1944477123
Directory /workspace/41.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/41.spi_device_extreme_fifo_size.2000140396
Short name T181
Test name
Test status
Simulation time 20142849037 ps
CPU time 44.5 seconds
Started Jan 17 03:36:34 PM PST 24
Finished Jan 17 03:37:19 PM PST 24
Peak memory 238720 kb
Host smart-0ed679ae-6bd8-4857-95a1-18b17f8e2d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000140396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_extreme_fifo_size.2000140396
Directory /workspace/41.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/41.spi_device_fifo_full.1340052976
Short name T182
Test name
Test status
Simulation time 8217770160 ps
CPU time 466.44 seconds
Started Jan 17 03:36:33 PM PST 24
Finished Jan 17 03:44:20 PM PST 24
Peak memory 270536 kb
Host smart-30ea65f2-2b47-4ad6-b5c1-560f3845855b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340052976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_fifo_full.1340052976
Directory /workspace/41.spi_device_fifo_full/latest

Test location /workspace/coverage/default/41.spi_device_fifo_underflow_overflow.2903305597
Short name T1625
Test name
Test status
Simulation time 202365258076 ps
CPU time 275.56 seconds
Started Jan 17 03:36:31 PM PST 24
Finished Jan 17 03:41:08 PM PST 24
Peak memory 311444 kb
Host smart-acab26e6-0df0-4b37-bf48-b3752b04f991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903305597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_fifo_underflow_overf
low.2903305597
Directory /workspace/41.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2288504154
Short name T1770
Test name
Test status
Simulation time 5540757497 ps
CPU time 56.14 seconds
Started Jan 17 03:36:53 PM PST 24
Finished Jan 17 03:37:53 PM PST 24
Peak memory 258096 kb
Host smart-9910b26b-2c1c-456e-95dc-75ba5a46359d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288504154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2288504154
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1612552129
Short name T1358
Test name
Test status
Simulation time 5117267753 ps
CPU time 54.78 seconds
Started Jan 17 03:36:53 PM PST 24
Finished Jan 17 03:37:52 PM PST 24
Peak memory 251036 kb
Host smart-88e6f340-42d6-444e-9cf2-d08c999b50f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612552129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1612552129
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3384127264
Short name T1708
Test name
Test status
Simulation time 11911514801 ps
CPU time 133.05 seconds
Started Jan 17 03:36:53 PM PST 24
Finished Jan 17 03:39:10 PM PST 24
Peak memory 274480 kb
Host smart-35c70537-6c43-4e20-a827-3f0b3abca2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384127264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3384127264
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2821207452
Short name T1033
Test name
Test status
Simulation time 5038603834 ps
CPU time 21.28 seconds
Started Jan 17 03:36:48 PM PST 24
Finished Jan 17 03:37:17 PM PST 24
Peak memory 236356 kb
Host smart-9c4416cd-3c8a-4c04-ab78-c89201823291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821207452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2821207452
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2405861195
Short name T872
Test name
Test status
Simulation time 110365099 ps
CPU time 4.01 seconds
Started Jan 17 03:36:54 PM PST 24
Finished Jan 17 03:37:01 PM PST 24
Peak memory 241260 kb
Host smart-ca130f67-df26-4e28-ab90-cc68beee9fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405861195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2405861195
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_intr.1506154849
Short name T851
Test name
Test status
Simulation time 20017037170 ps
CPU time 25.26 seconds
Started Jan 17 03:36:40 PM PST 24
Finished Jan 17 03:37:07 PM PST 24
Peak memory 224112 kb
Host smart-eaab1f2b-dfc2-4c00-8370-24008d645fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506154849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intr.1506154849
Directory /workspace/41.spi_device_intr/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1615376617
Short name T864
Test name
Test status
Simulation time 3538086239 ps
CPU time 10.29 seconds
Started Jan 17 03:36:53 PM PST 24
Finished Jan 17 03:37:07 PM PST 24
Peak memory 241500 kb
Host smart-06e21005-5281-46dc-b22d-59e7913bf0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615376617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1615376617
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1568504286
Short name T1753
Test name
Test status
Simulation time 18302600040 ps
CPU time 15.37 seconds
Started Jan 17 03:36:58 PM PST 24
Finished Jan 17 03:37:15 PM PST 24
Peak memory 219828 kb
Host smart-83d8059f-c0b8-452c-851a-2815da8680ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568504286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1568504286
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3178706646
Short name T230
Test name
Test status
Simulation time 580360660 ps
CPU time 9.38 seconds
Started Jan 17 03:36:45 PM PST 24
Finished Jan 17 03:36:57 PM PST 24
Peak memory 229868 kb
Host smart-9ef41ae5-5f88-4ac0-b5b4-61f9c20e404f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178706646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3178706646
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_perf.1894746707
Short name T740
Test name
Test status
Simulation time 99249503462 ps
CPU time 1635.28 seconds
Started Jan 17 03:36:32 PM PST 24
Finished Jan 17 04:03:48 PM PST 24
Peak memory 305724 kb
Host smart-5679076b-6261-43d0-958c-23a529576b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894746707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_perf.1894746707
Directory /workspace/41.spi_device_perf/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.960695493
Short name T1234
Test name
Test status
Simulation time 7254592005 ps
CPU time 6.81 seconds
Started Jan 17 03:36:46 PM PST 24
Finished Jan 17 03:36:55 PM PST 24
Peak memory 220768 kb
Host smart-1988e4ab-6895-47ba-a698-51f211142c86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=960695493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.960695493
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_rx_async_fifo_reset.3228182444
Short name T125
Test name
Test status
Simulation time 26800034 ps
CPU time 0.88 seconds
Started Jan 17 03:36:32 PM PST 24
Finished Jan 17 03:36:34 PM PST 24
Peak memory 208764 kb
Host smart-099e3f10-cc34-46e6-8686-a07b398b43ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228182444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_rx_async_fifo_reset.3228182444
Directory /workspace/41.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/41.spi_device_rx_timeout.1900189357
Short name T1180
Test name
Test status
Simulation time 811550214 ps
CPU time 6.21 seconds
Started Jan 17 03:36:38 PM PST 24
Finished Jan 17 03:36:45 PM PST 24
Peak memory 217112 kb
Host smart-e86d4556-6d9b-4816-902e-e140815af62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900189357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_rx_timeout.1900189357
Directory /workspace/41.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/41.spi_device_smoke.3071450130
Short name T604
Test name
Test status
Simulation time 37722792 ps
CPU time 1.17 seconds
Started Jan 17 03:36:34 PM PST 24
Finished Jan 17 03:36:35 PM PST 24
Peak memory 216968 kb
Host smart-4db8a89f-6a3b-42eb-bec8-342ca817723b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071450130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_smoke.3071450130
Directory /workspace/41.spi_device_smoke/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1712706089
Short name T1398
Test name
Test status
Simulation time 62810761691 ps
CPU time 1168.64 seconds
Started Jan 17 03:36:50 PM PST 24
Finished Jan 17 03:56:26 PM PST 24
Peak memory 334136 kb
Host smart-2d3418ae-415f-4d85-b6ee-a2f8719b5e02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712706089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1712706089
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.967238092
Short name T358
Test name
Test status
Simulation time 6539565653 ps
CPU time 59.5 seconds
Started Jan 17 03:36:33 PM PST 24
Finished Jan 17 03:37:33 PM PST 24
Peak memory 217216 kb
Host smart-152b58e9-a490-4912-9730-65ab393fba6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967238092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.967238092
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.371545616
Short name T1112
Test name
Test status
Simulation time 9205044232 ps
CPU time 24.68 seconds
Started Jan 17 03:36:36 PM PST 24
Finished Jan 17 03:37:01 PM PST 24
Peak memory 217168 kb
Host smart-90f30c0e-abf0-4c0c-82a7-36cd4776a0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371545616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.371545616
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2936519942
Short name T1544
Test name
Test status
Simulation time 343062291 ps
CPU time 2.82 seconds
Started Jan 17 03:36:46 PM PST 24
Finished Jan 17 03:36:50 PM PST 24
Peak memory 217120 kb
Host smart-8c3b6783-57d3-4fb5-9fd3-00a314ba1c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936519942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2936519942
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3329804781
Short name T843
Test name
Test status
Simulation time 80916680 ps
CPU time 0.82 seconds
Started Jan 17 03:36:45 PM PST 24
Finished Jan 17 03:36:48 PM PST 24
Peak memory 207236 kb
Host smart-a7f033bc-f75a-4682-b5b3-13d1930503ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329804781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3329804781
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_tx_async_fifo_reset.3986658296
Short name T698
Test name
Test status
Simulation time 75115556 ps
CPU time 0.77 seconds
Started Jan 17 03:36:34 PM PST 24
Finished Jan 17 03:36:36 PM PST 24
Peak memory 208732 kb
Host smart-e2566239-3a30-4a1e-8ebf-024db0b8d70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986658296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tx_async_fifo_reset.3986658296
Directory /workspace/41.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/41.spi_device_txrx.3473721245
Short name T733
Test name
Test status
Simulation time 73604889516 ps
CPU time 149.54 seconds
Started Jan 17 03:36:33 PM PST 24
Finished Jan 17 03:39:03 PM PST 24
Peak memory 235392 kb
Host smart-d8f27917-31db-4171-b2d5-0676468f80e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473721245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_txrx.3473721245
Directory /workspace/41.spi_device_txrx/latest

Test location /workspace/coverage/default/41.spi_device_upload.1630041928
Short name T1022
Test name
Test status
Simulation time 5471522606 ps
CPU time 19.2 seconds
Started Jan 17 03:36:47 PM PST 24
Finished Jan 17 03:37:07 PM PST 24
Peak memory 246900 kb
Host smart-be075d81-26ca-4923-a436-121e4b4834a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630041928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1630041928
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_abort.3428895912
Short name T676
Test name
Test status
Simulation time 20579065 ps
CPU time 0.73 seconds
Started Jan 17 03:36:56 PM PST 24
Finished Jan 17 03:36:58 PM PST 24
Peak memory 206984 kb
Host smart-39f7df15-842c-4fe9-8078-2f78ca6057b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428895912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_abort.3428895912
Directory /workspace/42.spi_device_abort/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2996982591
Short name T488
Test name
Test status
Simulation time 11565356 ps
CPU time 0.75 seconds
Started Jan 17 03:36:59 PM PST 24
Finished Jan 17 03:37:03 PM PST 24
Peak memory 206348 kb
Host smart-1592ac7c-268a-466a-927e-b1001439276f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996982591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2996982591
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_bit_transfer.1759808221
Short name T1469
Test name
Test status
Simulation time 67708616 ps
CPU time 2.11 seconds
Started Jan 17 03:37:05 PM PST 24
Finished Jan 17 03:37:08 PM PST 24
Peak memory 217080 kb
Host smart-67c90e91-f6be-4296-91cd-b706dcdd1314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759808221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_bit_transfer.1759808221
Directory /workspace/42.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/42.spi_device_byte_transfer.3310148448
Short name T1220
Test name
Test status
Simulation time 153477112 ps
CPU time 2.76 seconds
Started Jan 17 03:37:06 PM PST 24
Finished Jan 17 03:37:09 PM PST 24
Peak memory 217104 kb
Host smart-639b7635-30bd-41f0-93bc-b0de0bb01599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310148448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_byte_transfer.3310148448
Directory /workspace/42.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.967937795
Short name T1630
Test name
Test status
Simulation time 41845678 ps
CPU time 3.02 seconds
Started Jan 17 03:36:52 PM PST 24
Finished Jan 17 03:37:00 PM PST 24
Peak memory 238644 kb
Host smart-206a493f-7282-4db7-a241-2e078c0152af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967937795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.967937795
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.227990911
Short name T1405
Test name
Test status
Simulation time 36417929 ps
CPU time 0.79 seconds
Started Jan 17 03:36:58 PM PST 24
Finished Jan 17 03:37:02 PM PST 24
Peak memory 207972 kb
Host smart-74930b98-61fd-45b4-b463-5b68b7bda245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227990911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.227990911
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_dummy_item_extra_dly.2626210196
Short name T1534
Test name
Test status
Simulation time 126823388354 ps
CPU time 592.24 seconds
Started Jan 17 03:36:50 PM PST 24
Finished Jan 17 03:46:49 PM PST 24
Peak memory 268588 kb
Host smart-4e07269f-a0e4-4dd8-9343-e1d3e7528a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626210196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_dummy_item_extra_dly.2626210196
Directory /workspace/42.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/42.spi_device_extreme_fifo_size.329509413
Short name T1716
Test name
Test status
Simulation time 16543570408 ps
CPU time 440.41 seconds
Started Jan 17 03:37:04 PM PST 24
Finished Jan 17 03:44:26 PM PST 24
Peak memory 221820 kb
Host smart-f04e72c4-7e38-4687-af48-9f1c17b8f4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329509413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_extreme_fifo_size.329509413
Directory /workspace/42.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/42.spi_device_fifo_full.2658443383
Short name T694
Test name
Test status
Simulation time 449993678733 ps
CPU time 1092.83 seconds
Started Jan 17 03:37:01 PM PST 24
Finished Jan 17 03:55:17 PM PST 24
Peak memory 288488 kb
Host smart-ea442fbb-9ca2-4bd2-ba47-eac6a282ab7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658443383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_fifo_full.2658443383
Directory /workspace/42.spi_device_fifo_full/latest

Test location /workspace/coverage/default/42.spi_device_fifo_underflow_overflow.1403314226
Short name T188
Test name
Test status
Simulation time 70560195781 ps
CPU time 420.43 seconds
Started Jan 17 03:36:58 PM PST 24
Finished Jan 17 03:44:01 PM PST 24
Peak memory 376568 kb
Host smart-042675c4-0123-4322-84e6-58588b16e87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403314226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_fifo_underflow_overf
low.1403314226
Directory /workspace/42.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3502104660
Short name T1498
Test name
Test status
Simulation time 92026945583 ps
CPU time 268.83 seconds
Started Jan 17 03:36:56 PM PST 24
Finished Jan 17 03:41:26 PM PST 24
Peak memory 258212 kb
Host smart-272d8d85-4946-46b1-bfcf-a2805e461dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502104660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3502104660
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3914866363
Short name T1494
Test name
Test status
Simulation time 1069891989 ps
CPU time 17.35 seconds
Started Jan 17 03:36:57 PM PST 24
Finished Jan 17 03:37:17 PM PST 24
Peak memory 241776 kb
Host smart-6618eb71-4ade-4f49-9d50-8e2d9af4b120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914866363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3914866363
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2754362622
Short name T286
Test name
Test status
Simulation time 3932819732 ps
CPU time 45.22 seconds
Started Jan 17 03:36:59 PM PST 24
Finished Jan 17 03:37:48 PM PST 24
Peak memory 250776 kb
Host smart-b7e3162c-7534-4ee5-ac68-f0d171188404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754362622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2754362622
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3959630539
Short name T1261
Test name
Test status
Simulation time 9535802304 ps
CPU time 28.37 seconds
Started Jan 17 03:36:58 PM PST 24
Finished Jan 17 03:37:30 PM PST 24
Peak memory 247936 kb
Host smart-a710ad0c-89b0-4034-9481-b0fbe123088e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959630539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3959630539
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1236522764
Short name T1054
Test name
Test status
Simulation time 428132815 ps
CPU time 5.97 seconds
Started Jan 17 03:36:50 PM PST 24
Finished Jan 17 03:37:03 PM PST 24
Peak memory 238512 kb
Host smart-55595287-ea95-406a-a587-360094b4b9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236522764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1236522764
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_intr.210784031
Short name T1764
Test name
Test status
Simulation time 9362126520 ps
CPU time 43.24 seconds
Started Jan 17 03:36:58 PM PST 24
Finished Jan 17 03:37:43 PM PST 24
Peak memory 233388 kb
Host smart-dc38b653-647d-43c3-bb9e-aaf58e6169db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210784031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intr.210784031
Directory /workspace/42.spi_device_intr/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.63702692
Short name T240
Test name
Test status
Simulation time 44073505518 ps
CPU time 30.52 seconds
Started Jan 17 03:36:58 PM PST 24
Finished Jan 17 03:37:32 PM PST 24
Peak memory 218384 kb
Host smart-2fa2efc8-411e-4957-a2ed-406d86e94552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63702692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.63702692
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.540846017
Short name T739
Test name
Test status
Simulation time 16031130784 ps
CPU time 8.47 seconds
Started Jan 17 03:36:51 PM PST 24
Finished Jan 17 03:37:05 PM PST 24
Peak memory 227460 kb
Host smart-ea4cd332-d9a4-4aa4-b45f-d1df6ef7b6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540846017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.540846017
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2130602964
Short name T236
Test name
Test status
Simulation time 17028943886 ps
CPU time 25.93 seconds
Started Jan 17 03:36:50 PM PST 24
Finished Jan 17 03:37:23 PM PST 24
Peak memory 241820 kb
Host smart-bed8d765-7a95-4dd2-b239-a65e0ac1d5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130602964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2130602964
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_perf.708873491
Short name T1282
Test name
Test status
Simulation time 8276407865 ps
CPU time 282.24 seconds
Started Jan 17 03:37:04 PM PST 24
Finished Jan 17 03:41:48 PM PST 24
Peak memory 285372 kb
Host smart-8dc46c45-a0bc-4ecb-a4b2-4af9df35800b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708873491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_perf.708873491
Directory /workspace/42.spi_device_perf/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.117451229
Short name T508
Test name
Test status
Simulation time 3693560616 ps
CPU time 7.75 seconds
Started Jan 17 03:36:55 PM PST 24
Finished Jan 17 03:37:05 PM PST 24
Peak memory 234736 kb
Host smart-454ddfc6-4d41-49f2-85ec-2f2ce6f52d2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=117451229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.117451229
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_rx_async_fifo_reset.1824012260
Short name T1453
Test name
Test status
Simulation time 157186818 ps
CPU time 0.94 seconds
Started Jan 17 03:37:05 PM PST 24
Finished Jan 17 03:37:07 PM PST 24
Peak memory 208724 kb
Host smart-9492ed1c-cefd-47c3-9cd3-cc86c37c7256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824012260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_rx_async_fifo_reset.1824012260
Directory /workspace/42.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/42.spi_device_rx_timeout.2582721853
Short name T1439
Test name
Test status
Simulation time 7722269867 ps
CPU time 6.7 seconds
Started Jan 17 03:36:58 PM PST 24
Finished Jan 17 03:37:08 PM PST 24
Peak memory 217136 kb
Host smart-ad6f43fa-132f-4449-8620-2efe3968e9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582721853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_rx_timeout.2582721853
Directory /workspace/42.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/42.spi_device_smoke.3824940122
Short name T1718
Test name
Test status
Simulation time 246525818 ps
CPU time 1.19 seconds
Started Jan 17 03:36:48 PM PST 24
Finished Jan 17 03:36:57 PM PST 24
Peak memory 216928 kb
Host smart-fe774d82-2cf4-4117-b1e3-406e3f973b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824940122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_smoke.3824940122
Directory /workspace/42.spi_device_smoke/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.4281546808
Short name T362
Test name
Test status
Simulation time 10632598105 ps
CPU time 166.83 seconds
Started Jan 17 03:36:54 PM PST 24
Finished Jan 17 03:39:44 PM PST 24
Peak memory 218788 kb
Host smart-134e2879-7428-489c-bd8d-842c2ca48921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281546808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.4281546808
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3934673161
Short name T1487
Test name
Test status
Simulation time 3850786783 ps
CPU time 9.14 seconds
Started Jan 17 03:36:52 PM PST 24
Finished Jan 17 03:37:06 PM PST 24
Peak memory 217216 kb
Host smart-6b5802d0-d8c7-4925-b115-9d8a87b2527b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934673161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3934673161
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2944906057
Short name T1017
Test name
Test status
Simulation time 254609529 ps
CPU time 2.49 seconds
Started Jan 17 03:36:52 PM PST 24
Finished Jan 17 03:36:59 PM PST 24
Peak memory 217180 kb
Host smart-f8db3dda-168d-44d6-8d63-70224f370ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944906057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2944906057
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.345035431
Short name T1514
Test name
Test status
Simulation time 49694239 ps
CPU time 0.99 seconds
Started Jan 17 03:36:49 PM PST 24
Finished Jan 17 03:36:58 PM PST 24
Peak memory 208296 kb
Host smart-63987b77-70a7-45d5-9975-acf5590af49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345035431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.345035431
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_tx_async_fifo_reset.1841459621
Short name T1626
Test name
Test status
Simulation time 40869769 ps
CPU time 0.78 seconds
Started Jan 17 03:36:51 PM PST 24
Finished Jan 17 03:36:58 PM PST 24
Peak memory 208784 kb
Host smart-86ac12df-0ed4-41b4-b19f-d98fe923e1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841459621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tx_async_fifo_reset.1841459621
Directory /workspace/42.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/42.spi_device_txrx.4156652466
Short name T792
Test name
Test status
Simulation time 58621906914 ps
CPU time 1385.95 seconds
Started Jan 17 03:36:54 PM PST 24
Finished Jan 17 04:00:03 PM PST 24
Peak memory 261136 kb
Host smart-c4f36ce3-823f-4025-a6f6-1004c801616e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156652466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_txrx.4156652466
Directory /workspace/42.spi_device_txrx/latest

Test location /workspace/coverage/default/42.spi_device_upload.4213211102
Short name T1505
Test name
Test status
Simulation time 52066685848 ps
CPU time 47.79 seconds
Started Jan 17 03:36:51 PM PST 24
Finished Jan 17 03:37:45 PM PST 24
Peak memory 252268 kb
Host smart-c02f9c79-9d6c-4288-b65a-048c267c8ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213211102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.4213211102
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_abort.964356941
Short name T725
Test name
Test status
Simulation time 25243161 ps
CPU time 0.76 seconds
Started Jan 17 03:37:00 PM PST 24
Finished Jan 17 03:37:04 PM PST 24
Peak memory 206948 kb
Host smart-d7ac95a9-066d-46a3-8a6c-00b27ef70b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964356941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_abort.964356941
Directory /workspace/43.spi_device_abort/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.759385709
Short name T957
Test name
Test status
Simulation time 22417823 ps
CPU time 0.73 seconds
Started Jan 17 03:37:16 PM PST 24
Finished Jan 17 03:37:18 PM PST 24
Peak memory 206768 kb
Host smart-ddadc2fd-f504-4bff-983d-f52ff51bd9b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759385709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.759385709
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_bit_transfer.3222701184
Short name T1461
Test name
Test status
Simulation time 333242363 ps
CPU time 2.79 seconds
Started Jan 17 03:37:06 PM PST 24
Finished Jan 17 03:37:09 PM PST 24
Peak memory 217196 kb
Host smart-c5fe2db7-0218-4aff-81ab-b7a3009e5612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222701184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_bit_transfer.3222701184
Directory /workspace/43.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/43.spi_device_byte_transfer.4061361117
Short name T697
Test name
Test status
Simulation time 1873856350 ps
CPU time 3.54 seconds
Started Jan 17 03:37:03 PM PST 24
Finished Jan 17 03:37:09 PM PST 24
Peak memory 217124 kb
Host smart-607d5ac2-751e-4871-b1eb-3f22d6dfca20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061361117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_byte_transfer.4061361117
Directory /workspace/43.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1593921814
Short name T282
Test name
Test status
Simulation time 705082854 ps
CPU time 3.52 seconds
Started Jan 17 03:37:12 PM PST 24
Finished Jan 17 03:37:16 PM PST 24
Peak memory 238472 kb
Host smart-7062a2c7-1fb1-483c-84af-5ce55294442e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593921814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1593921814
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3635418023
Short name T1134
Test name
Test status
Simulation time 15835454 ps
CPU time 0.79 seconds
Started Jan 17 03:37:06 PM PST 24
Finished Jan 17 03:37:07 PM PST 24
Peak memory 207912 kb
Host smart-6f2eecd8-5c0a-4c8c-a7c4-b5ba33be32af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635418023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3635418023
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_dummy_item_extra_dly.2188754134
Short name T545
Test name
Test status
Simulation time 95224242576 ps
CPU time 239.48 seconds
Started Jan 17 03:37:01 PM PST 24
Finished Jan 17 03:41:03 PM PST 24
Peak memory 250076 kb
Host smart-a2dacfcc-0646-4c19-b1bc-88e7e8353217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188754134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_dummy_item_extra_dly.2188754134
Directory /workspace/43.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/43.spi_device_extreme_fifo_size.3252663883
Short name T512
Test name
Test status
Simulation time 91582766881 ps
CPU time 1878.49 seconds
Started Jan 17 03:36:59 PM PST 24
Finished Jan 17 04:08:21 PM PST 24
Peak memory 219160 kb
Host smart-70ab8b6f-4689-4faf-8f8a-56951d77b7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252663883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_extreme_fifo_size.3252663883
Directory /workspace/43.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/43.spi_device_fifo_full.4246865963
Short name T1010
Test name
Test status
Simulation time 229359052736 ps
CPU time 692.73 seconds
Started Jan 17 03:36:52 PM PST 24
Finished Jan 17 03:48:30 PM PST 24
Peak memory 254056 kb
Host smart-892ae1df-b459-448e-a5f2-6e31581102af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246865963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_fifo_full.4246865963
Directory /workspace/43.spi_device_fifo_full/latest

Test location /workspace/coverage/default/43.spi_device_fifo_underflow_overflow.4218326712
Short name T1715
Test name
Test status
Simulation time 33396534051 ps
CPU time 195.21 seconds
Started Jan 17 03:36:57 PM PST 24
Finished Jan 17 03:40:13 PM PST 24
Peak memory 317856 kb
Host smart-75c027b0-2395-4bd7-a76b-7c87f65cecef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218326712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_fifo_underflow_overf
low.4218326712
Directory /workspace/43.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.163318019
Short name T946
Test name
Test status
Simulation time 56488961488 ps
CPU time 278.57 seconds
Started Jan 17 03:37:12 PM PST 24
Finished Jan 17 03:41:51 PM PST 24
Peak memory 266472 kb
Host smart-083ae6b5-851d-4a75-896e-9849079c2c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163318019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.163318019
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1652162764
Short name T1430
Test name
Test status
Simulation time 105759015020 ps
CPU time 232.25 seconds
Started Jan 17 03:37:15 PM PST 24
Finished Jan 17 03:41:08 PM PST 24
Peak memory 256832 kb
Host smart-7df95977-b085-4077-9ce9-f03f82f3058e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652162764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1652162764
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1826478872
Short name T258
Test name
Test status
Simulation time 65663982621 ps
CPU time 194.64 seconds
Started Jan 17 03:37:07 PM PST 24
Finished Jan 17 03:40:23 PM PST 24
Peak memory 250064 kb
Host smart-2cce2cf4-e313-4eb4-a711-4a085210bbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826478872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1826478872
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2564433963
Short name T254
Test name
Test status
Simulation time 23262048367 ps
CPU time 24.68 seconds
Started Jan 17 03:37:12 PM PST 24
Finished Jan 17 03:37:38 PM PST 24
Peak memory 232836 kb
Host smart-89d2c3b3-a980-4cd2-9e6d-9c9ab6154a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564433963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2564433963
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3803121758
Short name T1006
Test name
Test status
Simulation time 3861171312 ps
CPU time 5.26 seconds
Started Jan 17 03:37:02 PM PST 24
Finished Jan 17 03:37:09 PM PST 24
Peak memory 219060 kb
Host smart-d7c359a4-e902-4e12-b3bc-821cfbb5ef67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803121758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3803121758
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_intr.3082593859
Short name T984
Test name
Test status
Simulation time 63915391631 ps
CPU time 38.43 seconds
Started Jan 17 03:37:00 PM PST 24
Finished Jan 17 03:37:42 PM PST 24
Peak memory 221696 kb
Host smart-156fa8de-a50e-4107-8a41-3212d70e0c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082593859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intr.3082593859
Directory /workspace/43.spi_device_intr/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3167604809
Short name T634
Test name
Test status
Simulation time 3928311423 ps
CPU time 8.23 seconds
Started Jan 17 03:37:16 PM PST 24
Finished Jan 17 03:37:25 PM PST 24
Peak memory 238968 kb
Host smart-b9002d41-218c-4e1f-a79e-1fd8bdc7eb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167604809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3167604809
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.4189165820
Short name T749
Test name
Test status
Simulation time 2016932769 ps
CPU time 4.89 seconds
Started Jan 17 03:37:05 PM PST 24
Finished Jan 17 03:37:11 PM PST 24
Peak memory 241424 kb
Host smart-825c5292-ca1e-415c-8cac-b286c93f4ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189165820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.4189165820
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_perf.7777240
Short name T713
Test name
Test status
Simulation time 47117607054 ps
CPU time 992.43 seconds
Started Jan 17 03:37:02 PM PST 24
Finished Jan 17 03:53:37 PM PST 24
Peak memory 257812 kb
Host smart-0335ce47-1e65-48f7-80cd-c170559873d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7777240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_perf.7777240
Directory /workspace/43.spi_device_perf/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3288616156
Short name T166
Test name
Test status
Simulation time 342949848 ps
CPU time 4.32 seconds
Started Jan 17 03:37:16 PM PST 24
Finished Jan 17 03:37:21 PM PST 24
Peak memory 219440 kb
Host smart-a11f9310-a5bf-4693-8a0a-983498dd4894
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3288616156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3288616156
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_rx_async_fifo_reset.294709622
Short name T1608
Test name
Test status
Simulation time 23578357 ps
CPU time 0.86 seconds
Started Jan 17 03:37:03 PM PST 24
Finished Jan 17 03:37:06 PM PST 24
Peak memory 208752 kb
Host smart-20663a5f-5f1c-490d-ac40-f91032b74485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294709622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_rx_async_fifo_reset.294709622
Directory /workspace/43.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/43.spi_device_rx_timeout.4046918772
Short name T828
Test name
Test status
Simulation time 1907267086 ps
CPU time 5.35 seconds
Started Jan 17 03:37:03 PM PST 24
Finished Jan 17 03:37:10 PM PST 24
Peak memory 217392 kb
Host smart-a793b129-01aa-4f25-8e29-9d96d8daab26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046918772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_rx_timeout.4046918772
Directory /workspace/43.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/43.spi_device_smoke.2019647979
Short name T651
Test name
Test status
Simulation time 100305754 ps
CPU time 1.25 seconds
Started Jan 17 03:36:56 PM PST 24
Finished Jan 17 03:36:58 PM PST 24
Peak memory 217108 kb
Host smart-d3b69fdb-9ffb-4603-a1d3-809922b41244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019647979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_smoke.2019647979
Directory /workspace/43.spi_device_smoke/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4179718628
Short name T1090
Test name
Test status
Simulation time 38585951846 ps
CPU time 866.32 seconds
Started Jan 17 03:37:13 PM PST 24
Finished Jan 17 03:51:40 PM PST 24
Peak memory 310388 kb
Host smart-6210bcba-85e9-493d-9f5f-f86a0c53f5e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179718628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4179718628
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1361808861
Short name T355
Test name
Test status
Simulation time 3533705991 ps
CPU time 17.33 seconds
Started Jan 17 03:37:11 PM PST 24
Finished Jan 17 03:37:30 PM PST 24
Peak memory 217288 kb
Host smart-adc1db45-dbc8-4c9a-8fa4-5d9dac5a3381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361808861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1361808861
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2425479644
Short name T750
Test name
Test status
Simulation time 12717591160 ps
CPU time 13.68 seconds
Started Jan 17 03:37:01 PM PST 24
Finished Jan 17 03:37:17 PM PST 24
Peak memory 217180 kb
Host smart-6f8880bb-dc6e-43bb-9c75-ef8c0cf7caca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425479644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2425479644
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2028524427
Short name T688
Test name
Test status
Simulation time 72658535 ps
CPU time 1.4 seconds
Started Jan 17 03:37:01 PM PST 24
Finished Jan 17 03:37:05 PM PST 24
Peak memory 208912 kb
Host smart-b3fc36e1-a0dd-4f7e-9c4c-6441e0d2889a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028524427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2028524427
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2588816915
Short name T1299
Test name
Test status
Simulation time 156777877 ps
CPU time 0.79 seconds
Started Jan 17 03:37:05 PM PST 24
Finished Jan 17 03:37:07 PM PST 24
Peak memory 207292 kb
Host smart-6eca0a33-20da-4eb2-92ae-38587096f444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588816915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2588816915
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_tx_async_fifo_reset.2560394923
Short name T1768
Test name
Test status
Simulation time 17970316 ps
CPU time 0.8 seconds
Started Jan 17 03:37:03 PM PST 24
Finished Jan 17 03:37:06 PM PST 24
Peak memory 208776 kb
Host smart-4b81d241-3cb3-4a63-bb32-8931d7ccc976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560394923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tx_async_fifo_reset.2560394923
Directory /workspace/43.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/43.spi_device_txrx.2775894242
Short name T1499
Test name
Test status
Simulation time 29014800348 ps
CPU time 263.04 seconds
Started Jan 17 03:36:54 PM PST 24
Finished Jan 17 03:41:20 PM PST 24
Peak memory 241056 kb
Host smart-22f5a6c2-0e42-47e2-bac6-9efa6fa233a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775894242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_txrx.2775894242
Directory /workspace/43.spi_device_txrx/latest

Test location /workspace/coverage/default/43.spi_device_upload.462375697
Short name T283
Test name
Test status
Simulation time 1210745217 ps
CPU time 6.58 seconds
Started Jan 17 03:37:16 PM PST 24
Finished Jan 17 03:37:23 PM PST 24
Peak memory 236648 kb
Host smart-861e58bf-18eb-434e-9902-bc187c6d04c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462375697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.462375697
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_abort.1051053676
Short name T1554
Test name
Test status
Simulation time 83437946 ps
CPU time 0.76 seconds
Started Jan 17 03:37:18 PM PST 24
Finished Jan 17 03:37:20 PM PST 24
Peak memory 206948 kb
Host smart-fab06351-d88a-4b9f-aa40-02923b8bb743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051053676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_abort.1051053676
Directory /workspace/44.spi_device_abort/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2641395811
Short name T1170
Test name
Test status
Simulation time 34568389 ps
CPU time 0.74 seconds
Started Jan 17 03:37:21 PM PST 24
Finished Jan 17 03:37:24 PM PST 24
Peak memory 206816 kb
Host smart-01fb6263-27a2-4145-8b7c-d6e467a9b759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641395811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2641395811
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_bit_transfer.1372073451
Short name T640
Test name
Test status
Simulation time 247450782 ps
CPU time 2.69 seconds
Started Jan 17 03:37:16 PM PST 24
Finished Jan 17 03:37:19 PM PST 24
Peak memory 217144 kb
Host smart-a644faaa-0250-4e90-88b7-ebda7719a9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372073451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_bit_transfer.1372073451
Directory /workspace/44.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/44.spi_device_byte_transfer.750363949
Short name T1473
Test name
Test status
Simulation time 507294575 ps
CPU time 3.04 seconds
Started Jan 17 03:37:16 PM PST 24
Finished Jan 17 03:37:20 PM PST 24
Peak memory 217140 kb
Host smart-cb735f84-bcbd-41e2-b26d-a93159cbc04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750363949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_byte_transfer.750363949
Directory /workspace/44.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.120754284
Short name T950
Test name
Test status
Simulation time 899134374 ps
CPU time 6.05 seconds
Started Jan 17 03:37:20 PM PST 24
Finished Jan 17 03:37:28 PM PST 24
Peak memory 221792 kb
Host smart-d7844318-0460-4383-a464-2b681d994fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120754284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.120754284
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.4232133937
Short name T629
Test name
Test status
Simulation time 65861852 ps
CPU time 0.78 seconds
Started Jan 17 03:37:16 PM PST 24
Finished Jan 17 03:37:18 PM PST 24
Peak memory 207976 kb
Host smart-46b8a4dc-470e-4761-bcd2-b823cdd0e337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232133937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.4232133937
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_dummy_item_extra_dly.2560640418
Short name T840
Test name
Test status
Simulation time 42440819567 ps
CPU time 348.72 seconds
Started Jan 17 03:37:22 PM PST 24
Finished Jan 17 03:43:12 PM PST 24
Peak memory 290228 kb
Host smart-f1d0cc35-62cb-401a-9e05-d13e3c335369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560640418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_dummy_item_extra_dly.2560640418
Directory /workspace/44.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/44.spi_device_extreme_fifo_size.2737383538
Short name T1149
Test name
Test status
Simulation time 845134046519 ps
CPU time 829.15 seconds
Started Jan 17 03:37:16 PM PST 24
Finished Jan 17 03:51:06 PM PST 24
Peak memory 219464 kb
Host smart-b2ca7589-f556-47ab-a6ee-52ae1d745327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737383538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_extreme_fifo_size.2737383538
Directory /workspace/44.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/44.spi_device_fifo_full.3992017031
Short name T889
Test name
Test status
Simulation time 50337812974 ps
CPU time 2862.61 seconds
Started Jan 17 03:37:11 PM PST 24
Finished Jan 17 04:24:55 PM PST 24
Peak memory 266388 kb
Host smart-e7cabb72-d5ff-4652-92cb-807229814dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992017031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_fifo_full.3992017031
Directory /workspace/44.spi_device_fifo_full/latest

Test location /workspace/coverage/default/44.spi_device_fifo_underflow_overflow.1626792549
Short name T1596
Test name
Test status
Simulation time 37707142569 ps
CPU time 295.78 seconds
Started Jan 17 03:37:22 PM PST 24
Finished Jan 17 03:42:24 PM PST 24
Peak memory 363044 kb
Host smart-ad032e01-382d-4e97-8bef-58e70074879a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626792549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_fifo_underflow_overf
low.1626792549
Directory /workspace/44.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1867143920
Short name T1071
Test name
Test status
Simulation time 6923105335 ps
CPU time 29.5 seconds
Started Jan 17 03:37:19 PM PST 24
Finished Jan 17 03:37:51 PM PST 24
Peak memory 257132 kb
Host smart-cfbb1feb-7441-46f2-978c-d5062f3c410f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867143920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1867143920
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2389413449
Short name T114
Test name
Test status
Simulation time 10153760836 ps
CPU time 51.84 seconds
Started Jan 17 03:37:21 PM PST 24
Finished Jan 17 03:38:14 PM PST 24
Peak memory 258304 kb
Host smart-f73804cb-5931-4b69-b0eb-abb235a87995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389413449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2389413449
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2331985210
Short name T905
Test name
Test status
Simulation time 52147283779 ps
CPU time 417.71 seconds
Started Jan 17 03:37:23 PM PST 24
Finished Jan 17 03:44:27 PM PST 24
Peak memory 258336 kb
Host smart-7bfee33d-5904-4906-b639-bc2811f4499e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331985210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2331985210
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1625573593
Short name T1357
Test name
Test status
Simulation time 27272154324 ps
CPU time 39.97 seconds
Started Jan 17 03:37:21 PM PST 24
Finished Jan 17 03:38:03 PM PST 24
Peak memory 248440 kb
Host smart-0f115942-f558-42f9-8467-70b2e9ee6f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625573593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1625573593
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3163026778
Short name T303
Test name
Test status
Simulation time 1525116254 ps
CPU time 6.53 seconds
Started Jan 17 03:37:21 PM PST 24
Finished Jan 17 03:37:29 PM PST 24
Peak memory 225348 kb
Host smart-396c9ed4-ee3a-4802-b11c-184ac116b89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163026778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3163026778
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_intr.1987699509
Short name T1685
Test name
Test status
Simulation time 14548521931 ps
CPU time 72.76 seconds
Started Jan 17 03:37:12 PM PST 24
Finished Jan 17 03:38:26 PM PST 24
Peak memory 241748 kb
Host smart-7efa5bbb-60e9-45d0-bdb3-c782d21040a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987699509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intr.1987699509
Directory /workspace/44.spi_device_intr/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.279999182
Short name T294
Test name
Test status
Simulation time 2607110496 ps
CPU time 5.33 seconds
Started Jan 17 03:37:21 PM PST 24
Finished Jan 17 03:37:28 PM PST 24
Peak memory 240936 kb
Host smart-e857a8f2-1664-4535-92b4-0f6f7f50c698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279999182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.279999182
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3482448910
Short name T249
Test name
Test status
Simulation time 29507948209 ps
CPU time 19.11 seconds
Started Jan 17 03:37:24 PM PST 24
Finished Jan 17 03:37:50 PM PST 24
Peak memory 228872 kb
Host smart-010c6b85-9a1b-46af-b1ec-0de45fd6dd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482448910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3482448910
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_perf.2192785719
Short name T1159
Test name
Test status
Simulation time 14277283893 ps
CPU time 359.48 seconds
Started Jan 17 03:37:22 PM PST 24
Finished Jan 17 03:43:28 PM PST 24
Peak memory 250992 kb
Host smart-003a6972-98fc-457e-ae62-df51825cd0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192785719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_perf.2192785719
Directory /workspace/44.spi_device_perf/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.4054085464
Short name T1392
Test name
Test status
Simulation time 2213569642 ps
CPU time 4.83 seconds
Started Jan 17 03:37:19 PM PST 24
Finished Jan 17 03:37:27 PM PST 24
Peak memory 221292 kb
Host smart-ff6c0ea0-3163-49e8-ab9a-bd489db7621e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4054085464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.4054085464
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_rx_async_fifo_reset.766377977
Short name T1042
Test name
Test status
Simulation time 64333547 ps
CPU time 0.9 seconds
Started Jan 17 03:37:22 PM PST 24
Finished Jan 17 03:37:30 PM PST 24
Peak memory 208784 kb
Host smart-847daf98-3bec-4fad-b094-752b2c2e63f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766377977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_rx_async_fifo_reset.766377977
Directory /workspace/44.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3845574774
Short name T1252
Test name
Test status
Simulation time 157376180702 ps
CPU time 611.46 seconds
Started Jan 17 03:37:21 PM PST 24
Finished Jan 17 03:47:34 PM PST 24
Peak memory 290360 kb
Host smart-8f63a2fd-78ef-4d90-b956-3c76081ecf24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845574774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3845574774
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1080622963
Short name T924
Test name
Test status
Simulation time 482195488 ps
CPU time 8.38 seconds
Started Jan 17 03:37:22 PM PST 24
Finished Jan 17 03:37:31 PM PST 24
Peak memory 218452 kb
Host smart-51d0b51c-d6c5-4813-9599-5cd793506a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080622963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1080622963
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1817110824
Short name T911
Test name
Test status
Simulation time 3502725812 ps
CPU time 12.73 seconds
Started Jan 17 03:37:15 PM PST 24
Finished Jan 17 03:37:29 PM PST 24
Peak memory 217200 kb
Host smart-ee331f99-434a-4f85-b380-541491824755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817110824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1817110824
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2547482157
Short name T1202
Test name
Test status
Simulation time 376708655 ps
CPU time 12.55 seconds
Started Jan 17 03:37:21 PM PST 24
Finished Jan 17 03:37:35 PM PST 24
Peak memory 217084 kb
Host smart-df34f8cb-f8d2-43a7-9301-21a37b171172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547482157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2547482157
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.465105527
Short name T1291
Test name
Test status
Simulation time 33954781 ps
CPU time 0.8 seconds
Started Jan 17 03:37:21 PM PST 24
Finished Jan 17 03:37:23 PM PST 24
Peak memory 207304 kb
Host smart-a90e625f-88ef-4d7f-86d2-1e7fd89ce55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465105527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.465105527
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_tx_async_fifo_reset.1495730307
Short name T1526
Test name
Test status
Simulation time 13728512 ps
CPU time 0.79 seconds
Started Jan 17 03:37:13 PM PST 24
Finished Jan 17 03:37:14 PM PST 24
Peak memory 208768 kb
Host smart-d6f53dc9-5638-4a43-b855-99a3f1f54ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495730307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tx_async_fifo_reset.1495730307
Directory /workspace/44.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/44.spi_device_txrx.2092189725
Short name T754
Test name
Test status
Simulation time 133977957941 ps
CPU time 310.17 seconds
Started Jan 17 03:37:11 PM PST 24
Finished Jan 17 03:42:22 PM PST 24
Peak memory 305456 kb
Host smart-e007c4f6-1faa-4d06-a8d7-2b2a532e6a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092189725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_txrx.2092189725
Directory /workspace/44.spi_device_txrx/latest

Test location /workspace/coverage/default/44.spi_device_upload.3166942273
Short name T18
Test name
Test status
Simulation time 20755514386 ps
CPU time 16.14 seconds
Started Jan 17 03:37:22 PM PST 24
Finished Jan 17 03:37:44 PM PST 24
Peak memory 235188 kb
Host smart-c7632f1b-9685-45fe-815e-6f08c564db3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166942273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3166942273
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2346585380
Short name T721
Test name
Test status
Simulation time 17205286 ps
CPU time 0.78 seconds
Started Jan 17 03:37:36 PM PST 24
Finished Jan 17 03:37:37 PM PST 24
Peak memory 206804 kb
Host smart-ee60d299-3ed9-4a44-b152-051cf1e6c60e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346585380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2346585380
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_bit_transfer.1957914480
Short name T955
Test name
Test status
Simulation time 991338009 ps
CPU time 2.43 seconds
Started Jan 17 03:37:35 PM PST 24
Finished Jan 17 03:37:39 PM PST 24
Peak memory 217120 kb
Host smart-cd40b486-a81c-4481-b26d-d738c185de16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957914480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_bit_transfer.1957914480
Directory /workspace/45.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/45.spi_device_byte_transfer.4112385960
Short name T1658
Test name
Test status
Simulation time 441068904 ps
CPU time 3.03 seconds
Started Jan 17 03:37:32 PM PST 24
Finished Jan 17 03:37:35 PM PST 24
Peak memory 217164 kb
Host smart-daa1745c-90d5-424c-ac45-cea8fff324a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112385960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_byte_transfer.4112385960
Directory /workspace/45.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.148905636
Short name T809
Test name
Test status
Simulation time 686154091 ps
CPU time 3.56 seconds
Started Jan 17 03:37:34 PM PST 24
Finished Jan 17 03:37:38 PM PST 24
Peak memory 241852 kb
Host smart-72e2c696-f913-4246-b2b6-8f49700d5d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148905636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.148905636
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2782651608
Short name T1197
Test name
Test status
Simulation time 68804306 ps
CPU time 0.75 seconds
Started Jan 17 03:37:21 PM PST 24
Finished Jan 17 03:37:23 PM PST 24
Peak memory 206880 kb
Host smart-3869c38e-328b-4144-a3cb-ab81ffe0f9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782651608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2782651608
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_dummy_item_extra_dly.613429346
Short name T686
Test name
Test status
Simulation time 38467431506 ps
CPU time 169.61 seconds
Started Jan 17 03:37:25 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 266432 kb
Host smart-35fcf7c6-296f-44fe-a7a6-41264615fcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613429346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_dummy_item_extra_dly.613429346
Directory /workspace/45.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/45.spi_device_extreme_fifo_size.304803806
Short name T995
Test name
Test status
Simulation time 75173908914 ps
CPU time 1208.12 seconds
Started Jan 17 03:37:21 PM PST 24
Finished Jan 17 03:57:31 PM PST 24
Peak memory 221364 kb
Host smart-ebab55d0-6c18-41b9-87f5-0738f1edabf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304803806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_extreme_fifo_size.304803806
Directory /workspace/45.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/45.spi_device_fifo_full.1473527020
Short name T1729
Test name
Test status
Simulation time 140596284182 ps
CPU time 746.26 seconds
Started Jan 17 03:37:21 PM PST 24
Finished Jan 17 03:49:49 PM PST 24
Peak memory 274080 kb
Host smart-7a7b1494-74ae-41fc-986f-41401fc4f715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473527020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_fifo_full.1473527020
Directory /workspace/45.spi_device_fifo_full/latest

Test location /workspace/coverage/default/45.spi_device_fifo_underflow_overflow.74311794
Short name T1065
Test name
Test status
Simulation time 53741370132 ps
CPU time 142.68 seconds
Started Jan 17 03:37:20 PM PST 24
Finished Jan 17 03:39:45 PM PST 24
Peak memory 273936 kb
Host smart-8f4e36c8-cfa0-403e-91b2-b22634f76299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74311794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_fifo_underflow_overflo
w.74311794
Directory /workspace/45.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2917700217
Short name T692
Test name
Test status
Simulation time 9250203761 ps
CPU time 53.44 seconds
Started Jan 17 03:37:36 PM PST 24
Finished Jan 17 03:38:30 PM PST 24
Peak memory 251116 kb
Host smart-0e175ccd-d59f-4d67-a8cd-5aad2dfe1b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917700217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2917700217
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3718275151
Short name T1775
Test name
Test status
Simulation time 113450681310 ps
CPU time 218.28 seconds
Started Jan 17 03:37:35 PM PST 24
Finished Jan 17 03:41:14 PM PST 24
Peak memory 266464 kb
Host smart-2b6dede8-c3cb-4c48-9d6a-70bff488eb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718275151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3718275151
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4091613191
Short name T1500
Test name
Test status
Simulation time 60848749492 ps
CPU time 499.01 seconds
Started Jan 17 03:37:34 PM PST 24
Finished Jan 17 03:45:54 PM PST 24
Peak memory 266480 kb
Host smart-2286d757-4bbf-4651-b988-46080b9390df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091613191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4091613191
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1566313279
Short name T165
Test name
Test status
Simulation time 4877875585 ps
CPU time 22.21 seconds
Started Jan 17 03:37:48 PM PST 24
Finished Jan 17 03:38:11 PM PST 24
Peak memory 250248 kb
Host smart-5b2381c2-4168-4343-a4fe-cc26c84ac187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566313279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1566313279
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.4045838257
Short name T954
Test name
Test status
Simulation time 36804801402 ps
CPU time 13.43 seconds
Started Jan 17 03:37:26 PM PST 24
Finished Jan 17 03:37:44 PM PST 24
Peak memory 221184 kb
Host smart-87039b6b-b207-468c-a71d-79da45234440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045838257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.4045838257
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_intr.1249538629
Short name T1391
Test name
Test status
Simulation time 33131728475 ps
CPU time 56.95 seconds
Started Jan 17 03:37:23 PM PST 24
Finished Jan 17 03:38:26 PM PST 24
Peak memory 233512 kb
Host smart-7707a6d9-bdf2-492d-b020-8ad463cf85c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249538629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intr.1249538629
Directory /workspace/45.spi_device_intr/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3342991869
Short name T1745
Test name
Test status
Simulation time 170686395 ps
CPU time 3.63 seconds
Started Jan 17 03:37:30 PM PST 24
Finished Jan 17 03:37:35 PM PST 24
Peak memory 238276 kb
Host smart-fe9273a9-a841-42d1-ab13-5bc247c9dbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342991869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3342991869
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1037719454
Short name T769
Test name
Test status
Simulation time 8167560607 ps
CPU time 13.29 seconds
Started Jan 17 03:37:27 PM PST 24
Finished Jan 17 03:37:44 PM PST 24
Peak memory 250752 kb
Host smart-f46f7bea-93d4-4f10-a794-694a848dfdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037719454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1037719454
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3085222761
Short name T1551
Test name
Test status
Simulation time 168134545 ps
CPU time 3.31 seconds
Started Jan 17 03:37:29 PM PST 24
Finished Jan 17 03:37:34 PM PST 24
Peak memory 239804 kb
Host smart-6061147b-d8e1-4f66-bbe8-2f38049399bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085222761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3085222761
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_perf.2268281890
Short name T1265
Test name
Test status
Simulation time 34728803094 ps
CPU time 282.67 seconds
Started Jan 17 03:37:25 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 299052 kb
Host smart-de9ceaf7-2a38-4612-8faf-e22d12834da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268281890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_perf.2268281890
Directory /workspace/45.spi_device_perf/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.615045380
Short name T1416
Test name
Test status
Simulation time 756916537 ps
CPU time 5.56 seconds
Started Jan 17 03:37:48 PM PST 24
Finished Jan 17 03:37:54 PM PST 24
Peak memory 218760 kb
Host smart-125d211b-4940-4348-9fb2-a00cac8388b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=615045380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.615045380
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_rx_async_fifo_reset.3579897604
Short name T1331
Test name
Test status
Simulation time 98539082 ps
CPU time 0.94 seconds
Started Jan 17 03:37:27 PM PST 24
Finished Jan 17 03:37:32 PM PST 24
Peak memory 208776 kb
Host smart-2d6cf05f-d5e4-48cc-8f8f-de03840b8014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579897604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_rx_async_fifo_reset.3579897604
Directory /workspace/45.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/45.spi_device_rx_timeout.1978326984
Short name T1735
Test name
Test status
Simulation time 975301553 ps
CPU time 6.1 seconds
Started Jan 17 03:37:26 PM PST 24
Finished Jan 17 03:37:37 PM PST 24
Peak memory 217188 kb
Host smart-1b0d26f2-c616-4737-80c9-4a4167f26e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978326984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_rx_timeout.1978326984
Directory /workspace/45.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/45.spi_device_smoke.3627194979
Short name T632
Test name
Test status
Simulation time 66704200 ps
CPU time 1.36 seconds
Started Jan 17 03:37:22 PM PST 24
Finished Jan 17 03:37:30 PM PST 24
Peak memory 217132 kb
Host smart-6ca31132-dbb1-4f84-a8dc-b68358b3dedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627194979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_smoke.3627194979
Directory /workspace/45.spi_device_smoke/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2162659864
Short name T548
Test name
Test status
Simulation time 212076003674 ps
CPU time 1111.63 seconds
Started Jan 17 03:37:34 PM PST 24
Finished Jan 17 03:56:07 PM PST 24
Peak memory 312596 kb
Host smart-b3f5ebea-73d5-4000-9b0a-4ef989f42392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162659864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2162659864
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1552682896
Short name T62
Test name
Test status
Simulation time 14820424523 ps
CPU time 30.25 seconds
Started Jan 17 03:37:30 PM PST 24
Finished Jan 17 03:38:02 PM PST 24
Peak memory 217152 kb
Host smart-00f0967c-d328-4c0c-8b46-dd37ddb27c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552682896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1552682896
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3809526679
Short name T980
Test name
Test status
Simulation time 36651778824 ps
CPU time 25.11 seconds
Started Jan 17 03:37:29 PM PST 24
Finished Jan 17 03:37:56 PM PST 24
Peak memory 217628 kb
Host smart-cae68f05-d6c3-4b61-b6e3-56cd8266fc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809526679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3809526679
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3200761853
Short name T922
Test name
Test status
Simulation time 29273680 ps
CPU time 0.88 seconds
Started Jan 17 03:37:31 PM PST 24
Finished Jan 17 03:37:33 PM PST 24
Peak memory 207256 kb
Host smart-69a71f40-dece-4793-a7de-7b5b559a2ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200761853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3200761853
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2526586910
Short name T1174
Test name
Test status
Simulation time 79524686 ps
CPU time 1 seconds
Started Jan 17 03:37:29 PM PST 24
Finished Jan 17 03:37:32 PM PST 24
Peak memory 208372 kb
Host smart-8fe05a31-9a0c-4f96-9a91-9055294d83e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526586910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2526586910
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_tx_async_fifo_reset.2925533533
Short name T560
Test name
Test status
Simulation time 47281130 ps
CPU time 0.8 seconds
Started Jan 17 03:37:30 PM PST 24
Finished Jan 17 03:37:33 PM PST 24
Peak memory 208732 kb
Host smart-7aa0d21f-a66f-4a29-92eb-2272cab3c864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925533533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tx_async_fifo_reset.2925533533
Directory /workspace/45.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/45.spi_device_txrx.2504613326
Short name T1633
Test name
Test status
Simulation time 230231090609 ps
CPU time 138.13 seconds
Started Jan 17 03:37:23 PM PST 24
Finished Jan 17 03:39:47 PM PST 24
Peak memory 274420 kb
Host smart-f2912288-f580-4cdc-bc28-cc779b19850d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504613326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_txrx.2504613326
Directory /workspace/45.spi_device_txrx/latest

Test location /workspace/coverage/default/46.spi_device_abort.2259201278
Short name T642
Test name
Test status
Simulation time 100038988 ps
CPU time 0.75 seconds
Started Jan 17 03:37:47 PM PST 24
Finished Jan 17 03:37:49 PM PST 24
Peak memory 207000 kb
Host smart-7894190e-f020-49a7-bd37-b6eb9984dd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259201278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_abort.2259201278
Directory /workspace/46.spi_device_abort/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3837320736
Short name T821
Test name
Test status
Simulation time 67305454 ps
CPU time 0.71 seconds
Started Jan 17 03:37:47 PM PST 24
Finished Jan 17 03:37:49 PM PST 24
Peak memory 206816 kb
Host smart-d160fdd8-00ec-4407-a8f7-ee1fd1632f87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837320736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3837320736
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_bit_transfer.4220729306
Short name T712
Test name
Test status
Simulation time 6045587654 ps
CPU time 2.91 seconds
Started Jan 17 03:37:40 PM PST 24
Finished Jan 17 03:37:45 PM PST 24
Peak memory 217148 kb
Host smart-edd15762-1bf4-4b6a-8fb3-edec36501106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220729306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_bit_transfer.4220729306
Directory /workspace/46.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/46.spi_device_byte_transfer.66210692
Short name T1262
Test name
Test status
Simulation time 1194045406 ps
CPU time 3.61 seconds
Started Jan 17 03:37:40 PM PST 24
Finished Jan 17 03:37:45 PM PST 24
Peak memory 217180 kb
Host smart-73ddc7f5-2ea8-4395-a003-b5422e61dab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66210692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_byte_transfer.66210692
Directory /workspace/46.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2496601953
Short name T1657
Test name
Test status
Simulation time 2383281214 ps
CPU time 5.52 seconds
Started Jan 17 03:37:50 PM PST 24
Finished Jan 17 03:38:04 PM PST 24
Peak memory 219200 kb
Host smart-bda45b05-be2f-4f5f-912f-d189c2de4edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496601953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2496601953
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2969395513
Short name T1611
Test name
Test status
Simulation time 48143174 ps
CPU time 0.73 seconds
Started Jan 17 03:37:38 PM PST 24
Finished Jan 17 03:37:39 PM PST 24
Peak memory 206928 kb
Host smart-c98e3609-72ab-431f-8978-0a4e5d9d9af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969395513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2969395513
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_dummy_item_extra_dly.333176769
Short name T535
Test name
Test status
Simulation time 66518471671 ps
CPU time 285.95 seconds
Started Jan 17 03:37:39 PM PST 24
Finished Jan 17 03:42:26 PM PST 24
Peak memory 258008 kb
Host smart-79823a42-15e1-4825-a7ff-92d043600b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333176769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_dummy_item_extra_dly.333176769
Directory /workspace/46.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/46.spi_device_extreme_fifo_size.4015698622
Short name T267
Test name
Test status
Simulation time 157162890347 ps
CPU time 2516.22 seconds
Started Jan 17 03:37:40 PM PST 24
Finished Jan 17 04:19:38 PM PST 24
Peak memory 220364 kb
Host smart-3e4f2f9c-c6d4-452b-a729-0fe124a1b03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015698622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_extreme_fifo_size.4015698622
Directory /workspace/46.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/46.spi_device_fifo_full.1900979520
Short name T515
Test name
Test status
Simulation time 48522633926 ps
CPU time 255 seconds
Started Jan 17 03:37:48 PM PST 24
Finished Jan 17 03:42:04 PM PST 24
Peak memory 273572 kb
Host smart-c4d8f2d1-c147-4b39-b89e-0636ea87205d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900979520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_fifo_full.1900979520
Directory /workspace/46.spi_device_fifo_full/latest

Test location /workspace/coverage/default/46.spi_device_fifo_underflow_overflow.1849771218
Short name T55
Test name
Test status
Simulation time 35229606129 ps
CPU time 177.73 seconds
Started Jan 17 03:37:39 PM PST 24
Finished Jan 17 03:40:38 PM PST 24
Peak memory 329740 kb
Host smart-afe8e0c8-e69a-4793-9557-d1d27ba34d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849771218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_fifo_underflow_overf
low.1849771218
Directory /workspace/46.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2129981936
Short name T539
Test name
Test status
Simulation time 17309251452 ps
CPU time 102.9 seconds
Started Jan 17 03:37:52 PM PST 24
Finished Jan 17 03:39:42 PM PST 24
Peak memory 252932 kb
Host smart-372e5d36-282f-493d-bd8b-4504daf61b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129981936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2129981936
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2755680858
Short name T875
Test name
Test status
Simulation time 312437983189 ps
CPU time 173.67 seconds
Started Jan 17 03:37:48 PM PST 24
Finished Jan 17 03:40:43 PM PST 24
Peak memory 250136 kb
Host smart-581e3f61-92fc-41e9-9051-ba28efceb754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755680858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2755680858
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3021242437
Short name T1690
Test name
Test status
Simulation time 8225408903 ps
CPU time 117.65 seconds
Started Jan 17 03:37:47 PM PST 24
Finished Jan 17 03:39:46 PM PST 24
Peak memory 266784 kb
Host smart-e08aeaa7-5a91-415a-9536-28959eb60c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021242437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3021242437
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.18165724
Short name T569
Test name
Test status
Simulation time 3186833080 ps
CPU time 27.35 seconds
Started Jan 17 03:37:52 PM PST 24
Finished Jan 17 03:38:26 PM PST 24
Peak memory 249804 kb
Host smart-ea98748c-d430-4ae0-b4c9-1bd8dbd2818c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18165724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.18165724
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2904240026
Short name T1385
Test name
Test status
Simulation time 4956457555 ps
CPU time 6.61 seconds
Started Jan 17 03:37:48 PM PST 24
Finished Jan 17 03:38:03 PM PST 24
Peak memory 240788 kb
Host smart-0cc1f141-ceb8-4c80-9e8e-a7ed08720613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904240026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2904240026
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_intr.595024566
Short name T1285
Test name
Test status
Simulation time 10527009209 ps
CPU time 11.84 seconds
Started Jan 17 03:37:48 PM PST 24
Finished Jan 17 03:38:01 PM PST 24
Peak memory 224928 kb
Host smart-bdab4329-1768-428e-b3aa-78696f950ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595024566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intr.595024566
Directory /workspace/46.spi_device_intr/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3815067338
Short name T1396
Test name
Test status
Simulation time 621361306 ps
CPU time 8.82 seconds
Started Jan 17 03:37:47 PM PST 24
Finished Jan 17 03:37:58 PM PST 24
Peak memory 250436 kb
Host smart-f2b7e736-c1ce-4832-b6c0-edac7d58a827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815067338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3815067338
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.777803574
Short name T1035
Test name
Test status
Simulation time 1909892038 ps
CPU time 11.67 seconds
Started Jan 17 03:37:42 PM PST 24
Finished Jan 17 03:37:54 PM PST 24
Peak memory 229784 kb
Host smart-a48f0c7f-f511-4aca-8fbf-285da654c686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777803574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.777803574
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1390862321
Short name T1741
Test name
Test status
Simulation time 5024735179 ps
CPU time 17.86 seconds
Started Jan 17 03:37:52 PM PST 24
Finished Jan 17 03:38:17 PM PST 24
Peak memory 241608 kb
Host smart-2d7eab70-20b3-496d-81ec-6b26c3f4d423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390862321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1390862321
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_perf.2461074697
Short name T799
Test name
Test status
Simulation time 4923611984 ps
CPU time 371.14 seconds
Started Jan 17 03:37:41 PM PST 24
Finished Jan 17 03:43:53 PM PST 24
Peak memory 274472 kb
Host smart-079034a8-994f-4e09-bd9d-224c5a9d847d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461074697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_perf.2461074697
Directory /workspace/46.spi_device_perf/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2736610512
Short name T1404
Test name
Test status
Simulation time 144772499 ps
CPU time 3.36 seconds
Started Jan 17 03:37:46 PM PST 24
Finished Jan 17 03:37:51 PM PST 24
Peak memory 220644 kb
Host smart-a00ed98b-a317-4f22-a119-38b43ae05bb3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2736610512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2736610512
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_rx_async_fifo_reset.4131731794
Short name T753
Test name
Test status
Simulation time 47046122 ps
CPU time 0.91 seconds
Started Jan 17 03:37:47 PM PST 24
Finished Jan 17 03:37:50 PM PST 24
Peak memory 208796 kb
Host smart-e98060fa-5f06-41fb-b3d7-8bd0c0111475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131731794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_rx_async_fifo_reset.4131731794
Directory /workspace/46.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/46.spi_device_rx_timeout.2701320635
Short name T113
Test name
Test status
Simulation time 1292363019 ps
CPU time 5.91 seconds
Started Jan 17 03:37:41 PM PST 24
Finished Jan 17 03:37:48 PM PST 24
Peak memory 217160 kb
Host smart-cc40831c-f0ab-4117-8556-6e8743b3446c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701320635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_rx_timeout.2701320635
Directory /workspace/46.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/46.spi_device_smoke.209506323
Short name T1119
Test name
Test status
Simulation time 28621611 ps
CPU time 1.01 seconds
Started Jan 17 03:37:36 PM PST 24
Finished Jan 17 03:37:38 PM PST 24
Peak memory 208728 kb
Host smart-f7737360-d30f-40cb-98c5-1e7b9a8c6467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209506323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_smoke.209506323
Directory /workspace/46.spi_device_smoke/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1180344927
Short name T1680
Test name
Test status
Simulation time 138579280553 ps
CPU time 1567.16 seconds
Started Jan 17 03:37:47 PM PST 24
Finished Jan 17 04:03:56 PM PST 24
Peak memory 734092 kb
Host smart-36f0b216-d215-4e51-b0a6-8c5732162fa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180344927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1180344927
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2156005164
Short name T356
Test name
Test status
Simulation time 95865258528 ps
CPU time 103.77 seconds
Started Jan 17 03:37:48 PM PST 24
Finished Jan 17 03:39:33 PM PST 24
Peak memory 217056 kb
Host smart-c87db75f-4998-4052-8ffb-e29f25eaa950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156005164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2156005164
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.97259492
Short name T109
Test name
Test status
Simulation time 3111156100 ps
CPU time 5.45 seconds
Started Jan 17 03:37:40 PM PST 24
Finished Jan 17 03:37:46 PM PST 24
Peak memory 217220 kb
Host smart-22b5accb-889d-492e-9b31-9ac62769a8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97259492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.97259492
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3349958307
Short name T506
Test name
Test status
Simulation time 100919253 ps
CPU time 1.12 seconds
Started Jan 17 03:37:47 PM PST 24
Finished Jan 17 03:37:50 PM PST 24
Peak memory 208272 kb
Host smart-dfc20211-c6e6-4d5e-9719-e183133dfc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349958307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3349958307
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.875901827
Short name T1013
Test name
Test status
Simulation time 71508211 ps
CPU time 0.8 seconds
Started Jan 17 03:37:47 PM PST 24
Finished Jan 17 03:37:49 PM PST 24
Peak memory 207288 kb
Host smart-4946f62a-3ec1-47ad-8d83-39cc60d68a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875901827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.875901827
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_tx_async_fifo_reset.425076836
Short name T131
Test name
Test status
Simulation time 214674699 ps
CPU time 0.75 seconds
Started Jan 17 03:37:38 PM PST 24
Finished Jan 17 03:37:39 PM PST 24
Peak memory 208740 kb
Host smart-f2ca7f3d-5544-496d-9af6-970e48bb1f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425076836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tx_async_fifo_reset.425076836
Directory /workspace/46.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/46.spi_device_txrx.206044303
Short name T1123
Test name
Test status
Simulation time 60198625064 ps
CPU time 279.15 seconds
Started Jan 17 03:37:37 PM PST 24
Finished Jan 17 03:42:17 PM PST 24
Peak memory 283460 kb
Host smart-4c986fb2-7209-48ef-af0b-2296e4e4ab04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206044303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_txrx.206044303
Directory /workspace/46.spi_device_txrx/latest

Test location /workspace/coverage/default/46.spi_device_upload.314165841
Short name T1355
Test name
Test status
Simulation time 3136753582 ps
CPU time 16.42 seconds
Started Jan 17 03:37:48 PM PST 24
Finished Jan 17 03:38:12 PM PST 24
Peak memory 240104 kb
Host smart-0cd18216-fa98-42af-820b-8c98cca9dc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314165841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.314165841
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_abort.824034766
Short name T1019
Test name
Test status
Simulation time 47855951 ps
CPU time 0.74 seconds
Started Jan 17 03:37:53 PM PST 24
Finished Jan 17 03:38:00 PM PST 24
Peak memory 207012 kb
Host smart-30ab8a76-3e5c-4fd8-8102-ef91174a219e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824034766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_abort.824034766
Directory /workspace/47.spi_device_abort/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2736082994
Short name T883
Test name
Test status
Simulation time 39679752 ps
CPU time 0.74 seconds
Started Jan 17 03:38:03 PM PST 24
Finished Jan 17 03:38:04 PM PST 24
Peak memory 206796 kb
Host smart-64a698c4-91b4-4509-a90d-f2e9b8d80493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736082994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2736082994
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_bit_transfer.1516346914
Short name T208
Test name
Test status
Simulation time 244413440 ps
CPU time 2.61 seconds
Started Jan 17 03:37:55 PM PST 24
Finished Jan 17 03:38:02 PM PST 24
Peak memory 217180 kb
Host smart-51faac0a-8b72-46f7-9a9e-8925d757f5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516346914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_bit_transfer.1516346914
Directory /workspace/47.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/47.spi_device_byte_transfer.4160175549
Short name T63
Test name
Test status
Simulation time 217047054 ps
CPU time 2.78 seconds
Started Jan 17 03:37:53 PM PST 24
Finished Jan 17 03:38:02 PM PST 24
Peak memory 217112 kb
Host smart-be5146e5-6922-489e-a962-325e496eb8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160175549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_byte_transfer.4160175549
Directory /workspace/47.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2306595496
Short name T307
Test name
Test status
Simulation time 128625240 ps
CPU time 3.73 seconds
Started Jan 17 03:38:01 PM PST 24
Finished Jan 17 03:38:05 PM PST 24
Peak memory 240608 kb
Host smart-dac21cf9-2942-4407-8c8e-f2057ed917d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306595496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2306595496
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3489267903
Short name T1752
Test name
Test status
Simulation time 24234848 ps
CPU time 0.82 seconds
Started Jan 17 03:37:53 PM PST 24
Finished Jan 17 03:38:00 PM PST 24
Peak memory 207908 kb
Host smart-70f4f0b0-4bb8-45bf-9e9d-d25e1a6cf7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489267903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3489267903
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_dummy_item_extra_dly.2210065596
Short name T1213
Test name
Test status
Simulation time 82721865498 ps
CPU time 632.2 seconds
Started Jan 17 03:37:51 PM PST 24
Finished Jan 17 03:48:31 PM PST 24
Peak memory 273276 kb
Host smart-02cc2bdb-488b-4246-b41e-f2b31a5f3517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210065596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_dummy_item_extra_dly.2210065596
Directory /workspace/47.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/47.spi_device_extreme_fifo_size.3773472748
Short name T897
Test name
Test status
Simulation time 113452734918 ps
CPU time 1795.24 seconds
Started Jan 17 03:37:53 PM PST 24
Finished Jan 17 04:07:54 PM PST 24
Peak memory 219272 kb
Host smart-afc556b5-146c-4ea3-936d-b5e612f06dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773472748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_extreme_fifo_size.3773472748
Directory /workspace/47.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/47.spi_device_fifo_full.1335776861
Short name T1350
Test name
Test status
Simulation time 25430938266 ps
CPU time 583.4 seconds
Started Jan 17 03:37:55 PM PST 24
Finished Jan 17 03:47:43 PM PST 24
Peak memory 291016 kb
Host smart-fb7562a8-345d-4ece-b550-321d6ea52c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335776861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_fifo_full.1335776861
Directory /workspace/47.spi_device_fifo_full/latest

Test location /workspace/coverage/default/47.spi_device_fifo_underflow_overflow.2583277171
Short name T1169
Test name
Test status
Simulation time 110962586063 ps
CPU time 573.2 seconds
Started Jan 17 03:37:54 PM PST 24
Finished Jan 17 03:47:32 PM PST 24
Peak memory 490000 kb
Host smart-6f04e613-9db2-4518-b0c5-70e78cf9e03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583277171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_fifo_underflow_overf
low.2583277171
Directory /workspace/47.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4096525410
Short name T261
Test name
Test status
Simulation time 3956948883 ps
CPU time 67.15 seconds
Started Jan 17 03:37:59 PM PST 24
Finished Jan 17 03:39:07 PM PST 24
Peak memory 264736 kb
Host smart-b88593fb-7ab9-45a4-9e81-d5a4dad2b5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096525410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4096525410
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.936808076
Short name T332
Test name
Test status
Simulation time 69900867375 ps
CPU time 138.07 seconds
Started Jan 17 03:37:58 PM PST 24
Finished Jan 17 03:40:18 PM PST 24
Peak memory 281484 kb
Host smart-a67f0d00-71f5-407a-b441-bdeed1364262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936808076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.936808076
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1488212630
Short name T1707
Test name
Test status
Simulation time 21182315030 ps
CPU time 70.64 seconds
Started Jan 17 03:38:04 PM PST 24
Finished Jan 17 03:39:15 PM PST 24
Peak memory 254036 kb
Host smart-3621f0ce-030e-4c3d-967e-54e84d37bbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488212630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1488212630
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1085961342
Short name T987
Test name
Test status
Simulation time 324035118 ps
CPU time 2.87 seconds
Started Jan 17 03:37:55 PM PST 24
Finished Jan 17 03:38:02 PM PST 24
Peak memory 219616 kb
Host smart-b6748054-cc7f-488c-ab33-503a933179c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085961342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1085961342
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_intr.4065815055
Short name T522
Test name
Test status
Simulation time 18041467711 ps
CPU time 75.87 seconds
Started Jan 17 03:37:54 PM PST 24
Finished Jan 17 03:39:15 PM PST 24
Peak memory 233484 kb
Host smart-4d960f3b-c8e5-4f72-9a4e-8f91f5aef6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065815055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intr.4065815055
Directory /workspace/47.spi_device_intr/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.929267160
Short name T835
Test name
Test status
Simulation time 18139259659 ps
CPU time 16.82 seconds
Started Jan 17 03:37:52 PM PST 24
Finished Jan 17 03:38:16 PM PST 24
Peak memory 233744 kb
Host smart-7129c4fa-b32b-4836-9e7a-a04c5a1ae566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929267160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.929267160
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3017017613
Short name T347
Test name
Test status
Simulation time 1235333334 ps
CPU time 3.4 seconds
Started Jan 17 03:37:52 PM PST 24
Finished Jan 17 03:38:02 PM PST 24
Peak memory 218488 kb
Host smart-c8aa232e-94f0-46df-9138-3d6ec5d44a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017017613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3017017613
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1376546283
Short name T854
Test name
Test status
Simulation time 756157386 ps
CPU time 10.85 seconds
Started Jan 17 03:37:51 PM PST 24
Finished Jan 17 03:38:10 PM PST 24
Peak memory 239516 kb
Host smart-cfdfb4f2-449b-4b3d-b038-fd27969cface
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376546283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1376546283
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_perf.237210173
Short name T502
Test name
Test status
Simulation time 50204141205 ps
CPU time 600.99 seconds
Started Jan 17 03:37:53 PM PST 24
Finished Jan 17 03:48:00 PM PST 24
Peak memory 287804 kb
Host smart-a26a4980-becf-46cb-bcad-278b7704963a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237210173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_perf.237210173
Directory /workspace/47.spi_device_perf/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1614456919
Short name T622
Test name
Test status
Simulation time 942702891 ps
CPU time 4.65 seconds
Started Jan 17 03:37:59 PM PST 24
Finished Jan 17 03:38:05 PM PST 24
Peak memory 235092 kb
Host smart-fbc7f3b8-5563-4326-8b8f-5dd37f7cb2bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1614456919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1614456919
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_rx_async_fifo_reset.4093323661
Short name T1397
Test name
Test status
Simulation time 134601381 ps
CPU time 0.83 seconds
Started Jan 17 03:37:53 PM PST 24
Finished Jan 17 03:38:00 PM PST 24
Peak memory 208804 kb
Host smart-665c5c22-0e98-406f-afa7-3acd161b48b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093323661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_rx_async_fifo_reset.4093323661
Directory /workspace/47.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/47.spi_device_rx_timeout.3596801073
Short name T1207
Test name
Test status
Simulation time 698568681 ps
CPU time 5.82 seconds
Started Jan 17 03:37:54 PM PST 24
Finished Jan 17 03:38:05 PM PST 24
Peak memory 217116 kb
Host smart-b9ec7a50-b34c-4480-94c1-bf5bc2729e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596801073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_rx_timeout.3596801073
Directory /workspace/47.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/47.spi_device_smoke.3180950427
Short name T1682
Test name
Test status
Simulation time 273600112 ps
CPU time 1.11 seconds
Started Jan 17 03:37:48 PM PST 24
Finished Jan 17 03:37:51 PM PST 24
Peak memory 208620 kb
Host smart-784543ff-cd46-4434-9240-04793f8270fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180950427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_smoke.3180950427
Directory /workspace/47.spi_device_smoke/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.352779619
Short name T1096
Test name
Test status
Simulation time 39915408110 ps
CPU time 77.91 seconds
Started Jan 17 03:37:53 PM PST 24
Finished Jan 17 03:39:17 PM PST 24
Peak memory 217264 kb
Host smart-fd43cfdf-c6cb-411c-b349-d86779b1611e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352779619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.352779619
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2537076743
Short name T825
Test name
Test status
Simulation time 3388541367 ps
CPU time 12.84 seconds
Started Jan 17 03:37:53 PM PST 24
Finished Jan 17 03:38:12 PM PST 24
Peak memory 217232 kb
Host smart-99c4c215-4d95-4ccd-9e9f-4388165876ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537076743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2537076743
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.720260129
Short name T999
Test name
Test status
Simulation time 576884074 ps
CPU time 6.72 seconds
Started Jan 17 03:37:55 PM PST 24
Finished Jan 17 03:38:06 PM PST 24
Peak memory 217184 kb
Host smart-64c2327f-8b7e-4c92-953e-4cf78bd2d290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720260129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.720260129
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1812357862
Short name T1363
Test name
Test status
Simulation time 183924118 ps
CPU time 0.88 seconds
Started Jan 17 03:37:53 PM PST 24
Finished Jan 17 03:38:00 PM PST 24
Peak memory 207236 kb
Host smart-70987490-cc24-4ce3-9d51-eb4e191d9b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812357862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1812357862
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_tx_async_fifo_reset.2413092818
Short name T761
Test name
Test status
Simulation time 25654791 ps
CPU time 0.78 seconds
Started Jan 17 03:37:51 PM PST 24
Finished Jan 17 03:38:00 PM PST 24
Peak memory 208980 kb
Host smart-b29fbb2c-6dae-428e-94a9-61b592a09eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413092818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tx_async_fifo_reset.2413092818
Directory /workspace/47.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/47.spi_device_txrx.3613505539
Short name T744
Test name
Test status
Simulation time 52302637111 ps
CPU time 455.3 seconds
Started Jan 17 03:37:51 PM PST 24
Finished Jan 17 03:45:34 PM PST 24
Peak memory 254092 kb
Host smart-d137fbaa-630e-4e52-8712-d274db59471c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613505539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_txrx.3613505539
Directory /workspace/47.spi_device_txrx/latest

Test location /workspace/coverage/default/47.spi_device_upload.2224171972
Short name T226
Test name
Test status
Simulation time 473841897 ps
CPU time 6.13 seconds
Started Jan 17 03:38:09 PM PST 24
Finished Jan 17 03:38:15 PM PST 24
Peak memory 238644 kb
Host smart-9ff09d9d-72f2-4da2-b390-2f33ec8e1521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224171972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2224171972
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_abort.2513914166
Short name T75
Test name
Test status
Simulation time 39734224 ps
CPU time 0.75 seconds
Started Jan 17 03:38:06 PM PST 24
Finished Jan 17 03:38:07 PM PST 24
Peak memory 207020 kb
Host smart-11e4f4e6-7886-4572-ad5b-a28350489a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513914166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_abort.2513914166
Directory /workspace/48.spi_device_abort/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2408335114
Short name T1139
Test name
Test status
Simulation time 178561992 ps
CPU time 0.72 seconds
Started Jan 17 03:38:06 PM PST 24
Finished Jan 17 03:38:07 PM PST 24
Peak memory 206816 kb
Host smart-380ddc02-1dc1-4227-914d-c07cf740cf24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408335114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2408335114
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_bit_transfer.366761999
Short name T654
Test name
Test status
Simulation time 670857984 ps
CPU time 3.36 seconds
Started Jan 17 03:38:00 PM PST 24
Finished Jan 17 03:38:04 PM PST 24
Peak memory 217176 kb
Host smart-bd0eef76-8cfa-4ec6-8a8c-cc168e70960b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366761999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_bit_transfer.366761999
Directory /workspace/48.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/48.spi_device_byte_transfer.478412324
Short name T937
Test name
Test status
Simulation time 88730800 ps
CPU time 2.42 seconds
Started Jan 17 03:38:08 PM PST 24
Finished Jan 17 03:38:11 PM PST 24
Peak memory 217116 kb
Host smart-f2d11a8f-def8-4e6a-b6a2-af2001fe62f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478412324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_byte_transfer.478412324
Directory /workspace/48.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3732514666
Short name T896
Test name
Test status
Simulation time 1303225937 ps
CPU time 7.48 seconds
Started Jan 17 03:38:11 PM PST 24
Finished Jan 17 03:38:19 PM PST 24
Peak memory 241036 kb
Host smart-174a5a40-f285-48d6-889f-ec7aa028c7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732514666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3732514666
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3966525365
Short name T1610
Test name
Test status
Simulation time 17400198 ps
CPU time 0.8 seconds
Started Jan 17 03:38:02 PM PST 24
Finished Jan 17 03:38:04 PM PST 24
Peak memory 207928 kb
Host smart-1e25ce40-c411-4f94-9f8c-5b3f78c4a405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966525365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3966525365
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_dummy_item_extra_dly.445934843
Short name T780
Test name
Test status
Simulation time 60457024986 ps
CPU time 308.7 seconds
Started Jan 17 03:38:03 PM PST 24
Finished Jan 17 03:43:12 PM PST 24
Peak memory 297156 kb
Host smart-52b89dac-f980-4d80-bd50-1b614593635c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445934843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_dummy_item_extra_dly.445934843
Directory /workspace/48.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/48.spi_device_extreme_fifo_size.2505988291
Short name T1233
Test name
Test status
Simulation time 64164460816 ps
CPU time 682.16 seconds
Started Jan 17 03:38:05 PM PST 24
Finished Jan 17 03:49:28 PM PST 24
Peak memory 225396 kb
Host smart-03845ae0-4040-4994-b0ac-8cfe057fa5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505988291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_extreme_fifo_size.2505988291
Directory /workspace/48.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/48.spi_device_fifo_full.510914212
Short name T206
Test name
Test status
Simulation time 64493328971 ps
CPU time 294.44 seconds
Started Jan 17 03:37:59 PM PST 24
Finished Jan 17 03:42:55 PM PST 24
Peak memory 263160 kb
Host smart-b808f932-3ea6-419a-9d93-8b640cc1affc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510914212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_fifo_full.510914212
Directory /workspace/48.spi_device_fifo_full/latest

Test location /workspace/coverage/default/48.spi_device_fifo_underflow_overflow.2142346916
Short name T831
Test name
Test status
Simulation time 45073278634 ps
CPU time 299.25 seconds
Started Jan 17 03:37:58 PM PST 24
Finished Jan 17 03:42:59 PM PST 24
Peak memory 459152 kb
Host smart-092cef4a-3156-4c69-abc8-b26c9bde3eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142346916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_fifo_underflow_overf
low.2142346916
Directory /workspace/48.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3082379061
Short name T1720
Test name
Test status
Simulation time 79746797204 ps
CPU time 596.46 seconds
Started Jan 17 03:38:06 PM PST 24
Finished Jan 17 03:48:03 PM PST 24
Peak memory 263836 kb
Host smart-fc7cd4b8-94ab-4416-bbc1-13dc92805052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082379061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3082379061
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2019407964
Short name T280
Test name
Test status
Simulation time 41569239603 ps
CPU time 190.83 seconds
Started Jan 17 03:38:07 PM PST 24
Finished Jan 17 03:41:19 PM PST 24
Peak memory 250136 kb
Host smart-bd8e116c-21e4-47bf-96ed-5dc3e67ffca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019407964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2019407964
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.122856767
Short name T353
Test name
Test status
Simulation time 8270340028 ps
CPU time 15.4 seconds
Started Jan 17 03:38:07 PM PST 24
Finished Jan 17 03:38:24 PM PST 24
Peak memory 233628 kb
Host smart-5b3577fd-8373-4714-911b-44adab0a946b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122856767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.122856767
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3178710013
Short name T1620
Test name
Test status
Simulation time 787893473 ps
CPU time 4.89 seconds
Started Jan 17 03:38:06 PM PST 24
Finished Jan 17 03:38:13 PM PST 24
Peak memory 219740 kb
Host smart-4e5af30e-d015-4e4f-8593-2a2fb65b44bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178710013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3178710013
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_intr.3982159135
Short name T1313
Test name
Test status
Simulation time 4786351579 ps
CPU time 37.81 seconds
Started Jan 17 03:38:02 PM PST 24
Finished Jan 17 03:38:40 PM PST 24
Peak memory 234596 kb
Host smart-83789aad-3a42-4a66-94ad-228ee31025d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982159135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intr.3982159135
Directory /workspace/48.spi_device_intr/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3887395475
Short name T1120
Test name
Test status
Simulation time 27585892840 ps
CPU time 22 seconds
Started Jan 17 03:38:06 PM PST 24
Finished Jan 17 03:38:29 PM PST 24
Peak memory 230452 kb
Host smart-86b53119-e1b2-42e2-b7b8-2281e1a279ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887395475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3887395475
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1841410565
Short name T1352
Test name
Test status
Simulation time 19909219228 ps
CPU time 32.52 seconds
Started Jan 17 03:38:06 PM PST 24
Finished Jan 17 03:38:39 PM PST 24
Peak memory 249968 kb
Host smart-4a1f9e62-0184-4feb-ac9e-2a246ce769df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841410565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1841410565
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2238266978
Short name T221
Test name
Test status
Simulation time 1763027133 ps
CPU time 7.9 seconds
Started Jan 17 03:38:06 PM PST 24
Finished Jan 17 03:38:14 PM PST 24
Peak memory 235212 kb
Host smart-e41d837c-1476-4b2c-bb6e-59eea9ab7de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238266978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2238266978
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_perf.3925769744
Short name T1525
Test name
Test status
Simulation time 24516408564 ps
CPU time 196 seconds
Started Jan 17 03:38:03 PM PST 24
Finished Jan 17 03:41:20 PM PST 24
Peak memory 267408 kb
Host smart-91902d1e-1d31-4bdd-939b-648854c1ccca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925769744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_perf.3925769744
Directory /workspace/48.spi_device_perf/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1124564654
Short name T782
Test name
Test status
Simulation time 458458228 ps
CPU time 4.18 seconds
Started Jan 17 03:38:06 PM PST 24
Finished Jan 17 03:38:12 PM PST 24
Peak memory 220656 kb
Host smart-b3d996a6-1f0b-4d29-b9d9-6d785adcdb64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1124564654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1124564654
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_rx_async_fifo_reset.3937304018
Short name T724
Test name
Test status
Simulation time 499887131 ps
CPU time 0.95 seconds
Started Jan 17 03:38:08 PM PST 24
Finished Jan 17 03:38:09 PM PST 24
Peak memory 208696 kb
Host smart-d1eb1ba9-a4e0-4c92-a2f8-5d838c3d7e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937304018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_rx_async_fifo_reset.3937304018
Directory /workspace/48.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/48.spi_device_rx_timeout.3432798901
Short name T1756
Test name
Test status
Simulation time 2457937240 ps
CPU time 5.42 seconds
Started Jan 17 03:38:03 PM PST 24
Finished Jan 17 03:38:09 PM PST 24
Peak memory 217160 kb
Host smart-33a205e6-068c-47eb-b86d-7fe3fa48a3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432798901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_rx_timeout.3432798901
Directory /workspace/48.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/48.spi_device_smoke.2250026733
Short name T64
Test name
Test status
Simulation time 43309661 ps
CPU time 0.91 seconds
Started Jan 17 03:38:02 PM PST 24
Finished Jan 17 03:38:03 PM PST 24
Peak memory 208332 kb
Host smart-56b6467d-1929-4554-a7bd-c140c5a52e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250026733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_smoke.2250026733
Directory /workspace/48.spi_device_smoke/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1788934961
Short name T54
Test name
Test status
Simulation time 457743595438 ps
CPU time 4306.16 seconds
Started Jan 17 03:38:09 PM PST 24
Finished Jan 17 04:49:56 PM PST 24
Peak memory 615768 kb
Host smart-d929db5a-3ab4-4def-8d28-f7770b81cafa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788934961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1788934961
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1641336355
Short name T1470
Test name
Test status
Simulation time 3696865300 ps
CPU time 47.95 seconds
Started Jan 17 03:38:03 PM PST 24
Finished Jan 17 03:38:51 PM PST 24
Peak memory 217540 kb
Host smart-fb52da2d-5dae-45f5-8f1f-434136112354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641336355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1641336355
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3377282012
Short name T1463
Test name
Test status
Simulation time 21150293714 ps
CPU time 14.72 seconds
Started Jan 17 03:38:08 PM PST 24
Finished Jan 17 03:38:23 PM PST 24
Peak memory 217168 kb
Host smart-031abfed-3fb8-4cf0-91a4-678e6b6601f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377282012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3377282012
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3692062789
Short name T965
Test name
Test status
Simulation time 42848238 ps
CPU time 1.04 seconds
Started Jan 17 03:38:09 PM PST 24
Finished Jan 17 03:38:11 PM PST 24
Peak memory 208336 kb
Host smart-8c6788c3-e687-4260-829b-455e970d7904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692062789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3692062789
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1181891920
Short name T827
Test name
Test status
Simulation time 834087919 ps
CPU time 1.01 seconds
Started Jan 17 03:38:06 PM PST 24
Finished Jan 17 03:38:09 PM PST 24
Peak memory 208328 kb
Host smart-227fcbb0-8270-4f29-9a5a-1aeadcde4643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181891920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1181891920
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_tx_async_fifo_reset.1327035959
Short name T1691
Test name
Test status
Simulation time 15208788 ps
CPU time 0.8 seconds
Started Jan 17 03:38:03 PM PST 24
Finished Jan 17 03:38:05 PM PST 24
Peak memory 208732 kb
Host smart-1b7d90de-698b-4d99-94ff-018a155f650e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327035959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tx_async_fifo_reset.1327035959
Directory /workspace/48.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/48.spi_device_txrx.2258404753
Short name T1294
Test name
Test status
Simulation time 197055502368 ps
CPU time 569.82 seconds
Started Jan 17 03:38:05 PM PST 24
Finished Jan 17 03:47:36 PM PST 24
Peak memory 274784 kb
Host smart-6e8c0bdc-0b29-4c07-b942-6350d8572131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258404753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_txrx.2258404753
Directory /workspace/48.spi_device_txrx/latest

Test location /workspace/coverage/default/48.spi_device_upload.2458579183
Short name T1400
Test name
Test status
Simulation time 10113493526 ps
CPU time 30.86 seconds
Started Jan 17 03:38:09 PM PST 24
Finished Jan 17 03:38:41 PM PST 24
Peak memory 231176 kb
Host smart-8d929bb2-c9cb-46b5-bde2-5ba8141b2026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458579183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2458579183
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_abort.368527075
Short name T1593
Test name
Test status
Simulation time 16060559 ps
CPU time 0.78 seconds
Started Jan 17 03:38:13 PM PST 24
Finished Jan 17 03:38:14 PM PST 24
Peak memory 207000 kb
Host smart-013d4f9d-9a53-4b9e-aedd-1501af20d24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368527075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_abort.368527075
Directory /workspace/49.spi_device_abort/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.533472196
Short name T1565
Test name
Test status
Simulation time 56277524 ps
CPU time 0.72 seconds
Started Jan 17 03:38:17 PM PST 24
Finished Jan 17 03:38:19 PM PST 24
Peak memory 206816 kb
Host smart-1630830e-a397-4dd1-ba96-5be65849627f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533472196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.533472196
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_bit_transfer.3938154358
Short name T1421
Test name
Test status
Simulation time 198814201 ps
CPU time 2.38 seconds
Started Jan 17 03:38:13 PM PST 24
Finished Jan 17 03:38:15 PM PST 24
Peak memory 217196 kb
Host smart-84a8b4f8-b7b5-43b1-8755-830bcc0d3109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938154358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_bit_transfer.3938154358
Directory /workspace/49.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/49.spi_device_byte_transfer.2445202154
Short name T65
Test name
Test status
Simulation time 886039854 ps
CPU time 3.03 seconds
Started Jan 17 03:38:16 PM PST 24
Finished Jan 17 03:38:20 PM PST 24
Peak memory 217068 kb
Host smart-a9fef4f6-bae9-4ebf-a8c2-cc4aeb2caa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445202154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_byte_transfer.2445202154
Directory /workspace/49.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1445518399
Short name T20
Test name
Test status
Simulation time 2776120730 ps
CPU time 10.67 seconds
Started Jan 17 03:38:17 PM PST 24
Finished Jan 17 03:38:30 PM PST 24
Peak memory 239660 kb
Host smart-701f7de4-77e1-4db7-90b2-0ab1a783ffc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445518399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1445518399
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1385895871
Short name T81
Test name
Test status
Simulation time 73714503 ps
CPU time 0.78 seconds
Started Jan 17 03:38:17 PM PST 24
Finished Jan 17 03:38:19 PM PST 24
Peak memory 207956 kb
Host smart-fb5254a8-28aa-4d7e-a26a-4e96810cf330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385895871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1385895871
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_dummy_item_extra_dly.514991846
Short name T656
Test name
Test status
Simulation time 30875853488 ps
CPU time 273.79 seconds
Started Jan 17 03:38:17 PM PST 24
Finished Jan 17 03:42:52 PM PST 24
Peak memory 256764 kb
Host smart-bb57d5a4-b60b-4933-b65a-25c79b140cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514991846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_dummy_item_extra_dly.514991846
Directory /workspace/49.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/49.spi_device_extreme_fifo_size.1427392007
Short name T1443
Test name
Test status
Simulation time 84567898514 ps
CPU time 415.93 seconds
Started Jan 17 03:38:14 PM PST 24
Finished Jan 17 03:45:11 PM PST 24
Peak memory 218272 kb
Host smart-32184869-c923-4bb7-addf-c1393557cf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427392007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_extreme_fifo_size.1427392007
Directory /workspace/49.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/49.spi_device_fifo_full.3704875286
Short name T537
Test name
Test status
Simulation time 74268456087 ps
CPU time 334.44 seconds
Started Jan 17 03:38:19 PM PST 24
Finished Jan 17 03:43:55 PM PST 24
Peak memory 247560 kb
Host smart-4f04dd3d-264b-4e6a-b988-d4411105a3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704875286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_fifo_full.3704875286
Directory /workspace/49.spi_device_fifo_full/latest

Test location /workspace/coverage/default/49.spi_device_fifo_underflow_overflow.1640344033
Short name T1201
Test name
Test status
Simulation time 705137111416 ps
CPU time 586.67 seconds
Started Jan 17 03:38:14 PM PST 24
Finished Jan 17 03:48:02 PM PST 24
Peak memory 449284 kb
Host smart-e2cc6f3f-534b-4bf9-b49e-7a3671b7dd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640344033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_fifo_underflow_overf
low.1640344033
Directory /workspace/49.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.980480315
Short name T691
Test name
Test status
Simulation time 14975953721 ps
CPU time 63.04 seconds
Started Jan 17 03:38:17 PM PST 24
Finished Jan 17 03:39:21 PM PST 24
Peak memory 251076 kb
Host smart-81933fd9-2368-4966-b00b-3701173e4a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980480315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.980480315
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3643696207
Short name T255
Test name
Test status
Simulation time 31765273099 ps
CPU time 253.6 seconds
Started Jan 17 03:38:18 PM PST 24
Finished Jan 17 03:42:33 PM PST 24
Peak memory 255100 kb
Host smart-e443ca82-24a5-4a65-80a1-6ded540e9e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643696207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3643696207
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1818865127
Short name T1549
Test name
Test status
Simulation time 5851801652 ps
CPU time 103.07 seconds
Started Jan 17 03:38:18 PM PST 24
Finished Jan 17 03:40:03 PM PST 24
Peak memory 266456 kb
Host smart-d7283a53-fa96-4613-b24e-6ea437e37732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818865127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1818865127
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.815220480
Short name T1070
Test name
Test status
Simulation time 243014352 ps
CPU time 7.47 seconds
Started Jan 17 03:38:19 PM PST 24
Finished Jan 17 03:38:28 PM PST 24
Peak memory 233820 kb
Host smart-8e6ed79e-2bd8-4634-892a-702ab2e47b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815220480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.815220480
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3642976390
Short name T95
Test name
Test status
Simulation time 1409131421 ps
CPU time 5.94 seconds
Started Jan 17 03:38:14 PM PST 24
Finished Jan 17 03:38:20 PM PST 24
Peak memory 234660 kb
Host smart-ef6423e9-cd11-4544-8650-917638ae131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642976390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3642976390
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_intr.1649465991
Short name T1144
Test name
Test status
Simulation time 35113020180 ps
CPU time 131.4 seconds
Started Jan 17 03:38:12 PM PST 24
Finished Jan 17 03:40:24 PM PST 24
Peak memory 251072 kb
Host smart-1204fde2-a08f-4796-b1fb-fe6ee9aac012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649465991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intr.1649465991
Directory /workspace/49.spi_device_intr/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1942949714
Short name T1185
Test name
Test status
Simulation time 650004661 ps
CPU time 9.75 seconds
Started Jan 17 03:38:12 PM PST 24
Finished Jan 17 03:38:22 PM PST 24
Peak memory 247292 kb
Host smart-0115f0c0-2b5b-429e-aafe-5fee575a0345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942949714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1942949714
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3373347412
Short name T1442
Test name
Test status
Simulation time 1665096642 ps
CPU time 7.1 seconds
Started Jan 17 03:38:17 PM PST 24
Finished Jan 17 03:38:25 PM PST 24
Peak memory 220568 kb
Host smart-eae82dc3-2af0-43e6-9e99-d0bbee0ce183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373347412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3373347412
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3567135527
Short name T1679
Test name
Test status
Simulation time 265852818 ps
CPU time 2.66 seconds
Started Jan 17 03:38:18 PM PST 24
Finished Jan 17 03:38:22 PM PST 24
Peak memory 219012 kb
Host smart-34de12af-deda-4c2f-bf77-517380efc8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567135527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3567135527
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_perf.2532640377
Short name T1558
Test name
Test status
Simulation time 10835034535 ps
CPU time 296.84 seconds
Started Jan 17 03:38:15 PM PST 24
Finished Jan 17 03:43:12 PM PST 24
Peak memory 274444 kb
Host smart-a4c2dbb8-f6c9-4d01-9285-166dfbe59bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532640377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_perf.2532640377
Directory /workspace/49.spi_device_perf/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2809825939
Short name T1098
Test name
Test status
Simulation time 452640198 ps
CPU time 4.02 seconds
Started Jan 17 03:38:20 PM PST 24
Finished Jan 17 03:38:25 PM PST 24
Peak memory 236728 kb
Host smart-04612f8d-587b-4d12-934d-ef28918178c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2809825939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2809825939
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_rx_async_fifo_reset.4267346544
Short name T1712
Test name
Test status
Simulation time 50723470 ps
CPU time 0.92 seconds
Started Jan 17 03:38:13 PM PST 24
Finished Jan 17 03:38:14 PM PST 24
Peak memory 208764 kb
Host smart-3fdac5b3-9bdc-46bf-ac23-1abf61acd256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267346544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_rx_async_fifo_reset.4267346544
Directory /workspace/49.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/49.spi_device_rx_timeout.2776933026
Short name T1257
Test name
Test status
Simulation time 614181256 ps
CPU time 5.71 seconds
Started Jan 17 03:38:15 PM PST 24
Finished Jan 17 03:38:21 PM PST 24
Peak memory 217120 kb
Host smart-016673eb-5720-40a1-a5b6-701a39670cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776933026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_rx_timeout.2776933026
Directory /workspace/49.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/49.spi_device_smoke.1028554341
Short name T653
Test name
Test status
Simulation time 42842273 ps
CPU time 0.94 seconds
Started Jan 17 03:38:13 PM PST 24
Finished Jan 17 03:38:14 PM PST 24
Peak memory 208224 kb
Host smart-9430d547-d2e2-4efb-864a-44cc322dfa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028554341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_smoke.1028554341
Directory /workspace/49.spi_device_smoke/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3870789133
Short name T853
Test name
Test status
Simulation time 229595286535 ps
CPU time 2846.8 seconds
Started Jan 17 03:38:18 PM PST 24
Finished Jan 17 04:25:47 PM PST 24
Peak memory 317872 kb
Host smart-39cb13ae-e824-4749-8dd8-313f0b90f749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870789133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3870789133
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2267813371
Short name T363
Test name
Test status
Simulation time 2178478464 ps
CPU time 21.75 seconds
Started Jan 17 03:38:13 PM PST 24
Finished Jan 17 03:38:35 PM PST 24
Peak memory 217408 kb
Host smart-e5db045f-d8a1-4be8-bc08-267846e33843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267813371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2267813371
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1875517460
Short name T601
Test name
Test status
Simulation time 1518982563 ps
CPU time 3.92 seconds
Started Jan 17 03:38:15 PM PST 24
Finished Jan 17 03:38:19 PM PST 24
Peak memory 217108 kb
Host smart-d9c5fd58-3129-48d7-9883-221b2f262e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875517460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1875517460
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.288452911
Short name T500
Test name
Test status
Simulation time 737478400 ps
CPU time 1.92 seconds
Started Jan 17 03:38:13 PM PST 24
Finished Jan 17 03:38:16 PM PST 24
Peak memory 217120 kb
Host smart-43d90ef2-3453-46e6-a186-921d3f52ffb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288452911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.288452911
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1763326863
Short name T981
Test name
Test status
Simulation time 361560124 ps
CPU time 1.07 seconds
Started Jan 17 03:38:21 PM PST 24
Finished Jan 17 03:38:28 PM PST 24
Peak memory 208292 kb
Host smart-17c644fb-166b-47f3-897c-694815a880f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763326863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1763326863
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_tx_async_fifo_reset.815197955
Short name T633
Test name
Test status
Simulation time 31359517 ps
CPU time 0.77 seconds
Started Jan 17 03:38:14 PM PST 24
Finished Jan 17 03:38:15 PM PST 24
Peak memory 208816 kb
Host smart-3b0318a2-b929-49bb-8122-11d2bd770cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815197955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tx_async_fifo_reset.815197955
Directory /workspace/49.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/49.spi_device_txrx.970309367
Short name T1532
Test name
Test status
Simulation time 170265521976 ps
CPU time 576.26 seconds
Started Jan 17 03:38:13 PM PST 24
Finished Jan 17 03:47:50 PM PST 24
Peak memory 300648 kb
Host smart-a182e4aa-45b8-4501-9754-392431e8cf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970309367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_txrx.970309367
Directory /workspace/49.spi_device_txrx/latest

Test location /workspace/coverage/default/49.spi_device_upload.134916155
Short name T609
Test name
Test status
Simulation time 2633457881 ps
CPU time 9.38 seconds
Started Jan 17 03:38:21 PM PST 24
Finished Jan 17 03:38:37 PM PST 24
Peak memory 219216 kb
Host smart-dfc01a99-406d-4156-a73e-1134367c0d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134916155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.134916155
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_abort.2021437790
Short name T788
Test name
Test status
Simulation time 98080104 ps
CPU time 0.73 seconds
Started Jan 17 03:29:27 PM PST 24
Finished Jan 17 03:29:31 PM PST 24
Peak memory 207020 kb
Host smart-a42cf270-f578-4881-a251-305e3285e55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021437790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_abort.2021437790
Directory /workspace/5.spi_device_abort/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3264811095
Short name T702
Test name
Test status
Simulation time 26112086 ps
CPU time 0.78 seconds
Started Jan 17 03:29:34 PM PST 24
Finished Jan 17 03:29:37 PM PST 24
Peak memory 206772 kb
Host smart-d7eb564a-114c-46a1-a49e-5da2d584238e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264811095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
264811095
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_bit_transfer.1895165937
Short name T1368
Test name
Test status
Simulation time 794339088 ps
CPU time 2.35 seconds
Started Jan 17 03:29:29 PM PST 24
Finished Jan 17 03:29:33 PM PST 24
Peak memory 217096 kb
Host smart-34834981-bfaa-46dd-9c91-6060e47c69f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895165937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_bit_transfer.1895165937
Directory /workspace/5.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/5.spi_device_byte_transfer.1082870140
Short name T1075
Test name
Test status
Simulation time 785641252 ps
CPU time 2.89 seconds
Started Jan 17 03:29:29 PM PST 24
Finished Jan 17 03:29:34 PM PST 24
Peak memory 217128 kb
Host smart-319157dd-b78f-4c1e-9a9e-2940622c7919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082870140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_byte_transfer.1082870140
Directory /workspace/5.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2750628943
Short name T98
Test name
Test status
Simulation time 178626504 ps
CPU time 2.42 seconds
Started Jan 17 03:29:35 PM PST 24
Finished Jan 17 03:29:40 PM PST 24
Peak memory 218836 kb
Host smart-3d9ce56e-ba82-4f5b-b025-3cc1a2d8485b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750628943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2750628943
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.842199504
Short name T1007
Test name
Test status
Simulation time 48150262 ps
CPU time 0.78 seconds
Started Jan 17 03:29:31 PM PST 24
Finished Jan 17 03:29:33 PM PST 24
Peak memory 206896 kb
Host smart-290e128d-8fd2-4a72-9e02-4f27271ac76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842199504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.842199504
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_dummy_item_extra_dly.2312065089
Short name T842
Test name
Test status
Simulation time 44356950519 ps
CPU time 360.32 seconds
Started Jan 17 03:29:24 PM PST 24
Finished Jan 17 03:35:30 PM PST 24
Peak memory 290636 kb
Host smart-021751e4-ea91-4ec7-82af-d04b00fd8127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312065089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_dummy_item_extra_dly.2312065089
Directory /workspace/5.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/5.spi_device_extreme_fifo_size.3070138416
Short name T11
Test name
Test status
Simulation time 14132648308 ps
CPU time 75.31 seconds
Started Jan 17 03:29:26 PM PST 24
Finished Jan 17 03:30:46 PM PST 24
Peak memory 233192 kb
Host smart-dbdf2941-c87e-46ac-a647-ec63a3cd0061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070138416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_extreme_fifo_size.3070138416
Directory /workspace/5.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/5.spi_device_fifo_full.551690528
Short name T1298
Test name
Test status
Simulation time 108558662756 ps
CPU time 455.55 seconds
Started Jan 17 03:29:27 PM PST 24
Finished Jan 17 03:37:06 PM PST 24
Peak memory 270440 kb
Host smart-bf2b609c-ac4c-46cc-a6f3-2c702daf71fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551690528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_fifo_full.551690528
Directory /workspace/5.spi_device_fifo_full/latest

Test location /workspace/coverage/default/5.spi_device_fifo_underflow_overflow.1724652835
Short name T708
Test name
Test status
Simulation time 251814703816 ps
CPU time 310.22 seconds
Started Jan 17 03:29:24 PM PST 24
Finished Jan 17 03:34:41 PM PST 24
Peak memory 328780 kb
Host smart-d632b67b-636f-4e9a-8168-a01e993b0c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724652835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_fifo_underflow_overfl
ow.1724652835
Directory /workspace/5.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2133252592
Short name T1031
Test name
Test status
Simulation time 8273771553 ps
CPU time 37.33 seconds
Started Jan 17 03:29:39 PM PST 24
Finished Jan 17 03:30:17 PM PST 24
Peak memory 250064 kb
Host smart-ed2e3458-34b6-467f-97fc-cb1babb661bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133252592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2133252592
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1016421469
Short name T29
Test name
Test status
Simulation time 20007698592 ps
CPU time 138.01 seconds
Started Jan 17 03:29:36 PM PST 24
Finished Jan 17 03:31:55 PM PST 24
Peak memory 254580 kb
Host smart-1bb6152b-16c1-405f-9bb2-92cb67ebac97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016421469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1016421469
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1372339822
Short name T1281
Test name
Test status
Simulation time 86059777788 ps
CPU time 170.19 seconds
Started Jan 17 03:29:31 PM PST 24
Finished Jan 17 03:32:23 PM PST 24
Peak memory 257592 kb
Host smart-a4b860b7-b17c-4ee9-b7f5-d5d571a13958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372339822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1372339822
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2334603248
Short name T1230
Test name
Test status
Simulation time 1934475782 ps
CPU time 14.26 seconds
Started Jan 17 03:29:37 PM PST 24
Finished Jan 17 03:29:52 PM PST 24
Peak memory 245492 kb
Host smart-0d30e52a-ff01-4c9a-bcf8-c24e5c76d5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334603248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2334603248
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2362705209
Short name T22
Test name
Test status
Simulation time 113396549 ps
CPU time 2.78 seconds
Started Jan 17 03:29:38 PM PST 24
Finished Jan 17 03:29:42 PM PST 24
Peak memory 219332 kb
Host smart-7107f750-6959-4277-8282-b8cf0759ae0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362705209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2362705209
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_intr.1795235338
Short name T763
Test name
Test status
Simulation time 3064548009 ps
CPU time 11.49 seconds
Started Jan 17 03:29:24 PM PST 24
Finished Jan 17 03:29:42 PM PST 24
Peak memory 218228 kb
Host smart-8aea0460-df27-4bb9-a329-5a435c6ec696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795235338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intr.1795235338
Directory /workspace/5.spi_device_intr/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.49581141
Short name T1041
Test name
Test status
Simulation time 10513497564 ps
CPU time 19.41 seconds
Started Jan 17 03:29:29 PM PST 24
Finished Jan 17 03:29:50 PM PST 24
Peak memory 233632 kb
Host smart-29c3e882-e3b3-4dee-b713-c03d1037ad89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49581141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.49581141
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3145938020
Short name T624
Test name
Test status
Simulation time 26237433 ps
CPU time 1.02 seconds
Started Jan 17 03:29:27 PM PST 24
Finished Jan 17 03:29:32 PM PST 24
Peak memory 219264 kb
Host smart-a69d3830-afa6-425a-b885-afdf4ff97df1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145938020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3145938020
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3340528888
Short name T301
Test name
Test status
Simulation time 619555585 ps
CPU time 5.49 seconds
Started Jan 17 03:29:29 PM PST 24
Finished Jan 17 03:29:36 PM PST 24
Peak memory 218976 kb
Host smart-988ffc9e-d498-4732-8be1-4d13fb7b1fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340528888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3340528888
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.671148530
Short name T1374
Test name
Test status
Simulation time 1894994962 ps
CPU time 4.66 seconds
Started Jan 17 03:29:29 PM PST 24
Finished Jan 17 03:29:35 PM PST 24
Peak memory 239028 kb
Host smart-f762abf3-b321-43ff-b5ed-344ea25a3693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671148530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.671148530
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_perf.2016311150
Short name T1401
Test name
Test status
Simulation time 61781841182 ps
CPU time 332.46 seconds
Started Jan 17 03:29:26 PM PST 24
Finished Jan 17 03:35:03 PM PST 24
Peak memory 302948 kb
Host smart-b05195c6-ad76-4ea6-9ed3-23f0a0a67733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016311150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_perf.2016311150
Directory /workspace/5.spi_device_perf/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.4234491356
Short name T717
Test name
Test status
Simulation time 17772487 ps
CPU time 0.72 seconds
Started Jan 17 03:29:29 PM PST 24
Finished Jan 17 03:29:31 PM PST 24
Peak memory 217020 kb
Host smart-27d83120-f26c-4346-b59c-e93ad8b7ed43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234491356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.4234491356
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1085808666
Short name T518
Test name
Test status
Simulation time 615008673 ps
CPU time 4.78 seconds
Started Jan 17 03:29:32 PM PST 24
Finished Jan 17 03:29:38 PM PST 24
Peak memory 236968 kb
Host smart-d664cc8d-ff86-47a6-a0ad-0ff97185c582
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1085808666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1085808666
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_rx_async_fifo_reset.2529052522
Short name T1348
Test name
Test status
Simulation time 106870481 ps
CPU time 0.91 seconds
Started Jan 17 03:29:32 PM PST 24
Finished Jan 17 03:29:33 PM PST 24
Peak memory 208752 kb
Host smart-14a1cbca-473f-4359-a126-e110d21f387a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529052522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_rx_async_fifo_reset.2529052522
Directory /workspace/5.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/5.spi_device_rx_timeout.3325352354
Short name T1668
Test name
Test status
Simulation time 595929096 ps
CPU time 6.11 seconds
Started Jan 17 03:29:28 PM PST 24
Finished Jan 17 03:29:37 PM PST 24
Peak memory 217080 kb
Host smart-7b38643f-270f-4088-b8b2-97bbd34debba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325352354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_rx_timeout.3325352354
Directory /workspace/5.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/5.spi_device_smoke.2265843504
Short name T605
Test name
Test status
Simulation time 45498685 ps
CPU time 1.21 seconds
Started Jan 17 03:29:25 PM PST 24
Finished Jan 17 03:29:32 PM PST 24
Peak memory 217124 kb
Host smart-e944c26c-0f53-42fd-bc10-21f24be5313f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265843504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_smoke.2265843504
Directory /workspace/5.spi_device_smoke/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1691829453
Short name T346
Test name
Test status
Simulation time 86963235461 ps
CPU time 1041.25 seconds
Started Jan 17 03:29:36 PM PST 24
Finished Jan 17 03:46:59 PM PST 24
Peak memory 305512 kb
Host smart-22fd013c-11f3-4405-9416-0f665dddb274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691829453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1691829453
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1691196484
Short name T970
Test name
Test status
Simulation time 30739174883 ps
CPU time 18.42 seconds
Started Jan 17 03:29:28 PM PST 24
Finished Jan 17 03:29:49 PM PST 24
Peak memory 217488 kb
Host smart-67416aa0-6f68-4998-adaa-e193a8003794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691196484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1691196484
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.255253315
Short name T614
Test name
Test status
Simulation time 39533419486 ps
CPU time 25.8 seconds
Started Jan 17 03:29:38 PM PST 24
Finished Jan 17 03:30:05 PM PST 24
Peak memory 217260 kb
Host smart-3b4850a4-7a04-4e71-a3cf-cb33df7a6302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255253315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.255253315
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1931985570
Short name T494
Test name
Test status
Simulation time 14075178 ps
CPU time 0.74 seconds
Started Jan 17 03:29:28 PM PST 24
Finished Jan 17 03:29:31 PM PST 24
Peak memory 207284 kb
Host smart-cb4272f8-226a-4328-a802-e82c098d253a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931985570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1931985570
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2471079128
Short name T108
Test name
Test status
Simulation time 43995843 ps
CPU time 0.84 seconds
Started Jan 17 03:29:27 PM PST 24
Finished Jan 17 03:29:32 PM PST 24
Peak memory 207284 kb
Host smart-19d77f08-1ef7-4462-993a-c8cca6b2b38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471079128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2471079128
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_tx_async_fifo_reset.2848752778
Short name T538
Test name
Test status
Simulation time 26408322 ps
CPU time 0.77 seconds
Started Jan 17 03:29:29 PM PST 24
Finished Jan 17 03:29:31 PM PST 24
Peak memory 208780 kb
Host smart-aa6e042a-b896-4927-8682-a3bf55f0a881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848752778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tx_async_fifo_reset.2848752778
Directory /workspace/5.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/5.spi_device_txrx.1506517872
Short name T1296
Test name
Test status
Simulation time 59292304592 ps
CPU time 111.38 seconds
Started Jan 17 03:29:25 PM PST 24
Finished Jan 17 03:31:22 PM PST 24
Peak memory 249296 kb
Host smart-33252170-490d-4541-9664-56e8bf341595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506517872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_txrx.1506517872
Directory /workspace/5.spi_device_txrx/latest

Test location /workspace/coverage/default/5.spi_device_upload.2203128411
Short name T722
Test name
Test status
Simulation time 10859060322 ps
CPU time 11.33 seconds
Started Jan 17 03:29:30 PM PST 24
Finished Jan 17 03:29:42 PM PST 24
Peak memory 225452 kb
Host smart-87d512c1-f950-4b9a-9eb9-4a7d0c07dee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203128411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2203128411
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_abort.4015498877
Short name T964
Test name
Test status
Simulation time 25002218 ps
CPU time 0.74 seconds
Started Jan 17 03:29:43 PM PST 24
Finished Jan 17 03:29:44 PM PST 24
Peak memory 206968 kb
Host smart-dc294c20-40ec-448d-b39d-b3bcabbc59be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015498877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_abort.4015498877
Directory /workspace/6.spi_device_abort/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1535332078
Short name T482
Test name
Test status
Simulation time 12790682 ps
CPU time 0.72 seconds
Started Jan 17 03:29:55 PM PST 24
Finished Jan 17 03:30:01 PM PST 24
Peak memory 206768 kb
Host smart-b676c1d9-1c46-4fad-bb1c-e2edefc4f0be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535332078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
535332078
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_bit_transfer.3104891418
Short name T1550
Test name
Test status
Simulation time 316543037 ps
CPU time 3.31 seconds
Started Jan 17 03:29:46 PM PST 24
Finished Jan 17 03:29:50 PM PST 24
Peak memory 217116 kb
Host smart-37bcf00a-b42d-4aba-b43a-27543fef9c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104891418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_bit_transfer.3104891418
Directory /workspace/6.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/6.spi_device_byte_transfer.802563506
Short name T929
Test name
Test status
Simulation time 1546615596 ps
CPU time 3.25 seconds
Started Jan 17 03:29:36 PM PST 24
Finished Jan 17 03:29:41 PM PST 24
Peak memory 217124 kb
Host smart-a1bc6f26-fc2f-4df1-b4bd-a14e628ec58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802563506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_byte_transfer.802563506
Directory /workspace/6.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3714656399
Short name T628
Test name
Test status
Simulation time 3502510892 ps
CPU time 13.82 seconds
Started Jan 17 03:29:58 PM PST 24
Finished Jan 17 03:30:14 PM PST 24
Peak memory 241748 kb
Host smart-31a51186-f23a-4af0-ad8e-8827599fbc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714656399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3714656399
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1369608828
Short name T921
Test name
Test status
Simulation time 61366525 ps
CPU time 0.76 seconds
Started Jan 17 03:29:38 PM PST 24
Finished Jan 17 03:29:39 PM PST 24
Peak memory 207932 kb
Host smart-2e07eae2-4413-443f-942c-abb262e123d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369608828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1369608828
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_dummy_item_extra_dly.847215597
Short name T787
Test name
Test status
Simulation time 61314906363 ps
CPU time 574.78 seconds
Started Jan 17 03:29:42 PM PST 24
Finished Jan 17 03:39:17 PM PST 24
Peak memory 261972 kb
Host smart-3c0e78fe-5f54-45d8-90af-c1a2373ac83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847215597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_dummy_item_extra_dly.847215597
Directory /workspace/6.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/6.spi_device_extreme_fifo_size.3747751058
Short name T1111
Test name
Test status
Simulation time 843436460897 ps
CPU time 904.28 seconds
Started Jan 17 03:29:37 PM PST 24
Finished Jan 17 03:44:42 PM PST 24
Peak memory 225452 kb
Host smart-d2b85f8b-3b42-4b99-b257-14207ceddefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747751058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_extreme_fifo_size.3747751058
Directory /workspace/6.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/6.spi_device_fifo_full.4091920213
Short name T486
Test name
Test status
Simulation time 11782159769 ps
CPU time 302.06 seconds
Started Jan 17 03:29:38 PM PST 24
Finished Jan 17 03:34:41 PM PST 24
Peak memory 281356 kb
Host smart-b95ba74a-55e6-4c73-a1ef-c02cf62968cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091920213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_fifo_full.4091920213
Directory /workspace/6.spi_device_fifo_full/latest

Test location /workspace/coverage/default/6.spi_device_fifo_underflow_overflow.278537996
Short name T49
Test name
Test status
Simulation time 38077093927 ps
CPU time 324.64 seconds
Started Jan 17 03:29:39 PM PST 24
Finished Jan 17 03:35:05 PM PST 24
Peak memory 399504 kb
Host smart-e3c9b875-4a01-4b80-8d04-a96a92378294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278537996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_fifo_underflow_overflo
w.278537996
Directory /workspace/6.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.31805808
Short name T908
Test name
Test status
Simulation time 1713458864 ps
CPU time 19.28 seconds
Started Jan 17 03:29:53 PM PST 24
Finished Jan 17 03:30:18 PM PST 24
Peak memory 235908 kb
Host smart-68c77842-1420-4643-8bc6-f29e4ce5136b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31805808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.31805808
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1288552478
Short name T40
Test name
Test status
Simulation time 27093876245 ps
CPU time 214.61 seconds
Started Jan 17 03:29:56 PM PST 24
Finished Jan 17 03:33:34 PM PST 24
Peak memory 251084 kb
Host smart-c088e86c-b473-4f9e-bd44-4704c400429b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288552478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1288552478
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3450779820
Short name T973
Test name
Test status
Simulation time 64411630059 ps
CPU time 84.18 seconds
Started Jan 17 03:29:52 PM PST 24
Finished Jan 17 03:31:17 PM PST 24
Peak memory 256808 kb
Host smart-7ad5844a-af11-45fe-8616-cac62cc16805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450779820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3450779820
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.898854263
Short name T251
Test name
Test status
Simulation time 171150400 ps
CPU time 3.17 seconds
Started Jan 17 03:29:53 PM PST 24
Finished Jan 17 03:30:03 PM PST 24
Peak memory 240704 kb
Host smart-bd80215c-844b-4dd1-a470-d67ea72fffaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898854263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.898854263
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_intr.1178631045
Short name T1641
Test name
Test status
Simulation time 15141725330 ps
CPU time 16.48 seconds
Started Jan 17 03:29:40 PM PST 24
Finished Jan 17 03:29:57 PM PST 24
Peak memory 223796 kb
Host smart-f9bde2c0-7866-4715-a685-8e8ed31ae1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178631045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intr.1178631045
Directory /workspace/6.spi_device_intr/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.320909180
Short name T235
Test name
Test status
Simulation time 4375013941 ps
CPU time 16.85 seconds
Started Jan 17 03:29:59 PM PST 24
Finished Jan 17 03:30:20 PM PST 24
Peak memory 238436 kb
Host smart-9c0c39f8-0d57-472d-804b-c7875da4d249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320909180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.320909180
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1246989068
Short name T1034
Test name
Test status
Simulation time 51187504 ps
CPU time 0.98 seconds
Started Jan 17 03:29:38 PM PST 24
Finished Jan 17 03:29:40 PM PST 24
Peak memory 218156 kb
Host smart-f2b47fbc-53de-46a7-a6b4-1dce3cc75e90
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246989068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1246989068
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.664827889
Short name T1153
Test name
Test status
Simulation time 2559770714 ps
CPU time 7.82 seconds
Started Jan 17 03:29:51 PM PST 24
Finished Jan 17 03:30:01 PM PST 24
Peak memory 218772 kb
Host smart-950614c5-beb1-4871-bdb6-b7988a07b43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664827889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
664827889
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3101047995
Short name T1403
Test name
Test status
Simulation time 298751611 ps
CPU time 5.23 seconds
Started Jan 17 03:29:50 PM PST 24
Finished Jan 17 03:29:58 PM PST 24
Peak memory 249432 kb
Host smart-d6b385ff-e641-4383-adcb-e6f3e287ffb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101047995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3101047995
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_perf.1478302865
Short name T1455
Test name
Test status
Simulation time 27976383155 ps
CPU time 326.98 seconds
Started Jan 17 03:29:37 PM PST 24
Finished Jan 17 03:35:05 PM PST 24
Peak memory 257964 kb
Host smart-5f63abfb-f6df-4de0-a25f-0e655fbc7d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478302865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_perf.1478302865
Directory /workspace/6.spi_device_perf/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.3232272682
Short name T947
Test name
Test status
Simulation time 23952574 ps
CPU time 0.77 seconds
Started Jan 17 03:29:42 PM PST 24
Finished Jan 17 03:29:44 PM PST 24
Peak memory 217076 kb
Host smart-fa99b184-c2af-489c-a896-9b77572a0dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232272682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.3232272682
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.4243847917
Short name T878
Test name
Test status
Simulation time 1344674794 ps
CPU time 6.81 seconds
Started Jan 17 03:29:51 PM PST 24
Finished Jan 17 03:30:00 PM PST 24
Peak memory 220524 kb
Host smart-e1e765a5-da36-4669-a269-52405870067c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4243847917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.4243847917
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_rx_async_fifo_reset.2343821323
Short name T1567
Test name
Test status
Simulation time 160416083 ps
CPU time 0.95 seconds
Started Jan 17 03:29:45 PM PST 24
Finished Jan 17 03:29:46 PM PST 24
Peak memory 208796 kb
Host smart-8b5dc1d0-8d37-436b-aa39-4bc432aaa4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343821323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_rx_async_fifo_reset.2343821323
Directory /workspace/6.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/6.spi_device_rx_timeout.2745099323
Short name T971
Test name
Test status
Simulation time 5258605790 ps
CPU time 6.09 seconds
Started Jan 17 03:29:38 PM PST 24
Finished Jan 17 03:29:44 PM PST 24
Peak memory 217228 kb
Host smart-0a12f45b-cdae-4b4a-9d1e-20ed7e4ab0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745099323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_rx_timeout.2745099323
Directory /workspace/6.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/6.spi_device_smoke.4075996097
Short name T495
Test name
Test status
Simulation time 53099469 ps
CPU time 0.95 seconds
Started Jan 17 03:29:36 PM PST 24
Finished Jan 17 03:29:38 PM PST 24
Peak memory 208172 kb
Host smart-77c6f97c-30ee-4acc-aa70-0b87093b3ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075996097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_smoke.4075996097
Directory /workspace/6.spi_device_smoke/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.4179649398
Short name T295
Test name
Test status
Simulation time 17378476474 ps
CPU time 157.58 seconds
Started Jan 17 03:29:56 PM PST 24
Finished Jan 17 03:32:37 PM PST 24
Peak memory 267480 kb
Host smart-8fb81742-98c8-4d75-be95-059a4474b476
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179649398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.4179649398
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3247279412
Short name T813
Test name
Test status
Simulation time 17557881404 ps
CPU time 146.57 seconds
Started Jan 17 03:29:46 PM PST 24
Finished Jan 17 03:32:13 PM PST 24
Peak memory 217208 kb
Host smart-d130a6bc-073c-46c4-b97d-a617b522ee0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247279412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3247279412
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3593112100
Short name T514
Test name
Test status
Simulation time 5764660835 ps
CPU time 8.12 seconds
Started Jan 17 03:29:42 PM PST 24
Finished Jan 17 03:29:51 PM PST 24
Peak memory 217184 kb
Host smart-7a0d3722-4983-483f-b502-53703bb4a237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593112100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3593112100
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3297762499
Short name T479
Test name
Test status
Simulation time 129134167 ps
CPU time 1.24 seconds
Started Jan 17 03:29:54 PM PST 24
Finished Jan 17 03:30:01 PM PST 24
Peak memory 208936 kb
Host smart-07169826-8072-489d-8ef8-ea66e0ef8d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297762499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3297762499
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3691089154
Short name T487
Test name
Test status
Simulation time 36439815 ps
CPU time 0.78 seconds
Started Jan 17 03:29:41 PM PST 24
Finished Jan 17 03:29:42 PM PST 24
Peak memory 207300 kb
Host smart-41ec446e-1a23-44a4-a9f3-9dd8cee6d1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691089154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3691089154
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_tx_async_fifo_reset.161516857
Short name T1190
Test name
Test status
Simulation time 30193249 ps
CPU time 0.79 seconds
Started Jan 17 03:29:43 PM PST 24
Finished Jan 17 03:29:44 PM PST 24
Peak memory 208788 kb
Host smart-090cf221-2e22-4331-804f-83bd2cd783ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161516857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tx_async_fifo_reset.161516857
Directory /workspace/6.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/6.spi_device_txrx.1902049207
Short name T839
Test name
Test status
Simulation time 148711467711 ps
CPU time 403.49 seconds
Started Jan 17 03:29:35 PM PST 24
Finished Jan 17 03:36:21 PM PST 24
Peak memory 266104 kb
Host smart-9bacb4b5-b1de-45ab-9fc3-a907aac08173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902049207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_txrx.1902049207
Directory /workspace/6.spi_device_txrx/latest

Test location /workspace/coverage/default/6.spi_device_upload.3316909891
Short name T526
Test name
Test status
Simulation time 1945090080 ps
CPU time 13.44 seconds
Started Jan 17 03:29:56 PM PST 24
Finished Jan 17 03:30:13 PM PST 24
Peak memory 222628 kb
Host smart-bf80ccce-2f53-4686-9abf-e12cbe88d919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316909891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3316909891
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_abort.708764230
Short name T766
Test name
Test status
Simulation time 13923692 ps
CPU time 0.75 seconds
Started Jan 17 03:29:58 PM PST 24
Finished Jan 17 03:30:01 PM PST 24
Peak memory 207016 kb
Host smart-477b9997-b087-43f7-9921-d5948f35db14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708764230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_abort.708764230
Directory /workspace/7.spi_device_abort/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4228645845
Short name T974
Test name
Test status
Simulation time 33283601 ps
CPU time 0.69 seconds
Started Jan 17 03:30:00 PM PST 24
Finished Jan 17 03:30:04 PM PST 24
Peak memory 206788 kb
Host smart-dacac966-0a79-485c-ba01-43ffeffd8bcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228645845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
228645845
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_bit_transfer.570426528
Short name T1263
Test name
Test status
Simulation time 80849225 ps
CPU time 1.92 seconds
Started Jan 17 03:29:59 PM PST 24
Finished Jan 17 03:30:02 PM PST 24
Peak memory 217140 kb
Host smart-4ba8380e-ae62-4e56-a068-7a8f05fdd011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570426528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_bit_transfer.570426528
Directory /workspace/7.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/7.spi_device_byte_transfer.609483305
Short name T1520
Test name
Test status
Simulation time 574550761 ps
CPU time 3.15 seconds
Started Jan 17 03:29:55 PM PST 24
Finished Jan 17 03:30:03 PM PST 24
Peak memory 217224 kb
Host smart-6d1c9e4f-7281-44ee-b9ac-979b8ba343cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609483305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_byte_transfer.609483305
Directory /workspace/7.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3903619545
Short name T524
Test name
Test status
Simulation time 25439846 ps
CPU time 0.75 seconds
Started Jan 17 03:29:56 PM PST 24
Finished Jan 17 03:30:01 PM PST 24
Peak memory 206940 kb
Host smart-f505f647-654f-4b84-8334-334cc8480be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903619545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3903619545
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_dummy_item_extra_dly.4045270145
Short name T877
Test name
Test status
Simulation time 123619474910 ps
CPU time 606.71 seconds
Started Jan 17 03:29:56 PM PST 24
Finished Jan 17 03:40:07 PM PST 24
Peak memory 261256 kb
Host smart-74303703-c0fe-4502-b683-f281ce7f4355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045270145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_dummy_item_extra_dly.4045270145
Directory /workspace/7.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/7.spi_device_extreme_fifo_size.2740319113
Short name T1103
Test name
Test status
Simulation time 486010432539 ps
CPU time 1020.23 seconds
Started Jan 17 03:29:53 PM PST 24
Finished Jan 17 03:46:58 PM PST 24
Peak memory 220392 kb
Host smart-ee59e4b5-b8c7-4b92-b5fb-c624f5ae955e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740319113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_extreme_fifo_size.2740319113
Directory /workspace/7.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/7.spi_device_fifo_full.402483319
Short name T800
Test name
Test status
Simulation time 31698107166 ps
CPU time 1906.58 seconds
Started Jan 17 03:29:56 PM PST 24
Finished Jan 17 04:01:47 PM PST 24
Peak memory 284848 kb
Host smart-cdd92e12-cc63-4615-8a3e-43bb5355cd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402483319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_fifo_full.402483319
Directory /workspace/7.spi_device_fifo_full/latest

Test location /workspace/coverage/default/7.spi_device_fifo_underflow_overflow.3318877290
Short name T773
Test name
Test status
Simulation time 39988302958 ps
CPU time 175.56 seconds
Started Jan 17 03:29:53 PM PST 24
Finished Jan 17 03:32:55 PM PST 24
Peak memory 282808 kb
Host smart-a99a364e-ae19-463d-a307-d8d16cf95117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318877290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_fifo_underflow_overfl
ow.3318877290
Directory /workspace/7.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3362286709
Short name T327
Test name
Test status
Simulation time 36335682399 ps
CPU time 65.01 seconds
Started Jan 17 03:30:03 PM PST 24
Finished Jan 17 03:31:09 PM PST 24
Peak memory 257876 kb
Host smart-e57f7629-cf91-4f05-8300-be754b757797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362286709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3362286709
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2887689551
Short name T791
Test name
Test status
Simulation time 46449825422 ps
CPU time 101.67 seconds
Started Jan 17 03:30:06 PM PST 24
Finished Jan 17 03:31:48 PM PST 24
Peak memory 251800 kb
Host smart-9fe5f8d0-b02d-45a9-be98-5cf5f209d50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887689551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2887689551
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.816740808
Short name T893
Test name
Test status
Simulation time 1147749321 ps
CPU time 11.3 seconds
Started Jan 17 03:30:09 PM PST 24
Finished Jan 17 03:30:20 PM PST 24
Peak memory 232128 kb
Host smart-812d3ff5-ed5e-4910-90f9-90e55d29588d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816740808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.816740808
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2701461752
Short name T1433
Test name
Test status
Simulation time 1235885722 ps
CPU time 7.19 seconds
Started Jan 17 03:29:56 PM PST 24
Finished Jan 17 03:30:07 PM PST 24
Peak memory 219840 kb
Host smart-73d3ac41-5ffd-4833-ac25-2d126b087f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701461752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2701461752
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_intr.2753451174
Short name T755
Test name
Test status
Simulation time 67080977724 ps
CPU time 71.46 seconds
Started Jan 17 03:29:58 PM PST 24
Finished Jan 17 03:31:11 PM PST 24
Peak memory 241472 kb
Host smart-38c3b477-2e36-43f8-9923-379decb60f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753451174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intr.2753451174
Directory /workspace/7.spi_device_intr/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1381636813
Short name T1662
Test name
Test status
Simulation time 1246541100 ps
CPU time 16.22 seconds
Started Jan 17 03:30:00 PM PST 24
Finished Jan 17 03:30:20 PM PST 24
Peak memory 257568 kb
Host smart-56a1d976-31fb-4a28-96d3-a1ddfa52dbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381636813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1381636813
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2047101467
Short name T579
Test name
Test status
Simulation time 45410159 ps
CPU time 1.02 seconds
Started Jan 17 03:29:59 PM PST 24
Finished Jan 17 03:30:02 PM PST 24
Peak memory 219088 kb
Host smart-1e7c4a67-c85a-49d1-89ad-43857723a837
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047101467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2047101467
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.546259542
Short name T816
Test name
Test status
Simulation time 10324345616 ps
CPU time 33.47 seconds
Started Jan 17 03:30:02 PM PST 24
Finished Jan 17 03:30:37 PM PST 24
Peak memory 247108 kb
Host smart-db3cd1f8-1338-4aef-bc37-9710a72792d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546259542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
546259542
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.532966925
Short name T1158
Test name
Test status
Simulation time 2000583067 ps
CPU time 6.52 seconds
Started Jan 17 03:29:58 PM PST 24
Finished Jan 17 03:30:06 PM PST 24
Peak memory 241700 kb
Host smart-f26168a7-5f16-4b8b-a658-73814f7acfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532966925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.532966925
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_perf.2551861891
Short name T485
Test name
Test status
Simulation time 23778336048 ps
CPU time 399.39 seconds
Started Jan 17 03:30:02 PM PST 24
Finished Jan 17 03:36:43 PM PST 24
Peak memory 250020 kb
Host smart-a872b74a-4369-4db2-af39-6e1e4457651d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551861891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_perf.2551861891
Directory /workspace/7.spi_device_perf/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.2697532473
Short name T863
Test name
Test status
Simulation time 34869961 ps
CPU time 0.71 seconds
Started Jan 17 03:29:59 PM PST 24
Finished Jan 17 03:30:01 PM PST 24
Peak memory 217084 kb
Host smart-9cedd028-7815-4307-bce1-05a97122376b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697532473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.2697532473
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4244636012
Short name T1476
Test name
Test status
Simulation time 71132891 ps
CPU time 3.95 seconds
Started Jan 17 03:30:00 PM PST 24
Finished Jan 17 03:30:07 PM PST 24
Peak memory 235680 kb
Host smart-528ace8a-0780-4485-bf5c-f2c5adce33d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4244636012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4244636012
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_rx_async_fifo_reset.2117064152
Short name T10
Test name
Test status
Simulation time 35634320 ps
CPU time 0.84 seconds
Started Jan 17 03:29:58 PM PST 24
Finished Jan 17 03:30:01 PM PST 24
Peak memory 208788 kb
Host smart-c865585a-2055-4f49-bc70-18ea2f558b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117064152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_rx_async_fifo_reset.2117064152
Directory /workspace/7.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/7.spi_device_rx_timeout.3309485482
Short name T1562
Test name
Test status
Simulation time 3208651071 ps
CPU time 5.82 seconds
Started Jan 17 03:30:00 PM PST 24
Finished Jan 17 03:30:09 PM PST 24
Peak memory 217148 kb
Host smart-753bdfaa-3b15-473c-888d-24177af8f6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309485482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_rx_timeout.3309485482
Directory /workspace/7.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/7.spi_device_smoke.2205763136
Short name T520
Test name
Test status
Simulation time 113433638 ps
CPU time 1.18 seconds
Started Jan 17 03:29:51 PM PST 24
Finished Jan 17 03:29:54 PM PST 24
Peak memory 216896 kb
Host smart-b3edf409-f924-4368-8ff8-84bce354d9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205763136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_smoke.2205763136
Directory /workspace/7.spi_device_smoke/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4142016978
Short name T1212
Test name
Test status
Simulation time 13960679887 ps
CPU time 54.97 seconds
Started Jan 17 03:30:01 PM PST 24
Finished Jan 17 03:30:59 PM PST 24
Peak memory 217376 kb
Host smart-95619717-22d2-4df3-8ace-7545e47ca7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142016978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4142016978
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3150514219
Short name T945
Test name
Test status
Simulation time 752729498 ps
CPU time 4.65 seconds
Started Jan 17 03:29:54 PM PST 24
Finished Jan 17 03:30:04 PM PST 24
Peak memory 217124 kb
Host smart-de5d64b2-fc00-4718-be44-242d9db7eb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150514219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3150514219
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2011718873
Short name T1696
Test name
Test status
Simulation time 108458552 ps
CPU time 1.28 seconds
Started Jan 17 03:29:58 PM PST 24
Finished Jan 17 03:30:01 PM PST 24
Peak memory 208928 kb
Host smart-69c6ea3d-7a48-4a7f-9630-d0f01f535ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011718873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2011718873
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2574956808
Short name T752
Test name
Test status
Simulation time 135025062 ps
CPU time 0.71 seconds
Started Jan 17 03:29:59 PM PST 24
Finished Jan 17 03:30:01 PM PST 24
Peak memory 207272 kb
Host smart-dd9558a2-35d6-4535-bd4c-860506fc9ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574956808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2574956808
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_tx_async_fifo_reset.1807346902
Short name T986
Test name
Test status
Simulation time 17060333 ps
CPU time 0.78 seconds
Started Jan 17 03:30:05 PM PST 24
Finished Jan 17 03:30:06 PM PST 24
Peak memory 208760 kb
Host smart-0cd5312c-7375-4a51-9340-4425d2a34dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807346902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tx_async_fifo_reset.1807346902
Directory /workspace/7.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/7.spi_device_txrx.4141654401
Short name T767
Test name
Test status
Simulation time 27373929326 ps
CPU time 225.62 seconds
Started Jan 17 03:29:53 PM PST 24
Finished Jan 17 03:33:39 PM PST 24
Peak memory 286012 kb
Host smart-edc5e3b2-adca-4448-b7d4-58a2b4d89498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141654401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_txrx.4141654401
Directory /workspace/7.spi_device_txrx/latest

Test location /workspace/coverage/default/7.spi_device_upload.3532060250
Short name T287
Test name
Test status
Simulation time 168164340 ps
CPU time 2.82 seconds
Started Jan 17 03:30:03 PM PST 24
Finished Jan 17 03:30:07 PM PST 24
Peak memory 226696 kb
Host smart-ad0c37d9-8fd5-4267-b4f4-03779ea0d75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532060250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3532060250
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_abort.846621046
Short name T1484
Test name
Test status
Simulation time 15450512 ps
CPU time 0.76 seconds
Started Jan 17 03:30:10 PM PST 24
Finished Jan 17 03:30:11 PM PST 24
Peak memory 207008 kb
Host smart-bbe56fc0-5651-4158-90ec-c863d6ec6fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846621046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_abort.846621046
Directory /workspace/8.spi_device_abort/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2844384939
Short name T1179
Test name
Test status
Simulation time 42014039 ps
CPU time 0.82 seconds
Started Jan 17 03:30:18 PM PST 24
Finished Jan 17 03:30:20 PM PST 24
Peak memory 206816 kb
Host smart-f13b2fa2-7e20-43fc-bac4-eb1bb03cbcca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844384939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
844384939
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_bit_transfer.957562887
Short name T599
Test name
Test status
Simulation time 698817219 ps
CPU time 2.35 seconds
Started Jan 17 03:30:07 PM PST 24
Finished Jan 17 03:30:10 PM PST 24
Peak memory 217084 kb
Host smart-a82edb5d-c80d-4ccd-9fbb-7b79a1409972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957562887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_bit_transfer.957562887
Directory /workspace/8.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/8.spi_device_byte_transfer.940027105
Short name T977
Test name
Test status
Simulation time 518194215 ps
CPU time 2.57 seconds
Started Jan 17 03:30:06 PM PST 24
Finished Jan 17 03:30:09 PM PST 24
Peak memory 217124 kb
Host smart-432d1e38-3023-43c3-bafd-59442e81c4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940027105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_byte_transfer.940027105
Directory /workspace/8.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3461129883
Short name T1279
Test name
Test status
Simulation time 1892945961 ps
CPU time 3.73 seconds
Started Jan 17 03:30:11 PM PST 24
Finished Jan 17 03:30:15 PM PST 24
Peak memory 225360 kb
Host smart-ee353353-7860-4c9f-945d-3f5b3540f503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461129883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3461129883
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1507212768
Short name T1652
Test name
Test status
Simulation time 23289757 ps
CPU time 0.81 seconds
Started Jan 17 03:30:03 PM PST 24
Finished Jan 17 03:30:05 PM PST 24
Peak memory 207900 kb
Host smart-0da4b9ed-83d0-4602-98a2-38d71b796503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507212768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1507212768
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_dummy_item_extra_dly.4245792259
Short name T1688
Test name
Test status
Simulation time 109684875243 ps
CPU time 1004.15 seconds
Started Jan 17 03:30:02 PM PST 24
Finished Jan 17 03:46:48 PM PST 24
Peak memory 284564 kb
Host smart-a72c4796-68de-49ac-96b5-2af368cf80ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245792259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_dummy_item_extra_dly.4245792259
Directory /workspace/8.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/8.spi_device_extreme_fifo_size.621660027
Short name T266
Test name
Test status
Simulation time 2569722017 ps
CPU time 28.77 seconds
Started Jan 17 03:30:03 PM PST 24
Finished Jan 17 03:30:33 PM PST 24
Peak memory 231704 kb
Host smart-21e953be-de94-4505-ad2e-8ea631d0e1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621660027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_extreme_fifo_size.621660027
Directory /workspace/8.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/8.spi_device_fifo_full.4274757594
Short name T1399
Test name
Test status
Simulation time 173213660639 ps
CPU time 860.06 seconds
Started Jan 17 03:30:05 PM PST 24
Finished Jan 17 03:44:26 PM PST 24
Peak memory 271012 kb
Host smart-88836379-414a-4cc3-8533-943b4b6a9028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274757594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_fifo_full.4274757594
Directory /workspace/8.spi_device_fifo_full/latest

Test location /workspace/coverage/default/8.spi_device_fifo_underflow_overflow.4095234822
Short name T557
Test name
Test status
Simulation time 56354765752 ps
CPU time 534.47 seconds
Started Jan 17 03:29:59 PM PST 24
Finished Jan 17 03:38:58 PM PST 24
Peak memory 434268 kb
Host smart-b0057adc-7bee-45a2-a69c-f4cb6ce1eac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095234822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_fifo_underflow_overfl
ow.4095234822
Directory /workspace/8.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2814830860
Short name T1602
Test name
Test status
Simulation time 121496840250 ps
CPU time 107.03 seconds
Started Jan 17 03:30:15 PM PST 24
Finished Jan 17 03:32:04 PM PST 24
Peak memory 250044 kb
Host smart-5c4281d3-6bc4-4b64-b206-10851c15524f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814830860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2814830860
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2251303850
Short name T1452
Test name
Test status
Simulation time 8970719777 ps
CPU time 16.99 seconds
Started Jan 17 03:30:08 PM PST 24
Finished Jan 17 03:30:25 PM PST 24
Peak memory 253884 kb
Host smart-327700f8-1f18-4e82-8088-88eb4e64a55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251303850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2251303850
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1881880607
Short name T1186
Test name
Test status
Simulation time 6369437099 ps
CPU time 12.71 seconds
Started Jan 17 03:30:11 PM PST 24
Finished Jan 17 03:30:24 PM PST 24
Peak memory 220920 kb
Host smart-1c9c520b-13d6-424c-8f8e-8d4f5015edd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881880607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1881880607
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_intr.1949479645
Short name T874
Test name
Test status
Simulation time 138671718440 ps
CPU time 64.91 seconds
Started Jan 17 03:30:04 PM PST 24
Finished Jan 17 03:31:10 PM PST 24
Peak memory 241156 kb
Host smart-4210867d-a75a-4e2c-b115-99887b4163cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949479645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intr.1949479645
Directory /workspace/8.spi_device_intr/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3179731331
Short name T1297
Test name
Test status
Simulation time 83504248119 ps
CPU time 26.12 seconds
Started Jan 17 03:30:10 PM PST 24
Finished Jan 17 03:30:37 PM PST 24
Peak memory 248768 kb
Host smart-ac9dd6c2-73b5-491c-9d97-55675a382315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179731331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3179731331
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1431320988
Short name T1701
Test name
Test status
Simulation time 14598317 ps
CPU time 1 seconds
Started Jan 17 03:30:04 PM PST 24
Finished Jan 17 03:30:06 PM PST 24
Peak memory 218100 kb
Host smart-fe8595a5-3997-42ba-ae99-c83ee640dc33
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431320988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1431320988
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1837540329
Short name T1489
Test name
Test status
Simulation time 1614246213 ps
CPU time 9.27 seconds
Started Jan 17 03:30:11 PM PST 24
Finished Jan 17 03:30:21 PM PST 24
Peak memory 255240 kb
Host smart-80a789c4-4e5e-4bdb-ad24-57d3f6752385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837540329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1837540329
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.492797528
Short name T1256
Test name
Test status
Simulation time 1777149817 ps
CPU time 6.82 seconds
Started Jan 17 03:30:07 PM PST 24
Finished Jan 17 03:30:14 PM PST 24
Peak memory 238488 kb
Host smart-099bdc57-ea70-47b3-bc80-fb75b2e1d9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492797528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.492797528
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_perf.3938747797
Short name T1422
Test name
Test status
Simulation time 458338703183 ps
CPU time 2881.26 seconds
Started Jan 17 03:30:00 PM PST 24
Finished Jan 17 04:18:05 PM PST 24
Peak memory 271704 kb
Host smart-ff63e7b5-409e-477f-b7a9-f03a6b04c900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938747797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_perf.3938747797
Directory /workspace/8.spi_device_perf/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.3623293726
Short name T1628
Test name
Test status
Simulation time 17304361 ps
CPU time 0.75 seconds
Started Jan 17 03:30:09 PM PST 24
Finished Jan 17 03:30:10 PM PST 24
Peak memory 217092 kb
Host smart-23896822-1e94-4f1e-ab11-0217372d3b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623293726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.3623293726
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.202597478
Short name T847
Test name
Test status
Simulation time 283738880 ps
CPU time 4.53 seconds
Started Jan 17 03:30:09 PM PST 24
Finished Jan 17 03:30:14 PM PST 24
Peak memory 236656 kb
Host smart-deef4c41-9008-46cb-bdd0-09dab4ba5c2c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=202597478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.202597478
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_rx_async_fifo_reset.1369105146
Short name T1379
Test name
Test status
Simulation time 246610210 ps
CPU time 0.94 seconds
Started Jan 17 03:30:09 PM PST 24
Finished Jan 17 03:30:11 PM PST 24
Peak memory 208804 kb
Host smart-09fa8006-941c-400c-b001-51f3635728d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369105146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_rx_async_fifo_reset.1369105146
Directory /workspace/8.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/8.spi_device_rx_timeout.2833060462
Short name T1215
Test name
Test status
Simulation time 3906167043 ps
CPU time 6.33 seconds
Started Jan 17 03:30:01 PM PST 24
Finished Jan 17 03:30:10 PM PST 24
Peak memory 217500 kb
Host smart-66a59dcd-f832-4c53-b4f3-bb33a7518d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833060462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_rx_timeout.2833060462
Directory /workspace/8.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/8.spi_device_smoke.1937376110
Short name T1655
Test name
Test status
Simulation time 46792796 ps
CPU time 1.11 seconds
Started Jan 17 03:30:05 PM PST 24
Finished Jan 17 03:30:06 PM PST 24
Peak memory 216956 kb
Host smart-0366d5e4-faef-4bca-9847-748aa82b4793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937376110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_smoke.1937376110
Directory /workspace/8.spi_device_smoke/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3986775783
Short name T1046
Test name
Test status
Simulation time 225663980640 ps
CPU time 7331.84 seconds
Started Jan 17 03:30:13 PM PST 24
Finished Jan 17 05:32:26 PM PST 24
Peak memory 353760 kb
Host smart-954da154-b10a-4334-a485-a5c60f56ba91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986775783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3986775783
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1570991979
Short name T802
Test name
Test status
Simulation time 791130404 ps
CPU time 7.75 seconds
Started Jan 17 03:30:10 PM PST 24
Finished Jan 17 03:30:18 PM PST 24
Peak memory 217352 kb
Host smart-4ef84234-85e9-4953-8c30-985e41ab6ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570991979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1570991979
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3969670821
Short name T1061
Test name
Test status
Simulation time 2067015995 ps
CPU time 13.48 seconds
Started Jan 17 03:30:02 PM PST 24
Finished Jan 17 03:30:17 PM PST 24
Peak memory 217136 kb
Host smart-ec3818f2-edca-4349-9d83-641240e5734a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969670821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3969670821
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1029474936
Short name T1077
Test name
Test status
Simulation time 33307751 ps
CPU time 0.74 seconds
Started Jan 17 03:30:07 PM PST 24
Finished Jan 17 03:30:08 PM PST 24
Peak memory 207280 kb
Host smart-55b6bdbe-baa9-458d-a448-21e926fc5381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029474936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1029474936
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2554945105
Short name T1370
Test name
Test status
Simulation time 94433909 ps
CPU time 1.06 seconds
Started Jan 17 03:30:07 PM PST 24
Finished Jan 17 03:30:09 PM PST 24
Peak memory 208456 kb
Host smart-9f39c332-f970-4542-91a1-b6c11c5bdf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554945105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2554945105
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_tx_async_fifo_reset.3961774107
Short name T621
Test name
Test status
Simulation time 28008029 ps
CPU time 0.79 seconds
Started Jan 17 03:30:10 PM PST 24
Finished Jan 17 03:30:11 PM PST 24
Peak memory 208740 kb
Host smart-fa03ec2e-57af-4fe2-95cd-a7b7823ac4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961774107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tx_async_fifo_reset.3961774107
Directory /workspace/8.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/8.spi_device_txrx.3504729493
Short name T1538
Test name
Test status
Simulation time 47714053229 ps
CPU time 154.33 seconds
Started Jan 17 03:30:09 PM PST 24
Finished Jan 17 03:32:44 PM PST 24
Peak memory 275292 kb
Host smart-1519a40b-2f23-4a91-b68b-03b78f2b4760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504729493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_txrx.3504729493
Directory /workspace/8.spi_device_txrx/latest

Test location /workspace/coverage/default/8.spi_device_upload.503692987
Short name T1742
Test name
Test status
Simulation time 7417241734 ps
CPU time 29.71 seconds
Started Jan 17 03:30:08 PM PST 24
Finished Jan 17 03:30:38 PM PST 24
Peak memory 231456 kb
Host smart-112b2d9d-965f-493e-bb7f-befa6bcaf26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503692987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.503692987
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_abort.1807707438
Short name T1684
Test name
Test status
Simulation time 16669310 ps
CPU time 0.76 seconds
Started Jan 17 03:30:21 PM PST 24
Finished Jan 17 03:30:26 PM PST 24
Peak memory 206964 kb
Host smart-32ba3476-78d4-4112-bbba-9370dd0f03fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807707438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_abort.1807707438
Directory /workspace/9.spi_device_abort/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.4033216511
Short name T643
Test name
Test status
Simulation time 71468936 ps
CPU time 0.75 seconds
Started Jan 17 03:30:18 PM PST 24
Finished Jan 17 03:30:20 PM PST 24
Peak memory 206780 kb
Host smart-404fdb42-a7bc-47ae-869f-2e777aa175bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033216511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4
033216511
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_bit_transfer.621558695
Short name T1266
Test name
Test status
Simulation time 277923265 ps
CPU time 2.37 seconds
Started Jan 17 03:30:25 PM PST 24
Finished Jan 17 03:30:29 PM PST 24
Peak memory 216784 kb
Host smart-b2c9fcbb-1fa4-4efe-a75f-f91e2fbee640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621558695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_bit_transfer.621558695
Directory /workspace/9.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/9.spi_device_byte_transfer.2962748668
Short name T906
Test name
Test status
Simulation time 213923738 ps
CPU time 2.68 seconds
Started Jan 17 03:30:14 PM PST 24
Finished Jan 17 03:30:19 PM PST 24
Peak memory 217092 kb
Host smart-d0a8eef6-1ad4-4d33-8b75-c9fb2c78a89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962748668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_byte_transfer.2962748668
Directory /workspace/9.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.563527234
Short name T285
Test name
Test status
Simulation time 927114906 ps
CPU time 5.94 seconds
Started Jan 17 03:30:15 PM PST 24
Finished Jan 17 03:30:23 PM PST 24
Peak memory 241268 kb
Host smart-a1503e59-bf60-4db3-8715-0c999da7c207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563527234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.563527234
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.531608733
Short name T1343
Test name
Test status
Simulation time 22497529 ps
CPU time 0.77 seconds
Started Jan 17 03:30:21 PM PST 24
Finished Jan 17 03:30:26 PM PST 24
Peak memory 207924 kb
Host smart-f1fb17f8-c11b-45c4-8903-9f16248047e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531608733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.531608733
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_dummy_item_extra_dly.4235158792
Short name T1221
Test name
Test status
Simulation time 102839329886 ps
CPU time 999.68 seconds
Started Jan 17 03:30:15 PM PST 24
Finished Jan 17 03:46:57 PM PST 24
Peak memory 321100 kb
Host smart-a17ec43d-e995-4a35-87ad-939bb241c6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235158792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_dummy_item_extra_dly.4235158792
Directory /workspace/9.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/9.spi_device_extreme_fifo_size.3275350983
Short name T1738
Test name
Test status
Simulation time 77196249291 ps
CPU time 3852.97 seconds
Started Jan 17 03:30:11 PM PST 24
Finished Jan 17 04:34:25 PM PST 24
Peak memory 222408 kb
Host smart-a2a30b52-de9a-4f88-bc64-5c7dd7599326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275350983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_extreme_fifo_size.3275350983
Directory /workspace/9.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/9.spi_device_fifo_full.2112983021
Short name T1108
Test name
Test status
Simulation time 163657986204 ps
CPU time 1939.59 seconds
Started Jan 17 03:30:21 PM PST 24
Finished Jan 17 04:02:45 PM PST 24
Peak memory 271756 kb
Host smart-7cbaa279-70ca-4fd7-9ec1-707d89dcccfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112983021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_fifo_full.2112983021
Directory /workspace/9.spi_device_fifo_full/latest

Test location /workspace/coverage/default/9.spi_device_fifo_underflow_overflow.892849840
Short name T53
Test name
Test status
Simulation time 60496761731 ps
CPU time 186.23 seconds
Started Jan 17 03:30:16 PM PST 24
Finished Jan 17 03:33:25 PM PST 24
Peak memory 306940 kb
Host smart-91ed9e81-c05e-4437-be3a-869499ff6fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892849840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_fifo_underflow_overflo
w.892849840
Directory /workspace/9.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2759514242
Short name T1250
Test name
Test status
Simulation time 5473086766 ps
CPU time 30.96 seconds
Started Jan 17 03:30:14 PM PST 24
Finished Jan 17 03:30:47 PM PST 24
Peak memory 239728 kb
Host smart-7ef908d7-5b4f-4b02-8910-e0f97fffcc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759514242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2759514242
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3854949721
Short name T196
Test name
Test status
Simulation time 101817285172 ps
CPU time 637.94 seconds
Started Jan 17 03:30:16 PM PST 24
Finished Jan 17 03:40:56 PM PST 24
Peak memory 268968 kb
Host smart-c7cf0f6b-78c9-4849-9e44-023b5187f03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854949721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3854949721
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.143940832
Short name T350
Test name
Test status
Simulation time 95066746711 ps
CPU time 313.8 seconds
Started Jan 17 03:30:18 PM PST 24
Finished Jan 17 03:35:33 PM PST 24
Peak memory 272156 kb
Host smart-f978db35-e1fd-4548-b4c4-b69cb34cf46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143940832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
143940832
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1992462412
Short name T263
Test name
Test status
Simulation time 720446561 ps
CPU time 14.3 seconds
Started Jan 17 03:30:12 PM PST 24
Finished Jan 17 03:30:27 PM PST 24
Peak memory 248760 kb
Host smart-322a4780-7c5f-4382-b714-c1f895368508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992462412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1992462412
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.4217701010
Short name T902
Test name
Test status
Simulation time 199621991 ps
CPU time 3.44 seconds
Started Jan 17 03:30:16 PM PST 24
Finished Jan 17 03:30:21 PM PST 24
Peak memory 234712 kb
Host smart-a6679ebe-9c72-4577-b19b-03863989ed12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217701010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.4217701010
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_intr.2142556048
Short name T662
Test name
Test status
Simulation time 10836972416 ps
CPU time 54.79 seconds
Started Jan 17 03:30:25 PM PST 24
Finished Jan 17 03:31:21 PM PST 24
Peak memory 233144 kb
Host smart-de9686a6-9999-4bbe-b34c-a6f0306f382b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142556048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intr.2142556048
Directory /workspace/9.spi_device_intr/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2964297952
Short name T308
Test name
Test status
Simulation time 5093475169 ps
CPU time 13.49 seconds
Started Jan 17 03:30:12 PM PST 24
Finished Jan 17 03:30:26 PM PST 24
Peak memory 226880 kb
Host smart-c1538d6c-555c-4d5d-8000-b1f6893db406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964297952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2964297952
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2490872427
Short name T1115
Test name
Test status
Simulation time 45000217 ps
CPU time 1.09 seconds
Started Jan 17 03:30:13 PM PST 24
Finished Jan 17 03:30:15 PM PST 24
Peak memory 219120 kb
Host smart-0db7474e-4f5e-4453-a76a-b27add3ca75e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490872427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2490872427
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.248027493
Short name T1089
Test name
Test status
Simulation time 645953222 ps
CPU time 5.18 seconds
Started Jan 17 03:30:14 PM PST 24
Finished Jan 17 03:30:21 PM PST 24
Peak memory 239064 kb
Host smart-e4f57de1-31cb-47f1-87be-d5a0eb623c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248027493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
248027493
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.4271121231
Short name T690
Test name
Test status
Simulation time 66125732823 ps
CPU time 18.1 seconds
Started Jan 17 03:30:15 PM PST 24
Finished Jan 17 03:30:35 PM PST 24
Peak memory 238196 kb
Host smart-b9b35b8c-352d-4b26-9b70-ef796d10d0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271121231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4271121231
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_perf.3774276797
Short name T1334
Test name
Test status
Simulation time 17228493233 ps
CPU time 274.95 seconds
Started Jan 17 03:30:18 PM PST 24
Finished Jan 17 03:34:54 PM PST 24
Peak memory 290972 kb
Host smart-6d799050-fc94-494b-b643-986fffb1263c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774276797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_perf.3774276797
Directory /workspace/9.spi_device_perf/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.2353116156
Short name T87
Test name
Test status
Simulation time 17482787 ps
CPU time 0.74 seconds
Started Jan 17 03:30:25 PM PST 24
Finished Jan 17 03:30:27 PM PST 24
Peak memory 216780 kb
Host smart-c4cebb45-db2e-4f58-9523-d903ba756cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353116156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.2353116156
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_rx_async_fifo_reset.1110481614
Short name T993
Test name
Test status
Simulation time 157845912 ps
CPU time 1 seconds
Started Jan 17 03:30:13 PM PST 24
Finished Jan 17 03:30:16 PM PST 24
Peak memory 208804 kb
Host smart-15829df4-4519-4105-a908-acaca7f0ba1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110481614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_rx_async_fifo_reset.1110481614
Directory /workspace/9.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/9.spi_device_rx_timeout.1352075742
Short name T577
Test name
Test status
Simulation time 561099807 ps
CPU time 5.55 seconds
Started Jan 17 03:30:12 PM PST 24
Finished Jan 17 03:30:18 PM PST 24
Peak memory 217084 kb
Host smart-5d86a5d9-7f99-4278-8f75-4ff5b56d6a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352075742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_rx_timeout.1352075742
Directory /workspace/9.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/9.spi_device_smoke.2627281439
Short name T895
Test name
Test status
Simulation time 266063515 ps
CPU time 1.16 seconds
Started Jan 17 03:30:12 PM PST 24
Finished Jan 17 03:30:14 PM PST 24
Peak memory 217132 kb
Host smart-a3341d88-a9e3-42bd-8460-7fbbfe181eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627281439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_smoke.2627281439
Directory /workspace/9.spi_device_smoke/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1349990564
Short name T349
Test name
Test status
Simulation time 505915485898 ps
CPU time 1052.34 seconds
Started Jan 17 03:30:20 PM PST 24
Finished Jan 17 03:47:58 PM PST 24
Peak memory 577964 kb
Host smart-8b0afe36-f9ac-4a14-bbc7-7d507171bd65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349990564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1349990564
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3571086035
Short name T1492
Test name
Test status
Simulation time 1848941543 ps
CPU time 26.34 seconds
Started Jan 17 03:30:12 PM PST 24
Finished Jan 17 03:30:39 PM PST 24
Peak memory 220360 kb
Host smart-954e61e9-a8f0-4fd1-8e54-a5921de4ced6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571086035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3571086035
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2654898274
Short name T1506
Test name
Test status
Simulation time 4455917860 ps
CPU time 11 seconds
Started Jan 17 03:30:12 PM PST 24
Finished Jan 17 03:30:23 PM PST 24
Peak memory 217220 kb
Host smart-94c4074e-037d-48fc-94bd-98eab066479a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654898274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2654898274
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2533122705
Short name T674
Test name
Test status
Simulation time 65478068 ps
CPU time 3.18 seconds
Started Jan 17 03:30:25 PM PST 24
Finished Jan 17 03:30:30 PM PST 24
Peak memory 217120 kb
Host smart-4c7312fc-996d-4307-9d4e-87010afac8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533122705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2533122705
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3188089649
Short name T1322
Test name
Test status
Simulation time 50357755 ps
CPU time 0.82 seconds
Started Jan 17 03:30:16 PM PST 24
Finished Jan 17 03:30:19 PM PST 24
Peak memory 207240 kb
Host smart-e5f705b3-d257-40d7-9680-81c40caff5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188089649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3188089649
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_tx_async_fifo_reset.2367639539
Short name T1466
Test name
Test status
Simulation time 21417859 ps
CPU time 0.76 seconds
Started Jan 17 03:30:11 PM PST 24
Finished Jan 17 03:30:13 PM PST 24
Peak memory 208768 kb
Host smart-70fc9161-a98b-41d9-8466-790f36dceb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367639539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tx_async_fifo_reset.2367639539
Directory /workspace/9.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/9.spi_device_txrx.515857094
Short name T1138
Test name
Test status
Simulation time 111191458967 ps
CPU time 247.74 seconds
Started Jan 17 03:30:12 PM PST 24
Finished Jan 17 03:34:20 PM PST 24
Peak memory 299952 kb
Host smart-cc2b0fab-9f00-4988-8af0-48494932a5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515857094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_txrx.515857094
Directory /workspace/9.spi_device_txrx/latest
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