Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7396889	1			T1	1		T2	209		T3	3045
all_values[1]	7396889	1			T1	1		T2	209		T3	3045
all_values[2]	7396889	1			T1	1		T2	209		T3	3045
all_values[3]	7396889	1			T1	1		T2	209		T3	3045
all_values[4]	7396889	1			T1	1		T2	209		T3	3045
all_values[5]	7396889	1			T1	1		T2	209		T3	3045

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42928663

1

T1

6

T2

1254

T3

18270

auto[1]

1452671

1

T20

35

T23

16

T29

179779

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44311708

1

T1

6

T2

1254

T3

18270

auto[1]

69626

1

T17

5

T4

613

T19

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	7080304	1			T1	1		T2	209		T3	3045
all_values[0]	auto[0]	auto[1]	40240	1			T4	401		T5	4		T6	17
all_values[0]	auto[1]	auto[0]	275387	1			T20	5		T29	1		T31	1
all_values[0]	auto[1]	auto[1]	958	1			T20	4		T29	3		T31	1
all_values[1]	auto[0]	auto[0]	7094468	1			T1	1		T2	209		T3	3045
all_values[1]	auto[0]	auto[1]	19212	1			T4	164		T20	3		T5	4
all_values[1]	auto[1]	auto[0]	282424	1			T23	1		T29	2		T31	1
all_values[1]	auto[1]	auto[1]	785	1			T20	4		T23	2		T29	1
all_values[2]	auto[0]	auto[0]	7040367	1			T1	1		T2	209		T3	3045
all_values[2]	auto[0]	auto[1]	6688	1			T4	48		T20	1		T23	33
all_values[2]	auto[1]	auto[0]	349403	1			T20	5		T23	4		T29	5
all_values[2]	auto[1]	auto[1]	431	1			T20	2		T29	1		T31	1
all_values[3]	auto[0]	auto[0]	7211739	1			T1	1		T2	209		T3	3045
all_values[3]	auto[0]	auto[1]	187	1			T20	2		T29	1		T31	1
all_values[3]	auto[1]	auto[0]	184774	1			T20	5		T23	1		T29	89878
all_values[3]	auto[1]	auto[1]	189	1			T20	1		T23	3		T29	5
all_values[4]	auto[0]	auto[0]	7141484	1			T1	1		T2	209		T3	3045
all_values[4]	auto[0]	auto[1]	221	1			T20	4		T29	1		T31	3
all_values[4]	auto[1]	auto[0]	255013	1			T20	3		T23	1		T29	3
all_values[4]	auto[1]	auto[1]	171	1			T20	2		T29	2		T31	2
all_values[5]	auto[0]	auto[0]	7293368	1			T1	1		T2	209		T3	3045
all_values[5]	auto[0]	auto[1]	385	1			T17	5		T19	5		T20	2
all_values[5]	auto[1]	auto[0]	102977	1			T20	2		T23	2		T29	89876
all_values[5]	auto[1]	auto[1]	159	1			T20	2		T23	2		T29	2