Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	44887	1			T7	8		T12	6		T4	627
auto[SpiFlashAddrCfg]	9272	1			T7	4		T8	4		T12	2
auto[SpiFlashAddr3b]	11064	1			T7	10		T8	4		T9	2
auto[SpiFlashAddr4b]	9247	1			T7	6		T8	4		T9	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41808

1

T8

12

T9

4

T12

18

auto[1]

32662

1

T7

28

T4

310

T14

20

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40031

1

T7

14

T8

4

T9

2

auto[1]

34439

1

T7

14

T8

8

T9

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	50515	1			T7	6		T12	4		T4	679
values[1]	1414	1			T7	4		T12	2		T4	4
values[2]	1808	1			T8	2		T4	10		T5	8
values[3]	1764	1			T4	7		T5	1		T23	8
values[4]	1832	1			T7	6		T13	4		T4	16
values[5]	1789	1			T8	2		T4	13		T5	1
values[6]	1724	1			T13	4		T4	13		T14	2
values[7]	1795	1			T4	11		T5	2		T6	1
values[8]	11829	1			T7	12		T8	8		T9	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39456

1

T7

28

T8

12

T9

4

auto[1]

35014

1

T6

47

T28

503

T29

539

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

71839

1

T7

28

T8

12

T9

4

write

2631

1

T4

17

T14

2

T5

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

23681

1

T7

16

T8

8

T9

4

valids[0x1]

50789

1

T7

12

T8

4

T12

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1912	1			T12	4		T4	10		T5	2
internal_process_ops[0x5a]	1844	1			T8	2		T4	15		T14	2
internal_process_ops[0x05]	28428	1			T4	549		T14	4		T5	6
internal_process_ops[0x35]	1834	1			T4	11		T5	2		T6	2
internal_process_ops[0x15]	1822	1			T4	8		T14	4		T5	1
internal_process_ops[0x03]	1294	1			T4	12		T23	8		T27	2
internal_process_ops[0x0b]	1268	1			T7	4		T4	11		T5	3
internal_process_ops[0x3b]	1404	1			T12	8		T13	4		T4	7
internal_process_ops[0x6b]	1379	1			T9	2		T4	10		T5	4
internal_process_ops[0xbb]	1442	1			T7	6		T13	4		T4	14
internal_process_ops[0xeb]	1354	1			T8	2		T9	2		T13	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73189

1

T7

28

T8

12

T9

4

auto[1]

1281

1

T4

10

T14

2

T23

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72031

1

T7

28

T8

12

T9

4

auto[1]

2439

1

T4

29

T5

1

T6

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

13188

1

T12

6

T4

409

T5

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

9085

1

T7

8

T4

214

T14

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2695

1

T8

4

T12

2

T4

23

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2278

1

T7

4

T4

21

T14

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

3286

1

T8

4

T9

2

T12

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2635

1

T7

10

T4

23

T14

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2660

1

T8

4

T9

2

T12

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2262

1

T7

6

T4

36

T14

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

112

1

T5

3

T148

6

T36

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

67

1

T4

1

T23

2

T27

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

71

1

T4

3

T5

2

T36

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

91

1

T36

2

T39

2

T40

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

96

1

T36

6

T39

3

T40

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

56

1

T23

2

T27

2

T38

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

77

1

T27

1

T36

4

T37

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

96

1

T4

6

T38

1

T39

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

110

1

T42

2

T36

1

T37

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

67

1

T36

2

T37

2

T38

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

83

1

T4

4

T5

1

T36

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

99

1

T23

1

T36

1

T37

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

102

1

T149

2

T150

2

T36

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

80

1

T23

1

T38

1

T39

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

59

1

T23

2

T40

3

T151

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

101

1

T4

3

T14

2

T35

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12524

1

T6

5

T28

204

T29

178

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

9471

1

T6

30

T28

74

T29

93

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1898

1

T6

1

T28

25

T29

43

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1739

1

T6

2

T28

41

T29

25

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2297

1

T6

1

T28

42

T29

34

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2152

1

T6

3

T28

33

T29

56

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1958

1

T6

3

T28

35

T29

48

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1711

1

T6

2

T28

29

T29

41

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

69

1

T28

1

T29

1

T69

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

58

1

T29

3

T69

1

T36

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

83

1

T30

2

T31

1

T121

9

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

68

1

T28

2

T29

2

T30

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

70

1

T29

4

T30

7

T120

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

80

1

T28

3

T69

4

T120

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

89

1

T28

3

T69

1

T121

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

98

1

T29

1

T30

2

T69

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

86

1

T28

3

T29

2

T30

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

81

1

T29

1

T30

3

T69

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

87

1

T28

1

T30

3

T36

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

81

1

T28

1

T29

4

T31

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

85

1

T28

1

T31

2

T120

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

83

1

T28

1

T29

1

T69

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

71

1

T28

1

T29

1

T30

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

75

1

T28

3

T29

1

T147

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4975	1			T4	57		T5	5		T23	28
auto[0]	values[0]	valids[0x1]	20757	1			T7	6		T12	4		T4	622
auto[0]	values[1]	valids[0x1]	772	1			T7	4		T12	2		T4	4
auto[0]	values[2]	valids[0x0]	667	1			T8	2		T4	5		T5	5
auto[0]	values[2]	valids[0x1]	365	1			T4	5		T5	3		T23	6
auto[0]	values[3]	valids[0x0]	678	1			T4	7		T23	7		T27	3
auto[0]	values[3]	valids[0x1]	347	1			T5	1		T23	1		T35	2
auto[0]	values[4]	valids[0x0]	708	1			T7	6		T13	4		T4	13
auto[0]	values[4]	valids[0x1]	402	1			T4	3		T5	3		T27	1
auto[0]	values[5]	valids[0x0]	668	1			T8	2		T4	8		T5	1
auto[0]	values[5]	valids[0x1]	397	1			T4	5		T23	2		T71	2
auto[0]	values[6]	valids[0x0]	642	1			T13	4		T4	10		T14	2
auto[0]	values[6]	valids[0x1]	327	1			T4	3		T5	4		T23	1
auto[0]	values[7]	valids[0x0]	701	1			T4	7		T5	2		T23	6
auto[0]	values[7]	valids[0x1]	344	1			T4	4		T23	3		T27	1
auto[0]	values[8]	valids[0x0]	4253	1			T7	10		T8	4		T9	4
auto[0]	values[8]	valids[0x1]	2453	1			T7	2		T8	4		T12	2
auto[1]	values[0]	valids[0x0]	4748	1			T6	6		T28	89		T29	109
auto[1]	values[0]	valids[0x1]	20035	1			T6	32		T28	251		T29	206
auto[1]	values[1]	valids[0x1]	642	1			T28	3		T29	12		T30	4
auto[1]	values[2]	valids[0x0]	470	1			T28	6		T29	19		T30	11
auto[1]	values[2]	valids[0x1]	306	1			T28	3		T29	10		T30	2
auto[1]	values[3]	valids[0x0]	475	1			T28	12		T29	8		T30	7
auto[1]	values[3]	valids[0x1]	264	1			T28	3		T29	6		T30	2
auto[1]	values[4]	valids[0x0]	419	1			T28	7		T29	8		T30	7
auto[1]	values[4]	valids[0x1]	303	1			T28	2		T29	3		T30	1
auto[1]	values[5]	valids[0x0]	405	1			T28	7		T29	4		T30	4
auto[1]	values[5]	valids[0x1]	319	1			T28	3		T29	11		T30	1
auto[1]	values[6]	valids[0x0]	443	1			T28	8		T29	9		T30	5
auto[1]	values[6]	valids[0x1]	312	1			T28	7		T29	9		T31	5
auto[1]	values[7]	valids[0x0]	446	1			T6	1		T28	1		T29	7
auto[1]	values[7]	valids[0x1]	304	1			T28	2		T29	3		T30	1
auto[1]	values[8]	valids[0x0]	2983	1			T6	7		T28	65		T29	63
auto[1]	values[8]	valids[0x1]	2140	1			T6	1		T28	34		T29	52