Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21575

1

T7

1

T8

1

T9

1

auto[1]

26483

1

T4

537

T5

3

T6

27

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16276

1

T7

1

T8

1

T9

1

auto[1]

31782

1

T4

568

T5

9

T6

30

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	7228	1			T7	1		T8	1		T9	1
auto[524288:1048575]	5841	1			T4	58		T5	1		T23	110
auto[1048576:1572863]	5802	1			T13	5		T4	51		T5	10
auto[1572864:2097151]	5799	1			T13	5		T4	114		T23	72
auto[2097152:2621439]	5795	1			T4	43		T5	1		T6	2
auto[2621440:3145727]	6360	1			T4	39		T5	5		T6	2
auto[3145728:3670015]	5873	1			T4	29		T5	1		T6	32
auto[3670016:4194303]	5360	1			T4	259		T5	2		T23	1

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47399

1

T7

1

T8

1

T9

1

auto[1]

659

1

T4

21

T23

8

T28

1

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23311

1

T7

1

T8

1

T9

1

auto[1]

24747

1

T13

4

T4

317

T5

13

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1354	1			T7	1		T8	1		T9	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	719	1			T4	6		T5	1		T23	1
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	749	1			T4	5		T23	6		T28	5
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	448	1			T4	4		T23	1		T34	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	940	1			T13	1		T4	2		T5	6
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	486	1			T4	2		T5	2		T34	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	881	1			T13	5		T4	4		T34	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	473	1			T4	3		T27	2		T28	7
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	828	1			T4	4		T5	1		T23	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	424	1			T4	2		T6	1		T23	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	808	1			T4	4		T6	1		T23	4
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	481	1			T4	1		T23	5		T28	8
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	779	1			T4	4		T6	2		T23	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	469	1			T4	2		T5	1		T6	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	765	1			T4	13		T5	1		T28	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	415	1			T4	6		T5	1		T28	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	880	1			T4	6		T5	5		T28	6
auto[0]	auto[1]	auto[0:524287]	auto[1]	480	1			T4	9		T28	2		T29	4
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	878	1			T4	5		T5	1		T23	9
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	506	1			T4	6		T23	4		T27	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	890	1			T13	4		T4	1		T5	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	483	1			T4	2		T5	1		T23	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	762	1			T4	4		T23	7		T27	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	449	1			T4	6		T23	5		T27	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	777	1			T4	1		T6	1		T27	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	461	1			T34	1		T27	3		T28	6
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	924	1			T4	6		T5	1		T23	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	466	1			T4	4		T5	1		T6	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	791	1			T4	1		T34	5		T27	14
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	491	1			T23	1		T34	4		T27	7
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	831	1			T4	14		T34	10		T28	7
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	487	1			T4	7		T23	1		T34	2
auto[1]	auto[0]	auto[0:524287]	auto[0]	200	1			T4	2		T27	1		T29	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	1857	1			T4	23		T27	2		T29	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	138	1			T4	2		T28	1		T29	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1346	1			T4	22		T28	3		T29	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	146	1			T4	1		T27	1		T28	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1225	1			T4	29		T27	12		T28	7
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	139	1			T27	1		T28	3		T36	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1600	1			T27	3		T28	6		T36	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	130	1			T4	2		T23	1		T28	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1266	1			T4	34		T23	1		T28	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	148	1			T4	1		T23	1		T28	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1443	1			T4	10		T23	28		T28	7
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	145	1			T4	2		T6	2		T23	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1280	1			T4	20		T6	25		T23	10
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	120	1			T4	6		T28	1		T29	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1109	1			T4	138		T28	50		T29	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	156	1			T4	3		T28	1		T29	3
auto[1]	auto[1]	auto[0:524287]	auto[1]	1582	1			T4	29		T28	2		T29	3
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	167	1			T4	1		T23	4		T27	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1609	1			T4	13		T23	86		T27	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	154	1			T4	1		T23	1		T29	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1478	1			T4	13		T23	23		T29	8
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	146	1			T4	3		T23	2		T29	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1349	1			T4	94		T23	58		T29	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	155	1			T28	2		T29	2		T69	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	1754	1			T28	10		T29	2		T69	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	161	1			T4	1		T5	1		T23	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1929	1			T4	12		T5	2		T23	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	163	1			T27	1		T28	1		T30	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1755	1			T27	1		T28	6		T30	19
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	171	1			T4	4		T28	2		T29	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1462	1			T4	71		T28	5		T29	3

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	10925	1			T7	1		T8	1		T9	1
auto[0]	auto[0]	auto[1]	94	1			T4	2		T23	1		T30	1
auto[0]	auto[1]	auto[0]	10453	1			T13	4		T4	67		T5	10
auto[0]	auto[1]	auto[1]	103	1			T4	5		T23	2		T30	3
auto[1]	auto[0]	auto[0]	12068	1			T4	286		T6	27		T23	41
auto[1]	auto[0]	auto[1]	224	1			T4	6		T23	2		T30	3
auto[1]	auto[1]	auto[0]	13953	1			T4	237		T5	3		T23	173
auto[1]	auto[1]	auto[1]	238	1			T4	8		T23	3		T28	1