Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22519

1

T8

12

T9

4

T12

18

auto[1]

16937

1

T7

28

T4

310

T14

20

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4849	1			T4	78		T5	43		T23	268
values[1]	4389	1			T8	12		T9	4		T13	12
values[2]	5774	1			T7	28		T12	18		T4	272
values[3]	4848	1			T23	44		T71	4		T37	45
values[4]	4145	1			T4	84		T23	25		T27	26
values[5]	5715	1			T4	50		T14	20		T5	20
values[6]	4703	1			T4	41		T27	20		T209	8
values[7]	5033	1			T4	243		T27	23		T36	60

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4920	1			T13	12		T4	317		T27	20
values[1]	5090	1			T23	89		T36	23		T37	40
values[2]	5538	1			T4	78		T23	45		T34	26
values[3]	4220	1			T4	49		T5	23		T27	76
values[4]	4448	1			T9	4		T4	117		T5	20
values[5]	4479	1			T4	64		T14	20		T23	20
values[6]	5162	1			T7	28		T8	12		T12	18
values[7]	5599	1			T23	225		T198	10		T196	22

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	309	1			T149	8		T206	24		T177	96
auto[0]	values[0]	values[1]	293	1			T23	82		T37	12		T210	2
auto[0]	values[0]	values[2]	359	1			T23	13		T38	15		T39	12
auto[0]	values[0]	values[3]	331	1			T5	6		T156	11		T176	10
auto[0]	values[0]	values[4]	265	1			T211	2		T39	10		T212	12
auto[0]	values[0]	values[5]	364	1			T38	17		T151	15		T205	14
auto[0]	values[0]	values[6]	307	1			T4	48		T5	10		T163	12
auto[0]	values[0]	values[7]	452	1			T23	20		T54	12		T213	4
auto[0]	values[1]	values[0]	284	1			T13	12		T38	39		T214	75
auto[0]	values[1]	values[1]	445	1			T39	23		T40	10		T215	18
auto[0]	values[1]	values[2]	265	1			T36	26		T151	11		T176	17
auto[0]	values[1]	values[3]	253	1			T4	40		T27	9		T38	12
auto[0]	values[1]	values[4]	343	1			T9	4		T151	12		T170	9
auto[0]	values[1]	values[5]	301	1			T40	7		T151	13		T169	12
auto[0]	values[1]	values[6]	373	1			T8	12		T39	11		T163	14
auto[0]	values[1]	values[7]	281	1			T198	10		T36	22		T151	11
auto[0]	values[2]	values[0]	614	1			T4	164		T38	10		T163	5
auto[0]	values[2]	values[1]	242	1			T216	4		T163	10		T161	18
auto[0]	values[2]	values[2]	498	1			T4	10		T70	12		T37	16
auto[0]	values[2]	values[3]	365	1			T27	12		T182	6		T204	14
auto[0]	values[2]	values[4]	437	1			T4	16		T39	17		T40	12
auto[0]	values[2]	values[5]	327	1			T151	13		T163	11		T217	14
auto[0]	values[2]	values[6]	473	1			T12	18		T39	7		T188	13
auto[0]	values[2]	values[7]	432	1			T151	13		T163	43		T194	9
auto[0]	values[3]	values[0]	327	1			T71	4		T39	8		T40	14
auto[0]	values[3]	values[1]	288	1			T39	11		T40	9		T218	8
auto[0]	values[3]	values[2]	354	1			T37	21		T173	6		T40	24
auto[0]	values[3]	values[3]	292	1			T37	8		T205	10		T157	12
auto[0]	values[3]	values[4]	352	1			T40	8		T172	14		T157	28
auto[0]	values[3]	values[5]	197	1			T39	17		T151	17		T156	15
auto[0]	values[3]	values[6]	456	1			T39	23		T219	20		T151	20
auto[0]	values[3]	values[7]	366	1			T23	39		T38	12		T39	10
auto[0]	values[4]	values[0]	286	1			T42	65		T39	12		T205	7
auto[0]	values[4]	values[1]	498	1			T40	14		T163	7		T164	41
auto[0]	values[4]	values[2]	174	1			T23	10		T27	10		T39	16
auto[0]	values[4]	values[3]	278	1			T40	44		T172	17		T176	15
auto[0]	values[4]	values[4]	315	1			T197	8		T40	39		T151	22
auto[0]	values[4]	values[5]	356	1			T4	47		T220	2		T38	18
auto[0]	values[4]	values[6]	297	1			T4	12		T36	17		T37	16
auto[0]	values[4]	values[7]	273	1			T188	9		T176	28		T221	8
auto[0]	values[5]	values[0]	314	1			T222	10		T151	14		T170	19
auto[0]	values[5]	values[1]	335	1			T36	15		T37	10		T151	30
auto[0]	values[5]	values[2]	423	1			T34	26		T148	30		T171	12
auto[0]	values[5]	values[3]	332	1			T27	11		T150	24		T163	11
auto[0]	values[5]	values[4]	362	1			T4	8		T5	12		T37	10
auto[0]	values[5]	values[5]	310	1			T23	11		T36	12		T38	20
auto[0]	values[5]	values[6]	427	1			T36	15		T38	12		T170	30
auto[0]	values[5]	values[7]	357	1			T23	12		T55	14		T151	10
auto[0]	values[6]	values[0]	356	1			T27	14		T223	20		T165	13
auto[0]	values[6]	values[1]	385	1			T38	20		T39	11		T224	34
auto[0]	values[6]	values[2]	639	1			T225	12		T36	21		T163	10
auto[0]	values[6]	values[3]	214	1			T205	21		T158	11		T226	15
auto[0]	values[6]	values[4]	239	1			T4	15		T209	8		T38	14
auto[0]	values[6]	values[5]	363	1			T227	2		T156	71		T194	22
auto[0]	values[6]	values[6]	383	1			T38	16		T228	10		T163	15
auto[0]	values[6]	values[7]	343	1			T196	22		T36	23		T163	12
auto[0]	values[7]	values[0]	615	1			T4	134		T36	14		T37	19
auto[0]	values[7]	values[1]	339	1			T151	13		T163	14		T165	9
auto[0]	values[7]	values[2]	433	1			T27	16		T40	20		T151	12
auto[0]	values[7]	values[3]	475	1			T36	11		T37	11		T38	14
auto[0]	values[7]	values[4]	239	1			T165	12		T156	16		T157	104
auto[0]	values[7]	values[5]	321	1			T229	34		T230	8		T231	2
auto[0]	values[7]	values[6]	306	1			T4	13		T164	8		T156	135
auto[0]	values[7]	values[7]	287	1			T36	14		T193	10		T39	12
auto[1]	values[0]	values[0]	256	1			T206	8		T177	10		T179	9
auto[1]	values[0]	values[1]	287	1			T23	7		T37	8		T232	13
auto[1]	values[0]	values[2]	217	1			T23	7		T38	15		T39	8
auto[1]	values[0]	values[3]	210	1			T5	17		T156	18		T176	10
auto[1]	values[0]	values[4]	243	1			T83	6		T39	10		T157	6
auto[1]	values[0]	values[5]	239	1			T38	7		T151	9		T205	8
auto[1]	values[0]	values[6]	226	1			T4	30		T5	10		T163	8
auto[1]	values[0]	values[7]	491	1			T23	139		T186	10		T179	10
auto[1]	values[1]	values[0]	239	1			T35	14		T38	10		T164	68
auto[1]	values[1]	values[1]	160	1			T39	7		T40	10		T163	6
auto[1]	values[1]	values[2]	175	1			T36	3		T151	14		T176	3
auto[1]	values[1]	values[3]	171	1			T4	9		T27	24		T38	8
auto[1]	values[1]	values[4]	336	1			T151	8		T170	11		T156	36
auto[1]	values[1]	values[5]	244	1			T40	13		T151	7		T169	11
auto[1]	values[1]	values[6]	176	1			T39	9		T163	6		T170	5
auto[1]	values[1]	values[7]	343	1			T36	6		T151	9		T170	31
auto[1]	values[2]	values[0]	350	1			T4	4		T38	10		T163	98
auto[1]	values[2]	values[1]	177	1			T163	10		T161	9		T233	12
auto[1]	values[2]	values[2]	470	1			T4	68		T37	4		T40	2
auto[1]	values[2]	values[3]	218	1			T27	11		T163	8		T170	6
auto[1]	values[2]	values[4]	293	1			T4	10		T39	3		T40	51
auto[1]	values[2]	values[5]	228	1			T151	17		T163	9		T157	10
auto[1]	values[2]	values[6]	242	1			T7	28		T39	31		T188	9
auto[1]	values[2]	values[7]	408	1			T151	7		T163	12		T194	134
auto[1]	values[3]	values[0]	330	1			T39	12		T40	55		T205	8
auto[1]	values[3]	values[1]	273	1			T39	15		T40	11		T172	9
auto[1]	values[3]	values[2]	315	1			T37	4		T40	16		T163	5
auto[1]	values[3]	values[3]	223	1			T37	12		T205	10		T157	8
auto[1]	values[3]	values[4]	249	1			T40	36		T172	6		T157	15
auto[1]	values[3]	values[5]	206	1			T39	11		T151	8		T156	5
auto[1]	values[3]	values[6]	329	1			T39	34		T151	5		T172	11
auto[1]	values[3]	values[7]	291	1			T23	5		T38	8		T39	10
auto[1]	values[4]	values[0]	129	1			T39	8		T205	13		T157	11
auto[1]	values[4]	values[1]	325	1			T40	6		T163	25		T164	8
auto[1]	values[4]	values[2]	214	1			T23	15		T27	16		T39	4
auto[1]	values[4]	values[3]	220	1			T40	9		T172	3		T234	16
auto[1]	values[4]	values[4]	155	1			T40	9		T151	10		T206	12
auto[1]	values[4]	values[5]	206	1			T4	17		T38	9		T163	8
auto[1]	values[4]	values[6]	231	1			T4	8		T36	3		T37	34
auto[1]	values[4]	values[7]	188	1			T188	23		T176	16		T235	14
auto[1]	values[5]	values[0]	133	1			T151	8		T170	7		T156	4
auto[1]	values[5]	values[1]	362	1			T36	8		T37	10		T151	21
auto[1]	values[5]	values[2]	295	1			T36	29		T37	6		T39	10
auto[1]	values[5]	values[3]	296	1			T27	9		T163	9		T164	7
auto[1]	values[5]	values[4]	314	1			T4	42		T5	8		T37	16
auto[1]	values[5]	values[5]	422	1			T14	20		T23	9		T36	10
auto[1]	values[5]	values[6]	428	1			T36	12		T38	14		T170	4
auto[1]	values[5]	values[7]	605	1			T23	10		T151	10		T170	20
auto[1]	values[6]	values[0]	148	1			T27	6		T165	7		T194	9
auto[1]	values[6]	values[1]	402	1			T38	12		T39	141		T181	10
auto[1]	values[6]	values[2]	281	1			T36	4		T187	28		T163	12
auto[1]	values[6]	values[3]	163	1			T205	5		T236	6		T158	9
auto[1]	values[6]	values[4]	143	1			T4	26		T38	9		T172	5
auto[1]	values[6]	values[5]	233	1			T156	12		T194	8		T206	12
auto[1]	values[6]	values[6]	233	1			T38	8		T163	5		T172	7
auto[1]	values[6]	values[7]	178	1			T36	29		T163	8		T156	10
auto[1]	values[7]	values[0]	230	1			T4	15		T36	6		T37	6
auto[1]	values[7]	values[1]	279	1			T151	9		T163	6		T165	11
auto[1]	values[7]	values[2]	426	1			T27	7		T40	120		T151	8
auto[1]	values[7]	values[3]	179	1			T36	9		T37	19		T38	6
auto[1]	values[7]	values[4]	163	1			T165	10		T156	8		T157	19
auto[1]	values[7]	values[5]	162	1			T205	7		T157	13		T194	6
auto[1]	values[7]	values[6]	275	1			T4	81		T164	12		T156	16
auto[1]	values[7]	values[7]	304	1			T36	6		T39	8		T237	12