Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	473	1			T13	2		T4	6		T5	2
auto[ReadAddrCrossIntoMailbox]	379	1			T13	4		T4	5		T5	1
auto[ReadAddrCrossOutOfMailbox]	421	1			T13	2		T4	5		T5	1
auto[ReadAddrCrossAllMailbox]	295	1			T13	2		T4	7		T23	1
auto[ReadAddrOutsideMailbox]	4377	1			T7	10		T8	2		T9	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2949

1

T7

5

T8

1

T9

2

auto[1]

2996

1

T7

5

T8

1

T9

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	915	1			T4	12		T23	8		T27	2
read_ops[0x0b]	942	1			T7	4		T4	11		T5	3
read_ops[0x3b]	1027	1			T12	8		T13	4		T4	7
read_ops[0x6b]	1040	1			T9	2		T4	10		T5	4
read_ops[0xbb]	1048	1			T7	6		T13	4		T4	14
read_ops[0xeb]	973	1			T8	2		T9	2		T13	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T4	1		T204	2		T163	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T4	1		T37	1		T40	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T27	1		T38	1		T40	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	38	1			T40	2		T151	1		T163	3
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T157	4		T177	1		T158	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T4	1		T23	1		T27	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	26	1			T4	2		T170	1		T238	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T36	1		T40	1		T151	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	329	1			T4	5		T23	2		T35	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	341	1			T4	2		T23	5		T35	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T4	1		T163	2		T170	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T27	1		T38	1		T238	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T4	1		T37	1		T39	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T38	1		T39	1		T40	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T40	1		T163	1		T238	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T39	1		T151	1		T163	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T38	1		T239	1		T165	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T4	3		T27	1		T39	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	348	1			T7	2		T4	3		T23	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	363	1			T7	2		T4	3		T5	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T198	1		T36	1		T37	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T198	1		T36	1		T38	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T211	1		T37	1		T40	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T5	1		T211	1		T36	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T13	1		T23	1		T197	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T13	1		T197	1		T37	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T164	1		T157	2		T240	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T40	1		T172	2		T240	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	400	1			T12	4		T13	1		T4	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	379	1			T12	4		T13	1		T4	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	51	1			T4	1		T5	1		T23	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T4	1		T198	4		T40	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T38	1		T40	1		T238	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T37	1		T40	2		T163	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	38	1			T4	1		T39	2		T40	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T23	1		T39	1		T151	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T163	1		T164	2		T170	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T4	1		T241	1		T172	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	378	1			T9	1		T4	2		T23	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	388	1			T9	1		T4	4		T5	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T27	1		T39	1		T151	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T5	1		T37	1		T170	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T13	1		T4	1		T23	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	37	1			T13	1		T4	2		T197	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	38	1			T209	1		T39	1		T40	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	48	1			T4	2		T23	1		T209	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T13	1		T209	1		T163	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	31	1			T13	1		T23	1		T209	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	400	1			T7	3		T4	4		T23	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	361	1			T7	3		T4	5		T5	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T13	1		T4	1		T37	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T13	1		T23	1		T38	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T13	1		T23	2		T38	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T13	1		T4	1		T23	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	39	1			T197	1		T37	2		T38	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	45	1			T4	1		T5	1		T23	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	28	1			T4	1		T163	1		T170	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T37	2		T40	2		T163	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	348	1			T8	1		T9	1		T4	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	342	1			T8	1		T9	1		T4	2