Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7396889	1			T1	1		T2	209		T3	3045
all_pins[1]	7396889	1			T1	1		T2	209		T3	3045
all_pins[2]	7396889	1			T1	1		T2	209		T3	3045
all_pins[3]	7396889	1			T1	1		T2	209		T3	3045
all_pins[4]	7396889	1			T1	1		T2	209		T3	3045
all_pins[5]	7396889	1			T1	1		T2	209		T3	3045

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	44376029	1			T1	6		T2	1254		T3	18270
values[0x1]	5305	1			T20	15		T23	7		T29	1960
transitions[0x0=>0x1]	4298	1			T20	10		T23	7		T29	1960
transitions[0x1=>0x0]	4315	1			T20	10		T23	7		T29	1960

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7395897	1			T1	1		T2	209		T3	3045
all_pins[0]	values[0x1]	992	1			T20	4		T29	3		T31	1
all_pins[0]	transitions[0x0=>0x1]	409	1			T20	1		T29	3		T31	1
all_pins[0]	transitions[0x1=>0x0]	225	1			T20	1		T23	2		T29	1
all_pins[1]	values[0x0]	7396081	1			T1	1		T2	209		T3	3045
all_pins[1]	values[0x1]	808	1			T20	4		T23	2		T29	1
all_pins[1]	transitions[0x0=>0x1]	564	1			T20	3		T23	2		T29	1
all_pins[1]	transitions[0x1=>0x0]	201	1			T20	1		T29	1		T31	1
all_pins[2]	values[0x0]	7396444	1			T1	1		T2	209		T3	3045
all_pins[2]	values[0x1]	445	1			T20	2		T29	1		T31	1
all_pins[2]	transitions[0x0=>0x1]	388	1			T20	2		T29	1		T31	1
all_pins[2]	transitions[0x1=>0x0]	132	1			T20	1		T23	3		T29	5
all_pins[3]	values[0x0]	7396700	1			T1	1		T2	209		T3	3045
all_pins[3]	values[0x1]	189	1			T20	1		T23	3		T29	5
all_pins[3]	transitions[0x0=>0x1]	153	1			T20	1		T23	3		T29	5
all_pins[3]	transitions[0x1=>0x0]	135	1			T20	2		T29	2		T31	2
all_pins[4]	values[0x0]	7396718	1			T1	1		T2	209		T3	3045
all_pins[4]	values[0x1]	171	1			T20	2		T29	2		T31	2
all_pins[4]	transitions[0x0=>0x1]	136	1			T20	2		T29	2		T31	2
all_pins[4]	transitions[0x1=>0x0]	2665	1			T20	2		T23	2		T29	1948
all_pins[5]	values[0x0]	7394189	1			T1	1		T2	209		T3	3045
all_pins[5]	values[0x1]	2700	1			T20	2		T23	2		T29	1948
all_pins[5]	transitions[0x0=>0x1]	2648	1			T20	1		T23	2		T29	1948
all_pins[5]	transitions[0x1=>0x0]	957	1			T20	3		T29	3		T31	1