Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5766	1			T8	12		T4	46		T5	20
values[1]	5126	1			T4	168		T34	26		T193	10
values[2]	4401	1			T9	4		T4	127		T27	33
values[3]	4848	1			T12	18		T4	49		T23	139
values[4]	4006	1			T7	28		T4	65		T14	20
values[5]	4752	1			T4	50		T23	66		T27	40
values[6]	5717	1			T4	216		T5	43		T23	154
values[7]	4840	1			T13	12		T4	96		T27	49

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4768	1			T13	12		T4	145		T5	20
values[1]	4577	1			T9	4		T4	193		T34	26
values[2]	4626	1			T4	114		T23	292		T27	56
values[3]	5374	1			T8	12		T4	238		T23	25
values[4]	4977	1			T5	20		T42	65		T36	20
values[5]	5506	1			T7	28		T12	18		T4	49
values[6]	5163	1			T27	20		T36	74		T193	10
values[7]	4465	1			T4	78		T23	20		T27	23

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38799

1

T7

28

T8

12

T9

4

auto[1]

657

1

T4

10

T14

2

T23

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	648	1			T4	25		T36	30		T39	20
auto[0]	values[0]	values[1]	773	1			T151	20		T242	6		T156	95
auto[0]	values[0]	values[2]	766	1			T4	20		T36	25		T164	20
auto[0]	values[0]	values[3]	688	1			T8	12		T36	20		T39	20
auto[0]	values[0]	values[4]	604	1			T5	20		T42	65		T151	32
auto[0]	values[0]	values[5]	811	1			T224	34		T40	187		T172	27
auto[0]	values[0]	values[6]	939	1			T36	20		T37	19		T39	20
auto[0]	values[0]	values[7]	438	1			T23	19		T40	53		T59	4
auto[0]	values[1]	values[0]	474	1			T39	37		T173	6		T40	20
auto[0]	values[1]	values[1]	570	1			T34	26		T37	40		T214	75
auto[0]	values[1]	values[2]	444	1			T38	26		T151	20		T243	6
auto[0]	values[1]	values[3]	1078	1			T4	168		T40	63		T54	12
auto[0]	values[1]	values[4]	478	1			T205	20		T221	8		T185	32
auto[0]	values[1]	values[5]	643	1			T37	29		T163	21		T156	20
auto[0]	values[1]	values[6]	735	1			T193	10		T188	18		T170	20
auto[0]	values[1]	values[7]	618	1			T163	33		T244	133		T245	30
auto[0]	values[2]	values[0]	638	1			T38	20		T151	22		T163	32
auto[0]	values[2]	values[1]	595	1			T9	4		T39	20		T163	20
auto[0]	values[2]	values[2]	595	1			T4	90		T27	33		T37	24
auto[0]	values[2]	values[3]	479	1			T36	47		T195	20		T162	20
auto[0]	values[2]	values[4]	644	1			T40	40		T151	20		T172	20
auto[0]	values[2]	values[5]	422	1			T70	12		T157	46		T233	28
auto[0]	values[2]	values[6]	501	1			T36	24		T38	24		T157	20
auto[0]	values[2]	values[7]	465	1			T4	33		T40	47		T156	24
auto[0]	values[3]	values[0]	524	1			T211	2		T38	64		T156	63
auto[0]	values[3]	values[1]	267	1			T39	62		T246	12		T194	20
auto[0]	values[3]	values[2]	784	1			T23	139		T27	23		T148	30
auto[0]	values[3]	values[3]	442	1			T38	26		T40	44		T194	20
auto[0]	values[3]	values[4]	594	1			T36	18		T163	54		T176	20
auto[0]	values[3]	values[5]	825	1			T12	18		T4	47		T36	26
auto[0]	values[3]	values[6]	650	1			T36	28		T219	20		T151	23
auto[0]	values[3]	values[7]	690	1			T198	10		T197	8		T37	20
auto[0]	values[4]	values[0]	427	1			T39	47		T227	2		T40	20
auto[0]	values[4]	values[1]	519	1			T38	24		T151	23		T174	14
auto[0]	values[4]	values[2]	375	1			T230	8		T170	20		T247	2
auto[0]	values[4]	values[3]	557	1			T4	20		T38	22		T232	31
auto[0]	values[4]	values[4]	526	1			T40	20		T210	2		T248	20
auto[0]	values[4]	values[5]	550	1			T7	28		T14	18		T182	6
auto[0]	values[4]	values[6]	461	1			T163	20		T170	34		T157	19
auto[0]	values[4]	values[7]	510	1			T4	44		T37	20		T204	14
auto[0]	values[5]	values[0]	628	1			T23	21		T196	22		T38	40
auto[0]	values[5]	values[1]	453	1			T36	22		T37	30		T151	29
auto[0]	values[5]	values[2]	487	1			T23	43		T36	23		T39	20
auto[0]	values[5]	values[3]	742	1			T4	50		T27	19		T151	22
auto[0]	values[5]	values[4]	505	1			T205	29		T157	20		T194	29
auto[0]	values[5]	values[5]	822	1			T222	10		T225	12		T39	20
auto[0]	values[5]	values[6]	471	1			T27	20		T39	26		T237	12
auto[0]	values[5]	values[7]	563	1			T209	8		T249	2		T172	50
auto[0]	values[6]	values[0]	631	1			T4	76		T5	20		T23	20
auto[0]	values[6]	values[1]	828	1			T4	138		T228	10		T151	20
auto[0]	values[6]	values[2]	518	1			T23	107		T205	45		T244	67
auto[0]	values[6]	values[3]	750	1			T23	24		T40	20		T250	10
auto[0]	values[6]	values[4]	995	1			T40	55		T163	49		T156	19
auto[0]	values[6]	values[5]	856	1			T5	23		T35	10		T157	20
auto[0]	values[6]	values[6]	625	1			T38	28		T251	24		T205	29
auto[0]	values[6]	values[7]	426	1			T71	4		T37	20		T39	20
auto[0]	values[7]	values[0]	714	1			T13	12		T4	41		T38	69
auto[0]	values[7]	values[1]	493	1			T4	55		T150	24		T194	143
auto[0]	values[7]	values[2]	574	1			T171	12		T194	19		T161	26
auto[0]	values[7]	values[3]	559	1			T83	6		T220	2		T252	4
auto[0]	values[7]	values[4]	547	1			T216	4		T164	76		T170	18
auto[0]	values[7]	values[5]	482	1			T27	24		T36	27		T151	20
auto[0]	values[7]	values[6]	693	1			T37	25		T156	46		T157	20
auto[0]	values[7]	values[7]	690	1			T27	23		T36	20		T37	23
auto[1]	values[0]	values[0]	13	1			T4	1		T36	1		T176	1
auto[1]	values[0]	values[1]	20	1			T179	1		T189	4		T253	1
auto[1]	values[0]	values[2]	10	1			T157	1		T254	2		T255	1
auto[1]	values[0]	values[3]	3	1			T256	1		T257	2		-	-
auto[1]	values[0]	values[4]	5	1			T163	1		T185	1		T191	1
auto[1]	values[0]	values[5]	21	1			T40	2		T156	1		T255	3
auto[1]	values[0]	values[6]	20	1			T37	1		T176	1		T186	3
auto[1]	values[0]	values[7]	7	1			T23	1		T156	2		T157	1
auto[1]	values[1]	values[0]	9	1			T157	1		T258	6		T259	1
auto[1]	values[1]	values[1]	17	1			T253	2		T260	10		T261	4
auto[1]	values[1]	values[2]	6	1			T38	1		T262	2		T185	2
auto[1]	values[1]	values[3]	16	1			T165	2		T157	4		T206	2
auto[1]	values[1]	values[4]	10	1			T185	1		T263	1		T264	1
auto[1]	values[1]	values[5]	9	1			T37	1		T163	1		T265	3
auto[1]	values[1]	values[6]	15	1			T188	2		T206	2		T161	2
auto[1]	values[1]	values[7]	4	1			T192	2		T266	1		T267	1
auto[1]	values[2]	values[0]	16	1			T156	2		T161	1		T192	2
auto[1]	values[2]	values[1]	7	1			T159	2		T268	2		T269	3
auto[1]	values[2]	values[2]	12	1			T4	4		T37	1		T156	2
auto[1]	values[2]	values[3]	1	1			T270	1		-	-		-	-
auto[1]	values[2]	values[4]	3	1			T194	1		T271	2		-	-
auto[1]	values[2]	values[5]	9	1			T157	4		T185	1		T179	2
auto[1]	values[2]	values[6]	6	1			T36	2		T180	1		T272	1
auto[1]	values[2]	values[7]	8	1			T40	1		T162	4		T268	3
auto[1]	values[3]	values[0]	5	1			T38	2		T157	2		T61	1
auto[1]	values[3]	values[1]	8	1			T39	6		T254	1		T273	1
auto[1]	values[3]	values[2]	11	1			T40	1		T205	1		T194	2
auto[1]	values[3]	values[3]	4	1			T207	2		T167	2		-	-
auto[1]	values[3]	values[4]	17	1			T36	2		T163	2		T253	4
auto[1]	values[3]	values[5]	8	1			T4	2		T157	2		T253	1
auto[1]	values[3]	values[6]	10	1			T151	1		T170	2		T189	1
auto[1]	values[3]	values[7]	9	1			T38	1		T187	2		T206	2
auto[1]	values[4]	values[0]	5	1			T39	1		T169	1		T170	2
auto[1]	values[4]	values[1]	7	1			T151	1		T233	1		T201	4
auto[1]	values[4]	values[2]	23	1			T156	1		T274	4		T186	2
auto[1]	values[4]	values[3]	14	1			T172	2		T157	2		T189	2
auto[1]	values[4]	values[4]	8	1			T189	1		T275	3		T276	1
auto[1]	values[4]	values[5]	12	1			T14	2		T163	2		T277	1
auto[1]	values[4]	values[6]	6	1			T170	2		T157	1		T277	2
auto[1]	values[4]	values[7]	6	1			T4	1		T172	4		T156	1
auto[1]	values[5]	values[0]	13	1			T23	1		T170	3		T178	1
auto[1]	values[5]	values[1]	10	1			T151	1		T170	1		T192	1
auto[1]	values[5]	values[2]	3	1			T23	1		T179	1		T278	1
auto[1]	values[5]	values[3]	12	1			T27	1		T151	3		T170	2
auto[1]	values[5]	values[4]	10	1			T194	1		T195	3		T255	3
auto[1]	values[5]	values[5]	12	1			T40	1		T151	1		T205	1
auto[1]	values[5]	values[6]	7	1			T151	3		T235	1		T177	1
auto[1]	values[5]	values[7]	14	1			T156	1		T244	2		T279	3
auto[1]	values[6]	values[0]	13	1			T4	2		T40	1		T157	1
auto[1]	values[6]	values[1]	5	1			T167	1		T269	1		T278	3
auto[1]	values[6]	values[2]	6	1			T23	2		T205	1		T255	1
auto[1]	values[6]	values[3]	14	1			T23	1		T244	5		T280	2
auto[1]	values[6]	values[4]	21	1			T163	6		T156	1		T206	4
auto[1]	values[6]	values[5]	15	1			T35	4		T177	3		T185	1
auto[1]	values[6]	values[6]	12	1			T38	2		T205	1		T172	2
auto[1]	values[6]	values[7]	2	1			T265	1		T271	1		-	-
auto[1]	values[7]	values[0]	10	1			T38	3		T195	1		T255	3
auto[1]	values[7]	values[1]	5	1			T189	2		T266	3		-	-
auto[1]	values[7]	values[2]	12	1			T194	1		T161	1		T158	1
auto[1]	values[7]	values[3]	15	1			T157	4		T253	3		T159	2
auto[1]	values[7]	values[4]	10	1			T164	3		T170	2		T158	2
auto[1]	values[7]	values[5]	9	1			T27	2		T36	2		T164	1
auto[1]	values[7]	values[6]	12	1			T37	1		T156	1		T194	2
auto[1]	values[7]	values[7]	15	1			T37	2		T40	3		T205	1