Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2643

1

T2

2

T3

4

T18

12

auto[1]

2588

1

T3

5

T18

18

T22

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2746

1

T2

2

T3

7

T19

1

auto[1]

2485

1

T3

2

T18

30

T22

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4180

1

T2

2

T3

6

T18

30

auto[1]

1051

1

T3

3

T5

5

T23

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1018	1			T3	3		T18	2		T5	4
valid[1]	1051	1			T2	1		T3	1		T18	6
valid[2]	1048	1			T3	2		T18	8		T5	7
valid[3]	1059	1			T2	1		T3	2		T18	9
valid[4]	1055	1			T3	1		T18	5		T22	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	163	1			T5	2		T27	2		T29	5
auto[0]	auto[0]	valid[0]	auto[1]	243	1			T3	1		T18	2		T41	4
auto[0]	auto[0]	valid[1]	auto[0]	170	1			T2	1		T5	2		T27	2
auto[0]	auto[0]	valid[1]	auto[1]	252	1			T3	1		T18	1		T28	1
auto[0]	auto[0]	valid[2]	auto[0]	182	1			T27	2		T28	1		T29	2
auto[0]	auto[0]	valid[2]	auto[1]	266	1			T18	4		T41	9		T64	4
auto[0]	auto[0]	valid[3]	auto[0]	177	1			T2	1		T19	1		T5	1
auto[0]	auto[0]	valid[3]	auto[1]	253	1			T18	4		T41	2		T28	2
auto[0]	auto[0]	valid[4]	auto[0]	166	1			T27	1		T28	2		T29	3
auto[0]	auto[0]	valid[4]	auto[1]	246	1			T18	1		T41	2		T28	1
auto[0]	auto[1]	valid[0]	auto[0]	172	1			T3	1		T5	2		T27	1
auto[0]	auto[1]	valid[0]	auto[1]	230	1			T41	3		T29	2		T64	3
auto[0]	auto[1]	valid[1]	auto[0]	166	1			T5	5		T27	2		T28	3
auto[0]	auto[1]	valid[1]	auto[1]	263	1			T18	5		T41	3		T29	1
auto[0]	auto[1]	valid[2]	auto[0]	149	1			T3	2		T5	3		T27	4
auto[0]	auto[1]	valid[2]	auto[1]	240	1			T18	4		T41	2		T28	1
auto[0]	auto[1]	valid[3]	auto[0]	182	1			T5	1		T27	1		T28	2
auto[0]	auto[1]	valid[3]	auto[1]	234	1			T18	5		T41	3		T64	1
auto[0]	auto[1]	valid[4]	auto[0]	168	1			T3	1		T5	2		T27	2
auto[0]	auto[1]	valid[4]	auto[1]	258	1			T18	4		T22	1		T41	3
auto[1]	auto[0]	valid[0]	auto[0]	115	1			T3	1		T27	1		T29	2
auto[1]	auto[0]	valid[1]	auto[0]	103	1			T23	1		T27	2		T29	1
auto[1]	auto[0]	valid[2]	auto[0]	103	1			T5	2		T23	1		T31	1
auto[1]	auto[0]	valid[3]	auto[0]	102	1			T3	1		T27	1		T29	5
auto[1]	auto[0]	valid[4]	auto[0]	102	1			T28	1		T29	3		T65	1
auto[1]	auto[1]	valid[0]	auto[0]	95	1			T29	1		T31	1		T105	1
auto[1]	auto[1]	valid[1]	auto[0]	97	1			T28	2		T31	2		T105	1
auto[1]	auto[1]	valid[2]	auto[0]	108	1			T5	2		T27	1		T28	1
auto[1]	auto[1]	valid[3]	auto[0]	111	1			T3	1		T5	1		T27	1
auto[1]	auto[1]	valid[4]	auto[0]	115	1			T28	2		T29	2		T105	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal