Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67477

1

T2

14

T3

152

T17

16

auto[1]

25515

1

T3

25

T18

411

T22

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68467

1

T2

10

T3

119

T17

9

auto[1]

24525

1

T2

4

T3

58

T17

7

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	47937	1			T2	8		T3	85		T17	7
others[1]	7963	1			T2	2		T3	20		T17	2
others[2]	7781	1			T3	12		T17	1		T18	42
others[3]	8717	1			T3	16		T17	1		T18	40
interest[1]	5262	1			T3	11		T17	1		T18	21
interest[4]	31385	1			T2	4		T3	60		T17	6
interest[64]	15332	1			T2	4		T3	33		T17	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	21963	1			T2	5		T3	41		T17	4
auto[0]	auto[0]	others[1]	3695	1			T2	1		T3	9		T5	26
auto[0]	auto[0]	others[2]	3680	1			T3	9		T19	1		T5	27
auto[0]	auto[0]	others[3]	3938	1			T3	10		T17	1		T19	2
auto[0]	auto[0]	interest[1]	2542	1			T3	3		T17	1		T5	21
auto[0]	auto[0]	interest[4]	14334	1			T2	2		T3	29		T17	4
auto[0]	auto[0]	interest[64]	7134	1			T2	4		T3	22		T17	3
auto[0]	auto[1]	others[0]	13423	1			T3	19		T18	203		T22	1
auto[0]	auto[1]	others[1]	2201	1			T3	2		T18	36		T41	34
auto[0]	auto[1]	others[2]	2002	1			T18	42		T23	2		T41	28
auto[0]	auto[1]	others[3]	2421	1			T18	40		T23	2		T41	33
auto[0]	auto[1]	interest[1]	1339	1			T3	4		T18	21		T23	1
auto[0]	auto[1]	interest[4]	8928	1			T3	13		T18	133		T22	1
auto[0]	auto[1]	interest[64]	4129	1			T18	69		T23	6		T41	61
auto[1]	auto[0]	others[0]	12551	1			T2	3		T3	25		T17	3
auto[1]	auto[0]	others[1]	2067	1			T2	1		T3	9		T17	2
auto[1]	auto[0]	others[2]	2099	1			T3	3		T17	1		T19	1
auto[1]	auto[0]	others[3]	2358	1			T3	6		T5	17		T23	4
auto[1]	auto[0]	interest[1]	1381	1			T3	4		T5	8		T23	3
auto[1]	auto[0]	interest[4]	8123	1			T2	2		T3	18		T17	2
auto[1]	auto[0]	interest[64]	4069	1			T3	11		T17	1		T19	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal