Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	2	34	94.44

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	2	34	94.44	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	787	1			T20	7		T23	4		T29	11
all_values[1]	787	1			T20	7		T23	4		T29	11
all_values[2]	787	1			T20	7		T23	4		T29	11
all_values[3]	787	1			T20	7		T23	4		T29	11
all_values[4]	787	1			T20	7		T23	4		T29	11
all_values[5]	787	1			T20	7		T23	4		T29	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2546

1

T20

16

T23

14

T29

44

auto[1]

2176

1

T20

26

T23

10

T29

22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1939

1

T20

12

T23

9

T29

32

auto[1]

2783

1

T20

30

T23

15

T29

34

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2717

1

T20

20

T23

13

T29

41

auto[1]

2005

1

T20

22

T23

11

T29

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	2	34	94.44	2
Automatically Generated Cross Bins	36	2	34	94.44	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	183	1			T23	1		T29	6		T31	1
all_values[0]	auto[0]	auto[0]	auto[1]	68	1			T23	1		T145	6		T36	1
all_values[0]	auto[0]	auto[1]	auto[0]	137	1			T20	3		T145	1		T146	2
all_values[0]	auto[0]	auto[1]	auto[1]	82	1			T20	2		T29	2		T36	1
all_values[0]	auto[1]	auto[0]	auto[1]	174	1			T23	2		T29	3		T31	4
all_values[0]	auto[1]	auto[1]	auto[1]	143	1			T20	2		T31	2		T145	3
all_values[1]	auto[0]	auto[0]	auto[0]	157	1			T29	5		T31	2		T145	5
all_values[1]	auto[0]	auto[0]	auto[1]	73	1			T20	1		T29	2		T31	1
all_values[1]	auto[0]	auto[1]	auto[0]	131	1			T29	1		T145	1		T36	1
all_values[1]	auto[0]	auto[1]	auto[1]	79	1			T23	2		T145	4		T147	4
all_values[1]	auto[1]	auto[0]	auto[1]	191	1			T20	2		T23	2		T29	3
all_values[1]	auto[1]	auto[1]	auto[1]	156	1			T20	4		T31	1		T145	4
all_values[2]	auto[0]	auto[0]	auto[0]	148	1			T29	2		T31	2		T145	1
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T29	2		T145	2		T146	2
all_values[2]	auto[0]	auto[1]	auto[0]	117	1			T20	2		T23	3		T29	2
all_values[2]	auto[0]	auto[1]	auto[1]	93	1			T31	1		T145	2		T146	2
all_values[2]	auto[1]	auto[0]	auto[1]	184	1			T20	1		T23	1		T29	4
all_values[2]	auto[1]	auto[1]	auto[1]	168	1			T20	4		T29	1		T145	2
all_values[3]	auto[0]	auto[0]	auto[0]	182	1			T20	1		T31	1		T145	3
all_values[3]	auto[0]	auto[0]	auto[1]	77	1			T20	2		T145	3		T146	1
all_values[3]	auto[0]	auto[1]	auto[0]	138	1			T20	3		T29	3		T31	2
all_values[3]	auto[0]	auto[1]	auto[1]	82	1			T23	1		T29	2		T31	2
all_values[3]	auto[1]	auto[0]	auto[1]	160	1			T20	1		T23	2		T29	3
all_values[3]	auto[1]	auto[1]	auto[1]	148	1			T23	1		T29	3		T31	1
all_values[4]	auto[0]	auto[0]	auto[0]	157	1			T23	3		T29	6		T145	3
all_values[4]	auto[0]	auto[0]	auto[1]	86	1			T20	2		T29	1		T31	2
all_values[4]	auto[0]	auto[1]	auto[0]	137	1			T29	2		T31	1		T145	3
all_values[4]	auto[0]	auto[1]	auto[1]	61	1			T20	1		T31	1		T145	3
all_values[4]	auto[1]	auto[0]	auto[1]	187	1			T20	4		T23	1		T29	1
all_values[4]	auto[1]	auto[1]	auto[1]	159	1			T29	1		T31	2		T145	3
all_values[5]	auto[0]	auto[0]	auto[0]	254	1			T20	1		T23	1		T29	3
all_values[5]	auto[0]	auto[1]	auto[0]	198	1			T20	2		T23	1		T29	2
all_values[5]	auto[1]	auto[0]	auto[1]	188	1			T20	1		T29	3		T31	2
all_values[5]	auto[1]	auto[1]	auto[1]	147	1			T20	3		T23	2		T29	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal