Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::all_modes_cg

Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	1	4	80.00
Crosses	5	1	4	80.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	1	2	66.67	100	1	1	0
cp_tpm_enabled	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	5	1	4	80.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	1	2	66.67

Automatically Generated Bins for cp_mode

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[GenericMode]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[FlashMode]

100232

1

T2

14

T3

177

T17

16

auto[PassthroughMode]

69995

1

T7

36

T8

16

T9

6

---

Summary for Variable cp_tpm_enabled

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tpm_enabled

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29194

1

T7

36

T8

16

T9

6

auto[1]

141033

1

T2

14

T3

177

T17

16

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Summary for Cross cr_all

Samples crossed: cp_mode cp_tpm_enabled

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	5	1	4	80.00	1
Automatically Generated Cross Bins	5	1	4	80.00	1
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_mode	cp_tpm_enabled	COUNT	AT LEAST	NUMBER	STATUS
[auto[GenericMode]]	[auto[0]]	0	1	1

Covered bins

cp_mode

cp_tpm_enabled

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[FlashMode]

auto[0]

12495

1

T6

47

T30

458

T43

25

auto[FlashMode]

auto[1]

87737

1

T2

14

T3

177

T17

16

auto[PassthroughMode]

auto[0]

16699

1

T7

36

T8

16

T9

6

auto[PassthroughMode]

auto[1]

53296

1

T5

562

T23

481

T27

732

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded