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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.34 98.54 94.89 98.60 90.20 97.31 96.54 98.29


Total test records in report: 1095
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T1004 /workspace/coverage/default/9.spi_device_cfg_cmd.1339129902 Jan 24 07:47:47 PM PST 24 Jan 24 07:47:51 PM PST 24 206712633 ps
T1005 /workspace/coverage/default/4.spi_device_ram_cfg.3541108421 Jan 24 08:36:26 PM PST 24 Jan 24 08:36:27 PM PST 24 40787627 ps
T1006 /workspace/coverage/default/18.spi_device_csb_read.708739587 Jan 24 07:49:51 PM PST 24 Jan 24 07:49:52 PM PST 24 15937640 ps
T1007 /workspace/coverage/default/3.spi_device_ram_cfg.1401543370 Jan 24 07:46:04 PM PST 24 Jan 24 07:46:06 PM PST 24 15298778 ps
T1008 /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2386941159 Jan 24 07:49:15 PM PST 24 Jan 24 07:49:32 PM PST 24 2682005836 ps
T1009 /workspace/coverage/default/32.spi_device_alert_test.1031981453 Jan 24 09:20:35 PM PST 24 Jan 24 09:20:36 PM PST 24 42699376 ps
T1010 /workspace/coverage/default/20.spi_device_flash_and_tpm.262335417 Jan 24 07:50:24 PM PST 24 Jan 24 07:51:36 PM PST 24 3890557229 ps
T1011 /workspace/coverage/default/36.spi_device_tpm_rw.2119429235 Jan 24 07:53:51 PM PST 24 Jan 24 07:53:57 PM PST 24 183796206 ps
T1012 /workspace/coverage/default/38.spi_device_read_buffer_direct.1860847460 Jan 24 07:54:23 PM PST 24 Jan 24 07:54:32 PM PST 24 214976765 ps
T1013 /workspace/coverage/default/0.spi_device_flash_mode.682208112 Jan 24 07:45:40 PM PST 24 Jan 24 07:45:55 PM PST 24 2960704452 ps
T1014 /workspace/coverage/default/26.spi_device_flash_and_tpm.3692384975 Jan 24 07:51:42 PM PST 24 Jan 24 07:53:08 PM PST 24 11749898001 ps
T1015 /workspace/coverage/default/46.spi_device_intercept.4161918497 Jan 24 07:56:06 PM PST 24 Jan 24 07:56:13 PM PST 24 1866009327 ps
T1016 /workspace/coverage/default/13.spi_device_alert_test.1471912655 Jan 24 07:48:38 PM PST 24 Jan 24 07:48:39 PM PST 24 39476242 ps
T1017 /workspace/coverage/default/31.spi_device_tpm_sts_read.3616234817 Jan 24 07:52:38 PM PST 24 Jan 24 07:52:40 PM PST 24 124002559 ps
T1018 /workspace/coverage/default/41.spi_device_stress_all.1748194594 Jan 24 07:55:03 PM PST 24 Jan 24 07:55:58 PM PST 24 28773430032 ps
T1019 /workspace/coverage/default/5.spi_device_upload.3016273820 Jan 24 07:46:54 PM PST 24 Jan 24 07:47:33 PM PST 24 47349210648 ps
T1020 /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2717654560 Jan 24 07:49:34 PM PST 24 Jan 24 07:49:43 PM PST 24 1300656181 ps
T1021 /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1687196417 Jan 24 07:55:50 PM PST 24 Jan 24 07:56:14 PM PST 24 33804012928 ps
T1022 /workspace/coverage/default/14.spi_device_intercept.1987376663 Jan 24 07:48:54 PM PST 24 Jan 24 07:49:02 PM PST 24 54040406 ps
T1023 /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3262130430 Jan 24 09:53:47 PM PST 24 Jan 24 09:54:11 PM PST 24 27662470092 ps
T1024 /workspace/coverage/default/4.spi_device_read_buffer_direct.3029520425 Jan 24 07:46:34 PM PST 24 Jan 24 07:46:39 PM PST 24 535764665 ps
T1025 /workspace/coverage/default/12.spi_device_flash_mode.2186877803 Jan 24 07:48:23 PM PST 24 Jan 24 07:48:32 PM PST 24 231102320 ps
T1026 /workspace/coverage/default/13.spi_device_flash_all.2475266752 Jan 24 07:48:34 PM PST 24 Jan 24 07:51:18 PM PST 24 26032366306 ps
T1027 /workspace/coverage/default/13.spi_device_read_buffer_direct.3322601821 Jan 24 07:48:40 PM PST 24 Jan 24 07:48:48 PM PST 24 1517786658 ps
T1028 /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1020725292 Jan 24 07:45:32 PM PST 24 Jan 24 07:45:45 PM PST 24 746911241 ps
T1029 /workspace/coverage/default/17.spi_device_upload.3713495535 Jan 24 07:49:32 PM PST 24 Jan 24 07:49:37 PM PST 24 1215946218 ps
T1030 /workspace/coverage/default/2.spi_device_flash_all.2339328731 Jan 24 07:46:04 PM PST 24 Jan 24 07:46:21 PM PST 24 1084864643 ps
T1031 /workspace/coverage/default/16.spi_device_flash_and_tpm.660654191 Jan 24 10:02:04 PM PST 24 Jan 24 10:02:50 PM PST 24 2904356721 ps
T1032 /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3309028277 Jan 24 07:45:43 PM PST 24 Jan 24 07:45:56 PM PST 24 7600106340 ps
T1033 /workspace/coverage/default/7.spi_device_cfg_cmd.3370118823 Jan 24 07:47:09 PM PST 24 Jan 24 07:47:13 PM PST 24 233553885 ps
T1034 /workspace/coverage/default/14.spi_device_mem_parity.3936558049 Jan 24 07:48:43 PM PST 24 Jan 24 07:48:45 PM PST 24 54195615 ps
T1035 /workspace/coverage/default/7.spi_device_stress_all.2665434801 Jan 24 07:47:12 PM PST 24 Jan 24 08:09:10 PM PST 24 376213968247 ps
T1036 /workspace/coverage/default/35.spi_device_tpm_all.1047671484 Jan 24 07:53:38 PM PST 24 Jan 24 07:54:47 PM PST 24 14676547013 ps
T1037 /workspace/coverage/default/26.spi_device_alert_test.3130382818 Jan 24 07:51:49 PM PST 24 Jan 24 07:51:51 PM PST 24 36363137 ps
T1038 /workspace/coverage/default/28.spi_device_pass_cmd_filtering.894741042 Jan 24 07:52:08 PM PST 24 Jan 24 07:52:12 PM PST 24 134481143 ps
T1039 /workspace/coverage/default/29.spi_device_intercept.3352184119 Jan 24 07:52:23 PM PST 24 Jan 24 07:52:29 PM PST 24 343778925 ps
T1040 /workspace/coverage/default/47.spi_device_tpm_rw.2871454040 Jan 24 09:44:32 PM PST 24 Jan 24 09:44:48 PM PST 24 1721580771 ps
T1041 /workspace/coverage/default/45.spi_device_read_buffer_direct.1258790078 Jan 24 09:11:58 PM PST 24 Jan 24 09:12:03 PM PST 24 136201913 ps
T1042 /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2421612454 Jan 24 07:46:00 PM PST 24 Jan 24 07:46:45 PM PST 24 4642149689 ps
T1043 /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2704831924 Jan 24 07:54:01 PM PST 24 Jan 24 07:54:25 PM PST 24 6559917484 ps
T1044 /workspace/coverage/default/20.spi_device_tpm_sts_read.2634652022 Jan 24 07:50:23 PM PST 24 Jan 24 07:50:25 PM PST 24 219403504 ps
T1045 /workspace/coverage/default/14.spi_device_csb_read.1750105835 Jan 24 07:48:37 PM PST 24 Jan 24 07:48:39 PM PST 24 47983594 ps
T1046 /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1863166753 Jan 24 09:04:23 PM PST 24 Jan 24 09:04:37 PM PST 24 4710824450 ps
T1047 /workspace/coverage/default/7.spi_device_tpm_sts_read.254459496 Jan 24 07:47:02 PM PST 24 Jan 24 07:47:06 PM PST 24 30055614 ps
T1048 /workspace/coverage/default/2.spi_device_ram_cfg.2007614853 Jan 24 07:46:00 PM PST 24 Jan 24 07:46:02 PM PST 24 23926677 ps
T1049 /workspace/coverage/default/14.spi_device_tpm_rw.1509190874 Jan 24 07:48:54 PM PST 24 Jan 24 07:49:00 PM PST 24 19531372 ps
T1050 /workspace/coverage/default/8.spi_device_tpm_sts_read.1833370135 Jan 24 07:47:22 PM PST 24 Jan 24 07:47:24 PM PST 24 766450936 ps
T1051 /workspace/coverage/default/12.spi_device_mem_parity.3791921509 Jan 24 08:10:01 PM PST 24 Jan 24 08:10:06 PM PST 24 25185306 ps
T1052 /workspace/coverage/default/40.spi_device_flash_mode.2135203952 Jan 24 07:54:48 PM PST 24 Jan 24 07:55:05 PM PST 24 6848121717 ps
T278 /workspace/coverage/default/13.spi_device_flash_and_tpm.1194658361 Jan 24 07:48:44 PM PST 24 Jan 24 07:50:46 PM PST 24 42210078797 ps
T1053 /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2492372714 Jan 24 07:55:56 PM PST 24 Jan 24 07:56:02 PM PST 24 798154808 ps
T1054 /workspace/coverage/default/17.spi_device_intercept.4024728013 Jan 24 07:49:34 PM PST 24 Jan 24 07:49:44 PM PST 24 6993297278 ps
T1055 /workspace/coverage/default/19.spi_device_cfg_cmd.411867488 Jan 24 08:35:16 PM PST 24 Jan 24 08:35:21 PM PST 24 5373989423 ps
T1056 /workspace/coverage/default/43.spi_device_flash_and_tpm.3438037377 Jan 24 07:55:30 PM PST 24 Jan 24 07:56:01 PM PST 24 7040609928 ps
T1057 /workspace/coverage/default/18.spi_device_flash_mode.1513930584 Jan 24 07:50:03 PM PST 24 Jan 24 07:50:29 PM PST 24 6377597424 ps
T1058 /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3568776022 Jan 24 07:53:25 PM PST 24 Jan 24 07:53:51 PM PST 24 37707085388 ps
T1059 /workspace/coverage/default/7.spi_device_flash_and_tpm.3079447729 Jan 24 07:47:12 PM PST 24 Jan 24 07:52:22 PM PST 24 169592910995 ps
T1060 /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1496812476 Jan 24 07:52:53 PM PST 24 Jan 24 07:53:01 PM PST 24 2718229522 ps
T1061 /workspace/coverage/default/44.spi_device_tpm_rw.3316060290 Jan 24 08:07:29 PM PST 24 Jan 24 08:07:31 PM PST 24 121457949 ps
T1062 /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3659996408 Jan 24 07:53:39 PM PST 24 Jan 24 07:54:35 PM PST 24 18626913043 ps
T267 /workspace/coverage/default/22.spi_device_flash_all.1494538734 Jan 24 07:50:48 PM PST 24 Jan 24 07:52:45 PM PST 24 21244613353 ps
T1063 /workspace/coverage/default/39.spi_device_flash_mode.3993595213 Jan 24 07:54:36 PM PST 24 Jan 24 07:54:54 PM PST 24 3630811879 ps
T1064 /workspace/coverage/default/4.spi_device_intercept.3202409789 Jan 24 07:46:28 PM PST 24 Jan 24 07:46:40 PM PST 24 14067999003 ps
T1065 /workspace/coverage/default/20.spi_device_intercept.2262501686 Jan 24 07:50:25 PM PST 24 Jan 24 07:50:32 PM PST 24 717427375 ps
T1066 /workspace/coverage/default/0.spi_device_mem_parity.456084376 Jan 24 09:15:32 PM PST 24 Jan 24 09:15:34 PM PST 24 26048571 ps
T1067 /workspace/coverage/default/24.spi_device_csb_read.2312451007 Jan 24 07:50:59 PM PST 24 Jan 24 07:51:01 PM PST 24 17347484 ps
T1068 /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1476470817 Jan 24 07:56:07 PM PST 24 Jan 24 07:56:12 PM PST 24 675545793 ps
T1069 /workspace/coverage/default/5.spi_device_tpm_sts_read.2112475864 Jan 24 07:46:50 PM PST 24 Jan 24 07:46:52 PM PST 24 506125288 ps
T1070 /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2307425639 Jan 24 07:55:57 PM PST 24 Jan 24 07:56:06 PM PST 24 3083908331 ps
T1071 /workspace/coverage/default/32.spi_device_flash_all.4204824934 Jan 24 07:53:08 PM PST 24 Jan 24 07:54:26 PM PST 24 97925025693 ps
T1072 /workspace/coverage/default/29.spi_device_tpm_rw.1091861792 Jan 24 09:16:34 PM PST 24 Jan 24 09:16:37 PM PST 24 52417396 ps
T1073 /workspace/coverage/default/4.spi_device_tpm_rw.789704094 Jan 24 07:46:28 PM PST 24 Jan 24 07:46:31 PM PST 24 61713385 ps
T1074 /workspace/coverage/default/40.spi_device_read_buffer_direct.1483635412 Jan 24 07:54:50 PM PST 24 Jan 24 07:55:01 PM PST 24 203605538 ps
T1075 /workspace/coverage/default/22.spi_device_csb_read.2652448801 Jan 24 07:50:35 PM PST 24 Jan 24 07:50:37 PM PST 24 19177207 ps
T1076 /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1082789067 Jan 24 07:49:52 PM PST 24 Jan 24 07:50:13 PM PST 24 6945099336 ps
T1077 /workspace/coverage/default/1.spi_device_csb_read.1677299057 Jan 24 07:45:43 PM PST 24 Jan 24 07:45:45 PM PST 24 222170615 ps
T1078 /workspace/coverage/default/19.spi_device_ram_cfg.3908204406 Jan 24 07:50:14 PM PST 24 Jan 24 07:50:16 PM PST 24 43932750 ps
T1079 /workspace/coverage/default/27.spi_device_tpm_all.84190639 Jan 24 07:51:40 PM PST 24 Jan 24 07:52:02 PM PST 24 3817749596 ps
T1080 /workspace/coverage/default/17.spi_device_ram_cfg.748656284 Jan 24 07:49:35 PM PST 24 Jan 24 07:49:38 PM PST 24 63526878 ps
T1081 /workspace/coverage/default/11.spi_device_mem_parity.1538983679 Jan 24 07:47:57 PM PST 24 Jan 24 07:48:05 PM PST 24 30409322 ps
T1082 /workspace/coverage/default/25.spi_device_csb_read.3905711298 Jan 24 07:51:20 PM PST 24 Jan 24 07:51:26 PM PST 24 46841378 ps
T1083 /workspace/coverage/default/40.spi_device_stress_all.3702851827 Jan 24 07:54:57 PM PST 24 Jan 24 08:03:46 PM PST 24 307516318349 ps
T1084 /workspace/coverage/default/7.spi_device_mem_parity.1471203882 Jan 24 07:46:59 PM PST 24 Jan 24 07:47:02 PM PST 24 26723730 ps
T1085 /workspace/coverage/default/11.spi_device_tpm_all.3171411988 Jan 24 07:48:10 PM PST 24 Jan 24 07:48:38 PM PST 24 3044168939 ps
T1086 /workspace/coverage/default/39.spi_device_alert_test.3097068876 Jan 24 07:54:47 PM PST 24 Jan 24 07:54:54 PM PST 24 13616148 ps
T1087 /workspace/coverage/default/9.spi_device_csb_read.1306285507 Jan 24 07:47:33 PM PST 24 Jan 24 07:47:34 PM PST 24 82612245 ps
T1088 /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2196289366 Jan 24 07:50:27 PM PST 24 Jan 24 07:50:38 PM PST 24 729514032 ps
T271 /workspace/coverage/default/49.spi_device_stress_all.3215045411 Jan 24 07:56:48 PM PST 24 Jan 24 07:58:18 PM PST 24 6648545533 ps
T1089 /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3022651317 Jan 24 07:56:38 PM PST 24 Jan 24 08:00:38 PM PST 24 34182001863 ps
T1090 /workspace/coverage/default/44.spi_device_mailbox.2897098067 Jan 24 07:55:40 PM PST 24 Jan 24 07:55:58 PM PST 24 8663031144 ps
T1091 /workspace/coverage/default/5.spi_device_csb_read.2741751537 Jan 24 07:46:44 PM PST 24 Jan 24 07:46:45 PM PST 24 24188840 ps
T1092 /workspace/coverage/default/46.spi_device_upload.1614600426 Jan 24 07:56:10 PM PST 24 Jan 24 07:56:15 PM PST 24 1186643883 ps
T1093 /workspace/coverage/default/43.spi_device_tpm_all.4028137204 Jan 24 08:39:11 PM PST 24 Jan 24 08:40:27 PM PST 24 7991646555 ps
T1094 /workspace/coverage/default/11.spi_device_read_buffer_direct.3470949689 Jan 24 08:10:57 PM PST 24 Jan 24 08:11:05 PM PST 24 1625241186 ps
T1095 /workspace/coverage/default/25.spi_device_mailbox.2571606383 Jan 24 07:51:29 PM PST 24 Jan 24 07:51:42 PM PST 24 10751112247 ps

Test location /workspace/coverage/default/0.spi_device_upload.1398354509
Short name T8
Test name
Test status
Simulation time 6374293577 ps
CPU time 8.61 seconds
Started Jan 24 07:45:32 PM PST 24
Finished Jan 24 07:45:45 PM PST 24
Peak memory 233232 kb
Host smart-c96291f7-6e7f-4eab-bf4f-54390d627468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398354509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1398354509
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2162546680
Short name T29
Test name
Test status
Simulation time 237913193518 ps
CPU time 539.17 seconds
Started Jan 24 07:50:10 PM PST 24
Finished Jan 24 07:59:11 PM PST 24
Peak memory 273168 kb
Host smart-f4aabf6c-2bc5-4836-a6a2-44abfa18a760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162546680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2162546680
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1799816663
Short name T23
Test name
Test status
Simulation time 28599568804 ps
CPU time 148.14 seconds
Started Jan 24 07:55:47 PM PST 24
Finished Jan 24 07:58:16 PM PST 24
Peak memory 254400 kb
Host smart-2a0defa6-8ab0-4b2c-a939-9677a692fa60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799816663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1799816663
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2263367442
Short name T36
Test name
Test status
Simulation time 311639196889 ps
CPU time 544.29 seconds
Started Jan 24 07:45:44 PM PST 24
Finished Jan 24 07:54:50 PM PST 24
Peak memory 272760 kb
Host smart-5bfddccf-a55e-4ddf-821a-5dcfc2f3d12c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263367442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2263367442
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2559430369
Short name T95
Test name
Test status
Simulation time 123834538 ps
CPU time 1.2 seconds
Started Jan 24 03:20:49 PM PST 24
Finished Jan 24 03:21:01 PM PST 24
Peak memory 214984 kb
Host smart-810cbe1c-2ed4-4aef-8af8-32a3988931ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559430369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2559430369
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1856461516
Short name T4
Test name
Test status
Simulation time 393033409942 ps
CPU time 200.39 seconds
Started Jan 24 07:56:34 PM PST 24
Finished Jan 24 07:59:55 PM PST 24
Peak memory 265196 kb
Host smart-af15a961-0c70-4346-b877-2f1d72184fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856461516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1856461516
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2033894013
Short name T75
Test name
Test status
Simulation time 47579853 ps
CPU time 3.61 seconds
Started Jan 24 02:52:58 PM PST 24
Finished Jan 24 02:53:08 PM PST 24
Peak memory 215048 kb
Host smart-ed1275ef-954a-4088-9ac4-1da06e910d20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033894013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
033894013
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2726690469
Short name T157
Test name
Test status
Simulation time 351744819838 ps
CPU time 723.81 seconds
Started Jan 24 07:51:19 PM PST 24
Finished Jan 24 08:03:28 PM PST 24
Peak memory 289856 kb
Host smart-21603930-59a8-4d90-93fd-478127f5fe9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726690469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2726690469
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.4017028069
Short name T685
Test name
Test status
Simulation time 33976013 ps
CPU time 0.72 seconds
Started Jan 24 07:45:24 PM PST 24
Finished Jan 24 07:45:32 PM PST 24
Peak memory 215860 kb
Host smart-283fa662-4472-41ca-92c3-b1c146cff40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017028069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.4017028069
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1759889581
Short name T48
Test name
Test status
Simulation time 207378892 ps
CPU time 0.95 seconds
Started Jan 24 07:46:34 PM PST 24
Finished Jan 24 07:46:36 PM PST 24
Peak memory 234640 kb
Host smart-2c26f906-fb5f-49b0-b8fb-6ebfca4a94de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759889581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1759889581
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1270342523
Short name T156
Test name
Test status
Simulation time 11015909091 ps
CPU time 240.86 seconds
Started Jan 24 07:56:11 PM PST 24
Finished Jan 24 08:00:13 PM PST 24
Peak memory 281540 kb
Host smart-9e75f014-ac72-4d0c-a329-31c53aee5fee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270342523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1270342523
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2701657406
Short name T53
Test name
Test status
Simulation time 263492071 ps
CPU time 8.53 seconds
Started Jan 24 07:53:34 PM PST 24
Finished Jan 24 07:53:43 PM PST 24
Peak memory 233184 kb
Host smart-f006421d-6e7f-415b-9cdb-fb08c38ca1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701657406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2701657406
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2580132780
Short name T39
Test name
Test status
Simulation time 17718828567 ps
CPU time 213.07 seconds
Started Jan 24 07:52:29 PM PST 24
Finished Jan 24 07:56:03 PM PST 24
Peak memory 272612 kb
Host smart-44275e8d-28f1-453c-8bd1-1a7aab13790b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580132780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2580132780
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1628881550
Short name T5
Test name
Test status
Simulation time 6166730519 ps
CPU time 72.97 seconds
Started Jan 24 07:53:49 PM PST 24
Finished Jan 24 07:55:03 PM PST 24
Peak memory 248948 kb
Host smart-36f38ced-d9fb-4e4b-9d3a-c60b1dc27919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628881550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1628881550
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2421778022
Short name T226
Test name
Test status
Simulation time 606932375061 ps
CPU time 780.96 seconds
Started Jan 24 07:52:52 PM PST 24
Finished Jan 24 08:05:54 PM PST 24
Peak memory 273480 kb
Host smart-16853719-c8c6-4c00-af9f-7baf429817da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421778022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2421778022
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1485167229
Short name T92
Test name
Test status
Simulation time 2180264678 ps
CPU time 15.3 seconds
Started Jan 24 02:52:29 PM PST 24
Finished Jan 24 02:52:56 PM PST 24
Peak memory 215108 kb
Host smart-a1740bb6-f698-4fb7-9e61-bc1bd0fd3993
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485167229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1485167229
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.929440982
Short name T40
Test name
Test status
Simulation time 134885814107 ps
CPU time 222.77 seconds
Started Jan 24 07:50:34 PM PST 24
Finished Jan 24 07:54:17 PM PST 24
Peak memory 272404 kb
Host smart-c9d61b56-7283-4fcc-802d-6db0fce276c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929440982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.929440982
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3190673846
Short name T38
Test name
Test status
Simulation time 358565577233 ps
CPU time 605.84 seconds
Started Jan 24 07:53:16 PM PST 24
Finished Jan 24 08:03:23 PM PST 24
Peak memory 254820 kb
Host smart-b3613a04-2174-4de7-9868-4ac5eb203c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190673846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3190673846
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1895515062
Short name T163
Test name
Test status
Simulation time 8958885442 ps
CPU time 148.49 seconds
Started Jan 24 07:48:01 PM PST 24
Finished Jan 24 07:50:36 PM PST 24
Peak memory 264084 kb
Host smart-0fc01ca5-610a-42e0-ab98-0397939b1e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895515062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1895515062
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1125546674
Short name T16
Test name
Test status
Simulation time 119080500 ps
CPU time 0.72 seconds
Started Jan 24 07:50:58 PM PST 24
Finished Jan 24 07:51:00 PM PST 24
Peak memory 203512 kb
Host smart-24d08a71-8f8e-4ead-9a57-aacd2da4d670
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125546674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1125546674
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.633781766
Short name T170
Test name
Test status
Simulation time 181110921711 ps
CPU time 507.1 seconds
Started Jan 24 07:45:57 PM PST 24
Finished Jan 24 07:54:26 PM PST 24
Peak memory 273264 kb
Host smart-e608231c-e74a-436c-a233-31f32e678da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633781766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.633781766
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3256593767
Short name T147
Test name
Test status
Simulation time 8279088188 ps
CPU time 82.73 seconds
Started Jan 24 07:53:41 PM PST 24
Finished Jan 24 07:55:05 PM PST 24
Peak memory 265324 kb
Host smart-d3c1448f-7542-4b23-8884-a4a0cc40dc18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256593767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3256593767
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1428128519
Short name T185
Test name
Test status
Simulation time 14020336375 ps
CPU time 133.75 seconds
Started Jan 24 07:50:34 PM PST 24
Finished Jan 24 07:52:49 PM PST 24
Peak memory 262316 kb
Host smart-e372ddcf-fcb7-4825-98aa-d48ab094fa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428128519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1428128519
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1943896346
Short name T194
Test name
Test status
Simulation time 11259900655 ps
CPU time 80.55 seconds
Started Jan 24 07:49:07 PM PST 24
Finished Jan 24 07:50:28 PM PST 24
Peak memory 250504 kb
Host smart-c900792c-5b3d-4b2a-b3cf-5488d67a5101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943896346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1943896346
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2917092771
Short name T701
Test name
Test status
Simulation time 230668030 ps
CPU time 1.03 seconds
Started Jan 24 07:45:47 PM PST 24
Finished Jan 24 07:45:49 PM PST 24
Peak memory 215572 kb
Host smart-b781d428-1526-4a72-b4df-f041f747871e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917092771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2917092771
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.888758681
Short name T253
Test name
Test status
Simulation time 96926267251 ps
CPU time 263.45 seconds
Started Jan 24 09:37:54 PM PST 24
Finished Jan 24 09:42:18 PM PST 24
Peak memory 250008 kb
Host smart-f0d2d556-b32a-452a-bb43-85bc77d75faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888758681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.888758681
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3263861011
Short name T959
Test name
Test status
Simulation time 74536149576 ps
CPU time 359.41 seconds
Started Jan 24 07:51:44 PM PST 24
Finished Jan 24 07:57:45 PM PST 24
Peak memory 265972 kb
Host smart-4585424f-33e7-4fef-9c29-ff57ad9c55a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263861011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3263861011
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.299296632
Short name T82
Test name
Test status
Simulation time 580775562 ps
CPU time 18.33 seconds
Started Jan 24 02:53:29 PM PST 24
Finished Jan 24 02:54:20 PM PST 24
Peak memory 214944 kb
Host smart-3fe27207-a1a5-453f-857e-ca0119e4208b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299296632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.299296632
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3391569726
Short name T282
Test name
Test status
Simulation time 50363647490 ps
CPU time 34.31 seconds
Started Jan 24 07:49:16 PM PST 24
Finished Jan 24 07:49:52 PM PST 24
Peak memory 221624 kb
Host smart-c5f1fc72-2031-477d-a19e-9aba32344004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391569726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3391569726
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1789735893
Short name T165
Test name
Test status
Simulation time 44449001985 ps
CPU time 345.13 seconds
Started Jan 24 07:52:55 PM PST 24
Finished Jan 24 07:58:41 PM PST 24
Peak memory 253496 kb
Host smart-2422ddea-e215-4bd3-80bb-210467b8e348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789735893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1789735893
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3815880088
Short name T18
Test name
Test status
Simulation time 2572405152 ps
CPU time 6.03 seconds
Started Jan 24 07:56:47 PM PST 24
Finished Jan 24 07:56:54 PM PST 24
Peak memory 215860 kb
Host smart-afbb80d7-5d04-409e-8d91-ce67a1870947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815880088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3815880088
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.224318641
Short name T266
Test name
Test status
Simulation time 6744394061 ps
CPU time 131.98 seconds
Started Jan 24 08:39:25 PM PST 24
Finished Jan 24 08:41:38 PM PST 24
Peak memory 272012 kb
Host smart-4883eb2c-6a15-4e60-a548-1cc078fdcc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224318641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.224318641
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1027158367
Short name T382
Test name
Test status
Simulation time 382369404 ps
CPU time 11.81 seconds
Started Jan 24 03:12:04 PM PST 24
Finished Jan 24 03:12:23 PM PST 24
Peak memory 215064 kb
Host smart-e6d31953-4c35-48e2-874e-4be94714d707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027158367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1027158367
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.187630089
Short name T233
Test name
Test status
Simulation time 8460525470 ps
CPU time 83.66 seconds
Started Jan 24 07:45:56 PM PST 24
Finished Jan 24 07:47:22 PM PST 24
Peak memory 248900 kb
Host smart-1ef1ddf3-2ae8-4d20-940f-6125ded58ff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187630089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.187630089
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3318215632
Short name T167
Test name
Test status
Simulation time 547229867829 ps
CPU time 441.85 seconds
Started Jan 24 07:54:03 PM PST 24
Finished Jan 24 08:01:27 PM PST 24
Peak memory 281880 kb
Host smart-18eef476-efc6-4fcb-9636-2dadae7d299b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318215632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3318215632
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3332573940
Short name T407
Test name
Test status
Simulation time 53616645 ps
CPU time 4.09 seconds
Started Jan 24 02:52:32 PM PST 24
Finished Jan 24 02:52:48 PM PST 24
Peak memory 215060 kb
Host smart-4597f7ec-3c06-4e7e-9530-347e8fc94687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332573940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
332573940
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2196263157
Short name T63
Test name
Test status
Simulation time 399429270661 ps
CPU time 308.75 seconds
Started Jan 24 07:48:21 PM PST 24
Finished Jan 24 07:53:33 PM PST 24
Peak memory 273024 kb
Host smart-cd54b777-2229-4cbd-b029-781bb9aed534
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196263157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2196263157
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4094048741
Short name T135
Test name
Test status
Simulation time 76351635 ps
CPU time 2.52 seconds
Started Jan 24 02:52:33 PM PST 24
Finished Jan 24 02:52:48 PM PST 24
Peak memory 216068 kb
Host smart-5b900fb5-ff51-4f04-a93b-41bc2eca6bfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094048741 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4094048741
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3020150435
Short name T510
Test name
Test status
Simulation time 40083681148 ps
CPU time 189.42 seconds
Started Jan 24 07:45:35 PM PST 24
Finished Jan 24 07:48:47 PM PST 24
Peak memory 239232 kb
Host smart-241db807-2248-46e1-970e-2bf352fa2b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020150435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3020150435
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1459805512
Short name T498
Test name
Test status
Simulation time 69088669731 ps
CPU time 105.62 seconds
Started Jan 24 07:48:23 PM PST 24
Finished Jan 24 07:50:12 PM PST 24
Peak memory 253172 kb
Host smart-58d62340-5d05-4e00-a51f-b63950e8a545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459805512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1459805512
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.431571970
Short name T186
Test name
Test status
Simulation time 111479364468 ps
CPU time 201.75 seconds
Started Jan 24 07:48:26 PM PST 24
Finished Jan 24 07:51:49 PM PST 24
Peak memory 268068 kb
Host smart-3f9736ee-f7c3-410c-963a-65c20a1b2ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431571970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.431571970
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.660654191
Short name T1031
Test name
Test status
Simulation time 2904356721 ps
CPU time 45.81 seconds
Started Jan 24 10:02:04 PM PST 24
Finished Jan 24 10:02:50 PM PST 24
Peak memory 248900 kb
Host smart-b710a15c-b598-4546-ae35-3707cd21c39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660654191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.660654191
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.592130060
Short name T256
Test name
Test status
Simulation time 127910520244 ps
CPU time 280.46 seconds
Started Jan 24 09:55:45 PM PST 24
Finished Jan 24 10:00:27 PM PST 24
Peak memory 266584 kb
Host smart-e702fd21-89f4-425e-904b-ee82b95e5541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592130060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
592130060
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2768492136
Short name T268
Test name
Test status
Simulation time 13514021495 ps
CPU time 82.98 seconds
Started Jan 24 07:53:41 PM PST 24
Finished Jan 24 07:55:05 PM PST 24
Peak memory 256996 kb
Host smart-ba746cb7-907e-467c-89de-36b7e87bef00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768492136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2768492136
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3980925945
Short name T270
Test name
Test status
Simulation time 61817414149 ps
CPU time 290.03 seconds
Started Jan 24 07:54:54 PM PST 24
Finished Jan 24 07:59:52 PM PST 24
Peak memory 265124 kb
Host smart-47b7603e-b545-46f7-9c01-58832bba0963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980925945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3980925945
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.640970758
Short name T265
Test name
Test status
Simulation time 94757912046 ps
CPU time 681.98 seconds
Started Jan 24 09:15:55 PM PST 24
Finished Jan 24 09:27:18 PM PST 24
Peak memory 264788 kb
Host smart-04997124-cea2-4e5c-b4db-300d7ec81211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640970758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.640970758
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1904009756
Short name T70
Test name
Test status
Simulation time 3949636593 ps
CPU time 8.97 seconds
Started Jan 24 07:47:56 PM PST 24
Finished Jan 24 07:48:13 PM PST 24
Peak memory 234148 kb
Host smart-a2a007b9-13e4-4def-aa72-f9c6d0b4c126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904009756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1904009756
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3716876505
Short name T91
Test name
Test status
Simulation time 87021066 ps
CPU time 2.33 seconds
Started Jan 24 02:53:26 PM PST 24
Finished Jan 24 02:54:02 PM PST 24
Peak memory 215104 kb
Host smart-89248aeb-6718-4acf-9ca6-e5ef943e99e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716876505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3716876505
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2470742069
Short name T416
Test name
Test status
Simulation time 1249990574 ps
CPU time 15.21 seconds
Started Jan 24 03:06:48 PM PST 24
Finished Jan 24 03:07:21 PM PST 24
Peak memory 206384 kb
Host smart-d12aa674-3443-4551-8051-b15457e00ef0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470742069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2470742069
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1935491546
Short name T415
Test name
Test status
Simulation time 2607903473 ps
CPU time 12.64 seconds
Started Jan 24 03:56:49 PM PST 24
Finished Jan 24 03:57:03 PM PST 24
Peak memory 206108 kb
Host smart-1e1ed06d-025e-4d2e-807c-7e1e0b6a8e81
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935491546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1935491546
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4117907374
Short name T359
Test name
Test status
Simulation time 114644769 ps
CPU time 0.93 seconds
Started Jan 24 02:52:28 PM PST 24
Finished Jan 24 02:52:41 PM PST 24
Peak memory 205716 kb
Host smart-6b154f14-5d09-4dae-b2a7-277fd8f9f4db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117907374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.4117907374
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.941025971
Short name T351
Test name
Test status
Simulation time 115638901 ps
CPU time 1.79 seconds
Started Jan 24 02:52:33 PM PST 24
Finished Jan 24 02:52:47 PM PST 24
Peak memory 214944 kb
Host smart-72744517-eaf7-4455-8d95-d84c52a2d3ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941025971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.941025971
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2217153137
Short name T378
Test name
Test status
Simulation time 11524164 ps
CPU time 0.76 seconds
Started Jan 24 02:52:31 PM PST 24
Finished Jan 24 02:52:44 PM PST 24
Peak memory 202108 kb
Host smart-b2326b51-eb1a-46a6-a9ec-36e19339af76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217153137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
217153137
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3081511890
Short name T118
Test name
Test status
Simulation time 33326557 ps
CPU time 1.3 seconds
Started Jan 24 02:52:32 PM PST 24
Finished Jan 24 02:52:45 PM PST 24
Peak memory 214824 kb
Host smart-7e31d3b5-58f6-4a93-9871-dbb3096a98a4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081511890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3081511890
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.432775115
Short name T409
Test name
Test status
Simulation time 11546647 ps
CPU time 0.66 seconds
Started Jan 24 05:49:07 PM PST 24
Finished Jan 24 05:49:08 PM PST 24
Peak memory 202136 kb
Host smart-88eabba5-1265-4b41-9763-77e289fd4e40
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432775115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.432775115
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1654136476
Short name T401
Test name
Test status
Simulation time 182701194 ps
CPU time 1.88 seconds
Started Jan 24 02:56:44 PM PST 24
Finished Jan 24 02:56:47 PM PST 24
Peak memory 206116 kb
Host smart-a0e7a1ab-f206-4cdd-af7d-f5f621b849c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654136476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1654136476
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.127558367
Short name T77
Test name
Test status
Simulation time 1231039727 ps
CPU time 7.63 seconds
Started Jan 24 02:52:31 PM PST 24
Finished Jan 24 02:52:51 PM PST 24
Peak memory 214884 kb
Host smart-4279918b-f69a-4af1-a547-d1fdb4d5191f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127558367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.127558367
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1423547067
Short name T376
Test name
Test status
Simulation time 1270350028 ps
CPU time 19.97 seconds
Started Jan 24 02:52:32 PM PST 24
Finished Jan 24 02:53:04 PM PST 24
Peak memory 206784 kb
Host smart-52470116-7a66-4f36-ac52-7ae897068f96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423547067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1423547067
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2790434940
Short name T360
Test name
Test status
Simulation time 373928906 ps
CPU time 21.92 seconds
Started Jan 24 02:52:37 PM PST 24
Finished Jan 24 02:53:10 PM PST 24
Peak memory 206680 kb
Host smart-4fc00ee8-c9da-402b-bd3e-a51174a0fffb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790434940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2790434940
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2869265014
Short name T100
Test name
Test status
Simulation time 60547134 ps
CPU time 2.8 seconds
Started Jan 24 02:52:32 PM PST 24
Finished Jan 24 02:52:47 PM PST 24
Peak memory 223160 kb
Host smart-33f41d1b-dc72-49f3-bb69-fdb38a71980a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869265014 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2869265014
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2572927849
Short name T402
Test name
Test status
Simulation time 85355347 ps
CPU time 2.56 seconds
Started Jan 24 04:34:37 PM PST 24
Finished Jan 24 04:34:46 PM PST 24
Peak memory 214936 kb
Host smart-d12a0086-cdd9-422a-8caa-ee733e99d303
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572927849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
572927849
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.314362493
Short name T311
Test name
Test status
Simulation time 13224504 ps
CPU time 0.76 seconds
Started Jan 24 03:55:34 PM PST 24
Finished Jan 24 03:55:36 PM PST 24
Peak memory 202220 kb
Host smart-9b5fbff2-b4fa-4b29-8d14-4aa92cf0781f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314362493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.314362493
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1910332952
Short name T108
Test name
Test status
Simulation time 75657458 ps
CPU time 1.27 seconds
Started Jan 24 04:35:18 PM PST 24
Finished Jan 24 04:35:26 PM PST 24
Peak memory 214876 kb
Host smart-b1acba40-a1df-4883-8583-daaee96e3294
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910332952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1910332952
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.375863151
Short name T397
Test name
Test status
Simulation time 11672839 ps
CPU time 0.66 seconds
Started Jan 24 02:52:28 PM PST 24
Finished Jan 24 02:52:41 PM PST 24
Peak memory 202476 kb
Host smart-728f1190-8f1d-4ff1-9e40-8d82aa916dbe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375863151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.375863151
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.367919264
Short name T310
Test name
Test status
Simulation time 227911964 ps
CPU time 3.81 seconds
Started Jan 24 02:52:31 PM PST 24
Finished Jan 24 02:52:47 PM PST 24
Peak memory 206580 kb
Host smart-06def05c-7586-4a64-9774-5bbdb36c56e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367919264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.367919264
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2904167804
Short name T411
Test name
Test status
Simulation time 206788267 ps
CPU time 1.68 seconds
Started Jan 24 04:24:17 PM PST 24
Finished Jan 24 04:24:21 PM PST 24
Peak memory 215088 kb
Host smart-84adbe94-2718-43ba-bac3-c02ebccbb97f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904167804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
904167804
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3728419812
Short name T406
Test name
Test status
Simulation time 45501489 ps
CPU time 1.53 seconds
Started Jan 24 02:53:29 PM PST 24
Finished Jan 24 02:54:04 PM PST 24
Peak memory 215028 kb
Host smart-be1925d0-482c-4aa7-800e-e1ccb6a42218
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728419812 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3728419812
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1605455683
Short name T97
Test name
Test status
Simulation time 702915002 ps
CPU time 1.23 seconds
Started Jan 24 02:53:33 PM PST 24
Finished Jan 24 02:54:07 PM PST 24
Peak memory 206772 kb
Host smart-f2dc8e0c-526a-456f-a905-0b0d938f6dca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605455683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1605455683
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3144971814
Short name T390
Test name
Test status
Simulation time 26070704 ps
CPU time 0.7 seconds
Started Jan 24 02:53:24 PM PST 24
Finished Jan 24 02:53:56 PM PST 24
Peak memory 202196 kb
Host smart-e55de721-a01f-4918-904b-28e5ee88ea70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144971814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3144971814
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2650447692
Short name T132
Test name
Test status
Simulation time 269851825 ps
CPU time 2.89 seconds
Started Jan 24 02:53:27 PM PST 24
Finished Jan 24 02:54:03 PM PST 24
Peak memory 206676 kb
Host smart-f96acf0e-f95f-4b57-8204-378b9a462405
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650447692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2650447692
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1189937266
Short name T377
Test name
Test status
Simulation time 1818122898 ps
CPU time 20.77 seconds
Started Jan 24 02:53:27 PM PST 24
Finished Jan 24 02:54:21 PM PST 24
Peak memory 214964 kb
Host smart-657a7d8d-d772-4c2c-abd5-f7118dbe8d32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189937266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1189937266
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2484487651
Short name T366
Test name
Test status
Simulation time 53753439 ps
CPU time 1.22 seconds
Started Jan 24 02:53:22 PM PST 24
Finished Jan 24 02:53:54 PM PST 24
Peak memory 214976 kb
Host smart-d45140cf-4492-4d42-a2d9-dc15d00d2ef0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484487651 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2484487651
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2478876169
Short name T380
Test name
Test status
Simulation time 134542163 ps
CPU time 1.26 seconds
Started Jan 24 02:53:27 PM PST 24
Finished Jan 24 02:54:01 PM PST 24
Peak memory 214860 kb
Host smart-d48a082a-8c00-48b7-81ed-892a15abb805
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478876169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2478876169
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2073050881
Short name T339
Test name
Test status
Simulation time 12977157 ps
CPU time 0.72 seconds
Started Jan 24 02:53:28 PM PST 24
Finished Jan 24 02:54:02 PM PST 24
Peak memory 202216 kb
Host smart-411c33cb-6c48-4df4-884a-9f67916505f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073050881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2073050881
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2934746615
Short name T137
Test name
Test status
Simulation time 304408201 ps
CPU time 3.24 seconds
Started Jan 24 02:53:28 PM PST 24
Finished Jan 24 02:54:05 PM PST 24
Peak memory 206340 kb
Host smart-18705719-8a0b-4301-a4df-55e6c574b6d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934746615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2934746615
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1510588931
Short name T368
Test name
Test status
Simulation time 53784000 ps
CPU time 1.58 seconds
Started Jan 24 02:53:27 PM PST 24
Finished Jan 24 02:54:01 PM PST 24
Peak memory 215124 kb
Host smart-5f597869-73ea-446a-b52f-f32da5d18383
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510588931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1510588931
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.458340731
Short name T101
Test name
Test status
Simulation time 1972648204 ps
CPU time 7.49 seconds
Started Jan 24 02:53:27 PM PST 24
Finished Jan 24 02:54:07 PM PST 24
Peak memory 214956 kb
Host smart-e2bc1c06-900e-4047-adef-167ec79b2111
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458340731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.458340731
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2610452164
Short name T391
Test name
Test status
Simulation time 24804223 ps
CPU time 2.55 seconds
Started Jan 24 02:53:29 PM PST 24
Finished Jan 24 02:54:05 PM PST 24
Peak memory 215908 kb
Host smart-1261e9c0-8334-4051-bd72-4ab0955330aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610452164 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2610452164
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2856690059
Short name T116
Test name
Test status
Simulation time 387992087 ps
CPU time 1.75 seconds
Started Jan 24 02:53:27 PM PST 24
Finished Jan 24 02:54:02 PM PST 24
Peak memory 206688 kb
Host smart-beab0e14-e653-48bb-98bf-7f9e403df6b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856690059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2856690059
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.409553656
Short name T321
Test name
Test status
Simulation time 39111618 ps
CPU time 0.7 seconds
Started Jan 24 02:53:28 PM PST 24
Finished Jan 24 02:54:02 PM PST 24
Peak memory 202536 kb
Host smart-54376ff4-5882-4ca6-9420-3c9ce58a635c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409553656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.409553656
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.450020325
Short name T335
Test name
Test status
Simulation time 44254718 ps
CPU time 2.95 seconds
Started Jan 24 02:53:29 PM PST 24
Finished Jan 24 02:54:05 PM PST 24
Peak memory 206120 kb
Host smart-d0d23b55-0da3-49f8-8c4e-f3b312a9acbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450020325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.450020325
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2521203569
Short name T90
Test name
Test status
Simulation time 161906575 ps
CPU time 2.72 seconds
Started Jan 24 02:53:26 PM PST 24
Finished Jan 24 02:54:01 PM PST 24
Peak memory 215028 kb
Host smart-e81f20f0-4c6b-496c-8b15-a8f692a6c797
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521203569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2521203569
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.669884700
Short name T73
Test name
Test status
Simulation time 197206527 ps
CPU time 2.65 seconds
Started Jan 24 02:53:47 PM PST 24
Finished Jan 24 02:54:17 PM PST 24
Peak memory 216100 kb
Host smart-f7c80bac-7b72-4af2-9d33-e18e07ae63ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669884700 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.669884700
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2904381452
Short name T340
Test name
Test status
Simulation time 46609588 ps
CPU time 1.29 seconds
Started Jan 24 02:53:45 PM PST 24
Finished Jan 24 02:54:14 PM PST 24
Peak memory 206696 kb
Host smart-4360120c-0f86-42c4-b7c9-20e9c4ac33be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904381452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2904381452
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2606270438
Short name T315
Test name
Test status
Simulation time 31787615 ps
CPU time 0.71 seconds
Started Jan 24 02:53:40 PM PST 24
Finished Jan 24 02:54:09 PM PST 24
Peak memory 202228 kb
Host smart-fd92daf9-1a11-47b1-b330-27982c00000f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606270438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2606270438
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2227877854
Short name T131
Test name
Test status
Simulation time 391871433 ps
CPU time 4.1 seconds
Started Jan 24 02:53:46 PM PST 24
Finished Jan 24 02:54:17 PM PST 24
Peak memory 206748 kb
Host smart-c6adcf2a-0fe8-4e02-86b8-e6f3553e160f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227877854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2227877854
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3373875638
Short name T86
Test name
Test status
Simulation time 84413076 ps
CPU time 1.69 seconds
Started Jan 24 02:53:40 PM PST 24
Finished Jan 24 02:54:13 PM PST 24
Peak memory 215116 kb
Host smart-8f89e244-dee0-4764-974d-8c8aa2f3f6cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373875638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3373875638
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3747769770
Short name T72
Test name
Test status
Simulation time 817758625 ps
CPU time 12.46 seconds
Started Jan 24 02:53:46 PM PST 24
Finished Jan 24 02:54:26 PM PST 24
Peak memory 215036 kb
Host smart-5ce05a73-5c8b-47a0-9648-efc00690388c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747769770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3747769770
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2588166941
Short name T370
Test name
Test status
Simulation time 100481832 ps
CPU time 1.75 seconds
Started Jan 24 02:53:35 PM PST 24
Finished Jan 24 02:54:08 PM PST 24
Peak memory 214988 kb
Host smart-7db89542-e5c9-4c4a-b244-da139b56dcce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588166941 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2588166941
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3760642591
Short name T367
Test name
Test status
Simulation time 225409361 ps
CPU time 1.83 seconds
Started Jan 24 02:53:37 PM PST 24
Finished Jan 24 02:54:10 PM PST 24
Peak memory 214924 kb
Host smart-9510fdff-7eba-4a41-a327-237288e882ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760642591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3760642591
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.720444797
Short name T343
Test name
Test status
Simulation time 43630543 ps
CPU time 0.77 seconds
Started Jan 24 02:53:40 PM PST 24
Finished Jan 24 02:54:12 PM PST 24
Peak memory 201728 kb
Host smart-7c4ff3a1-c9e3-4c63-b1e9-c5925df59a79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720444797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.720444797
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4242212829
Short name T138
Test name
Test status
Simulation time 59303748 ps
CPU time 3.27 seconds
Started Jan 24 02:53:45 PM PST 24
Finished Jan 24 02:54:16 PM PST 24
Peak memory 206684 kb
Host smart-a6d03d14-3a0d-44fa-b50c-20f620379994
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242212829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.4242212829
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1668974841
Short name T405
Test name
Test status
Simulation time 89952946 ps
CPU time 2.33 seconds
Started Jan 24 02:53:37 PM PST 24
Finished Jan 24 02:54:11 PM PST 24
Peak memory 214984 kb
Host smart-1bd83532-6df1-437d-a2d0-2a8c842613d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668974841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1668974841
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3770572414
Short name T102
Test name
Test status
Simulation time 304588026 ps
CPU time 7.91 seconds
Started Jan 24 02:53:40 PM PST 24
Finished Jan 24 02:54:17 PM PST 24
Peak memory 214900 kb
Host smart-26a00e27-c980-4586-8551-69544e4aad00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770572414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3770572414
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1162323141
Short name T133
Test name
Test status
Simulation time 40582439 ps
CPU time 2.16 seconds
Started Jan 24 02:53:47 PM PST 24
Finished Jan 24 02:54:17 PM PST 24
Peak memory 214932 kb
Host smart-b6e36d64-b033-4908-a463-b1f3fcd9d875
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162323141 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1162323141
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3549320659
Short name T347
Test name
Test status
Simulation time 193690918 ps
CPU time 2.04 seconds
Started Jan 24 02:53:46 PM PST 24
Finished Jan 24 02:54:15 PM PST 24
Peak memory 214984 kb
Host smart-c19463bc-9138-45ad-b6e8-eef7f04d948a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549320659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3549320659
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2360191667
Short name T373
Test name
Test status
Simulation time 40910158 ps
CPU time 0.74 seconds
Started Jan 24 02:53:36 PM PST 24
Finished Jan 24 02:54:09 PM PST 24
Peak memory 202208 kb
Host smart-abda47aa-2f0c-4866-a23f-74176a386591
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360191667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2360191667
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.913774717
Short name T410
Test name
Test status
Simulation time 380616679 ps
CPU time 4.09 seconds
Started Jan 24 02:53:40 PM PST 24
Finished Jan 24 02:54:13 PM PST 24
Peak memory 206244 kb
Host smart-7bc9c4e1-5b9a-4f48-9bad-6391db2da0e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913774717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.913774717
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2577132328
Short name T80
Test name
Test status
Simulation time 111716282 ps
CPU time 3.24 seconds
Started Jan 24 02:53:43 PM PST 24
Finished Jan 24 02:54:15 PM PST 24
Peak memory 214992 kb
Host smart-97b69f02-84e8-4209-ba44-15140b1f7324
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577132328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2577132328
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3333205892
Short name T154
Test name
Test status
Simulation time 282798894 ps
CPU time 7.07 seconds
Started Jan 24 02:53:44 PM PST 24
Finished Jan 24 02:54:19 PM PST 24
Peak memory 214960 kb
Host smart-48c5ef0b-b4f2-413d-9df0-36516941a977
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333205892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3333205892
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.962936333
Short name T394
Test name
Test status
Simulation time 18721018 ps
CPU time 1.71 seconds
Started Jan 24 02:53:43 PM PST 24
Finished Jan 24 02:54:14 PM PST 24
Peak memory 215960 kb
Host smart-34ca803b-dd65-4b59-ae38-fe00ec4d8503
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962936333 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.962936333
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3651546665
Short name T338
Test name
Test status
Simulation time 28850464 ps
CPU time 1.82 seconds
Started Jan 24 02:53:45 PM PST 24
Finished Jan 24 02:54:15 PM PST 24
Peak memory 214988 kb
Host smart-f68e1d97-7a3f-4d42-8f20-84104af5ae21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651546665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3651546665
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3282750341
Short name T396
Test name
Test status
Simulation time 24751098 ps
CPU time 0.73 seconds
Started Jan 24 02:53:43 PM PST 24
Finished Jan 24 02:54:12 PM PST 24
Peak memory 202152 kb
Host smart-110df9a1-f078-4fb9-b016-83cc5a4305c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282750341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3282750341
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.838561171
Short name T320
Test name
Test status
Simulation time 124805204 ps
CPU time 3.98 seconds
Started Jan 24 02:53:40 PM PST 24
Finished Jan 24 02:54:15 PM PST 24
Peak memory 206668 kb
Host smart-83fdd4bf-7dcf-435f-af02-56ada59ec2ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838561171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.838561171
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2621364010
Short name T414
Test name
Test status
Simulation time 39479564 ps
CPU time 2.84 seconds
Started Jan 24 02:53:46 PM PST 24
Finished Jan 24 02:54:17 PM PST 24
Peak memory 215008 kb
Host smart-c23d27bd-5ff1-421c-b32a-705c630a3d47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621364010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2621364010
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.615174973
Short name T78
Test name
Test status
Simulation time 542240371 ps
CPU time 6.95 seconds
Started Jan 24 02:53:43 PM PST 24
Finished Jan 24 02:54:19 PM PST 24
Peak memory 214888 kb
Host smart-8723c1ae-177c-4583-967a-3d3b4919ea7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615174973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.615174973
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1685373859
Short name T357
Test name
Test status
Simulation time 43281112 ps
CPU time 1.49 seconds
Started Jan 24 02:53:51 PM PST 24
Finished Jan 24 02:54:22 PM PST 24
Peak memory 214700 kb
Host smart-bed7f7a3-1be3-4d5e-911c-dadbf9002d19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685373859 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1685373859
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.317953233
Short name T389
Test name
Test status
Simulation time 107549817 ps
CPU time 1.84 seconds
Started Jan 24 02:53:52 PM PST 24
Finished Jan 24 02:54:23 PM PST 24
Peak memory 206572 kb
Host smart-dca72625-32fd-4976-b25e-52f1e871a082
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317953233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.317953233
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2361951313
Short name T332
Test name
Test status
Simulation time 28386544 ps
CPU time 0.77 seconds
Started Jan 24 02:53:47 PM PST 24
Finished Jan 24 02:54:15 PM PST 24
Peak memory 202180 kb
Host smart-e0565b4b-9cb0-4a25-8e10-6362529cb02b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361951313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2361951313
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3417868119
Short name T374
Test name
Test status
Simulation time 28989676 ps
CPU time 1.59 seconds
Started Jan 24 02:53:45 PM PST 24
Finished Jan 24 02:54:14 PM PST 24
Peak memory 206628 kb
Host smart-f4444dc6-b1fb-4cbe-84e6-49b39701a809
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417868119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3417868119
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2603637417
Short name T381
Test name
Test status
Simulation time 149512659 ps
CPU time 2.21 seconds
Started Jan 24 02:53:47 PM PST 24
Finished Jan 24 02:54:17 PM PST 24
Peak memory 215004 kb
Host smart-b504930a-1938-4261-a779-46be976b5524
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603637417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2603637417
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3643825829
Short name T365
Test name
Test status
Simulation time 110078278 ps
CPU time 6.6 seconds
Started Jan 24 02:53:47 PM PST 24
Finished Jan 24 02:54:21 PM PST 24
Peak memory 215048 kb
Host smart-3f87246a-ec99-4f67-b6be-1c3305c1b136
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643825829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3643825829
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3362424579
Short name T361
Test name
Test status
Simulation time 31634101 ps
CPU time 2.56 seconds
Started Jan 24 02:53:42 PM PST 24
Finished Jan 24 02:54:14 PM PST 24
Peak memory 216016 kb
Host smart-f2d0720e-3832-47f1-84ec-8412fa2a6965
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362424579 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3362424579
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.33540995
Short name T384
Test name
Test status
Simulation time 20447038 ps
CPU time 1.19 seconds
Started Jan 24 02:56:17 PM PST 24
Finished Jan 24 02:56:22 PM PST 24
Peak memory 206632 kb
Host smart-50e52bea-18ce-4250-8a6f-3d656c05d063
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33540995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.33540995
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2777284450
Short name T364
Test name
Test status
Simulation time 16741322 ps
CPU time 0.79 seconds
Started Jan 24 02:53:45 PM PST 24
Finished Jan 24 02:54:14 PM PST 24
Peak memory 202124 kb
Host smart-ca63e139-6314-49f1-ac09-25327edd427f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777284450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2777284450
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1072854695
Short name T358
Test name
Test status
Simulation time 1106473912 ps
CPU time 4.24 seconds
Started Jan 24 02:53:47 PM PST 24
Finished Jan 24 02:54:19 PM PST 24
Peak memory 206624 kb
Host smart-b06858cc-34a0-48e3-aa2a-bee4da2582fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072854695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1072854695
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3511881721
Short name T81
Test name
Test status
Simulation time 150535363 ps
CPU time 1.54 seconds
Started Jan 24 02:53:46 PM PST 24
Finished Jan 24 02:54:15 PM PST 24
Peak memory 214988 kb
Host smart-c77c359e-90e8-4894-a7b3-3ed3560fdff7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511881721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3511881721
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.854058814
Short name T153
Test name
Test status
Simulation time 103752798 ps
CPU time 6.67 seconds
Started Jan 24 02:53:51 PM PST 24
Finished Jan 24 02:54:28 PM PST 24
Peak memory 214668 kb
Host smart-fcbfe2dd-d134-40d4-9a2e-c46437324888
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854058814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.854058814
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3247212461
Short name T76
Test name
Test status
Simulation time 22110472 ps
CPU time 2.34 seconds
Started Jan 24 02:53:46 PM PST 24
Finished Jan 24 02:54:16 PM PST 24
Peak memory 220288 kb
Host smart-f3afbc62-22ed-4972-9e72-c611e76aa8a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247212461 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3247212461
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2347300118
Short name T107
Test name
Test status
Simulation time 118889617 ps
CPU time 2.19 seconds
Started Jan 24 02:53:52 PM PST 24
Finished Jan 24 02:54:24 PM PST 24
Peak memory 214668 kb
Host smart-a9f2c2c5-0f25-4d66-bfcc-5d9fd2924477
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347300118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2347300118
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3206506242
Short name T385
Test name
Test status
Simulation time 59357499 ps
CPU time 0.81 seconds
Started Jan 24 02:53:52 PM PST 24
Finished Jan 24 02:54:22 PM PST 24
Peak memory 202212 kb
Host smart-427845a0-d690-43fa-b579-ffeeea6876c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206506242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3206506242
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3405515675
Short name T308
Test name
Test status
Simulation time 27223908 ps
CPU time 1.74 seconds
Started Jan 24 02:53:46 PM PST 24
Finished Jan 24 02:54:15 PM PST 24
Peak memory 214948 kb
Host smart-ca8ff8f0-037d-4f49-b728-151387d44f1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405515675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3405515675
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.360256569
Short name T400
Test name
Test status
Simulation time 621824762 ps
CPU time 4.2 seconds
Started Jan 24 02:53:47 PM PST 24
Finished Jan 24 02:54:19 PM PST 24
Peak memory 215180 kb
Host smart-116d54da-3ab6-4c2a-9b25-131137495054
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360256569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.360256569
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.780522992
Short name T393
Test name
Test status
Simulation time 1180901924 ps
CPU time 18.5 seconds
Started Jan 24 02:53:46 PM PST 24
Finished Jan 24 02:54:33 PM PST 24
Peak memory 214968 kb
Host smart-8f9ea4d6-f165-4721-afe8-7c8c0a28018f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780522992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.780522992
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4122071173
Short name T114
Test name
Test status
Simulation time 111144791 ps
CPU time 7.34 seconds
Started Jan 24 02:52:58 PM PST 24
Finished Jan 24 02:53:11 PM PST 24
Peak memory 206484 kb
Host smart-f9e9e8af-d1a1-4bb2-ba1d-a865a6b2da62
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122071173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.4122071173
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4250127964
Short name T372
Test name
Test status
Simulation time 6903337705 ps
CPU time 26.09 seconds
Started Jan 24 02:52:49 PM PST 24
Finished Jan 24 02:53:23 PM PST 24
Peak memory 206304 kb
Host smart-c40de4ab-4cc6-4376-bbbb-25db4b3942d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250127964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.4250127964
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3512035947
Short name T395
Test name
Test status
Simulation time 49464315 ps
CPU time 0.93 seconds
Started Jan 24 02:52:47 PM PST 24
Finished Jan 24 02:52:56 PM PST 24
Peak memory 205548 kb
Host smart-572f2c61-8d13-4985-8b72-59d1a22a4ba6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512035947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3512035947
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3811767145
Short name T329
Test name
Test status
Simulation time 84572058 ps
CPU time 1.35 seconds
Started Jan 24 02:52:54 PM PST 24
Finished Jan 24 02:53:03 PM PST 24
Peak memory 216712 kb
Host smart-5c224cca-7624-4b5f-aecd-72004286af3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811767145 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3811767145
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4016506255
Short name T111
Test name
Test status
Simulation time 254058787 ps
CPU time 2.2 seconds
Started Jan 24 02:52:47 PM PST 24
Finished Jan 24 02:52:57 PM PST 24
Peak memory 206664 kb
Host smart-b9be49a7-e1fe-4fb4-94b6-09f48ce63f4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016506255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
016506255
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1640620359
Short name T363
Test name
Test status
Simulation time 33800151 ps
CPU time 0.74 seconds
Started Jan 24 02:52:54 PM PST 24
Finished Jan 24 02:53:01 PM PST 24
Peak memory 202116 kb
Host smart-c453e2af-2da9-4dfc-a750-9ae46cab10be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640620359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
640620359
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1553285398
Short name T323
Test name
Test status
Simulation time 41095554 ps
CPU time 1.42 seconds
Started Jan 24 02:52:48 PM PST 24
Finished Jan 24 02:52:57 PM PST 24
Peak memory 214868 kb
Host smart-d548c9db-61ed-45ec-beae-edb30cc49049
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553285398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1553285398
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2047488924
Short name T418
Test name
Test status
Simulation time 14840414 ps
CPU time 0.71 seconds
Started Jan 24 02:52:48 PM PST 24
Finished Jan 24 02:52:56 PM PST 24
Peak memory 202148 kb
Host smart-c47458cb-0e7b-4c52-89de-eee0575055f2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047488924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2047488924
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1719618015
Short name T99
Test name
Test status
Simulation time 95238855 ps
CPU time 1.87 seconds
Started Jan 24 02:52:55 PM PST 24
Finished Jan 24 02:53:04 PM PST 24
Peak memory 206700 kb
Host smart-93af419d-7796-4625-a9b6-6fbebd63f9cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719618015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1719618015
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3862469761
Short name T79
Test name
Test status
Simulation time 433611155 ps
CPU time 3.43 seconds
Started Jan 24 03:02:46 PM PST 24
Finished Jan 24 03:03:02 PM PST 24
Peak memory 215032 kb
Host smart-7804571e-8bbd-41ab-8926-4a66d69c3266
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862469761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
862469761
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1035296199
Short name T155
Test name
Test status
Simulation time 204180218 ps
CPU time 12.13 seconds
Started Jan 24 02:52:55 PM PST 24
Finished Jan 24 02:53:14 PM PST 24
Peak memory 214884 kb
Host smart-0923d362-2c14-4080-97d9-fada485d5dfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035296199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1035296199
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3081480127
Short name T314
Test name
Test status
Simulation time 11163874 ps
CPU time 0.69 seconds
Started Jan 24 02:54:01 PM PST 24
Finished Jan 24 02:54:32 PM PST 24
Peak memory 202144 kb
Host smart-a9745766-1b2a-4d35-8b62-028a51127769
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081480127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3081480127
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2563979647
Short name T318
Test name
Test status
Simulation time 14921890 ps
CPU time 0.74 seconds
Started Jan 24 02:54:04 PM PST 24
Finished Jan 24 02:54:34 PM PST 24
Peak memory 202524 kb
Host smart-f8f28155-817b-4cc4-b934-c6af31c88b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563979647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2563979647
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3142919181
Short name T371
Test name
Test status
Simulation time 12487268 ps
CPU time 0.67 seconds
Started Jan 24 02:53:57 PM PST 24
Finished Jan 24 02:54:28 PM PST 24
Peak memory 202188 kb
Host smart-17c3f67b-3c79-491d-a80d-11694288ea08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142919181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3142919181
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2378554907
Short name T379
Test name
Test status
Simulation time 48964724 ps
CPU time 0.69 seconds
Started Jan 24 02:53:54 PM PST 24
Finished Jan 24 02:54:25 PM PST 24
Peak memory 202120 kb
Host smart-840b0309-acf5-4716-8d8f-4853dd059c72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378554907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2378554907
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.222087546
Short name T417
Test name
Test status
Simulation time 142322991 ps
CPU time 0.7 seconds
Started Jan 24 02:54:06 PM PST 24
Finished Jan 24 02:54:37 PM PST 24
Peak memory 202212 kb
Host smart-a1c90d9b-faa6-4f91-9d21-92907df4f5d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222087546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.222087546
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1479553392
Short name T312
Test name
Test status
Simulation time 12110045 ps
CPU time 0.68 seconds
Started Jan 24 02:53:55 PM PST 24
Finished Jan 24 02:54:26 PM PST 24
Peak memory 202208 kb
Host smart-72a75916-cdc6-4393-afd2-8ac6c4dbcc87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479553392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1479553392
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3780713391
Short name T362
Test name
Test status
Simulation time 12630362 ps
CPU time 0.72 seconds
Started Jan 24 02:54:00 PM PST 24
Finished Jan 24 02:54:31 PM PST 24
Peak memory 202556 kb
Host smart-d8b2db90-3c03-4a47-9a5b-50b6e41e4a1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780713391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3780713391
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3114645890
Short name T103
Test name
Test status
Simulation time 54802775 ps
CPU time 0.76 seconds
Started Jan 24 02:54:06 PM PST 24
Finished Jan 24 02:54:37 PM PST 24
Peak memory 202204 kb
Host smart-c16edb58-2eee-472f-8048-0c46666cccfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114645890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3114645890
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2734553142
Short name T399
Test name
Test status
Simulation time 17483271 ps
CPU time 0.73 seconds
Started Jan 24 02:54:00 PM PST 24
Finished Jan 24 02:54:31 PM PST 24
Peak memory 202188 kb
Host smart-afb656c8-79d5-44a2-b30f-e09e175ad502
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734553142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2734553142
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1855257781
Short name T369
Test name
Test status
Simulation time 104967712 ps
CPU time 0.7 seconds
Started Jan 24 02:54:01 PM PST 24
Finished Jan 24 02:54:32 PM PST 24
Peak memory 202460 kb
Host smart-013fc511-3ee1-4f1a-b9b4-b4521afb70ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855257781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1855257781
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.766860469
Short name T130
Test name
Test status
Simulation time 8498371886 ps
CPU time 26.74 seconds
Started Jan 24 02:52:49 PM PST 24
Finished Jan 24 02:53:24 PM PST 24
Peak memory 214964 kb
Host smart-f8e79e09-4709-4c07-963e-d43b67f8e8cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766860469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.766860469
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1212717263
Short name T115
Test name
Test status
Simulation time 2239755400 ps
CPU time 35.33 seconds
Started Jan 24 02:52:49 PM PST 24
Finished Jan 24 02:53:31 PM PST 24
Peak memory 206912 kb
Host smart-bf28becf-9efd-44ef-a355-cc205f44b507
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212717263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1212717263
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3616730429
Short name T356
Test name
Test status
Simulation time 75156085 ps
CPU time 1.45 seconds
Started Jan 24 02:52:55 PM PST 24
Finished Jan 24 02:53:03 PM PST 24
Peak memory 214900 kb
Host smart-6cf9f1b0-4759-4301-a93b-67d0a7759aff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616730429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3616730429
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.388574572
Short name T98
Test name
Test status
Simulation time 42659234 ps
CPU time 1.35 seconds
Started Jan 24 02:52:48 PM PST 24
Finished Jan 24 02:52:57 PM PST 24
Peak memory 215048 kb
Host smart-2569a5cc-fa8b-430f-bbe8-c7c86f6d2dd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388574572 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.388574572
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.572641229
Short name T330
Test name
Test status
Simulation time 34994131 ps
CPU time 1.3 seconds
Started Jan 24 02:52:53 PM PST 24
Finished Jan 24 02:53:01 PM PST 24
Peak memory 206644 kb
Host smart-536c57c4-d3f7-48ff-aa46-43edaef6fd54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572641229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.572641229
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1492207058
Short name T322
Test name
Test status
Simulation time 62898086 ps
CPU time 0.79 seconds
Started Jan 24 02:52:47 PM PST 24
Finished Jan 24 02:52:56 PM PST 24
Peak memory 202228 kb
Host smart-47cdf0eb-fba1-46cd-a730-38ae4162e7ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492207058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
492207058
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.337464132
Short name T112
Test name
Test status
Simulation time 29569576 ps
CPU time 1.24 seconds
Started Jan 24 02:52:55 PM PST 24
Finished Jan 24 02:53:03 PM PST 24
Peak memory 214836 kb
Host smart-d29146fd-95ee-46a7-9071-0a547635e1eb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337464132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.337464132
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1907560741
Short name T309
Test name
Test status
Simulation time 25694696 ps
CPU time 0.64 seconds
Started Jan 24 02:52:54 PM PST 24
Finished Jan 24 02:53:02 PM PST 24
Peak memory 202136 kb
Host smart-dffd90e5-280d-44db-a21c-fadb44d8ea81
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907560741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1907560741
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2798061914
Short name T392
Test name
Test status
Simulation time 80028662 ps
CPU time 2.08 seconds
Started Jan 24 02:52:48 PM PST 24
Finished Jan 24 02:52:58 PM PST 24
Peak memory 206692 kb
Host smart-2ccd0a86-ee46-437d-8351-f4e26687f52b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798061914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2798061914
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2051969627
Short name T87
Test name
Test status
Simulation time 64877991 ps
CPU time 4.32 seconds
Started Jan 24 02:52:55 PM PST 24
Finished Jan 24 02:53:06 PM PST 24
Peak memory 216032 kb
Host smart-f8f67cf1-159d-403f-b8b9-8cbe9b045340
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051969627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
051969627
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3056520541
Short name T93
Test name
Test status
Simulation time 1183538680 ps
CPU time 19.36 seconds
Started Jan 24 02:52:56 PM PST 24
Finished Jan 24 02:53:22 PM PST 24
Peak memory 214900 kb
Host smart-d04662bd-2965-4473-8ea0-9b9eee84173a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056520541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3056520541
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.490757750
Short name T327
Test name
Test status
Simulation time 12578651 ps
CPU time 0.73 seconds
Started Jan 24 02:54:01 PM PST 24
Finished Jan 24 02:54:32 PM PST 24
Peak memory 202136 kb
Host smart-40dd14d9-8dba-4449-94ef-d2a31c9cf085
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490757750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.490757750
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2289390249
Short name T136
Test name
Test status
Simulation time 14030597 ps
CPU time 0.75 seconds
Started Jan 24 02:53:53 PM PST 24
Finished Jan 24 02:54:23 PM PST 24
Peak memory 202520 kb
Host smart-d2631017-7cf9-4df4-80de-03605c2882d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289390249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2289390249
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.990328620
Short name T352
Test name
Test status
Simulation time 13059790 ps
CPU time 0.7 seconds
Started Jan 24 02:54:00 PM PST 24
Finished Jan 24 02:54:31 PM PST 24
Peak memory 202120 kb
Host smart-062eaf35-b904-41be-b3eb-5264305a3aa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990328620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.990328620
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.777844229
Short name T349
Test name
Test status
Simulation time 35359867 ps
CPU time 0.72 seconds
Started Jan 24 03:04:28 PM PST 24
Finished Jan 24 03:04:47 PM PST 24
Peak memory 202556 kb
Host smart-51414076-fab0-490c-9ee1-34f4ffaf2580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777844229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.777844229
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3363197644
Short name T313
Test name
Test status
Simulation time 12826896 ps
CPU time 0.72 seconds
Started Jan 24 02:54:01 PM PST 24
Finished Jan 24 02:54:32 PM PST 24
Peak memory 202140 kb
Host smart-be736fd3-8ab2-4373-bbaf-01d56545615e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363197644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3363197644
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3199995844
Short name T348
Test name
Test status
Simulation time 14546117 ps
CPU time 0.74 seconds
Started Jan 24 02:54:06 PM PST 24
Finished Jan 24 02:54:36 PM PST 24
Peak memory 202204 kb
Host smart-f33a4e3e-ca02-4f18-b330-410f3cdf29e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199995844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3199995844
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.447869897
Short name T375
Test name
Test status
Simulation time 17666287 ps
CPU time 0.71 seconds
Started Jan 24 02:54:11 PM PST 24
Finished Jan 24 02:54:38 PM PST 24
Peak memory 202512 kb
Host smart-45e07423-9141-4c0a-ac96-4e835db3669f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447869897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.447869897
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.525143114
Short name T342
Test name
Test status
Simulation time 22838282 ps
CPU time 0.77 seconds
Started Jan 24 02:54:10 PM PST 24
Finished Jan 24 02:54:38 PM PST 24
Peak memory 202504 kb
Host smart-ad9d3020-14e7-4e04-bc64-529ffd94a9a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525143114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.525143114
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2699246919
Short name T317
Test name
Test status
Simulation time 93740925 ps
CPU time 0.69 seconds
Started Jan 24 02:54:10 PM PST 24
Finished Jan 24 02:54:38 PM PST 24
Peak memory 202492 kb
Host smart-0a19c860-5510-41ab-bb77-2620f1a47a4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699246919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2699246919
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.594845246
Short name T413
Test name
Test status
Simulation time 42680998 ps
CPU time 0.7 seconds
Started Jan 24 02:54:08 PM PST 24
Finished Jan 24 02:54:37 PM PST 24
Peak memory 202140 kb
Host smart-de707b6c-989c-45c0-a840-cf75d1f64f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594845246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.594845246
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3845906549
Short name T350
Test name
Test status
Simulation time 720625584 ps
CPU time 8.23 seconds
Started Jan 24 02:53:17 PM PST 24
Finished Jan 24 02:53:53 PM PST 24
Peak memory 206708 kb
Host smart-802be975-66a8-406e-9b72-1464a623bbbb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845906549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3845906549
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1260923693
Short name T398
Test name
Test status
Simulation time 556835638 ps
CPU time 34.95 seconds
Started Jan 24 02:53:16 PM PST 24
Finished Jan 24 02:54:19 PM PST 24
Peak memory 206648 kb
Host smart-340fccd2-fd5e-4720-9eb2-a65e6efb243d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260923693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1260923693
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3335429917
Short name T408
Test name
Test status
Simulation time 109220837 ps
CPU time 1.11 seconds
Started Jan 24 02:52:59 PM PST 24
Finished Jan 24 02:53:07 PM PST 24
Peak memory 206704 kb
Host smart-07689af4-530c-40d8-a2a1-90a27faa770b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335429917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3335429917
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2778435166
Short name T129
Test name
Test status
Simulation time 28675886 ps
CPU time 1.65 seconds
Started Jan 24 02:53:10 PM PST 24
Finished Jan 24 02:53:26 PM PST 24
Peak memory 222492 kb
Host smart-fbcc8ac0-fc0d-40de-a616-fc178a6d0476
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778435166 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2778435166
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3056083756
Short name T117
Test name
Test status
Simulation time 183401348 ps
CPU time 2.41 seconds
Started Jan 24 02:53:09 PM PST 24
Finished Jan 24 02:53:24 PM PST 24
Peak memory 214956 kb
Host smart-f569a5d8-5066-488e-8830-9b28ee67f577
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056083756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
056083756
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.310983836
Short name T139
Test name
Test status
Simulation time 52091605 ps
CPU time 0.74 seconds
Started Jan 24 02:53:10 PM PST 24
Finished Jan 24 02:53:25 PM PST 24
Peak memory 202508 kb
Host smart-3002b54f-6ded-4f7e-a1ba-2b3dac607737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310983836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.310983836
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4096895628
Short name T110
Test name
Test status
Simulation time 52954116 ps
CPU time 1.77 seconds
Started Jan 24 02:53:11 PM PST 24
Finished Jan 24 02:53:28 PM PST 24
Peak memory 214844 kb
Host smart-895f2749-8f01-471d-a6c6-3d4d55fcfcae
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096895628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4096895628
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1446279669
Short name T403
Test name
Test status
Simulation time 36771170 ps
CPU time 0.65 seconds
Started Jan 24 02:53:02 PM PST 24
Finished Jan 24 02:53:11 PM PST 24
Peak memory 202100 kb
Host smart-93783a96-b1cf-4923-bf7d-09fa24e60bf2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446279669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1446279669
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.40284908
Short name T113
Test name
Test status
Simulation time 85244729 ps
CPU time 3.57 seconds
Started Jan 24 02:53:06 PM PST 24
Finished Jan 24 02:53:21 PM PST 24
Peak memory 206500 kb
Host smart-9c40ebc6-0591-48d6-ad1b-0f66affd1431
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40284908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_same_csr_outstanding.40284908
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4289709387
Short name T88
Test name
Test status
Simulation time 177518634 ps
CPU time 4.06 seconds
Started Jan 24 02:53:06 PM PST 24
Finished Jan 24 02:53:20 PM PST 24
Peak memory 215084 kb
Host smart-8f26c041-7fc7-407a-9868-5e5f7168e89c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289709387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4
289709387
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.802270751
Short name T94
Test name
Test status
Simulation time 290694678 ps
CPU time 7.03 seconds
Started Jan 24 02:53:03 PM PST 24
Finished Jan 24 02:53:19 PM PST 24
Peak memory 214904 kb
Host smart-d2b37e3d-9a14-4850-8ee7-8ff2ac1b6558
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802270751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.802270751
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2206427121
Short name T337
Test name
Test status
Simulation time 43168278 ps
CPU time 0.8 seconds
Started Jan 24 02:54:08 PM PST 24
Finished Jan 24 02:54:38 PM PST 24
Peak memory 202152 kb
Host smart-80853d27-1c35-4ad5-9595-82b8b7195cad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206427121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2206427121
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2660960739
Short name T345
Test name
Test status
Simulation time 12910571 ps
CPU time 0.68 seconds
Started Jan 24 02:54:16 PM PST 24
Finished Jan 24 02:54:41 PM PST 24
Peak memory 202188 kb
Host smart-a97936f8-dfc0-420e-ae1f-ea794fcbc9fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660960739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2660960739
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.712727609
Short name T326
Test name
Test status
Simulation time 14802458 ps
CPU time 0.71 seconds
Started Jan 24 02:54:08 PM PST 24
Finished Jan 24 02:54:37 PM PST 24
Peak memory 202180 kb
Host smart-6d6b0698-49cf-4ccf-9301-e7ba7e4e9bb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712727609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.712727609
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3678517961
Short name T324
Test name
Test status
Simulation time 71743781 ps
CPU time 0.75 seconds
Started Jan 24 02:54:13 PM PST 24
Finished Jan 24 02:54:39 PM PST 24
Peak memory 202204 kb
Host smart-4248c852-2ec3-48d3-8d9c-9d9e04f4117a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678517961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3678517961
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2126906913
Short name T140
Test name
Test status
Simulation time 35253582 ps
CPU time 0.76 seconds
Started Jan 24 02:56:33 PM PST 24
Finished Jan 24 02:56:36 PM PST 24
Peak memory 202236 kb
Host smart-cf19b3d5-2f6d-4e1b-909e-66d695f25c59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126906913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2126906913
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3625186371
Short name T141
Test name
Test status
Simulation time 17090851 ps
CPU time 0.7 seconds
Started Jan 24 02:56:28 PM PST 24
Finished Jan 24 02:56:30 PM PST 24
Peak memory 202460 kb
Host smart-9bf7ffe7-a40c-4bd3-9ece-23e4153f2b51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625186371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3625186371
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1243879220
Short name T319
Test name
Test status
Simulation time 44780258 ps
CPU time 0.73 seconds
Started Jan 24 02:56:37 PM PST 24
Finished Jan 24 02:56:39 PM PST 24
Peak memory 202172 kb
Host smart-aa25a83f-f3db-499f-804b-1b8e5203477f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243879220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1243879220
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.257851155
Short name T336
Test name
Test status
Simulation time 67150222 ps
CPU time 0.72 seconds
Started Jan 24 02:56:30 PM PST 24
Finished Jan 24 02:56:32 PM PST 24
Peak memory 202500 kb
Host smart-ea0fedaa-ece1-4851-a509-3cc21e1d9fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257851155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.257851155
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2620837225
Short name T316
Test name
Test status
Simulation time 15545987 ps
CPU time 0.72 seconds
Started Jan 24 02:56:27 PM PST 24
Finished Jan 24 02:56:29 PM PST 24
Peak memory 202200 kb
Host smart-54582fc3-e166-49fe-b860-833b54fecb4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620837225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2620837225
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2221193568
Short name T346
Test name
Test status
Simulation time 39144268 ps
CPU time 0.68 seconds
Started Jan 24 02:56:26 PM PST 24
Finished Jan 24 02:56:28 PM PST 24
Peak memory 202144 kb
Host smart-e75946f7-06dd-4b26-8c7c-2465f236afb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221193568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2221193568
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2693412141
Short name T44
Test name
Test status
Simulation time 67030982 ps
CPU time 1.4 seconds
Started Jan 24 02:53:07 PM PST 24
Finished Jan 24 02:53:19 PM PST 24
Peak memory 214948 kb
Host smart-f380eb06-1729-4831-8aa2-a1a14fceb0bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693412141 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2693412141
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3045114067
Short name T106
Test name
Test status
Simulation time 160165625 ps
CPU time 1.79 seconds
Started Jan 24 02:53:12 PM PST 24
Finished Jan 24 02:53:28 PM PST 24
Peak memory 214888 kb
Host smart-e2a3b438-a2f3-44ea-b379-86dde8eb7ac8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045114067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
045114067
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2513926808
Short name T388
Test name
Test status
Simulation time 12440287 ps
CPU time 0.69 seconds
Started Jan 24 02:53:16 PM PST 24
Finished Jan 24 02:53:43 PM PST 24
Peak memory 202180 kb
Host smart-d0bcbd4f-c8fc-4efe-b3f3-7497785c62bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513926808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
513926808
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1213528090
Short name T96
Test name
Test status
Simulation time 54082087 ps
CPU time 1.91 seconds
Started Jan 24 02:53:00 PM PST 24
Finished Jan 24 02:53:10 PM PST 24
Peak memory 206620 kb
Host smart-226d405a-2b84-4981-a47e-fc0a2e59fce3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213528090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1213528090
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3683264128
Short name T412
Test name
Test status
Simulation time 93385536 ps
CPU time 1.48 seconds
Started Jan 24 02:53:12 PM PST 24
Finished Jan 24 02:53:28 PM PST 24
Peak memory 206768 kb
Host smart-0798537b-47b5-47d2-803e-9490e5e47c99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683264128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
683264128
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1055945557
Short name T74
Test name
Test status
Simulation time 6689120572 ps
CPU time 15.02 seconds
Started Jan 24 02:53:11 PM PST 24
Finished Jan 24 02:53:41 PM PST 24
Peak memory 215144 kb
Host smart-c604491e-294f-4973-b711-dd8e8801c826
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055945557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1055945557
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1629609996
Short name T104
Test name
Test status
Simulation time 40760220 ps
CPU time 2.2 seconds
Started Jan 24 02:53:09 PM PST 24
Finished Jan 24 02:53:26 PM PST 24
Peak memory 215968 kb
Host smart-189dda49-6d34-4894-985c-dd60e6f79f19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629609996 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1629609996
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2269259105
Short name T383
Test name
Test status
Simulation time 54339957 ps
CPU time 1.3 seconds
Started Jan 24 02:53:11 PM PST 24
Finished Jan 24 02:53:27 PM PST 24
Peak memory 206588 kb
Host smart-a5762e27-a8a3-46e4-ab9d-1682ce7b6f51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269259105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
269259105
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3063960451
Short name T333
Test name
Test status
Simulation time 60580063 ps
CPU time 0.69 seconds
Started Jan 24 02:53:11 PM PST 24
Finished Jan 24 02:53:27 PM PST 24
Peak memory 202184 kb
Host smart-f3607b74-51b8-4df6-a1b5-f55acba11e6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063960451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
063960451
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1462797980
Short name T331
Test name
Test status
Simulation time 29310948 ps
CPU time 1.69 seconds
Started Jan 24 02:53:03 PM PST 24
Finished Jan 24 02:53:13 PM PST 24
Peak memory 204864 kb
Host smart-9f595e48-df63-4d2d-901d-f8f269acb3e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462797980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1462797980
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3089045705
Short name T344
Test name
Test status
Simulation time 729211162 ps
CPU time 16.56 seconds
Started Jan 24 02:53:04 PM PST 24
Finished Jan 24 02:53:30 PM PST 24
Peak memory 223084 kb
Host smart-7bb8d4af-b111-4fa9-9773-d67ba13c3a51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089045705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3089045705
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1904126512
Short name T353
Test name
Test status
Simulation time 84011188 ps
CPU time 1.39 seconds
Started Jan 24 05:58:34 PM PST 24
Finished Jan 24 05:58:36 PM PST 24
Peak memory 215008 kb
Host smart-5fa5014f-2418-4094-b220-ea6509794e99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904126512 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1904126512
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2376908018
Short name T354
Test name
Test status
Simulation time 350628014 ps
CPU time 2.61 seconds
Started Jan 24 02:53:04 PM PST 24
Finished Jan 24 02:53:17 PM PST 24
Peak memory 214972 kb
Host smart-3120ed13-dac9-4476-8602-53c738591009
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376908018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
376908018
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.156125862
Short name T334
Test name
Test status
Simulation time 16423968 ps
CPU time 0.73 seconds
Started Jan 24 02:53:04 PM PST 24
Finished Jan 24 02:53:15 PM PST 24
Peak memory 202216 kb
Host smart-ac4e81e1-92db-47ad-abfc-d6d7cf3f5c90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156125862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.156125862
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.837109545
Short name T404
Test name
Test status
Simulation time 184978334 ps
CPU time 4.15 seconds
Started Jan 24 02:53:05 PM PST 24
Finished Jan 24 02:53:19 PM PST 24
Peak memory 215088 kb
Host smart-e8e6d0dd-3c93-42e4-b2e6-1547037d9650
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837109545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.837109545
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.338146293
Short name T152
Test name
Test status
Simulation time 3735976226 ps
CPU time 21.76 seconds
Started Jan 24 02:53:01 PM PST 24
Finished Jan 24 02:53:31 PM PST 24
Peak memory 215128 kb
Host smart-a0342235-cf0a-451c-a9e8-5c5b64e0ba68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338146293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.338146293
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3931539373
Short name T341
Test name
Test status
Simulation time 23950808 ps
CPU time 2.32 seconds
Started Jan 24 04:41:08 PM PST 24
Finished Jan 24 04:41:11 PM PST 24
Peak memory 222128 kb
Host smart-fb661441-6ba3-4dbc-83f8-78b7c7176d0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931539373 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3931539373
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3913928747
Short name T328
Test name
Test status
Simulation time 72241655 ps
CPU time 1.31 seconds
Started Jan 24 02:53:17 PM PST 24
Finished Jan 24 02:53:45 PM PST 24
Peak memory 206636 kb
Host smart-97e393f7-6987-4bed-82e4-2b6590283212
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913928747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
913928747
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1229643171
Short name T325
Test name
Test status
Simulation time 28344862 ps
CPU time 0.69 seconds
Started Jan 24 02:53:14 PM PST 24
Finished Jan 24 02:53:30 PM PST 24
Peak memory 202536 kb
Host smart-6bd6ce69-3844-4ab5-9e6d-66b311b6c3c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229643171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
229643171
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.637247886
Short name T387
Test name
Test status
Simulation time 875562269 ps
CPU time 4.22 seconds
Started Jan 24 02:53:14 PM PST 24
Finished Jan 24 02:53:34 PM PST 24
Peak memory 206720 kb
Host smart-0d89607e-0054-4eb5-bfce-6ac4f368a6f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637247886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.637247886
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2741867036
Short name T85
Test name
Test status
Simulation time 882396106 ps
CPU time 4.95 seconds
Started Jan 24 02:53:18 PM PST 24
Finished Jan 24 02:53:52 PM PST 24
Peak memory 215000 kb
Host smart-2dabc078-a0ce-460b-a4f7-aa0fa9bce177
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741867036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
741867036
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2709393698
Short name T134
Test name
Test status
Simulation time 165533467 ps
CPU time 1.2 seconds
Started Jan 24 02:53:26 PM PST 24
Finished Jan 24 02:54:00 PM PST 24
Peak memory 220368 kb
Host smart-5acc5eb8-aff7-4b81-b6b4-72ee84f236fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709393698 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2709393698
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.673137642
Short name T109
Test name
Test status
Simulation time 89923929 ps
CPU time 2.58 seconds
Started Jan 24 02:53:29 PM PST 24
Finished Jan 24 02:54:05 PM PST 24
Peak memory 214944 kb
Host smart-398f1283-f6a9-408c-9cef-c80c805214e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673137642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.673137642
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2509005237
Short name T355
Test name
Test status
Simulation time 13485879 ps
CPU time 0.73 seconds
Started Jan 24 02:53:14 PM PST 24
Finished Jan 24 02:53:30 PM PST 24
Peak memory 202536 kb
Host smart-3c6fbf3a-ca53-49db-bcf7-cf19d38c8586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509005237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
509005237
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.825046882
Short name T386
Test name
Test status
Simulation time 113270519 ps
CPU time 2.97 seconds
Started Jan 24 02:53:25 PM PST 24
Finished Jan 24 02:54:00 PM PST 24
Peak memory 206188 kb
Host smart-f5472697-43f0-4708-baa0-12413fd334bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825046882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.825046882
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4095739036
Short name T89
Test name
Test status
Simulation time 263435372 ps
CPU time 2.09 seconds
Started Jan 24 02:53:15 PM PST 24
Finished Jan 24 02:53:36 PM PST 24
Peak memory 215124 kb
Host smart-92c7a183-0f36-4b0b-8d7d-55eb67457b0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095739036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
095739036
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1467276551
Short name T712
Test name
Test status
Simulation time 14339274 ps
CPU time 0.7 seconds
Started Jan 24 07:45:53 PM PST 24
Finished Jan 24 07:45:55 PM PST 24
Peak memory 204096 kb
Host smart-ed510903-035c-4918-b1de-d1f46b20aa99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467276551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
467276551
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.722839872
Short name T631
Test name
Test status
Simulation time 4021957963 ps
CPU time 4.64 seconds
Started Jan 24 07:45:29 PM PST 24
Finished Jan 24 07:45:37 PM PST 24
Peak memory 220528 kb
Host smart-86627955-6ec1-4944-803b-d02c6aa7ff80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722839872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.722839872
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.920647553
Short name T866
Test name
Test status
Simulation time 18990299 ps
CPU time 0.79 seconds
Started Jan 24 07:45:23 PM PST 24
Finished Jan 24 07:45:29 PM PST 24
Peak memory 204212 kb
Host smart-bca2df2d-dac5-4f0f-9ed3-33af995e8181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920647553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.920647553
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1802355199
Short name T30
Test name
Test status
Simulation time 48527864624 ps
CPU time 125.84 seconds
Started Jan 24 07:45:41 PM PST 24
Finished Jan 24 07:47:48 PM PST 24
Peak memory 250096 kb
Host smart-986acad6-ec7f-4a08-baf2-4b6073585153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802355199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1802355199
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.4081218229
Short name T993
Test name
Test status
Simulation time 17039734251 ps
CPU time 46.09 seconds
Started Jan 24 07:45:40 PM PST 24
Finished Jan 24 07:46:28 PM PST 24
Peak memory 252244 kb
Host smart-2510d72c-c880-40d8-b61c-897e55f0f1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081218229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.4081218229
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.682208112
Short name T1013
Test name
Test status
Simulation time 2960704452 ps
CPU time 13.83 seconds
Started Jan 24 07:45:40 PM PST 24
Finished Jan 24 07:45:55 PM PST 24
Peak memory 248748 kb
Host smart-0b20f7e5-c099-4f42-a8fa-7c9af9e6ca48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682208112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.682208112
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3615539959
Short name T218
Test name
Test status
Simulation time 571590092 ps
CPU time 3.78 seconds
Started Jan 24 07:45:32 PM PST 24
Finished Jan 24 07:45:40 PM PST 24
Peak memory 232676 kb
Host smart-f0f1dd0c-5f5a-4b07-bade-609c3098c5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615539959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3615539959
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1108851607
Short name T307
Test name
Test status
Simulation time 67406874459 ps
CPU time 49.02 seconds
Started Jan 24 07:58:14 PM PST 24
Finished Jan 24 07:59:04 PM PST 24
Peak memory 233468 kb
Host smart-bc49d033-b7c3-4a73-b3bb-567f4b77c28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108851607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1108851607
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.456084376
Short name T1066
Test name
Test status
Simulation time 26048571 ps
CPU time 1.03 seconds
Started Jan 24 09:15:32 PM PST 24
Finished Jan 24 09:15:34 PM PST 24
Peak memory 215788 kb
Host smart-601ac3b8-67a4-4cde-b75b-eda122273400
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456084376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.456084376
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1020725292
Short name T1028
Test name
Test status
Simulation time 746911241 ps
CPU time 8.63 seconds
Started Jan 24 07:45:32 PM PST 24
Finished Jan 24 07:45:45 PM PST 24
Peak memory 235904 kb
Host smart-a5624cc9-3b9d-43c2-8442-8b2b0c0bd32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020725292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1020725292
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2863207476
Short name T645
Test name
Test status
Simulation time 127542377 ps
CPU time 3.11 seconds
Started Jan 24 08:19:29 PM PST 24
Finished Jan 24 08:19:37 PM PST 24
Peak memory 233060 kb
Host smart-f976abe2-f88b-4b68-acdf-e08c1c8938cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863207476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2863207476
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.702490725
Short name T974
Test name
Test status
Simulation time 4166066809 ps
CPU time 4.99 seconds
Started Jan 24 07:45:40 PM PST 24
Finished Jan 24 07:45:47 PM PST 24
Peak memory 216012 kb
Host smart-89de3770-9dd1-4235-b8f3-0c977f534c2b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=702490725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.702490725
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1230132781
Short name T49
Test name
Test status
Simulation time 328667046 ps
CPU time 1.11 seconds
Started Jan 24 07:45:44 PM PST 24
Finished Jan 24 07:45:47 PM PST 24
Peak memory 234596 kb
Host smart-f631712a-4237-488b-a007-07b145ecdc76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230132781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1230132781
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3004912694
Short name T723
Test name
Test status
Simulation time 3712139151 ps
CPU time 34.63 seconds
Started Jan 24 07:45:28 PM PST 24
Finished Jan 24 07:46:06 PM PST 24
Peak memory 215988 kb
Host smart-e0c1a974-689f-47a1-84c4-2f12cb165291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004912694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3004912694
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3262130430
Short name T1023
Test name
Test status
Simulation time 27662470092 ps
CPU time 23.21 seconds
Started Jan 24 09:53:47 PM PST 24
Finished Jan 24 09:54:11 PM PST 24
Peak memory 215992 kb
Host smart-963bf888-127f-45c6-8bac-1910436adb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262130430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3262130430
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1162886019
Short name T562
Test name
Test status
Simulation time 105345331 ps
CPU time 1.37 seconds
Started Jan 24 09:15:03 PM PST 24
Finished Jan 24 09:15:06 PM PST 24
Peak memory 215404 kb
Host smart-32483924-22c2-44ae-ae4b-4a1cfa0624cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162886019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1162886019
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2385007742
Short name T768
Test name
Test status
Simulation time 213725637 ps
CPU time 0.84 seconds
Started Jan 24 07:45:40 PM PST 24
Finished Jan 24 07:45:43 PM PST 24
Peak memory 204572 kb
Host smart-fb219247-1f18-4813-a3ec-7b18457681b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385007742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2385007742
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2132486438
Short name T520
Test name
Test status
Simulation time 56128549 ps
CPU time 0.73 seconds
Started Jan 24 07:45:58 PM PST 24
Finished Jan 24 07:46:00 PM PST 24
Peak memory 204480 kb
Host smart-3271a100-ae83-4fef-b80a-4bbea7ba52c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132486438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
132486438
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.712368920
Short name T466
Test name
Test status
Simulation time 2183621868 ps
CPU time 3.36 seconds
Started Jan 24 07:45:53 PM PST 24
Finished Jan 24 07:45:58 PM PST 24
Peak memory 217244 kb
Host smart-d71ae0c5-ebfa-4853-b126-f5795554ef6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712368920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.712368920
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1677299057
Short name T1077
Test name
Test status
Simulation time 222170615 ps
CPU time 0.75 seconds
Started Jan 24 07:45:43 PM PST 24
Finished Jan 24 07:45:45 PM PST 24
Peak memory 205244 kb
Host smart-eb749e06-abcf-4223-9cf2-2044e9194446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677299057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1677299057
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3215649828
Short name T67
Test name
Test status
Simulation time 51085563727 ps
CPU time 222.81 seconds
Started Jan 24 07:45:53 PM PST 24
Finished Jan 24 07:49:37 PM PST 24
Peak memory 260776 kb
Host smart-b48777dd-900c-4f5e-b8c8-6d3a4b13e82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215649828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3215649828
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2421612454
Short name T1042
Test name
Test status
Simulation time 4642149689 ps
CPU time 43.32 seconds
Started Jan 24 07:46:00 PM PST 24
Finished Jan 24 07:46:45 PM PST 24
Peak memory 248920 kb
Host smart-2bbe7bd0-eada-44b2-9ccc-6ed86d524119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421612454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2421612454
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3755031336
Short name T992
Test name
Test status
Simulation time 1045784402 ps
CPU time 12.55 seconds
Started Jan 24 07:45:43 PM PST 24
Finished Jan 24 07:45:57 PM PST 24
Peak memory 239748 kb
Host smart-72de40b7-4a71-46bb-911c-e2f218291779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755031336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3755031336
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1444297579
Short name T59
Test name
Test status
Simulation time 553447052 ps
CPU time 3.26 seconds
Started Jan 24 07:45:45 PM PST 24
Finished Jan 24 07:45:50 PM PST 24
Peak memory 232700 kb
Host smart-ce0428e4-d745-46c2-9d36-17beb4ee8379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444297579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1444297579
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3185941244
Short name T967
Test name
Test status
Simulation time 51513776568 ps
CPU time 35.71 seconds
Started Jan 24 07:45:45 PM PST 24
Finished Jan 24 07:46:22 PM PST 24
Peak memory 228800 kb
Host smart-89896a5a-ec47-45f2-a695-d7bc4d24efa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185941244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3185941244
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3705259680
Short name T623
Test name
Test status
Simulation time 1010972064 ps
CPU time 5.14 seconds
Started Jan 24 07:45:53 PM PST 24
Finished Jan 24 07:45:59 PM PST 24
Peak memory 232468 kb
Host smart-2ff76016-17a6-4a0d-873c-2e466a371f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705259680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3705259680
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1542963705
Short name T9
Test name
Test status
Simulation time 1454438175 ps
CPU time 5.46 seconds
Started Jan 24 07:45:43 PM PST 24
Finished Jan 24 07:45:50 PM PST 24
Peak memory 216212 kb
Host smart-f722d577-cdcd-4a10-b89e-62b4d0990521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542963705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1542963705
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.3209562821
Short name T798
Test name
Test status
Simulation time 19098367 ps
CPU time 0.77 seconds
Started Jan 24 07:45:53 PM PST 24
Finished Jan 24 07:45:55 PM PST 24
Peak memory 215900 kb
Host smart-c3209785-2fab-487a-84d2-3fe2fb297f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209562821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.3209562821
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4125542425
Short name T897
Test name
Test status
Simulation time 520118976 ps
CPU time 3.36 seconds
Started Jan 24 07:45:47 PM PST 24
Finished Jan 24 07:45:51 PM PST 24
Peak memory 215924 kb
Host smart-2f5d5f49-06c6-4c0d-8db2-c256fe15b958
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4125542425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4125542425
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.349845066
Short name T50
Test name
Test status
Simulation time 33031746 ps
CPU time 0.98 seconds
Started Jan 24 07:46:00 PM PST 24
Finished Jan 24 07:46:03 PM PST 24
Peak memory 233760 kb
Host smart-513be07c-0ced-4b13-bd59-396e9f17a007
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349845066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.349845066
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.203299977
Short name T525
Test name
Test status
Simulation time 666400599 ps
CPU time 8.25 seconds
Started Jan 24 07:52:29 PM PST 24
Finished Jan 24 07:52:38 PM PST 24
Peak memory 215936 kb
Host smart-04ee72f0-a95b-4fa6-9748-9375f358fdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203299977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.203299977
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3309028277
Short name T1032
Test name
Test status
Simulation time 7600106340 ps
CPU time 12.26 seconds
Started Jan 24 07:45:43 PM PST 24
Finished Jan 24 07:45:56 PM PST 24
Peak memory 215952 kb
Host smart-3077a361-4ad3-4856-9d81-a7a030e86387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309028277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3309028277
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1579199646
Short name T442
Test name
Test status
Simulation time 170086250 ps
CPU time 2.44 seconds
Started Jan 24 07:45:44 PM PST 24
Finished Jan 24 07:45:48 PM PST 24
Peak memory 208072 kb
Host smart-0d9bc5fb-1a59-44f7-ae76-071a604420c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579199646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1579199646
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3551399911
Short name T767
Test name
Test status
Simulation time 348397342 ps
CPU time 1.01 seconds
Started Jan 24 07:45:42 PM PST 24
Finished Jan 24 07:45:45 PM PST 24
Peak memory 205612 kb
Host smart-51f7ee9c-6f95-4947-b17c-2bd7b8105a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551399911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3551399911
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3861937422
Short name T660
Test name
Test status
Simulation time 3530472428 ps
CPU time 5.27 seconds
Started Jan 24 07:45:53 PM PST 24
Finished Jan 24 07:45:59 PM PST 24
Peak memory 216736 kb
Host smart-5456fc59-8640-4de7-9dd1-f43df21cc1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861937422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3861937422
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3486084374
Short name T635
Test name
Test status
Simulation time 27640444 ps
CPU time 0.72 seconds
Started Jan 24 07:48:02 PM PST 24
Finished Jan 24 07:48:09 PM PST 24
Peak memory 203564 kb
Host smart-14eff725-c89a-43d1-bae8-a92fbc37cb01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486084374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3486084374
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2742814752
Short name T227
Test name
Test status
Simulation time 887340986 ps
CPU time 5.24 seconds
Started Jan 24 07:47:59 PM PST 24
Finished Jan 24 07:48:10 PM PST 24
Peak memory 232668 kb
Host smart-e13e28b7-65de-4eaa-8a61-03b0b1d0bf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742814752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2742814752
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.4240925432
Short name T568
Test name
Test status
Simulation time 16740469 ps
CPU time 0.74 seconds
Started Jan 24 09:36:17 PM PST 24
Finished Jan 24 09:36:19 PM PST 24
Peak memory 204284 kb
Host smart-6b92b5bf-b107-4642-bd54-d22393bdf3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240925432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4240925432
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.923514708
Short name T121
Test name
Test status
Simulation time 16049947285 ps
CPU time 118.7 seconds
Started Jan 24 07:48:04 PM PST 24
Finished Jan 24 07:50:08 PM PST 24
Peak memory 250012 kb
Host smart-a19af589-b5ee-43cc-9064-cbe74a5b5119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923514708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.923514708
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1821907009
Short name T830
Test name
Test status
Simulation time 11885121002 ps
CPU time 10.69 seconds
Started Jan 24 07:47:48 PM PST 24
Finished Jan 24 07:48:00 PM PST 24
Peak memory 217260 kb
Host smart-a7b90663-f15f-40b3-b1de-58543631e608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821907009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1821907009
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.623762632
Short name T239
Test name
Test status
Simulation time 5525303450 ps
CPU time 19.87 seconds
Started Jan 24 07:48:01 PM PST 24
Finished Jan 24 07:48:28 PM PST 24
Peak memory 230600 kb
Host smart-f7573488-7ae3-47bc-a28f-e9c311ca8eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623762632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.623762632
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3121637542
Short name T503
Test name
Test status
Simulation time 17482333 ps
CPU time 1.06 seconds
Started Jan 24 07:47:56 PM PST 24
Finished Jan 24 07:48:05 PM PST 24
Peak memory 217000 kb
Host smart-0238294e-7ecd-4f31-a062-0294af06c00e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121637542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3121637542
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1781566402
Short name T846
Test name
Test status
Simulation time 423830366 ps
CPU time 5.02 seconds
Started Jan 24 07:47:58 PM PST 24
Finished Jan 24 07:48:09 PM PST 24
Peak memory 232808 kb
Host smart-c0346c11-8a98-4a03-b47b-f245308ea9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781566402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1781566402
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.3316482311
Short name T494
Test name
Test status
Simulation time 23254154 ps
CPU time 0.76 seconds
Started Jan 24 07:47:50 PM PST 24
Finished Jan 24 07:47:52 PM PST 24
Peak memory 215880 kb
Host smart-2e77a9fd-f57d-4005-a0ef-6482c609b347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316482311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.3316482311
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.441930416
Short name T459
Test name
Test status
Simulation time 10921186652 ps
CPU time 5.59 seconds
Started Jan 24 07:48:00 PM PST 24
Finished Jan 24 07:48:10 PM PST 24
Peak memory 221348 kb
Host smart-e7608b38-c2b7-4d09-a3c7-88db6913e0c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=441930416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.441930416
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2363248781
Short name T518
Test name
Test status
Simulation time 2844447680 ps
CPU time 25.21 seconds
Started Jan 24 07:47:53 PM PST 24
Finished Jan 24 07:48:20 PM PST 24
Peak memory 216052 kb
Host smart-a274a194-05a7-4321-893a-682f88c9783f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363248781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2363248781
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2146313957
Short name T483
Test name
Test status
Simulation time 1861307777 ps
CPU time 4.75 seconds
Started Jan 24 07:47:49 PM PST 24
Finished Jan 24 07:47:55 PM PST 24
Peak memory 207244 kb
Host smart-ad2f58ea-d8a8-474a-9223-307d482e9822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146313957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2146313957
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1152162883
Short name T500
Test name
Test status
Simulation time 241740490 ps
CPU time 4.33 seconds
Started Jan 24 07:47:50 PM PST 24
Finished Jan 24 07:47:55 PM PST 24
Peak memory 207792 kb
Host smart-c203ed0e-92d6-4b47-897e-6f0369cbbeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152162883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1152162883
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2455880469
Short name T930
Test name
Test status
Simulation time 75739713 ps
CPU time 0.92 seconds
Started Jan 24 07:47:51 PM PST 24
Finished Jan 24 07:47:53 PM PST 24
Peak memory 204616 kb
Host smart-4a599577-0388-4857-8451-89ff8bf2f89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455880469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2455880469
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2288357612
Short name T630
Test name
Test status
Simulation time 3327565613 ps
CPU time 10.83 seconds
Started Jan 24 07:47:58 PM PST 24
Finished Jan 24 07:48:15 PM PST 24
Peak memory 226696 kb
Host smart-6e7a9cad-4d46-4e94-9660-7a6f6c4044d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288357612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2288357612
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2164012308
Short name T119
Test name
Test status
Simulation time 39447119 ps
CPU time 0.71 seconds
Started Jan 24 09:12:48 PM PST 24
Finished Jan 24 09:12:49 PM PST 24
Peak memory 204120 kb
Host smart-58c048f1-0ea1-43a1-9996-85b16f103d10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164012308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2164012308
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3198709079
Short name T709
Test name
Test status
Simulation time 855452069 ps
CPU time 4.38 seconds
Started Jan 24 07:48:15 PM PST 24
Finished Jan 24 07:48:22 PM PST 24
Peak memory 217976 kb
Host smart-a63f96d7-91f1-4d36-93f3-c1a1348fc256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198709079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3198709079
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.400961465
Short name T956
Test name
Test status
Simulation time 73523136 ps
CPU time 0.78 seconds
Started Jan 24 07:47:57 PM PST 24
Finished Jan 24 07:48:05 PM PST 24
Peak memory 205284 kb
Host smart-1a0a7a84-53ea-496d-a234-a46b888bac18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400961465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.400961465
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1276330448
Short name T990
Test name
Test status
Simulation time 459694118095 ps
CPU time 307.46 seconds
Started Jan 24 08:01:29 PM PST 24
Finished Jan 24 08:06:37 PM PST 24
Peak memory 264708 kb
Host smart-832d15f9-4cc1-412e-bad5-3d75207af7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276330448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1276330448
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3550785303
Short name T188
Test name
Test status
Simulation time 49461391484 ps
CPU time 95.13 seconds
Started Jan 24 08:28:24 PM PST 24
Finished Jan 24 08:30:00 PM PST 24
Peak memory 248240 kb
Host smart-89ac4dc6-957d-4c9d-8c5c-c03245447f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550785303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3550785303
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1920415141
Short name T572
Test name
Test status
Simulation time 25448572539 ps
CPU time 217.39 seconds
Started Jan 24 07:48:19 PM PST 24
Finished Jan 24 07:52:01 PM PST 24
Peak memory 253628 kb
Host smart-7f71cfda-4e24-457e-8336-4c0ff1d00394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920415141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1920415141
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1757100950
Short name T590
Test name
Test status
Simulation time 32691430577 ps
CPU time 28.19 seconds
Started Jan 24 07:48:18 PM PST 24
Finished Jan 24 07:48:51 PM PST 24
Peak memory 242616 kb
Host smart-1fe8b720-fb18-4502-b970-b9b34083ea76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757100950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1757100950
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1858764696
Short name T580
Test name
Test status
Simulation time 3338848315 ps
CPU time 11.49 seconds
Started Jan 24 07:48:15 PM PST 24
Finished Jan 24 07:48:29 PM PST 24
Peak memory 218716 kb
Host smart-bab63f98-f6f6-4d18-93f6-7a8e78491b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858764696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1858764696
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2683992998
Short name T211
Test name
Test status
Simulation time 249408829 ps
CPU time 2.73 seconds
Started Jan 24 07:48:15 PM PST 24
Finished Jan 24 07:48:20 PM PST 24
Peak memory 216404 kb
Host smart-e967aacd-514a-4995-bf9f-85e9b7486ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683992998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2683992998
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1538983679
Short name T1081
Test name
Test status
Simulation time 30409322 ps
CPU time 1 seconds
Started Jan 24 07:47:57 PM PST 24
Finished Jan 24 07:48:05 PM PST 24
Peak memory 215784 kb
Host smart-ff96cc20-39e2-484b-aef4-8c043b57b031
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538983679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1538983679
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2606094187
Short name T207
Test name
Test status
Simulation time 535674426 ps
CPU time 7.91 seconds
Started Jan 24 07:48:16 PM PST 24
Finished Jan 24 07:48:26 PM PST 24
Peak memory 222920 kb
Host smart-168c6e3f-f2d3-43a5-be35-568dc3f0d68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606094187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2606094187
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2954664220
Short name T250
Test name
Test status
Simulation time 4846164239 ps
CPU time 15.93 seconds
Started Jan 24 07:48:11 PM PST 24
Finished Jan 24 07:48:32 PM PST 24
Peak memory 230192 kb
Host smart-c377ed04-4438-43de-a3fe-d4ecb930de85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954664220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2954664220
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.470770753
Short name T488
Test name
Test status
Simulation time 25497557 ps
CPU time 0.74 seconds
Started Jan 24 07:47:59 PM PST 24
Finished Jan 24 07:48:05 PM PST 24
Peak memory 215836 kb
Host smart-b3fb8afb-0300-4d59-aaff-8147e107289f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470770753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.470770753
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3470949689
Short name T1094
Test name
Test status
Simulation time 1625241186 ps
CPU time 7.37 seconds
Started Jan 24 08:10:57 PM PST 24
Finished Jan 24 08:11:05 PM PST 24
Peak memory 221628 kb
Host smart-234702d4-3658-4f49-938f-fb16493d07c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3470949689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3470949689
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2817644761
Short name T814
Test name
Test status
Simulation time 253492152079 ps
CPU time 460.11 seconds
Started Jan 24 07:48:17 PM PST 24
Finished Jan 24 07:56:02 PM PST 24
Peak memory 253528 kb
Host smart-d8460ff1-7756-4b93-a33c-b01d2f916326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817644761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2817644761
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3171411988
Short name T1085
Test name
Test status
Simulation time 3044168939 ps
CPU time 22.38 seconds
Started Jan 24 07:48:10 PM PST 24
Finished Jan 24 07:48:38 PM PST 24
Peak memory 218300 kb
Host smart-ab3c0078-7ac8-4a9e-bf90-7fc4215f4890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171411988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3171411988
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.738944997
Short name T294
Test name
Test status
Simulation time 8426851177 ps
CPU time 22.84 seconds
Started Jan 24 07:47:59 PM PST 24
Finished Jan 24 07:48:27 PM PST 24
Peak memory 216004 kb
Host smart-90eb278c-f8ab-47a8-8e61-043aa15bb7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738944997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.738944997
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.773969332
Short name T812
Test name
Test status
Simulation time 1028264528 ps
CPU time 4.09 seconds
Started Jan 24 07:48:12 PM PST 24
Finished Jan 24 07:48:21 PM PST 24
Peak memory 216280 kb
Host smart-4a655597-9a93-4ada-a74f-904b27f7eb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773969332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.773969332
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.700502185
Short name T874
Test name
Test status
Simulation time 36283024 ps
CPU time 0.89 seconds
Started Jan 24 07:48:10 PM PST 24
Finished Jan 24 07:48:17 PM PST 24
Peak memory 204596 kb
Host smart-83c12a69-0274-4629-bf95-183bd6412633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700502185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.700502185
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2998787217
Short name T656
Test name
Test status
Simulation time 1908185780 ps
CPU time 9.61 seconds
Started Jan 24 07:48:10 PM PST 24
Finished Jan 24 07:48:25 PM PST 24
Peak memory 217264 kb
Host smart-21fd0017-09f1-4961-bfa8-3dd1b5757dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998787217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2998787217
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.533161886
Short name T769
Test name
Test status
Simulation time 38673927 ps
CPU time 0.73 seconds
Started Jan 24 07:48:27 PM PST 24
Finished Jan 24 07:48:28 PM PST 24
Peak memory 204464 kb
Host smart-cc088bc2-ee0d-474d-a7a4-07f2289087fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533161886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.533161886
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3657324032
Short name T870
Test name
Test status
Simulation time 300412889 ps
CPU time 4.3 seconds
Started Jan 24 07:48:26 PM PST 24
Finished Jan 24 07:48:32 PM PST 24
Peak memory 218288 kb
Host smart-ab64f258-7d2b-45ea-947b-19c1700d2505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657324032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3657324032
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.882880460
Short name T674
Test name
Test status
Simulation time 43606079 ps
CPU time 0.76 seconds
Started Jan 24 07:48:19 PM PST 24
Finished Jan 24 07:48:25 PM PST 24
Peak memory 204240 kb
Host smart-e5c0da41-b3a7-4ba2-91a2-64f10969be6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882880460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.882880460
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2186877803
Short name T1025
Test name
Test status
Simulation time 231102320 ps
CPU time 6.21 seconds
Started Jan 24 07:48:23 PM PST 24
Finished Jan 24 07:48:32 PM PST 24
Peak memory 233388 kb
Host smart-6404340a-5be2-4800-9bd6-b6e0ccd08a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186877803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2186877803
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3448349239
Short name T954
Test name
Test status
Simulation time 8505441019 ps
CPU time 7.28 seconds
Started Jan 24 07:48:23 PM PST 24
Finished Jan 24 07:48:33 PM PST 24
Peak memory 217324 kb
Host smart-8d16ae84-230b-4ed3-a30a-0c7db1a15122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448349239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3448349239
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.4242150533
Short name T174
Test name
Test status
Simulation time 1246143654 ps
CPU time 4.33 seconds
Started Jan 24 07:48:23 PM PST 24
Finished Jan 24 07:48:30 PM PST 24
Peak memory 223348 kb
Host smart-c60d2c5a-9a1f-4cba-b0a0-a57bb48bd036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242150533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4242150533
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3791921509
Short name T1051
Test name
Test status
Simulation time 25185306 ps
CPU time 1.04 seconds
Started Jan 24 08:10:01 PM PST 24
Finished Jan 24 08:10:06 PM PST 24
Peak memory 217028 kb
Host smart-c9681004-a441-4a60-a580-8ac7d2573891
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791921509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3791921509
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1907688224
Short name T932
Test name
Test status
Simulation time 469297893 ps
CPU time 6.4 seconds
Started Jan 24 07:48:26 PM PST 24
Finished Jan 24 07:48:34 PM PST 24
Peak memory 217216 kb
Host smart-b1b56a25-5ffa-487e-829a-6aaf4d7c02ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907688224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1907688224
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.4200281772
Short name T783
Test name
Test status
Simulation time 1670292349 ps
CPU time 4.51 seconds
Started Jan 24 09:29:13 PM PST 24
Finished Jan 24 09:29:20 PM PST 24
Peak memory 216180 kb
Host smart-30819dfc-e6b6-4419-8aba-38accfcbe9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200281772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.4200281772
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3079052782
Short name T430
Test name
Test status
Simulation time 3609121763 ps
CPU time 5.96 seconds
Started Jan 24 07:48:22 PM PST 24
Finished Jan 24 07:48:31 PM PST 24
Peak memory 221944 kb
Host smart-503198bb-2f79-4fdb-b03d-e987a70afead
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3079052782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3079052782
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2850454148
Short name T544
Test name
Test status
Simulation time 9399873611 ps
CPU time 27.91 seconds
Started Jan 24 07:48:15 PM PST 24
Finished Jan 24 07:48:45 PM PST 24
Peak memory 216040 kb
Host smart-eb09a2b3-62db-4577-b3c1-556360405f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850454148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2850454148
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.4257299080
Short name T664
Test name
Test status
Simulation time 4647247537 ps
CPU time 13.77 seconds
Started Jan 24 07:48:13 PM PST 24
Finished Jan 24 07:48:31 PM PST 24
Peak memory 216044 kb
Host smart-700488fa-7c0a-439c-aa6b-0d87a721a6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257299080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.4257299080
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1732344296
Short name T19
Test name
Test status
Simulation time 118014210 ps
CPU time 2.07 seconds
Started Jan 24 07:48:24 PM PST 24
Finished Jan 24 07:48:29 PM PST 24
Peak memory 208120 kb
Host smart-64b5b301-8668-41af-8105-91fca3f8f8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732344296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1732344296
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1582665627
Short name T773
Test name
Test status
Simulation time 71699886 ps
CPU time 0.89 seconds
Started Jan 24 07:48:21 PM PST 24
Finished Jan 24 07:48:25 PM PST 24
Peak memory 205632 kb
Host smart-d837c908-0afe-4c63-a9da-125f87fd32e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582665627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1582665627
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2720495765
Short name T776
Test name
Test status
Simulation time 3686687921 ps
CPU time 8.83 seconds
Started Jan 24 07:48:22 PM PST 24
Finished Jan 24 07:48:34 PM PST 24
Peak memory 233116 kb
Host smart-ab59b282-de0f-4556-96d0-cbd8d19b3a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720495765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2720495765
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1471912655
Short name T1016
Test name
Test status
Simulation time 39476242 ps
CPU time 0.69 seconds
Started Jan 24 07:48:38 PM PST 24
Finished Jan 24 07:48:39 PM PST 24
Peak memory 204400 kb
Host smart-f45acfa8-3ad8-4fb1-89ff-a589ffb23324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471912655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1471912655
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3644449075
Short name T833
Test name
Test status
Simulation time 234644131 ps
CPU time 4.56 seconds
Started Jan 24 07:48:43 PM PST 24
Finished Jan 24 07:48:49 PM PST 24
Peak memory 232316 kb
Host smart-7e33a44a-043c-4ba4-8d9b-c3efe7e3f8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644449075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3644449075
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3611193301
Short name T21
Test name
Test status
Simulation time 112484981 ps
CPU time 0.78 seconds
Started Jan 24 07:48:21 PM PST 24
Finished Jan 24 07:48:25 PM PST 24
Peak memory 205596 kb
Host smart-f2e52666-5454-407a-be08-53ef122c55ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611193301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3611193301
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2475266752
Short name T1026
Test name
Test status
Simulation time 26032366306 ps
CPU time 163.44 seconds
Started Jan 24 07:48:34 PM PST 24
Finished Jan 24 07:51:18 PM PST 24
Peak memory 265248 kb
Host smart-1a25b1ad-4ed1-46d0-8144-ffee52014c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475266752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2475266752
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1194658361
Short name T278
Test name
Test status
Simulation time 42210078797 ps
CPU time 121.52 seconds
Started Jan 24 07:48:44 PM PST 24
Finished Jan 24 07:50:46 PM PST 24
Peak memory 265344 kb
Host smart-7d34937d-898e-420a-bbfa-3d6fad8f163e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194658361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1194658361
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.745081374
Short name T27
Test name
Test status
Simulation time 4302030300 ps
CPU time 78.35 seconds
Started Jan 24 07:48:38 PM PST 24
Finished Jan 24 07:49:57 PM PST 24
Peak memory 249488 kb
Host smart-0b2c40d9-2508-45ea-bf96-de4d391fbd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745081374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.745081374
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3086831874
Short name T551
Test name
Test status
Simulation time 20120640958 ps
CPU time 14.41 seconds
Started Jan 24 07:48:36 PM PST 24
Finished Jan 24 07:48:51 PM PST 24
Peak memory 232372 kb
Host smart-f9bc10a4-d8fd-4cc2-8945-7e8ed4b5b549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086831874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3086831874
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2275306456
Short name T168
Test name
Test status
Simulation time 2007383867 ps
CPU time 8.78 seconds
Started Jan 24 07:48:36 PM PST 24
Finished Jan 24 07:48:46 PM PST 24
Peak memory 217276 kb
Host smart-43467fbd-62eb-4166-bff2-34304690a24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275306456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2275306456
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2205753669
Short name T202
Test name
Test status
Simulation time 1508893284 ps
CPU time 9.99 seconds
Started Jan 24 07:48:40 PM PST 24
Finished Jan 24 07:48:51 PM PST 24
Peak memory 239772 kb
Host smart-35952b6e-4e6c-4e95-9340-0c7a32ffa91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205753669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2205753669
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.469915824
Short name T913
Test name
Test status
Simulation time 59086918 ps
CPU time 1.09 seconds
Started Jan 24 07:48:43 PM PST 24
Finished Jan 24 07:48:45 PM PST 24
Peak memory 215768 kb
Host smart-0408f76e-8b53-4e18-be27-fb0e0bfaf6b6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469915824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.469915824
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2716350062
Short name T987
Test name
Test status
Simulation time 2295446818 ps
CPU time 11.18 seconds
Started Jan 24 07:48:40 PM PST 24
Finished Jan 24 07:48:53 PM PST 24
Peak memory 232460 kb
Host smart-a4b6eb11-4e46-4daf-8f50-a28c09baa926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716350062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2716350062
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1168354378
Short name T171
Test name
Test status
Simulation time 3763015212 ps
CPU time 15.77 seconds
Started Jan 24 07:48:30 PM PST 24
Finished Jan 24 07:48:47 PM PST 24
Peak memory 224284 kb
Host smart-432e40ab-94eb-40a5-a0ea-7f56542d0436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168354378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1168354378
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.3147818010
Short name T539
Test name
Test status
Simulation time 112947382 ps
CPU time 0.73 seconds
Started Jan 24 07:48:36 PM PST 24
Finished Jan 24 07:48:38 PM PST 24
Peak memory 215908 kb
Host smart-e3e486e4-6d7b-4852-8c87-23dcc508e68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147818010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.3147818010
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3322601821
Short name T1027
Test name
Test status
Simulation time 1517786658 ps
CPU time 6.92 seconds
Started Jan 24 07:48:40 PM PST 24
Finished Jan 24 07:48:48 PM PST 24
Peak memory 221176 kb
Host smart-47126f63-f8ac-4817-9d2b-359fb9acaf73
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3322601821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3322601821
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3042811542
Short name T263
Test name
Test status
Simulation time 88682833507 ps
CPU time 367.67 seconds
Started Jan 24 07:48:35 PM PST 24
Finished Jan 24 07:54:44 PM PST 24
Peak memory 267540 kb
Host smart-68ccdee9-bfdf-4e05-a6f8-641293a7d977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042811542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3042811542
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1478526016
Short name T820
Test name
Test status
Simulation time 7814582216 ps
CPU time 34.46 seconds
Started Jan 24 07:48:43 PM PST 24
Finished Jan 24 07:49:18 PM PST 24
Peak memory 218632 kb
Host smart-944a892e-4419-4c95-b606-63f92d055325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478526016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1478526016
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2893456519
Short name T534
Test name
Test status
Simulation time 9948483071 ps
CPU time 5.32 seconds
Started Jan 24 07:48:38 PM PST 24
Finished Jan 24 07:48:44 PM PST 24
Peak memory 215972 kb
Host smart-bc8b1791-491a-4181-b9d6-777230b9fa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893456519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2893456519
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3848450701
Short name T658
Test name
Test status
Simulation time 68586799 ps
CPU time 1.44 seconds
Started Jan 24 07:48:29 PM PST 24
Finished Jan 24 07:48:32 PM PST 24
Peak memory 207680 kb
Host smart-e80e4184-4b9d-4a4f-9b8c-259390480eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848450701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3848450701
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.929948987
Short name T722
Test name
Test status
Simulation time 133529445 ps
CPU time 0.79 seconds
Started Jan 24 07:48:35 PM PST 24
Finished Jan 24 07:48:36 PM PST 24
Peak memory 204576 kb
Host smart-f3250d53-f776-4d86-91fa-ed0cb946da34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929948987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.929948987
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2880865738
Short name T695
Test name
Test status
Simulation time 7411711284 ps
CPU time 16.27 seconds
Started Jan 24 07:48:38 PM PST 24
Finished Jan 24 07:48:55 PM PST 24
Peak memory 223844 kb
Host smart-3bdf5139-09e8-4239-b148-6b03bd6c9f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880865738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2880865738
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2731247624
Short name T950
Test name
Test status
Simulation time 92238107 ps
CPU time 0.76 seconds
Started Jan 24 07:49:07 PM PST 24
Finished Jan 24 07:49:09 PM PST 24
Peak memory 204452 kb
Host smart-c88f9806-6bd5-45e5-ae9c-cfdf634937c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731247624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2731247624
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3980510284
Short name T845
Test name
Test status
Simulation time 206780128 ps
CPU time 2.53 seconds
Started Jan 24 07:48:58 PM PST 24
Finished Jan 24 07:49:03 PM PST 24
Peak memory 216384 kb
Host smart-05831932-bdb5-4204-9599-169b74689f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980510284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3980510284
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1750105835
Short name T1045
Test name
Test status
Simulation time 47983594 ps
CPU time 0.76 seconds
Started Jan 24 07:48:37 PM PST 24
Finished Jan 24 07:48:39 PM PST 24
Peak memory 205620 kb
Host smart-7b2f096a-23a0-481f-b636-32c1ec1f0ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750105835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1750105835
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2762651857
Short name T566
Test name
Test status
Simulation time 1276697687 ps
CPU time 4.37 seconds
Started Jan 24 07:48:53 PM PST 24
Finished Jan 24 07:49:02 PM PST 24
Peak memory 224196 kb
Host smart-4ba3799a-a89f-4c22-85ff-6682815b6cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762651857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2762651857
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2308892737
Short name T122
Test name
Test status
Simulation time 17976920941 ps
CPU time 128.74 seconds
Started Jan 24 07:48:58 PM PST 24
Finished Jan 24 07:51:09 PM PST 24
Peak memory 273040 kb
Host smart-cb2db0e2-6217-4085-b5f9-28f0fb18d689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308892737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2308892737
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.4260350415
Short name T609
Test name
Test status
Simulation time 436143370 ps
CPU time 13.56 seconds
Started Jan 24 08:25:05 PM PST 24
Finished Jan 24 08:25:22 PM PST 24
Peak memory 232976 kb
Host smart-761687b4-77b2-44dc-b29e-653eb59e8938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260350415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4260350415
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1987376663
Short name T1022
Test name
Test status
Simulation time 54040406 ps
CPU time 2.61 seconds
Started Jan 24 07:48:54 PM PST 24
Finished Jan 24 07:49:02 PM PST 24
Peak memory 232408 kb
Host smart-15aa6c20-341f-4ee2-895f-82e1fee844e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987376663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1987376663
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.4112791067
Short name T491
Test name
Test status
Simulation time 9787113044 ps
CPU time 28.08 seconds
Started Jan 24 11:20:00 PM PST 24
Finished Jan 24 11:20:30 PM PST 24
Peak memory 237636 kb
Host smart-437296c1-6b2d-424a-994e-a847313f0ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112791067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.4112791067
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3936558049
Short name T1034
Test name
Test status
Simulation time 54195615 ps
CPU time 0.98 seconds
Started Jan 24 07:48:43 PM PST 24
Finished Jan 24 07:48:45 PM PST 24
Peak memory 215788 kb
Host smart-943879c3-9aff-491a-892e-a3b78abcf2da
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936558049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3936558049
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.730820355
Short name T187
Test name
Test status
Simulation time 2745068413 ps
CPU time 10.66 seconds
Started Jan 24 07:55:58 PM PST 24
Finished Jan 24 07:56:10 PM PST 24
Peak memory 228972 kb
Host smart-d6463aaf-743c-442a-ab4e-0c1f99be49cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730820355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.730820355
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.4272365318
Short name T639
Test name
Test status
Simulation time 145209655 ps
CPU time 2.25 seconds
Started Jan 24 07:48:58 PM PST 24
Finished Jan 24 07:49:03 PM PST 24
Peak memory 215940 kb
Host smart-de379ea3-f28c-4af6-a01f-3a61b8b1c42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272365318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.4272365318
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.4201289961
Short name T703
Test name
Test status
Simulation time 19326153 ps
CPU time 0.74 seconds
Started Jan 24 07:48:43 PM PST 24
Finished Jan 24 07:48:45 PM PST 24
Peak memory 215880 kb
Host smart-4543102d-ddae-4f2b-868d-7500ab0a51eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201289961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.4201289961
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3821185631
Short name T303
Test name
Test status
Simulation time 211708176 ps
CPU time 3.14 seconds
Started Jan 24 07:48:58 PM PST 24
Finished Jan 24 07:49:04 PM PST 24
Peak memory 216068 kb
Host smart-bc45311b-f72c-453a-9cd2-104ceb8d6516
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3821185631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3821185631
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1199329907
Short name T762
Test name
Test status
Simulation time 189241735 ps
CPU time 4.4 seconds
Started Jan 24 07:48:43 PM PST 24
Finished Jan 24 07:48:48 PM PST 24
Peak memory 216308 kb
Host smart-b58b7923-0ef4-4bff-8d1e-b2229711acb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199329907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1199329907
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.844487301
Short name T718
Test name
Test status
Simulation time 79860776397 ps
CPU time 17.21 seconds
Started Jan 24 07:48:45 PM PST 24
Finished Jan 24 07:49:03 PM PST 24
Peak memory 216056 kb
Host smart-f05b054e-61c0-46f1-af66-cd312eb59bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844487301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.844487301
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1509190874
Short name T1049
Test name
Test status
Simulation time 19531372 ps
CPU time 0.81 seconds
Started Jan 24 07:48:54 PM PST 24
Finished Jan 24 07:49:00 PM PST 24
Peak memory 204592 kb
Host smart-8cab962a-780c-4fc2-a445-7e17c99e363b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509190874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1509190874
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3800912405
Short name T955
Test name
Test status
Simulation time 120999893 ps
CPU time 1.04 seconds
Started Jan 24 07:48:56 PM PST 24
Finished Jan 24 07:49:01 PM PST 24
Peak memory 205572 kb
Host smart-4e37118d-7b74-46d1-bf04-f6e3da4d8f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800912405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3800912405
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2121418638
Short name T997
Test name
Test status
Simulation time 1123104702 ps
CPU time 5.69 seconds
Started Jan 24 09:01:39 PM PST 24
Finished Jan 24 09:01:45 PM PST 24
Peak memory 233148 kb
Host smart-f1d04bab-7b76-4178-a96a-4498568bb174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121418638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2121418638
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1260636812
Short name T290
Test name
Test status
Simulation time 43986204 ps
CPU time 0.7 seconds
Started Jan 24 07:49:18 PM PST 24
Finished Jan 24 07:49:20 PM PST 24
Peak memory 204104 kb
Host smart-00e275e7-a673-4dc2-926d-a5b1701148ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260636812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1260636812
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.287461689
Short name T246
Test name
Test status
Simulation time 4174970595 ps
CPU time 5.96 seconds
Started Jan 24 07:49:16 PM PST 24
Finished Jan 24 07:49:24 PM PST 24
Peak memory 232572 kb
Host smart-0769642a-b1b7-4523-bd4a-e953fc413550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287461689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.287461689
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.875011022
Short name T753
Test name
Test status
Simulation time 33016438 ps
CPU time 0.75 seconds
Started Jan 24 07:49:00 PM PST 24
Finished Jan 24 07:49:06 PM PST 24
Peak memory 204276 kb
Host smart-d078e431-4e0a-4e77-a889-b81f7a602789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875011022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.875011022
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3400355169
Short name T206
Test name
Test status
Simulation time 13623637966 ps
CPU time 117.71 seconds
Started Jan 24 07:49:17 PM PST 24
Finished Jan 24 07:51:17 PM PST 24
Peak memory 271224 kb
Host smart-12bf4038-b62b-4222-87dd-47a352dfc428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400355169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3400355169
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2088090736
Short name T69
Test name
Test status
Simulation time 9901837887 ps
CPU time 73.23 seconds
Started Jan 24 07:49:16 PM PST 24
Finished Jan 24 07:50:31 PM PST 24
Peak memory 249424 kb
Host smart-0fcd0180-489a-4727-ac6d-74d03ad95a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088090736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2088090736
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1061929961
Short name T151
Test name
Test status
Simulation time 254743384951 ps
CPU time 966.56 seconds
Started Jan 24 09:15:36 PM PST 24
Finished Jan 24 09:31:43 PM PST 24
Peak memory 281432 kb
Host smart-87977a4a-fdc6-4173-aad4-f807f6d10f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061929961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1061929961
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3730426730
Short name T717
Test name
Test status
Simulation time 2575847841 ps
CPU time 6.01 seconds
Started Jan 24 07:49:08 PM PST 24
Finished Jan 24 07:49:15 PM PST 24
Peak memory 232884 kb
Host smart-379fecb5-734f-48b7-a402-4d21b476ff34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730426730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3730426730
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.986105948
Short name T948
Test name
Test status
Simulation time 44741337927 ps
CPU time 24 seconds
Started Jan 24 07:49:12 PM PST 24
Finished Jan 24 07:49:37 PM PST 24
Peak memory 234628 kb
Host smart-69887395-c4d9-4d53-adaf-b57c8a0bc47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986105948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.986105948
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.4030017608
Short name T971
Test name
Test status
Simulation time 18036079 ps
CPU time 1.01 seconds
Started Jan 24 07:49:09 PM PST 24
Finished Jan 24 07:49:11 PM PST 24
Peak memory 215756 kb
Host smart-799c088a-a3a3-4262-8cdd-d6d523c6925c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030017608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.4030017608
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3581654108
Short name T260
Test name
Test status
Simulation time 712954465 ps
CPU time 9.84 seconds
Started Jan 24 07:49:14 PM PST 24
Finished Jan 24 07:49:25 PM PST 24
Peak memory 230696 kb
Host smart-486d97e8-b9ba-4929-b662-d6f524aec6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581654108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3581654108
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.235042935
Short name T183
Test name
Test status
Simulation time 524180472 ps
CPU time 8.02 seconds
Started Jan 24 07:49:08 PM PST 24
Finished Jan 24 07:49:17 PM PST 24
Peak memory 240092 kb
Host smart-96875478-2f69-49ca-a37c-50d5147bab6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235042935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.235042935
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.2902089226
Short name T747
Test name
Test status
Simulation time 16028887 ps
CPU time 0.74 seconds
Started Jan 24 07:49:09 PM PST 24
Finished Jan 24 07:49:11 PM PST 24
Peak memory 215844 kb
Host smart-19a5b54b-a5e1-45c0-8b6f-bc62e803707b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902089226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.2902089226
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3746410232
Short name T739
Test name
Test status
Simulation time 1729701874 ps
CPU time 5.42 seconds
Started Jan 24 07:49:13 PM PST 24
Finished Jan 24 07:49:20 PM PST 24
Peak memory 221688 kb
Host smart-ae2ea4f7-d7f9-4ecc-a872-87f3258b57d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3746410232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3746410232
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.4286678108
Short name T178
Test name
Test status
Simulation time 18606906299 ps
CPU time 262.95 seconds
Started Jan 24 07:49:16 PM PST 24
Finished Jan 24 07:53:40 PM PST 24
Peak memory 272368 kb
Host smart-b254458f-f49c-41bc-86c6-dd74bbf029cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286678108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.4286678108
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1963821522
Short name T653
Test name
Test status
Simulation time 6340234620 ps
CPU time 33.14 seconds
Started Jan 24 07:48:58 PM PST 24
Finished Jan 24 07:49:33 PM PST 24
Peak memory 216064 kb
Host smart-341843dd-dda7-4d37-82e2-8bb0ffa0499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963821522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1963821522
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3076610472
Short name T41
Test name
Test status
Simulation time 1950675097 ps
CPU time 4.9 seconds
Started Jan 24 07:49:09 PM PST 24
Finished Jan 24 07:49:15 PM PST 24
Peak memory 207380 kb
Host smart-163705ff-98f9-4ef5-b398-017dc2622d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076610472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3076610472
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.719165757
Short name T659
Test name
Test status
Simulation time 103199712 ps
CPU time 2.24 seconds
Started Jan 24 07:49:11 PM PST 24
Finished Jan 24 07:49:14 PM PST 24
Peak memory 208092 kb
Host smart-179a1adf-4d12-4e95-bedd-d5f7f0c0f423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719165757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.719165757
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2811104778
Short name T465
Test name
Test status
Simulation time 69999319 ps
CPU time 0.78 seconds
Started Jan 24 07:48:59 PM PST 24
Finished Jan 24 07:49:06 PM PST 24
Peak memory 204604 kb
Host smart-c2dc50a2-6f30-4a60-86bc-5e344a44fe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811104778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2811104778
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.29752343
Short name T215
Test name
Test status
Simulation time 5343996006 ps
CPU time 19.2 seconds
Started Jan 24 07:49:15 PM PST 24
Finished Jan 24 07:49:36 PM PST 24
Peak memory 228480 kb
Host smart-dd79a737-0f52-4125-9e42-bfc1b9084f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29752343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.29752343
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.226900541
Short name T557
Test name
Test status
Simulation time 17601956 ps
CPU time 0.67 seconds
Started Jan 24 07:49:30 PM PST 24
Finished Jan 24 07:49:32 PM PST 24
Peak memory 203564 kb
Host smart-8586b957-81a1-42b1-afdc-f3bdfcfebbc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226900541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.226900541
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2905264735
Short name T633
Test name
Test status
Simulation time 4202295643 ps
CPU time 5.49 seconds
Started Jan 24 07:49:24 PM PST 24
Finished Jan 24 07:49:30 PM PST 24
Peak memory 218808 kb
Host smart-529eba91-737b-47a1-a93b-bbb962b0588f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905264735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2905264735
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.4088040823
Short name T458
Test name
Test status
Simulation time 73332488 ps
CPU time 0.76 seconds
Started Jan 24 07:49:16 PM PST 24
Finished Jan 24 07:49:18 PM PST 24
Peak memory 205236 kb
Host smart-36e3295e-17f0-4e98-9091-f527162efcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088040823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.4088040823
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1931595366
Short name T496
Test name
Test status
Simulation time 11673317748 ps
CPU time 40.07 seconds
Started Jan 24 07:49:33 PM PST 24
Finished Jan 24 07:50:14 PM PST 24
Peak memory 250988 kb
Host smart-0a27a3a1-5ba0-4a9d-a659-e33be351c14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931595366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1931595366
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1518808942
Short name T850
Test name
Test status
Simulation time 2747443506 ps
CPU time 48.81 seconds
Started Jan 24 09:09:43 PM PST 24
Finished Jan 24 09:10:33 PM PST 24
Peak memory 251724 kb
Host smart-99fef742-ae02-4f8c-9c9a-3cadfecd282a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518808942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1518808942
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1268670193
Short name T283
Test name
Test status
Simulation time 53926144402 ps
CPU time 43.92 seconds
Started Jan 24 07:49:26 PM PST 24
Finished Jan 24 07:50:11 PM PST 24
Peak memory 248848 kb
Host smart-454bff89-1de9-4755-9fae-c3e443650861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268670193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1268670193
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.117447587
Short name T614
Test name
Test status
Simulation time 562518592 ps
CPU time 4.93 seconds
Started Jan 24 07:49:32 PM PST 24
Finished Jan 24 07:49:38 PM PST 24
Peak memory 217552 kb
Host smart-59310fc6-b69f-4440-b972-7d6eacd7ca6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117447587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.117447587
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.802994214
Short name T946
Test name
Test status
Simulation time 63004903326 ps
CPU time 9.73 seconds
Started Jan 24 07:49:26 PM PST 24
Finished Jan 24 07:49:37 PM PST 24
Peak memory 216548 kb
Host smart-85092457-24c9-4647-9b40-0e493888c83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802994214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.802994214
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2912059054
Short name T672
Test name
Test status
Simulation time 94623694 ps
CPU time 1.01 seconds
Started Jan 24 07:49:19 PM PST 24
Finished Jan 24 07:49:22 PM PST 24
Peak memory 216996 kb
Host smart-81f47fc0-ec30-45d8-94ed-c6f8a0841e1c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912059054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2912059054
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3697881625
Short name T782
Test name
Test status
Simulation time 5234762095 ps
CPU time 6.06 seconds
Started Jan 24 09:30:22 PM PST 24
Finished Jan 24 09:30:29 PM PST 24
Peak memory 236132 kb
Host smart-01b66e27-7cc7-415e-b2d1-77d47d9c383b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697881625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3697881625
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1973015646
Short name T805
Test name
Test status
Simulation time 367440925 ps
CPU time 4.07 seconds
Started Jan 24 07:49:14 PM PST 24
Finished Jan 24 07:49:20 PM PST 24
Peak memory 216092 kb
Host smart-6dd63e96-0792-463a-a585-6d7b527bc3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973015646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1973015646
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.3419658370
Short name T47
Test name
Test status
Simulation time 14816231 ps
CPU time 0.77 seconds
Started Jan 24 11:43:47 PM PST 24
Finished Jan 24 11:43:52 PM PST 24
Peak memory 215888 kb
Host smart-25e31c6e-02f2-4100-9f33-763ac3fb5b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419658370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.3419658370
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3597644529
Short name T68
Test name
Test status
Simulation time 5819470983 ps
CPU time 5.22 seconds
Started Jan 24 07:49:31 PM PST 24
Finished Jan 24 07:49:37 PM PST 24
Peak memory 221500 kb
Host smart-5b90af9b-eba0-420a-b795-cc86748e9b22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3597644529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3597644529
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1035147207
Short name T208
Test name
Test status
Simulation time 7200424942 ps
CPU time 48.63 seconds
Started Jan 24 08:15:50 PM PST 24
Finished Jan 24 08:16:39 PM PST 24
Peak memory 251848 kb
Host smart-c5ad0cb5-90f6-4f63-a61d-7b013e2dc2e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035147207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1035147207
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2014028544
Short name T438
Test name
Test status
Simulation time 1453202243 ps
CPU time 19.82 seconds
Started Jan 24 07:49:16 PM PST 24
Finished Jan 24 07:49:37 PM PST 24
Peak memory 216256 kb
Host smart-269cceb5-b262-4c50-9ef4-ca0fabd042a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014028544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2014028544
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2386941159
Short name T1008
Test name
Test status
Simulation time 2682005836 ps
CPU time 15.24 seconds
Started Jan 24 07:49:15 PM PST 24
Finished Jan 24 07:49:32 PM PST 24
Peak memory 215980 kb
Host smart-78ca4d37-0d92-44b4-bf6d-9807fc3f7d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386941159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2386941159
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2428923029
Short name T479
Test name
Test status
Simulation time 387299095 ps
CPU time 6.46 seconds
Started Jan 24 08:00:38 PM PST 24
Finished Jan 24 08:00:46 PM PST 24
Peak memory 217256 kb
Host smart-11cea5fe-218e-4f91-b2b2-76230ea51231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428923029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2428923029
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4272057705
Short name T427
Test name
Test status
Simulation time 68361202 ps
CPU time 0.83 seconds
Started Jan 24 07:49:15 PM PST 24
Finished Jan 24 07:49:18 PM PST 24
Peak memory 204640 kb
Host smart-2712da2d-866f-4b1b-9a45-d6d225f40e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272057705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4272057705
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1127210654
Short name T243
Test name
Test status
Simulation time 254249358 ps
CPU time 4.26 seconds
Started Jan 24 07:49:27 PM PST 24
Finished Jan 24 07:49:32 PM PST 24
Peak memory 222400 kb
Host smart-2bcf98f0-dbf1-488c-8133-3b1b16e85ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127210654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1127210654
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2835214681
Short name T425
Test name
Test status
Simulation time 17003830 ps
CPU time 0.7 seconds
Started Jan 24 07:49:41 PM PST 24
Finished Jan 24 07:49:42 PM PST 24
Peak memory 204116 kb
Host smart-6084f244-60d4-47fa-b760-659db54971f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835214681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2835214681
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3779222956
Short name T210
Test name
Test status
Simulation time 188956915 ps
CPU time 3.77 seconds
Started Jan 24 07:49:46 PM PST 24
Finished Jan 24 07:49:50 PM PST 24
Peak memory 233336 kb
Host smart-cfc4ee58-fc2c-4241-ac01-c8d201d5a5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779222956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3779222956
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2960991550
Short name T616
Test name
Test status
Simulation time 33858126 ps
CPU time 0.8 seconds
Started Jan 24 07:49:35 PM PST 24
Finished Jan 24 07:49:38 PM PST 24
Peak memory 205300 kb
Host smart-6390fbda-7365-4f81-9760-6147a513cb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960991550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2960991550
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.765567289
Short name T255
Test name
Test status
Simulation time 163382938631 ps
CPU time 231.64 seconds
Started Jan 24 07:49:46 PM PST 24
Finished Jan 24 07:53:38 PM PST 24
Peak memory 266360 kb
Host smart-1c528b85-adeb-41d5-9293-ff8974db6d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765567289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.765567289
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1252391187
Short name T634
Test name
Test status
Simulation time 143658509868 ps
CPU time 271.4 seconds
Started Jan 24 07:49:42 PM PST 24
Finished Jan 24 07:54:14 PM PST 24
Peak memory 249924 kb
Host smart-64bed47a-a6b1-4750-bf9f-014a79185a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252391187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1252391187
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_intercept.4024728013
Short name T1054
Test name
Test status
Simulation time 6993297278 ps
CPU time 8.09 seconds
Started Jan 24 07:49:34 PM PST 24
Finished Jan 24 07:49:44 PM PST 24
Peak memory 219056 kb
Host smart-7f19350b-5204-4724-b35c-1d31c3d1cc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024728013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.4024728013
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3428149794
Short name T815
Test name
Test status
Simulation time 980932457 ps
CPU time 9.31 seconds
Started Jan 24 07:49:31 PM PST 24
Finished Jan 24 07:49:42 PM PST 24
Peak memory 221592 kb
Host smart-2c4718dd-0a32-4a25-ab25-ae794bc37536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428149794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3428149794
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1180150162
Short name T24
Test name
Test status
Simulation time 16275048 ps
CPU time 1.04 seconds
Started Jan 24 07:49:34 PM PST 24
Finished Jan 24 07:49:36 PM PST 24
Peak memory 216996 kb
Host smart-0b7a52eb-7ef5-4e0f-bc3d-aa68ef1d46e0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180150162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1180150162
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3172451673
Short name T460
Test name
Test status
Simulation time 565295222 ps
CPU time 4.2 seconds
Started Jan 24 07:49:40 PM PST 24
Finished Jan 24 07:49:45 PM PST 24
Peak memory 232416 kb
Host smart-4cdff2bc-350d-44b4-9896-bcd66f75ef92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172451673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3172451673
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1728878289
Short name T799
Test name
Test status
Simulation time 10236233912 ps
CPU time 17.23 seconds
Started Jan 24 07:49:34 PM PST 24
Finished Jan 24 07:49:52 PM PST 24
Peak memory 218316 kb
Host smart-f4b27289-c06f-45e6-9d73-cd7ee47fb133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728878289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1728878289
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.748656284
Short name T1080
Test name
Test status
Simulation time 63526878 ps
CPU time 0.74 seconds
Started Jan 24 07:49:35 PM PST 24
Finished Jan 24 07:49:38 PM PST 24
Peak memory 215896 kb
Host smart-37e6c924-d207-455a-86f1-178d3c94e89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748656284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.748656284
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3988615112
Short name T485
Test name
Test status
Simulation time 1398042260 ps
CPU time 4.16 seconds
Started Jan 24 07:49:45 PM PST 24
Finished Jan 24 07:49:50 PM PST 24
Peak memory 220636 kb
Host smart-d07297f7-20e9-4c34-9015-b126d5a79d41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3988615112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3988615112
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1524194978
Short name T888
Test name
Test status
Simulation time 198739461 ps
CPU time 1.08 seconds
Started Jan 24 07:49:43 PM PST 24
Finished Jan 24 07:49:45 PM PST 24
Peak memory 205684 kb
Host smart-3006563b-ee4e-4b5b-893b-8205c81efef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524194978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1524194978
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2140984550
Short name T463
Test name
Test status
Simulation time 7354861665 ps
CPU time 10.38 seconds
Started Jan 24 07:49:35 PM PST 24
Finished Jan 24 07:49:48 PM PST 24
Peak memory 218236 kb
Host smart-b0f7bc08-1863-46e1-a187-7c0614186f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140984550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2140984550
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2717654560
Short name T1020
Test name
Test status
Simulation time 1300656181 ps
CPU time 7.96 seconds
Started Jan 24 07:49:34 PM PST 24
Finished Jan 24 07:49:43 PM PST 24
Peak memory 207672 kb
Host smart-33fedfb3-e936-4bb6-8a24-09e08e828f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717654560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2717654560
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1706507111
Short name T763
Test name
Test status
Simulation time 81815374 ps
CPU time 2.97 seconds
Started Jan 24 07:49:34 PM PST 24
Finished Jan 24 07:49:38 PM PST 24
Peak memory 207880 kb
Host smart-5b5ad8d3-4984-4e16-9569-11d30bf97f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706507111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1706507111
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1476948106
Short name T556
Test name
Test status
Simulation time 26522251 ps
CPU time 0.78 seconds
Started Jan 24 07:49:36 PM PST 24
Finished Jan 24 07:49:39 PM PST 24
Peak memory 204608 kb
Host smart-773e9682-9cde-4333-9c3e-affb37799c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476948106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1476948106
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3713495535
Short name T1029
Test name
Test status
Simulation time 1215946218 ps
CPU time 4 seconds
Started Jan 24 07:49:32 PM PST 24
Finished Jan 24 07:49:37 PM PST 24
Peak memory 233000 kb
Host smart-9d03cf8c-b081-4b1e-b815-8da0a326cb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713495535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3713495535
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3734393803
Short name T829
Test name
Test status
Simulation time 13100803 ps
CPU time 0.78 seconds
Started Jan 24 07:50:07 PM PST 24
Finished Jan 24 07:50:09 PM PST 24
Peak memory 204140 kb
Host smart-8f0da9af-09f7-458a-b7eb-3dbfd2673a9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734393803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3734393803
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3795609812
Short name T222
Test name
Test status
Simulation time 1876412973 ps
CPU time 3.56 seconds
Started Jan 24 07:49:59 PM PST 24
Finished Jan 24 07:50:04 PM PST 24
Peak memory 232668 kb
Host smart-8e992690-1217-48fc-b4ee-39a00337c49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795609812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3795609812
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.708739587
Short name T1006
Test name
Test status
Simulation time 15937640 ps
CPU time 0.76 seconds
Started Jan 24 07:49:51 PM PST 24
Finished Jan 24 07:49:52 PM PST 24
Peak memory 204592 kb
Host smart-5dbf8d93-f5d8-42b3-bec6-03a539849b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708739587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.708739587
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1556147233
Short name T917
Test name
Test status
Simulation time 18122240581 ps
CPU time 53.38 seconds
Started Jan 24 07:50:02 PM PST 24
Finished Jan 24 07:50:57 PM PST 24
Peak memory 238332 kb
Host smart-e8b5ab25-b332-42ef-a9bf-e965268fd9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556147233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1556147233
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.453323486
Short name T927
Test name
Test status
Simulation time 3672318421 ps
CPU time 69.53 seconds
Started Jan 24 07:50:00 PM PST 24
Finished Jan 24 07:51:11 PM PST 24
Peak memory 262800 kb
Host smart-cdf76090-8318-418e-bc4b-9bfe46b9c373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453323486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.453323486
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1513930584
Short name T1057
Test name
Test status
Simulation time 6377597424 ps
CPU time 23.53 seconds
Started Jan 24 07:50:03 PM PST 24
Finished Jan 24 07:50:29 PM PST 24
Peak memory 248484 kb
Host smart-89e7c199-7a26-4ee2-ba51-85cff732ebf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513930584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1513930584
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2471992581
Short name T824
Test name
Test status
Simulation time 171506958 ps
CPU time 3.07 seconds
Started Jan 24 07:49:52 PM PST 24
Finished Jan 24 07:49:56 PM PST 24
Peak memory 216224 kb
Host smart-81b5d8a4-2be4-4423-8522-f67d471a1195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471992581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2471992581
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3218622756
Short name T574
Test name
Test status
Simulation time 1532477830 ps
CPU time 6.89 seconds
Started Jan 24 08:06:39 PM PST 24
Finished Jan 24 08:06:47 PM PST 24
Peak memory 223328 kb
Host smart-0a77e3f6-9d96-4ed9-908c-2b70ce69e086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218622756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3218622756
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3009894694
Short name T749
Test name
Test status
Simulation time 41587060 ps
CPU time 0.98 seconds
Started Jan 24 07:49:42 PM PST 24
Finished Jan 24 07:49:43 PM PST 24
Peak memory 217064 kb
Host smart-9ebd6a29-1484-41df-9f9d-c15a16d58567
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009894694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3009894694
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1082789067
Short name T1076
Test name
Test status
Simulation time 6945099336 ps
CPU time 19.72 seconds
Started Jan 24 07:49:52 PM PST 24
Finished Jan 24 07:50:13 PM PST 24
Peak memory 232296 kb
Host smart-13fb4fc0-08a7-464f-8dae-4a3736d87167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082789067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1082789067
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2013558584
Short name T548
Test name
Test status
Simulation time 10082150230 ps
CPU time 13.52 seconds
Started Jan 24 07:49:48 PM PST 24
Finished Jan 24 07:50:02 PM PST 24
Peak memory 222016 kb
Host smart-f847131e-5e76-4cbe-91c2-60c2a0ae62d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013558584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2013558584
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.2298251946
Short name T945
Test name
Test status
Simulation time 33333254 ps
CPU time 0.71 seconds
Started Jan 24 07:49:49 PM PST 24
Finished Jan 24 07:49:50 PM PST 24
Peak memory 215852 kb
Host smart-1f88e918-4fb1-4fe0-8249-19bd832ee86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298251946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.2298251946
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1274088032
Short name T567
Test name
Test status
Simulation time 350941678 ps
CPU time 3.31 seconds
Started Jan 24 07:49:58 PM PST 24
Finished Jan 24 07:50:03 PM PST 24
Peak memory 221840 kb
Host smart-16b190d0-98a9-4e02-b889-131472c3b8b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1274088032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1274088032
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3109376676
Short name T834
Test name
Test status
Simulation time 28323085544 ps
CPU time 61.43 seconds
Started Jan 24 07:49:51 PM PST 24
Finished Jan 24 07:50:53 PM PST 24
Peak memory 216244 kb
Host smart-44ef1a25-b72f-42e6-8da1-070a59337f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109376676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3109376676
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1713799311
Short name T64
Test name
Test status
Simulation time 2766615599 ps
CPU time 6.52 seconds
Started Jan 24 08:57:17 PM PST 24
Finished Jan 24 08:57:24 PM PST 24
Peak memory 207764 kb
Host smart-adf8c811-f01e-40dd-824e-a3ccece5a623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713799311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1713799311
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2742534864
Short name T517
Test name
Test status
Simulation time 226155252 ps
CPU time 3.19 seconds
Started Jan 24 08:53:03 PM PST 24
Finished Jan 24 08:53:06 PM PST 24
Peak memory 207776 kb
Host smart-976d4a73-c4ee-4c6c-99b2-8f2e740b30af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742534864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2742534864
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1106472741
Short name T764
Test name
Test status
Simulation time 25055369 ps
CPU time 0.82 seconds
Started Jan 24 07:49:52 PM PST 24
Finished Jan 24 07:49:54 PM PST 24
Peak memory 203880 kb
Host smart-dfe670e6-0b2e-49ab-bf11-dd306f001884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106472741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1106472741
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.439966172
Short name T698
Test name
Test status
Simulation time 338996484905 ps
CPU time 57.26 seconds
Started Jan 24 07:49:49 PM PST 24
Finished Jan 24 07:50:48 PM PST 24
Peak memory 237892 kb
Host smart-c1fb6629-12e6-47b7-98c0-f3404948589d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439966172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.439966172
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2003908488
Short name T637
Test name
Test status
Simulation time 29477512 ps
CPU time 0.78 seconds
Started Jan 24 07:50:13 PM PST 24
Finished Jan 24 07:50:15 PM PST 24
Peak memory 203564 kb
Host smart-ca532c86-90fc-441f-8d62-6b211cc12e12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003908488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2003908488
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.411867488
Short name T1055
Test name
Test status
Simulation time 5373989423 ps
CPU time 3.56 seconds
Started Jan 24 08:35:16 PM PST 24
Finished Jan 24 08:35:21 PM PST 24
Peak memory 232432 kb
Host smart-96222b15-5a4b-4ee0-9189-fa7209b7e095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411867488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.411867488
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.4270086973
Short name T706
Test name
Test status
Simulation time 64225851 ps
CPU time 0.89 seconds
Started Jan 24 07:50:04 PM PST 24
Finished Jan 24 07:50:07 PM PST 24
Peak memory 205284 kb
Host smart-0f9c9b2f-e83f-4b5b-a350-f2ec8e8a4f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270086973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4270086973
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1691175683
Short name T775
Test name
Test status
Simulation time 569768802376 ps
CPU time 151.02 seconds
Started Jan 24 07:50:16 PM PST 24
Finished Jan 24 07:52:48 PM PST 24
Peak memory 248848 kb
Host smart-a3bf2f95-fa3b-4d58-b977-405055acf63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691175683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1691175683
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2770962475
Short name T784
Test name
Test status
Simulation time 8831623973 ps
CPU time 40.45 seconds
Started Jan 24 07:50:13 PM PST 24
Finished Jan 24 07:50:55 PM PST 24
Peak memory 234056 kb
Host smart-01242b4b-5af7-4ed8-af3f-4bfee4f5681b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770962475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2770962475
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2022520108
Short name T195
Test name
Test status
Simulation time 5843051598 ps
CPU time 24.89 seconds
Started Jan 24 07:50:15 PM PST 24
Finished Jan 24 07:50:41 PM PST 24
Peak memory 250200 kb
Host smart-5cabac47-35df-4212-8d71-333a3b8240c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022520108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2022520108
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2944599799
Short name T587
Test name
Test status
Simulation time 249336823 ps
CPU time 10.55 seconds
Started Jan 24 07:50:19 PM PST 24
Finished Jan 24 07:50:31 PM PST 24
Peak memory 233208 kb
Host smart-9e30cba3-6af7-4388-b677-5e68100b1d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944599799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2944599799
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.264058448
Short name T863
Test name
Test status
Simulation time 23360061573 ps
CPU time 9.39 seconds
Started Jan 24 07:50:06 PM PST 24
Finished Jan 24 07:50:18 PM PST 24
Peak memory 218660 kb
Host smart-bd1809e0-4edd-4bc6-ab35-d62552269ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264058448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.264058448
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.4273582718
Short name T563
Test name
Test status
Simulation time 4469916464 ps
CPU time 9.59 seconds
Started Jan 24 07:50:03 PM PST 24
Finished Jan 24 07:50:15 PM PST 24
Peak memory 240604 kb
Host smart-8a19fc33-5d1b-476c-b3dd-2f7f830190f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273582718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.4273582718
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3252330656
Short name T809
Test name
Test status
Simulation time 31182559 ps
CPU time 1.03 seconds
Started Jan 24 07:50:08 PM PST 24
Finished Jan 24 07:50:10 PM PST 24
Peak memory 217028 kb
Host smart-139ef3e2-a786-4a66-885a-7b715c1b7517
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252330656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3252330656
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1718284336
Short name T999
Test name
Test status
Simulation time 1450669583 ps
CPU time 6.04 seconds
Started Jan 24 07:50:06 PM PST 24
Finished Jan 24 07:50:13 PM PST 24
Peak memory 216080 kb
Host smart-1a2b2457-8d28-4af5-a4e3-85ea439c4464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718284336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1718284336
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2232536432
Short name T969
Test name
Test status
Simulation time 92477049 ps
CPU time 2.18 seconds
Started Jan 24 07:50:06 PM PST 24
Finished Jan 24 07:50:09 PM PST 24
Peak memory 216016 kb
Host smart-380d1afb-badc-4da1-8f34-048cf29941e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232536432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2232536432
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.3908204406
Short name T1078
Test name
Test status
Simulation time 43932750 ps
CPU time 0.79 seconds
Started Jan 24 07:50:14 PM PST 24
Finished Jan 24 07:50:16 PM PST 24
Peak memory 215888 kb
Host smart-82284811-3ebd-4ecc-a275-74881d564861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908204406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.3908204406
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1525916649
Short name T606
Test name
Test status
Simulation time 734037832 ps
CPU time 3.35 seconds
Started Jan 24 08:04:11 PM PST 24
Finished Jan 24 08:04:19 PM PST 24
Peak memory 215888 kb
Host smart-aec059a5-0780-466c-8c1e-f9635d6b9413
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1525916649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1525916649
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3346939727
Short name T169
Test name
Test status
Simulation time 34963394348 ps
CPU time 268.14 seconds
Started Jan 24 07:50:13 PM PST 24
Finished Jan 24 07:54:42 PM PST 24
Peak memory 248968 kb
Host smart-add7cb9c-f8e1-450d-b084-b5a72e093eb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346939727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3346939727
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2927897094
Short name T285
Test name
Test status
Simulation time 1302866768 ps
CPU time 23.91 seconds
Started Jan 24 07:50:07 PM PST 24
Finished Jan 24 07:50:32 PM PST 24
Peak memory 215944 kb
Host smart-7823ce5f-58a4-4d73-b3cd-ce3925edc167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927897094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2927897094
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.92508257
Short name T519
Test name
Test status
Simulation time 2244525569 ps
CPU time 2.74 seconds
Started Jan 24 07:50:07 PM PST 24
Finished Jan 24 07:50:12 PM PST 24
Peak memory 207408 kb
Host smart-9b1ba40d-ad74-44cc-abeb-9212a0e9d187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92508257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.92508257
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.26053479
Short name T702
Test name
Test status
Simulation time 288030264 ps
CPU time 3.72 seconds
Started Jan 24 07:50:03 PM PST 24
Finished Jan 24 07:50:09 PM PST 24
Peak memory 207740 kb
Host smart-97d26132-8d8f-482f-afbb-b57158fd8669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26053479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.26053479
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.483544955
Short name T919
Test name
Test status
Simulation time 407099028 ps
CPU time 1.08 seconds
Started Jan 24 07:50:08 PM PST 24
Finished Jan 24 07:50:11 PM PST 24
Peak memory 205612 kb
Host smart-1d0e820d-67d6-4e65-a709-a2304c27ae8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483544955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.483544955
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3856938118
Short name T735
Test name
Test status
Simulation time 2447642288 ps
CPU time 7.18 seconds
Started Jan 24 07:50:08 PM PST 24
Finished Jan 24 07:50:17 PM PST 24
Peak memory 217580 kb
Host smart-635aa75f-438e-4b19-b1fc-ed6d2e46313a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856938118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3856938118
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.239113036
Short name T746
Test name
Test status
Simulation time 39724354 ps
CPU time 0.71 seconds
Started Jan 24 07:46:04 PM PST 24
Finished Jan 24 07:46:07 PM PST 24
Peak memory 203516 kb
Host smart-38ee69f4-8c45-40a2-88a2-c0014bdbc88f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239113036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.239113036
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3705647422
Short name T624
Test name
Test status
Simulation time 5892059168 ps
CPU time 6.07 seconds
Started Jan 24 07:46:02 PM PST 24
Finished Jan 24 07:46:11 PM PST 24
Peak memory 218432 kb
Host smart-2f26c034-32f6-481b-9696-2f7de1cad207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705647422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3705647422
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1484682321
Short name T904
Test name
Test status
Simulation time 13161832 ps
CPU time 0.76 seconds
Started Jan 24 07:45:58 PM PST 24
Finished Jan 24 07:46:00 PM PST 24
Peak memory 204576 kb
Host smart-5d336e86-9ac9-4981-8761-62ca4dada50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484682321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1484682321
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2339328731
Short name T1030
Test name
Test status
Simulation time 1084864643 ps
CPU time 15.76 seconds
Started Jan 24 07:46:04 PM PST 24
Finished Jan 24 07:46:21 PM PST 24
Peak memory 240564 kb
Host smart-8eb7d5cd-e717-40f1-bc84-61efb479161e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339328731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2339328731
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.665191773
Short name T994
Test name
Test status
Simulation time 22802379964 ps
CPU time 38.76 seconds
Started Jan 24 08:20:52 PM PST 24
Finished Jan 24 08:21:37 PM PST 24
Peak memory 240552 kb
Host smart-b40a7bec-4efd-421a-8a20-8c862096e81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665191773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.665191773
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.733377781
Short name T728
Test name
Test status
Simulation time 2889776412 ps
CPU time 19.72 seconds
Started Jan 24 08:07:24 PM PST 24
Finished Jan 24 08:07:44 PM PST 24
Peak memory 232028 kb
Host smart-9bf40e7b-3eff-49e2-af94-e25814b51344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733377781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.733377781
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3356943890
Short name T198
Test name
Test status
Simulation time 374184993 ps
CPU time 3.51 seconds
Started Jan 24 07:46:11 PM PST 24
Finished Jan 24 07:46:16 PM PST 24
Peak memory 218460 kb
Host smart-aa8b0b06-8724-49b8-81f3-cb6337ae0be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356943890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3356943890
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.4209579067
Short name T13
Test name
Test status
Simulation time 1855434546 ps
CPU time 3.81 seconds
Started Jan 24 08:32:27 PM PST 24
Finished Jan 24 08:32:32 PM PST 24
Peak memory 232804 kb
Host smart-3250c30d-284e-44bd-af1a-6e6399a099c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209579067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.4209579067
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.319638177
Short name T841
Test name
Test status
Simulation time 94879553 ps
CPU time 1.01 seconds
Started Jan 24 07:45:57 PM PST 24
Finished Jan 24 07:46:00 PM PST 24
Peak memory 216984 kb
Host smart-8b287551-547e-43f1-a708-0764d474355f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319638177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.319638177
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2434697395
Short name T237
Test name
Test status
Simulation time 211238264 ps
CPU time 4.62 seconds
Started Jan 24 07:46:05 PM PST 24
Finished Jan 24 07:46:12 PM PST 24
Peak memory 232864 kb
Host smart-3d497253-d14a-4684-ab9d-f4810f112aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434697395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2434697395
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.44386675
Short name T929
Test name
Test status
Simulation time 10175971837 ps
CPU time 14.81 seconds
Started Jan 24 07:46:12 PM PST 24
Finished Jan 24 07:46:29 PM PST 24
Peak memory 227608 kb
Host smart-d2768651-74a8-462b-a7c9-2fee181ae6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44386675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.44386675
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.2007614853
Short name T1048
Test name
Test status
Simulation time 23926677 ps
CPU time 0.72 seconds
Started Jan 24 07:46:00 PM PST 24
Finished Jan 24 07:46:02 PM PST 24
Peak memory 215892 kb
Host smart-69822514-f7aa-45b3-a3e9-084d560e9ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007614853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.2007614853
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3243554234
Short name T555
Test name
Test status
Simulation time 5168685033 ps
CPU time 6.27 seconds
Started Jan 24 08:20:06 PM PST 24
Finished Jan 24 08:20:13 PM PST 24
Peak memory 222116 kb
Host smart-f912d96d-e1f4-4039-bce7-2dd558e28d0d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3243554234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3243554234
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1685514389
Short name T51
Test name
Test status
Simulation time 187926083 ps
CPU time 1.01 seconds
Started Jan 24 07:46:09 PM PST 24
Finished Jan 24 07:46:12 PM PST 24
Peak memory 234560 kb
Host smart-7bdf2a9e-c2dc-48a1-b820-bbfcfb78b7e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685514389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1685514389
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1570574986
Short name T1001
Test name
Test status
Simulation time 6904039571 ps
CPU time 43.47 seconds
Started Jan 24 07:46:06 PM PST 24
Finished Jan 24 07:46:51 PM PST 24
Peak memory 248904 kb
Host smart-22c1a19f-1a54-4430-9abb-463f5bcdcdd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570574986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1570574986
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2574600270
Short name T540
Test name
Test status
Simulation time 33034330461 ps
CPU time 69.78 seconds
Started Jan 24 07:46:05 PM PST 24
Finished Jan 24 07:47:16 PM PST 24
Peak memory 216076 kb
Host smart-4237df66-101a-4279-ab56-ddcd32912455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574600270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2574600270
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1293775753
Short name T471
Test name
Test status
Simulation time 2844081335 ps
CPU time 9.81 seconds
Started Jan 24 07:45:55 PM PST 24
Finished Jan 24 07:46:07 PM PST 24
Peak memory 216000 kb
Host smart-336910d1-acce-4e54-902d-bab4995fece2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293775753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1293775753
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3001384506
Short name T564
Test name
Test status
Simulation time 34804543 ps
CPU time 1.23 seconds
Started Jan 24 07:46:08 PM PST 24
Finished Jan 24 07:46:11 PM PST 24
Peak memory 207132 kb
Host smart-23c4b2fd-76b5-4054-ba2b-64cd822a502a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001384506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3001384506
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.4210935004
Short name T444
Test name
Test status
Simulation time 62617226 ps
CPU time 0.81 seconds
Started Jan 24 07:46:05 PM PST 24
Finished Jan 24 07:46:08 PM PST 24
Peak memory 204560 kb
Host smart-7fd32f72-ec26-47be-a2ff-1bafcda409a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210935004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4210935004
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2213882401
Short name T149
Test name
Test status
Simulation time 759275711 ps
CPU time 3.92 seconds
Started Jan 24 07:46:04 PM PST 24
Finished Jan 24 07:46:10 PM PST 24
Peak memory 232752 kb
Host smart-52892a27-886e-4008-9696-ba43227c5560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213882401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2213882401
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.249657957
Short name T724
Test name
Test status
Simulation time 39941313 ps
CPU time 0.71 seconds
Started Jan 24 07:50:35 PM PST 24
Finished Jan 24 07:50:38 PM PST 24
Peak memory 204472 kb
Host smart-49c60eff-1a41-4699-808e-9debe06f2990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249657957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.249657957
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.883682018
Short name T875
Test name
Test status
Simulation time 845172436 ps
CPU time 4.93 seconds
Started Jan 24 07:50:28 PM PST 24
Finished Jan 24 07:50:34 PM PST 24
Peak memory 219108 kb
Host smart-7bce4415-e3da-450c-b43f-2adc63bfca13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883682018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.883682018
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1715883593
Short name T1
Test name
Test status
Simulation time 21360002 ps
CPU time 0.81 seconds
Started Jan 24 07:50:15 PM PST 24
Finished Jan 24 07:50:17 PM PST 24
Peak memory 205600 kb
Host smart-57afe2c9-ed4b-47f6-8a60-73b3a38802c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715883593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1715883593
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2662365226
Short name T816
Test name
Test status
Simulation time 3683759477 ps
CPU time 5.27 seconds
Started Jan 24 07:50:28 PM PST 24
Finished Jan 24 07:50:34 PM PST 24
Peak memory 233644 kb
Host smart-8ab2e877-2499-408c-bb49-d98e9a8fe4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662365226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2662365226
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.262335417
Short name T1010
Test name
Test status
Simulation time 3890557229 ps
CPU time 70.89 seconds
Started Jan 24 07:50:24 PM PST 24
Finished Jan 24 07:51:36 PM PST 24
Peak memory 250852 kb
Host smart-77d0f4c7-39e6-4574-a898-5fbd45849f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262335417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.262335417
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.4058993915
Short name T916
Test name
Test status
Simulation time 1154977104 ps
CPU time 12.91 seconds
Started Jan 24 07:50:34 PM PST 24
Finished Jan 24 07:50:48 PM PST 24
Peak memory 237504 kb
Host smart-cf8137c2-a8cf-48a7-8a98-5c3700cf13dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058993915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.4058993915
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2262501686
Short name T1065
Test name
Test status
Simulation time 717427375 ps
CPU time 6.6 seconds
Started Jan 24 07:50:25 PM PST 24
Finished Jan 24 07:50:32 PM PST 24
Peak memory 233424 kb
Host smart-1c5e6cda-5902-49ba-a867-ae0867f5a843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262501686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2262501686
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2553225642
Short name T740
Test name
Test status
Simulation time 16076392826 ps
CPU time 16.05 seconds
Started Jan 24 07:50:22 PM PST 24
Finished Jan 24 07:50:39 PM PST 24
Peak memory 228848 kb
Host smart-ef897508-ee63-4ff9-a842-dec57dc3d7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553225642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2553225642
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2196289366
Short name T1088
Test name
Test status
Simulation time 729514032 ps
CPU time 10.32 seconds
Started Jan 24 07:50:27 PM PST 24
Finished Jan 24 07:50:38 PM PST 24
Peak memory 245704 kb
Host smart-da6c15d1-1ee5-4ae3-a226-0dfaf5847de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196289366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2196289366
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.350984568
Short name T299
Test name
Test status
Simulation time 3922020877 ps
CPU time 5.18 seconds
Started Jan 24 07:50:22 PM PST 24
Finished Jan 24 07:50:28 PM PST 24
Peak memory 218040 kb
Host smart-213522c7-d775-4eca-867c-6dc87cd769c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350984568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.350984568
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.413952620
Short name T982
Test name
Test status
Simulation time 179996460 ps
CPU time 3.66 seconds
Started Jan 24 07:50:28 PM PST 24
Finished Jan 24 07:50:33 PM PST 24
Peak memory 216080 kb
Host smart-ca6417f2-70f8-48b1-9a68-dd33861185fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=413952620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.413952620
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2933071898
Short name T31
Test name
Test status
Simulation time 31737962345 ps
CPU time 65.56 seconds
Started Jan 24 07:50:31 PM PST 24
Finished Jan 24 07:51:37 PM PST 24
Peak memory 239976 kb
Host smart-327019ef-1623-4521-bd08-e2b8f1a947b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933071898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2933071898
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1235578487
Short name T65
Test name
Test status
Simulation time 5330283597 ps
CPU time 23.34 seconds
Started Jan 24 07:50:12 PM PST 24
Finished Jan 24 07:50:37 PM PST 24
Peak memory 216312 kb
Host smart-23b2c3fe-2a6c-45d5-b695-d43b052852f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235578487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1235578487
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4210721047
Short name T957
Test name
Test status
Simulation time 32895106817 ps
CPU time 29.53 seconds
Started Jan 24 08:08:54 PM PST 24
Finished Jan 24 08:09:24 PM PST 24
Peak memory 216000 kb
Host smart-027acb36-4cf0-4156-85d0-a8ab4ee59176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210721047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4210721047
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1225879362
Short name T615
Test name
Test status
Simulation time 51075475 ps
CPU time 0.94 seconds
Started Jan 24 07:50:25 PM PST 24
Finished Jan 24 07:50:26 PM PST 24
Peak memory 205444 kb
Host smart-2fa4ccd6-ddb3-4475-96ac-0770232064e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225879362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1225879362
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2634652022
Short name T1044
Test name
Test status
Simulation time 219403504 ps
CPU time 1.1 seconds
Started Jan 24 07:50:23 PM PST 24
Finished Jan 24 07:50:25 PM PST 24
Peak memory 205612 kb
Host smart-8cfa1935-90ba-4278-9119-03b63a8ebe02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634652022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2634652022
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1358445832
Short name T504
Test name
Test status
Simulation time 3819941998 ps
CPU time 9.02 seconds
Started Jan 24 07:56:29 PM PST 24
Finished Jan 24 07:56:39 PM PST 24
Peak memory 234988 kb
Host smart-9665f3b2-ee82-45e5-a969-2a0927cb29a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358445832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1358445832
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.256963030
Short name T617
Test name
Test status
Simulation time 16705982 ps
CPU time 0.68 seconds
Started Jan 24 07:50:32 PM PST 24
Finished Jan 24 07:50:34 PM PST 24
Peak memory 204108 kb
Host smart-57362a15-0692-4daf-83fc-355bcc4555ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256963030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.256963030
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3711966167
Short name T449
Test name
Test status
Simulation time 5944465662 ps
CPU time 6.76 seconds
Started Jan 24 07:50:35 PM PST 24
Finished Jan 24 07:50:43 PM PST 24
Peak memory 233088 kb
Host smart-7849d65f-4ee2-442c-b392-f98358cec54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711966167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3711966167
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.4170221491
Short name T514
Test name
Test status
Simulation time 134259827 ps
CPU time 0.74 seconds
Started Jan 24 07:50:32 PM PST 24
Finished Jan 24 07:50:33 PM PST 24
Peak memory 204612 kb
Host smart-ebb1bedb-e341-4c14-b17e-2e5183fc6803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170221491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.4170221491
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.881524654
Short name T276
Test name
Test status
Simulation time 64200021804 ps
CPU time 205.38 seconds
Started Jan 24 07:50:35 PM PST 24
Finished Jan 24 07:54:02 PM PST 24
Peak memory 265064 kb
Host smart-77bbdca3-1937-46e7-824a-c67e0d41060b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881524654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.881524654
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.229129420
Short name T819
Test name
Test status
Simulation time 5387984320 ps
CPU time 51.02 seconds
Started Jan 24 07:50:35 PM PST 24
Finished Jan 24 07:51:27 PM PST 24
Peak memory 252164 kb
Host smart-8ae5acbe-15b8-4062-8fde-6865b9e2e403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229129420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.229129420
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.249049733
Short name T543
Test name
Test status
Simulation time 1749276658 ps
CPU time 14.33 seconds
Started Jan 24 07:50:38 PM PST 24
Finished Jan 24 07:50:53 PM PST 24
Peak memory 224108 kb
Host smart-c6f23386-89cd-4109-b085-d079bddced6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249049733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.249049733
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1938232678
Short name T883
Test name
Test status
Simulation time 247337223 ps
CPU time 4.48 seconds
Started Jan 24 07:50:33 PM PST 24
Finished Jan 24 07:50:38 PM PST 24
Peak memory 218244 kb
Host smart-864054b7-1057-455e-a934-d1ffd79d7e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938232678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1938232678
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1617664089
Short name T981
Test name
Test status
Simulation time 2693118726 ps
CPU time 4.31 seconds
Started Jan 24 07:50:35 PM PST 24
Finished Jan 24 07:50:41 PM PST 24
Peak memory 217652 kb
Host smart-d4c4d263-9c58-4ee9-ad72-9b720ecfda4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617664089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1617664089
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3131932293
Short name T477
Test name
Test status
Simulation time 2023382090 ps
CPU time 4.89 seconds
Started Jan 24 07:50:35 PM PST 24
Finished Jan 24 07:50:42 PM PST 24
Peak memory 216396 kb
Host smart-8ed6a4ac-0859-4310-aa2c-c4f41ce1eb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131932293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3131932293
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2583884091
Short name T475
Test name
Test status
Simulation time 1282908343 ps
CPU time 6.41 seconds
Started Jan 24 07:50:34 PM PST 24
Finished Jan 24 07:50:41 PM PST 24
Peak memory 234120 kb
Host smart-4f2fb638-329a-4cb9-a90b-22cba2e19f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583884091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2583884091
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2162366795
Short name T433
Test name
Test status
Simulation time 4223273417 ps
CPU time 5.4 seconds
Started Jan 24 07:50:35 PM PST 24
Finished Jan 24 07:50:42 PM PST 24
Peak memory 216980 kb
Host smart-dfa08dbc-3ea6-426d-a1aa-f102e97ebf95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2162366795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2162366795
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.760130213
Short name T537
Test name
Test status
Simulation time 397790174325 ps
CPU time 436.54 seconds
Started Jan 24 07:50:35 PM PST 24
Finished Jan 24 07:57:52 PM PST 24
Peak memory 281748 kb
Host smart-721c3ce4-a7f7-4efd-93c3-2da35533fee4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760130213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.760130213
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1932347064
Short name T761
Test name
Test status
Simulation time 439230603 ps
CPU time 3.73 seconds
Started Jan 24 07:50:32 PM PST 24
Finished Jan 24 07:50:36 PM PST 24
Peak memory 207512 kb
Host smart-849083a5-db82-4772-bd4f-6ac6d4634cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932347064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1932347064
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3793737965
Short name T293
Test name
Test status
Simulation time 32436506 ps
CPU time 1.86 seconds
Started Jan 24 09:59:50 PM PST 24
Finished Jan 24 09:59:52 PM PST 24
Peak memory 207872 kb
Host smart-cf5cf0f4-11b0-4a34-8bf5-7e21dfef9381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793737965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3793737965
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2212159378
Short name T474
Test name
Test status
Simulation time 23054409 ps
CPU time 0.76 seconds
Started Jan 24 07:50:29 PM PST 24
Finished Jan 24 07:50:31 PM PST 24
Peak memory 204588 kb
Host smart-5baa4dc2-a517-4d44-9701-9b91be682d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212159378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2212159378
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1724881966
Short name T937
Test name
Test status
Simulation time 2432234785 ps
CPU time 11.9 seconds
Started Jan 24 09:06:03 PM PST 24
Finished Jan 24 09:06:15 PM PST 24
Peak memory 232688 kb
Host smart-6c42c176-dc31-44e3-a44a-ed251f05ee6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724881966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1724881966
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3723003801
Short name T481
Test name
Test status
Simulation time 466462626 ps
CPU time 4.4 seconds
Started Jan 24 08:53:54 PM PST 24
Finished Jan 24 08:54:00 PM PST 24
Peak memory 233848 kb
Host smart-656d4df2-f419-447f-b0f9-44ad65d2585f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723003801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3723003801
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2652448801
Short name T1075
Test name
Test status
Simulation time 19177207 ps
CPU time 0.84 seconds
Started Jan 24 07:50:35 PM PST 24
Finished Jan 24 07:50:37 PM PST 24
Peak memory 205296 kb
Host smart-f782b5bc-5e8b-400b-be28-3159f45ab419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652448801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2652448801
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1494538734
Short name T267
Test name
Test status
Simulation time 21244613353 ps
CPU time 116.47 seconds
Started Jan 24 07:50:48 PM PST 24
Finished Jan 24 07:52:45 PM PST 24
Peak memory 273184 kb
Host smart-f911dd87-7d28-494c-ab44-087150c960f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494538734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1494538734
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2787395741
Short name T704
Test name
Test status
Simulation time 9075958904 ps
CPU time 96.84 seconds
Started Jan 24 09:06:45 PM PST 24
Finished Jan 24 09:08:22 PM PST 24
Peak memory 254588 kb
Host smart-a4d0f835-3d87-49eb-9146-c45b25cefd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787395741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2787395741
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.28531540
Short name T813
Test name
Test status
Simulation time 11391518719 ps
CPU time 76.46 seconds
Started Jan 24 07:50:58 PM PST 24
Finished Jan 24 07:52:15 PM PST 24
Peak memory 248948 kb
Host smart-765edfdd-bd76-4c19-b097-d713fa9dfa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28531540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.28531540
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.708285533
Short name T873
Test name
Test status
Simulation time 381052771 ps
CPU time 6.53 seconds
Started Jan 24 09:26:21 PM PST 24
Finished Jan 24 09:26:28 PM PST 24
Peak memory 232408 kb
Host smart-d87d3693-2208-497c-84db-58e675673316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708285533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.708285533
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1337129244
Short name T173
Test name
Test status
Simulation time 1464960149 ps
CPU time 6.65 seconds
Started Jan 24 10:45:25 PM PST 24
Finished Jan 24 10:45:32 PM PST 24
Peak memory 234628 kb
Host smart-b27b6121-2258-406b-8276-f8742a8251e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337129244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1337129244
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.861180140
Short name T193
Test name
Test status
Simulation time 13148662475 ps
CPU time 4.29 seconds
Started Jan 24 07:50:51 PM PST 24
Finished Jan 24 07:50:56 PM PST 24
Peak memory 232488 kb
Host smart-c4bccc05-8b9d-4784-baae-d4cf193a35c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861180140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.861180140
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.367396205
Short name T236
Test name
Test status
Simulation time 1232808005 ps
CPU time 2.86 seconds
Started Jan 24 07:50:48 PM PST 24
Finished Jan 24 07:50:51 PM PST 24
Peak memory 232620 kb
Host smart-41647c1d-28f4-4bb5-9a3b-378254510721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367396205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.367396205
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.548232090
Short name T223
Test name
Test status
Simulation time 847145683 ps
CPU time 5.56 seconds
Started Jan 24 07:50:50 PM PST 24
Finished Jan 24 07:50:56 PM PST 24
Peak memory 226708 kb
Host smart-316fe8b2-7912-4c09-b798-68be5cade8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548232090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.548232090
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1114852273
Short name T938
Test name
Test status
Simulation time 2197906774 ps
CPU time 4.94 seconds
Started Jan 24 11:36:07 PM PST 24
Finished Jan 24 11:36:18 PM PST 24
Peak memory 216312 kb
Host smart-c8597604-090b-4578-a7ea-0d8dd241847f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1114852273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1114852273
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1130490684
Short name T279
Test name
Test status
Simulation time 244379480248 ps
CPU time 228.61 seconds
Started Jan 24 07:50:54 PM PST 24
Finished Jan 24 07:54:43 PM PST 24
Peak memory 289772 kb
Host smart-90e5d7ee-4b29-4eca-9569-5d3486989625
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130490684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1130490684
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2397657396
Short name T922
Test name
Test status
Simulation time 1594739169 ps
CPU time 24.05 seconds
Started Jan 24 07:55:35 PM PST 24
Finished Jan 24 07:55:59 PM PST 24
Peak memory 216144 kb
Host smart-ca16790b-5421-4d2e-8808-e3989585f552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397657396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2397657396
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2814857755
Short name T560
Test name
Test status
Simulation time 1270690261 ps
CPU time 6.12 seconds
Started Jan 24 07:50:35 PM PST 24
Finished Jan 24 07:50:42 PM PST 24
Peak memory 207624 kb
Host smart-48753604-5b65-4100-a644-ad2811d8d9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814857755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2814857755
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.4276014159
Short name T683
Test name
Test status
Simulation time 184702272 ps
CPU time 7.43 seconds
Started Jan 24 07:50:51 PM PST 24
Finished Jan 24 07:50:59 PM PST 24
Peak memory 207696 kb
Host smart-07df5aa2-698a-4528-b4a9-40f8593db26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276014159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.4276014159
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1450574914
Short name T699
Test name
Test status
Simulation time 81637573 ps
CPU time 0.86 seconds
Started Jan 24 07:50:36 PM PST 24
Finished Jan 24 07:50:38 PM PST 24
Peak memory 204584 kb
Host smart-835b93e5-0abe-41fc-871f-988c207f9022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450574914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1450574914
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3349907006
Short name T861
Test name
Test status
Simulation time 2138815497 ps
CPU time 8.42 seconds
Started Jan 24 07:50:49 PM PST 24
Finished Jan 24 07:50:58 PM PST 24
Peak memory 218144 kb
Host smart-a0bf49c4-428e-412c-aae8-2821900fcb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349907006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3349907006
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2028648778
Short name T441
Test name
Test status
Simulation time 87475456 ps
CPU time 0.75 seconds
Started Jan 24 07:50:58 PM PST 24
Finished Jan 24 07:50:59 PM PST 24
Peak memory 204136 kb
Host smart-42d97098-bebd-4e5d-833c-67e15fd567bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028648778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2028648778
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.146775522
Short name T817
Test name
Test status
Simulation time 233468082 ps
CPU time 3.46 seconds
Started Jan 24 09:13:38 PM PST 24
Finished Jan 24 09:13:43 PM PST 24
Peak memory 218128 kb
Host smart-040cbc4b-c4ce-4667-a2e2-461a2f484902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146775522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.146775522
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3252117685
Short name T947
Test name
Test status
Simulation time 35978700 ps
CPU time 0.8 seconds
Started Jan 24 07:50:56 PM PST 24
Finished Jan 24 07:50:58 PM PST 24
Peak memory 205292 kb
Host smart-e501e9ae-8987-4575-b800-102c0445603c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252117685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3252117685
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2606879885
Short name T452
Test name
Test status
Simulation time 61204429676 ps
CPU time 306.75 seconds
Started Jan 24 07:51:02 PM PST 24
Finished Jan 24 07:56:10 PM PST 24
Peak memory 264476 kb
Host smart-5670c8b6-3891-49de-b05d-e360396109bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606879885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2606879885
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2635550169
Short name T143
Test name
Test status
Simulation time 16070994704 ps
CPU time 85.56 seconds
Started Jan 24 07:51:03 PM PST 24
Finished Jan 24 07:52:34 PM PST 24
Peak memory 255680 kb
Host smart-31a78424-211e-4819-a493-4128946b5d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635550169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2635550169
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3481644619
Short name T926
Test name
Test status
Simulation time 25405084265 ps
CPU time 34 seconds
Started Jan 24 07:51:00 PM PST 24
Finished Jan 24 07:51:35 PM PST 24
Peak memory 247964 kb
Host smart-f7a026e3-c963-4bda-acd6-f61d1396a620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481644619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3481644619
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.269703194
Short name T538
Test name
Test status
Simulation time 1680299078 ps
CPU time 8.99 seconds
Started Jan 24 07:51:01 PM PST 24
Finished Jan 24 07:51:11 PM PST 24
Peak memory 219276 kb
Host smart-9a921565-c089-4bdf-9f1f-7bab8a49097d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269703194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.269703194
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4293418198
Short name T802
Test name
Test status
Simulation time 2614938617 ps
CPU time 11.68 seconds
Started Jan 24 07:51:00 PM PST 24
Finished Jan 24 07:51:13 PM PST 24
Peak memory 235896 kb
Host smart-8737bd9c-f451-4cd5-915b-4fffa3ff8e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293418198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4293418198
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2649948761
Short name T14
Test name
Test status
Simulation time 18105521689 ps
CPU time 46.57 seconds
Started Jan 24 07:51:00 PM PST 24
Finished Jan 24 07:51:47 PM PST 24
Peak memory 245056 kb
Host smart-2f635ac3-868f-49e0-809c-58c3e0439bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649948761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2649948761
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2401070875
Short name T229
Test name
Test status
Simulation time 1130186846 ps
CPU time 7.81 seconds
Started Jan 24 07:51:02 PM PST 24
Finished Jan 24 07:51:11 PM PST 24
Peak memory 216268 kb
Host smart-e02744f4-2b87-4f03-966c-068d38c6dc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401070875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2401070875
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2417598804
Short name T552
Test name
Test status
Simulation time 342804029 ps
CPU time 3.8 seconds
Started Jan 24 07:51:00 PM PST 24
Finished Jan 24 07:51:05 PM PST 24
Peak memory 221872 kb
Host smart-09f3a42a-cce7-46e3-88b9-aa84128ba190
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2417598804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2417598804
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2948712405
Short name T678
Test name
Test status
Simulation time 20373448580 ps
CPU time 56.85 seconds
Started Jan 24 07:55:32 PM PST 24
Finished Jan 24 07:56:31 PM PST 24
Peak memory 220108 kb
Host smart-acbb6b44-1268-4e43-bc3f-dd7fba019041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948712405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2948712405
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.123201117
Short name T549
Test name
Test status
Simulation time 2920983722 ps
CPU time 4.36 seconds
Started Jan 24 07:55:35 PM PST 24
Finished Jan 24 07:55:41 PM PST 24
Peak memory 215992 kb
Host smart-c206812d-2c8c-4850-b3ce-c0b5f961837e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123201117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.123201117
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1613300427
Short name T419
Test name
Test status
Simulation time 130723761 ps
CPU time 5.87 seconds
Started Jan 24 07:51:00 PM PST 24
Finished Jan 24 07:51:07 PM PST 24
Peak memory 207744 kb
Host smart-0d685c51-f524-499f-94a9-02445ca05be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613300427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1613300427
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1202993775
Short name T886
Test name
Test status
Simulation time 165109852 ps
CPU time 0.9 seconds
Started Jan 24 07:50:58 PM PST 24
Finished Jan 24 07:50:59 PM PST 24
Peak memory 205596 kb
Host smart-5d925416-8891-43d6-910e-6aefc091cacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202993775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1202993775
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2144837888
Short name T977
Test name
Test status
Simulation time 3613775187 ps
CPU time 6.13 seconds
Started Jan 24 07:51:01 PM PST 24
Finished Jan 24 07:51:08 PM PST 24
Peak memory 233096 kb
Host smart-38eaa8c6-57bc-43c6-bd9e-63cb813632c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144837888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2144837888
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1403205301
Short name T584
Test name
Test status
Simulation time 78437190 ps
CPU time 0.69 seconds
Started Jan 24 07:51:19 PM PST 24
Finished Jan 24 07:51:25 PM PST 24
Peak memory 204152 kb
Host smart-4e8786e0-ebfc-41b3-8355-826944a8be32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403205301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1403205301
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3532336050
Short name T909
Test name
Test status
Simulation time 795106484 ps
CPU time 2.69 seconds
Started Jan 24 07:51:20 PM PST 24
Finished Jan 24 07:51:28 PM PST 24
Peak memory 232804 kb
Host smart-dd96a85b-eef5-4061-8f3b-39c38f554501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532336050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3532336050
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2312451007
Short name T1067
Test name
Test status
Simulation time 17347484 ps
CPU time 0.76 seconds
Started Jan 24 07:50:59 PM PST 24
Finished Jan 24 07:51:01 PM PST 24
Peak memory 205592 kb
Host smart-93f317fd-c51e-44a7-837f-cfd0c3695d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312451007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2312451007
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3648316691
Short name T191
Test name
Test status
Simulation time 22761946038 ps
CPU time 63.45 seconds
Started Jan 24 07:51:20 PM PST 24
Finished Jan 24 07:52:28 PM PST 24
Peak memory 248736 kb
Host smart-eba5ba48-1cdd-4ec5-ad3a-6dc19ed0db06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648316691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3648316691
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.512281934
Short name T840
Test name
Test status
Simulation time 15068666051 ps
CPU time 153.23 seconds
Started Jan 24 07:51:16 PM PST 24
Finished Jan 24 07:53:57 PM PST 24
Peak memory 250080 kb
Host smart-1d0f45e0-4aee-4124-8bc9-bac1935de534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512281934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.512281934
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3929154344
Short name T61
Test name
Test status
Simulation time 33796729572 ps
CPU time 229.28 seconds
Started Jan 24 07:51:19 PM PST 24
Finished Jan 24 07:55:14 PM PST 24
Peak memory 254732 kb
Host smart-caf1ee5f-e975-4c91-88bc-0f7e11e8a965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929154344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3929154344
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2963159269
Short name T770
Test name
Test status
Simulation time 24120216118 ps
CPU time 19.18 seconds
Started Jan 24 07:51:20 PM PST 24
Finished Jan 24 07:51:44 PM PST 24
Peak memory 238388 kb
Host smart-4cb5fc71-42ce-413c-9b50-38e3375d439e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963159269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2963159269
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1052277685
Short name T996
Test name
Test status
Simulation time 921989285 ps
CPU time 4.38 seconds
Started Jan 24 07:51:20 PM PST 24
Finished Jan 24 07:51:29 PM PST 24
Peak memory 232384 kb
Host smart-73dbd41a-4a30-453e-b35d-f5568d188c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052277685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1052277685
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.4152154045
Short name T872
Test name
Test status
Simulation time 3853795119 ps
CPU time 14.3 seconds
Started Jan 24 07:51:21 PM PST 24
Finished Jan 24 07:51:39 PM PST 24
Peak memory 232592 kb
Host smart-a9bff2a1-e434-4934-ab34-9bc39fc09eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152154045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.4152154045
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.888570937
Short name T35
Test name
Test status
Simulation time 4556300065 ps
CPU time 11.8 seconds
Started Jan 24 07:51:10 PM PST 24
Finished Jan 24 07:51:26 PM PST 24
Peak memory 238508 kb
Host smart-13f2231f-facc-4992-bafb-97b6aca62e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888570937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.888570937
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2524994773
Short name T795
Test name
Test status
Simulation time 11919125206 ps
CPU time 30.32 seconds
Started Jan 24 07:51:10 PM PST 24
Finished Jan 24 07:51:45 PM PST 24
Peak memory 218080 kb
Host smart-aedf1ca2-f60d-49d5-8d06-7ed4b2b80439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524994773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2524994773
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2070065954
Short name T521
Test name
Test status
Simulation time 1059648121 ps
CPU time 3.67 seconds
Started Jan 24 07:51:22 PM PST 24
Finished Jan 24 07:51:29 PM PST 24
Peak memory 216088 kb
Host smart-96f9b096-5d8f-4d82-9174-62fccffff5dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2070065954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2070065954
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3469366684
Short name T963
Test name
Test status
Simulation time 9786861557 ps
CPU time 41.82 seconds
Started Jan 24 07:51:11 PM PST 24
Finished Jan 24 07:51:58 PM PST 24
Peak memory 216028 kb
Host smart-0a07433f-7156-47c4-aeef-cfba6a99d24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469366684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3469366684
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2503610746
Short name T968
Test name
Test status
Simulation time 11499102690 ps
CPU time 30.09 seconds
Started Jan 24 07:51:15 PM PST 24
Finished Jan 24 07:51:54 PM PST 24
Peak memory 215968 kb
Host smart-087046f1-3899-4e93-9870-c8fb88126116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503610746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2503610746
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1645552695
Short name T785
Test name
Test status
Simulation time 211192676 ps
CPU time 2.63 seconds
Started Jan 24 07:51:10 PM PST 24
Finished Jan 24 07:51:17 PM PST 24
Peak memory 217300 kb
Host smart-c7c338ef-cd2e-48ce-94d8-908b3357300e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645552695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1645552695
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2621680306
Short name T597
Test name
Test status
Simulation time 55004772 ps
CPU time 0.82 seconds
Started Jan 24 07:51:09 PM PST 24
Finished Jan 24 07:51:14 PM PST 24
Peak memory 204612 kb
Host smart-d39ee0c5-6507-4c14-b26b-00d9757a46c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621680306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2621680306
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1517769847
Short name T860
Test name
Test status
Simulation time 35257586957 ps
CPU time 11.26 seconds
Started Jan 24 07:51:16 PM PST 24
Finished Jan 24 07:51:35 PM PST 24
Peak memory 233576 kb
Host smart-897a4f1a-de21-43c3-b868-590ec7a0a4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517769847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1517769847
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1538454298
Short name T300
Test name
Test status
Simulation time 159570791 ps
CPU time 0.76 seconds
Started Jan 24 07:51:33 PM PST 24
Finished Jan 24 07:51:35 PM PST 24
Peak memory 204424 kb
Host smart-827913a2-121a-4c55-83a6-454428cf6446
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538454298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1538454298
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.269042088
Short name T692
Test name
Test status
Simulation time 963756300 ps
CPU time 4.79 seconds
Started Jan 24 07:51:33 PM PST 24
Finished Jan 24 07:51:39 PM PST 24
Peak memory 218204 kb
Host smart-48111301-3de3-4176-974e-7080c947da8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269042088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.269042088
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3905711298
Short name T1082
Test name
Test status
Simulation time 46841378 ps
CPU time 0.74 seconds
Started Jan 24 07:51:20 PM PST 24
Finished Jan 24 07:51:26 PM PST 24
Peak memory 204236 kb
Host smart-a7e67b6e-258b-4461-a23c-478ef920ba94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905711298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3905711298
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.4131202421
Short name T235
Test name
Test status
Simulation time 11187316021 ps
CPU time 66.79 seconds
Started Jan 24 07:51:29 PM PST 24
Finished Jan 24 07:52:37 PM PST 24
Peak memory 224056 kb
Host smart-1e96ca05-fe49-4c20-92ef-909c3d28c244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131202421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.4131202421
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2728516486
Short name T570
Test name
Test status
Simulation time 188499607286 ps
CPU time 268.39 seconds
Started Jan 24 07:51:34 PM PST 24
Finished Jan 24 07:56:05 PM PST 24
Peak memory 269968 kb
Host smart-e91c0010-cbf4-4a7c-bd44-2c8c1af4143f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728516486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2728516486
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1460338069
Short name T794
Test name
Test status
Simulation time 4478821771 ps
CPU time 30.13 seconds
Started Jan 24 07:51:29 PM PST 24
Finished Jan 24 07:52:01 PM PST 24
Peak memory 233448 kb
Host smart-9ede2529-3b05-4664-8b3e-8eb5a2bb2e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460338069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1460338069
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3279512187
Short name T865
Test name
Test status
Simulation time 317300004 ps
CPU time 3.87 seconds
Started Jan 24 07:51:29 PM PST 24
Finished Jan 24 07:51:34 PM PST 24
Peak memory 233408 kb
Host smart-7a2c1fc8-2e28-4387-adec-b64e36a78972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279512187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3279512187
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2571606383
Short name T1095
Test name
Test status
Simulation time 10751112247 ps
CPU time 11.11 seconds
Started Jan 24 07:51:29 PM PST 24
Finished Jan 24 07:51:42 PM PST 24
Peak memory 239660 kb
Host smart-f2133716-963d-4f80-a8b5-b015e5654d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571606383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2571606383
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1065636012
Short name T772
Test name
Test status
Simulation time 2407298763 ps
CPU time 8.52 seconds
Started Jan 24 07:51:34 PM PST 24
Finished Jan 24 07:51:44 PM PST 24
Peak memory 217132 kb
Host smart-bea08808-75c7-4608-b585-e5f76bb6726f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065636012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1065636012
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2874153939
Short name T150
Test name
Test status
Simulation time 1553423666 ps
CPU time 10.34 seconds
Started Jan 24 07:51:31 PM PST 24
Finished Jan 24 07:51:42 PM PST 24
Peak memory 232804 kb
Host smart-568acf85-7a31-4a84-921f-acd5757b2b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874153939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2874153939
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3355981456
Short name T421
Test name
Test status
Simulation time 1336250290 ps
CPU time 3.29 seconds
Started Jan 24 07:51:31 PM PST 24
Finished Jan 24 07:51:35 PM PST 24
Peak memory 221200 kb
Host smart-d12be5b6-615d-43c9-8c86-557dce89fffb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3355981456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3355981456
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3637474956
Short name T998
Test name
Test status
Simulation time 33796693006 ps
CPU time 264.1 seconds
Started Jan 24 07:51:37 PM PST 24
Finished Jan 24 07:56:02 PM PST 24
Peak memory 237908 kb
Host smart-f9910be5-08e1-4716-af51-4a29432c34da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637474956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3637474956
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.314748007
Short name T600
Test name
Test status
Simulation time 2772492975 ps
CPU time 42.55 seconds
Started Jan 24 07:51:20 PM PST 24
Finished Jan 24 07:52:08 PM PST 24
Peak memory 216400 kb
Host smart-bce81956-c29d-4ebb-a1da-d2604aa6aa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314748007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.314748007
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3934591642
Short name T296
Test name
Test status
Simulation time 2933984087 ps
CPU time 11.84 seconds
Started Jan 24 07:51:21 PM PST 24
Finished Jan 24 07:51:37 PM PST 24
Peak memory 215944 kb
Host smart-cab2eca0-ff22-4109-9c38-eb405532710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934591642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3934591642
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3400952000
Short name T908
Test name
Test status
Simulation time 83407754 ps
CPU time 0.93 seconds
Started Jan 24 07:51:37 PM PST 24
Finished Jan 24 07:51:39 PM PST 24
Peak memory 205792 kb
Host smart-ab9396eb-6cfa-4429-9370-30e21366ede2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400952000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3400952000
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2019620677
Short name T788
Test name
Test status
Simulation time 167083571 ps
CPU time 0.8 seconds
Started Jan 24 07:51:21 PM PST 24
Finished Jan 24 07:51:26 PM PST 24
Peak memory 204564 kb
Host smart-264d5189-aff0-4105-8304-643b86d2f16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019620677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2019620677
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2306996082
Short name T148
Test name
Test status
Simulation time 650678407 ps
CPU time 7.32 seconds
Started Jan 24 07:51:34 PM PST 24
Finished Jan 24 07:51:44 PM PST 24
Peak memory 218556 kb
Host smart-b441f377-f05c-4c1d-ac0d-4228c62a8eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306996082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2306996082
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3130382818
Short name T1037
Test name
Test status
Simulation time 36363137 ps
CPU time 0.7 seconds
Started Jan 24 07:51:49 PM PST 24
Finished Jan 24 07:51:51 PM PST 24
Peak memory 204432 kb
Host smart-583e153d-0da5-4e59-8f93-b4ebea5abfe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130382818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3130382818
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.577650194
Short name T513
Test name
Test status
Simulation time 8874943733 ps
CPU time 8.02 seconds
Started Jan 24 07:51:34 PM PST 24
Finished Jan 24 07:51:44 PM PST 24
Peak memory 218900 kb
Host smart-9e740c8b-29a9-4625-bd86-78b57bcc722d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577650194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.577650194
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1736114166
Short name T848
Test name
Test status
Simulation time 18071048 ps
CPU time 0.75 seconds
Started Jan 24 07:51:35 PM PST 24
Finished Jan 24 07:51:38 PM PST 24
Peak memory 204272 kb
Host smart-0eee8204-09cf-4845-8273-86455cc3ee6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736114166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1736114166
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3692384975
Short name T1014
Test name
Test status
Simulation time 11749898001 ps
CPU time 84.7 seconds
Started Jan 24 07:51:42 PM PST 24
Finished Jan 24 07:53:08 PM PST 24
Peak memory 236740 kb
Host smart-a9f64bca-f3b7-4a06-9a88-40c324f7eb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692384975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3692384975
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2590427108
Short name T576
Test name
Test status
Simulation time 3653754048 ps
CPU time 63.79 seconds
Started Jan 24 07:51:41 PM PST 24
Finished Jan 24 07:52:46 PM PST 24
Peak memory 251588 kb
Host smart-57f1c790-0779-48f9-ba51-26c4b755b35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590427108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2590427108
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.536992092
Short name T891
Test name
Test status
Simulation time 948838354 ps
CPU time 13.79 seconds
Started Jan 24 07:51:47 PM PST 24
Finished Jan 24 07:52:02 PM PST 24
Peak memory 238024 kb
Host smart-c80b301f-76a3-41ec-8b6e-7fc6d003af76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536992092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.536992092
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.959074322
Short name T249
Test name
Test status
Simulation time 3660183514 ps
CPU time 6.86 seconds
Started Jan 24 07:51:34 PM PST 24
Finished Jan 24 07:51:42 PM PST 24
Peak memory 233116 kb
Host smart-70c096bf-ef93-4dc6-b12b-3b79e6d417e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959074322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.959074322
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3006229372
Short name T166
Test name
Test status
Simulation time 5841495507 ps
CPU time 12.91 seconds
Started Jan 24 07:51:37 PM PST 24
Finished Jan 24 07:51:51 PM PST 24
Peak memory 235872 kb
Host smart-9bfba28c-3f5a-44b7-bc9d-9b3c37c51209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006229372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3006229372
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.555495187
Short name T274
Test name
Test status
Simulation time 1780737582 ps
CPU time 11.57 seconds
Started Jan 24 07:51:34 PM PST 24
Finished Jan 24 07:51:48 PM PST 24
Peak memory 240592 kb
Host smart-98bfa9bd-a142-458b-a34e-502a33a05b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555495187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.555495187
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1343957741
Short name T852
Test name
Test status
Simulation time 119726474321 ps
CPU time 45.99 seconds
Started Jan 24 07:51:35 PM PST 24
Finished Jan 24 07:52:23 PM PST 24
Peak memory 238964 kb
Host smart-e00ebdca-96a4-4e44-a4bf-a7ae7a606ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343957741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1343957741
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.710395949
Short name T641
Test name
Test status
Simulation time 2599881368 ps
CPU time 3.55 seconds
Started Jan 24 07:51:47 PM PST 24
Finished Jan 24 07:51:52 PM PST 24
Peak memory 216960 kb
Host smart-2971307f-9959-4d1f-b86b-0ee0392ffdd3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=710395949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.710395949
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.742895326
Short name T84
Test name
Test status
Simulation time 12168912849 ps
CPU time 179.55 seconds
Started Jan 24 07:51:34 PM PST 24
Finished Jan 24 07:54:36 PM PST 24
Peak memory 216288 kb
Host smart-08bfe0fa-e1da-42a5-8ab2-bfb35562e93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742895326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.742895326
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3869749831
Short name T862
Test name
Test status
Simulation time 9348320451 ps
CPU time 11.01 seconds
Started Jan 24 07:51:32 PM PST 24
Finished Jan 24 07:51:44 PM PST 24
Peak memory 215772 kb
Host smart-51a0130b-1eb2-4eb3-9e28-66522b2f020f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869749831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3869749831
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1547144754
Short name T530
Test name
Test status
Simulation time 350499150 ps
CPU time 1.44 seconds
Started Jan 24 07:51:34 PM PST 24
Finished Jan 24 07:51:38 PM PST 24
Peak memory 207596 kb
Host smart-99546e66-ef9d-45d4-b130-ab79f3486c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547144754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1547144754
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1100885323
Short name T912
Test name
Test status
Simulation time 24718319 ps
CPU time 0.75 seconds
Started Jan 24 07:51:35 PM PST 24
Finished Jan 24 07:51:37 PM PST 24
Peak memory 204564 kb
Host smart-dbdeaea5-5cab-4834-8070-604888388bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100885323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1100885323
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.689808704
Short name T725
Test name
Test status
Simulation time 126849490 ps
CPU time 2.24 seconds
Started Jan 24 07:51:33 PM PST 24
Finished Jan 24 07:51:38 PM PST 24
Peak memory 216076 kb
Host smart-4113b1f8-f2de-49c4-abdb-836e1410bd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689808704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.689808704
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3770208671
Short name T898
Test name
Test status
Simulation time 40640433 ps
CPU time 0.8 seconds
Started Jan 24 07:52:00 PM PST 24
Finished Jan 24 07:52:04 PM PST 24
Peak memory 204468 kb
Host smart-9d5243d3-2db8-4c0b-87b4-5e737add0423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770208671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3770208671
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1398709170
Short name T792
Test name
Test status
Simulation time 86555381 ps
CPU time 2.66 seconds
Started Jan 24 07:51:51 PM PST 24
Finished Jan 24 07:51:55 PM PST 24
Peak memory 232820 kb
Host smart-67c5a94c-f143-4605-a90a-9a02cc885702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398709170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1398709170
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2487894219
Short name T533
Test name
Test status
Simulation time 18727878 ps
CPU time 0.76 seconds
Started Jan 24 07:51:42 PM PST 24
Finished Jan 24 07:51:44 PM PST 24
Peak memory 204288 kb
Host smart-2b8b2ea4-af6e-4994-8149-783c9c2f0696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487894219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2487894219
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2917903801
Short name T914
Test name
Test status
Simulation time 128907859235 ps
CPU time 300.33 seconds
Started Jan 24 07:51:57 PM PST 24
Finished Jan 24 07:57:00 PM PST 24
Peak memory 254500 kb
Host smart-c31b591b-1598-4494-8a3c-f6736454966a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917903801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2917903801
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1042097037
Short name T818
Test name
Test status
Simulation time 58550748407 ps
CPU time 138.52 seconds
Started Jan 24 08:07:43 PM PST 24
Finished Jan 24 08:10:03 PM PST 24
Peak memory 240704 kb
Host smart-c3ef167f-e1f8-4050-a154-ae29a0591c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042097037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1042097037
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1651987294
Short name T666
Test name
Test status
Simulation time 12367006086 ps
CPU time 18.4 seconds
Started Jan 24 08:45:50 PM PST 24
Finished Jan 24 08:46:10 PM PST 24
Peak memory 231792 kb
Host smart-712feeca-996d-453d-b541-9899301a3818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651987294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1651987294
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1720562705
Short name T160
Test name
Test status
Simulation time 486459174 ps
CPU time 5.11 seconds
Started Jan 24 08:03:25 PM PST 24
Finished Jan 24 08:03:34 PM PST 24
Peak memory 233028 kb
Host smart-6ed53dd7-50a2-4b52-8780-fb9c49a32646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720562705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1720562705
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3565642800
Short name T184
Test name
Test status
Simulation time 23297654294 ps
CPU time 69.07 seconds
Started Jan 24 07:51:46 PM PST 24
Finished Jan 24 07:52:56 PM PST 24
Peak memory 247132 kb
Host smart-a84dbb55-e01d-4364-9468-a8118e49739e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565642800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3565642800
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2680009248
Short name T629
Test name
Test status
Simulation time 3252129108 ps
CPU time 3.57 seconds
Started Jan 24 08:57:19 PM PST 24
Finished Jan 24 08:57:24 PM PST 24
Peak memory 232692 kb
Host smart-b1fe6c0f-a655-40e9-af78-dfa91c9e1c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680009248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2680009248
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.665797685
Short name T745
Test name
Test status
Simulation time 25036032327 ps
CPU time 16.45 seconds
Started Jan 24 08:02:10 PM PST 24
Finished Jan 24 08:02:29 PM PST 24
Peak memory 233516 kb
Host smart-3f0346d7-2f24-47bd-a922-a43ba720db6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665797685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.665797685
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3830832552
Short name T902
Test name
Test status
Simulation time 219524611 ps
CPU time 3.96 seconds
Started Jan 24 07:51:51 PM PST 24
Finished Jan 24 07:51:57 PM PST 24
Peak memory 221148 kb
Host smart-bd94f814-ffd0-4e44-add3-7a8c1b08986a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3830832552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3830832552
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3487148928
Short name T205
Test name
Test status
Simulation time 48767795458 ps
CPU time 383.49 seconds
Started Jan 24 09:26:38 PM PST 24
Finished Jan 24 09:33:02 PM PST 24
Peak memory 255788 kb
Host smart-e04a007d-1630-42cc-9b75-ce19eafca3f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487148928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3487148928
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.84190639
Short name T1079
Test name
Test status
Simulation time 3817749596 ps
CPU time 20.78 seconds
Started Jan 24 07:51:40 PM PST 24
Finished Jan 24 07:52:02 PM PST 24
Peak memory 216260 kb
Host smart-95545c4f-04f2-4ad9-b4ff-01221b79905f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84190639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.84190639
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1358845775
Short name T305
Test name
Test status
Simulation time 3603023459 ps
CPU time 12.8 seconds
Started Jan 24 07:51:44 PM PST 24
Finished Jan 24 07:51:58 PM PST 24
Peak memory 216028 kb
Host smart-b1b4a9f7-69ba-484b-91a3-bb2a475e74f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358845775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1358845775
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3381157023
Short name T741
Test name
Test status
Simulation time 185600039 ps
CPU time 3.69 seconds
Started Jan 24 07:51:48 PM PST 24
Finished Jan 24 07:51:53 PM PST 24
Peak memory 207548 kb
Host smart-24138ec5-ffbe-417c-b610-bfe85565ce5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381157023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3381157023
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3156192804
Short name T547
Test name
Test status
Simulation time 39615738 ps
CPU time 0.73 seconds
Started Jan 24 07:51:53 PM PST 24
Finished Jan 24 07:52:00 PM PST 24
Peak memory 204584 kb
Host smart-5da39c1b-76ec-4052-96a3-8c32462a5ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156192804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3156192804
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.4147777267
Short name T247
Test name
Test status
Simulation time 85257244 ps
CPU time 2.25 seconds
Started Jan 24 07:51:51 PM PST 24
Finished Jan 24 07:51:55 PM PST 24
Peak memory 216028 kb
Host smart-f37e0922-36dd-4348-95f8-6ea7e0c78361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147777267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.4147777267
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.326385706
Short name T32
Test name
Test status
Simulation time 13112753 ps
CPU time 0.76 seconds
Started Jan 24 07:52:16 PM PST 24
Finished Jan 24 07:52:18 PM PST 24
Peak memory 204056 kb
Host smart-7c620799-68d3-45cf-a258-86474d7210e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326385706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.326385706
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3392525856
Short name T571
Test name
Test status
Simulation time 8149444660 ps
CPU time 7.67 seconds
Started Jan 24 07:52:13 PM PST 24
Finished Jan 24 07:52:22 PM PST 24
Peak memory 233360 kb
Host smart-8dfa4949-d4dd-4d8d-9e96-c65e157a574a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392525856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3392525856
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.385517801
Short name T478
Test name
Test status
Simulation time 21595933 ps
CPU time 0.79 seconds
Started Jan 24 07:51:56 PM PST 24
Finished Jan 24 07:52:00 PM PST 24
Peak memory 205624 kb
Host smart-b5d05100-dac5-483c-a576-66759e34aa8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385517801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.385517801
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.778281085
Short name T970
Test name
Test status
Simulation time 12169814865 ps
CPU time 56.92 seconds
Started Jan 24 08:18:33 PM PST 24
Finished Jan 24 08:19:31 PM PST 24
Peak memory 250896 kb
Host smart-9578bfe9-606d-4e1a-858d-e154976d6a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778281085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.778281085
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3462943982
Short name T611
Test name
Test status
Simulation time 2681112991 ps
CPU time 35.25 seconds
Started Jan 24 07:52:15 PM PST 24
Finished Jan 24 07:52:51 PM PST 24
Peak memory 255240 kb
Host smart-40b9d27b-b231-42b3-bf41-9163dbb1b334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462943982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3462943982
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3306008424
Short name T177
Test name
Test status
Simulation time 43643092013 ps
CPU time 108.9 seconds
Started Jan 24 08:12:47 PM PST 24
Finished Jan 24 08:14:37 PM PST 24
Peak memory 255264 kb
Host smart-54b3687a-e1bc-4032-90f4-54bbe3d38716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306008424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3306008424
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2592526964
Short name T662
Test name
Test status
Simulation time 9803549023 ps
CPU time 46.1 seconds
Started Jan 24 07:52:11 PM PST 24
Finished Jan 24 07:52:58 PM PST 24
Peak memory 237172 kb
Host smart-2bf47c25-49b0-40fa-9893-8706d8dc1987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592526964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2592526964
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3166609498
Short name T750
Test name
Test status
Simulation time 174646578 ps
CPU time 3.32 seconds
Started Jan 24 07:52:13 PM PST 24
Finished Jan 24 07:52:18 PM PST 24
Peak memory 233336 kb
Host smart-657829aa-e52c-424f-9ab0-f1598b6a5197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166609498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3166609498
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3070158026
Short name T760
Test name
Test status
Simulation time 358656852 ps
CPU time 8.42 seconds
Started Jan 24 07:52:13 PM PST 24
Finished Jan 24 07:52:22 PM PST 24
Peak memory 237448 kb
Host smart-e30ccc53-03fe-4409-ab71-d311801b6012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070158026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3070158026
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.333675862
Short name T677
Test name
Test status
Simulation time 1397149017 ps
CPU time 10.33 seconds
Started Jan 24 07:52:11 PM PST 24
Finished Jan 24 07:52:23 PM PST 24
Peak memory 227932 kb
Host smart-ef14059a-b8a6-450a-8e22-346490d70ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333675862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.333675862
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.894741042
Short name T1038
Test name
Test status
Simulation time 134481143 ps
CPU time 3.07 seconds
Started Jan 24 07:52:08 PM PST 24
Finished Jan 24 07:52:12 PM PST 24
Peak memory 218192 kb
Host smart-ad61da52-5719-445c-b347-013fa146cc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894741042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.894741042
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3250907593
Short name T622
Test name
Test status
Simulation time 918054555 ps
CPU time 3.7 seconds
Started Jan 24 07:52:18 PM PST 24
Finished Jan 24 07:52:23 PM PST 24
Peak memory 215904 kb
Host smart-f7d44add-72d7-4c1a-acc8-ff5adc4a5adb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3250907593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3250907593
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3243418381
Short name T907
Test name
Test status
Simulation time 37884211069 ps
CPU time 192.45 seconds
Started Jan 24 09:54:10 PM PST 24
Finished Jan 24 09:57:24 PM PST 24
Peak memory 216100 kb
Host smart-c5ede7f3-4666-4f24-be7b-d2e6fc14bd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243418381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3243418381
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2568674195
Short name T730
Test name
Test status
Simulation time 29051518744 ps
CPU time 17.11 seconds
Started Jan 24 07:51:56 PM PST 24
Finished Jan 24 07:52:16 PM PST 24
Peak memory 216060 kb
Host smart-0f3af489-e679-4289-891d-04e30cd14686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568674195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2568674195
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2304928809
Short name T889
Test name
Test status
Simulation time 193724736 ps
CPU time 0.98 seconds
Started Jan 24 07:52:07 PM PST 24
Finished Jan 24 07:52:09 PM PST 24
Peak memory 205768 kb
Host smart-7f9f5014-742e-4a59-b572-aba860ff2e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304928809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2304928809
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.4137633116
Short name T437
Test name
Test status
Simulation time 279398291 ps
CPU time 1.01 seconds
Started Jan 24 07:52:12 PM PST 24
Finished Jan 24 07:52:14 PM PST 24
Peak memory 205616 kb
Host smart-7c6766b1-d705-4efa-bdd9-9dd0a17edb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137633116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.4137633116
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.4265414130
Short name T779
Test name
Test status
Simulation time 988646836 ps
CPU time 3.93 seconds
Started Jan 24 07:52:13 PM PST 24
Finished Jan 24 07:52:18 PM PST 24
Peak memory 235800 kb
Host smart-d514da1a-63bc-475c-ace5-69cbe5577b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265414130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.4265414130
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.45595117
Short name T302
Test name
Test status
Simulation time 36609856 ps
CPU time 0.73 seconds
Started Jan 24 07:52:21 PM PST 24
Finished Jan 24 07:52:23 PM PST 24
Peak memory 204452 kb
Host smart-dde6e393-2a9e-4956-b9bd-c54af35fd9ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45595117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.45595117
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.60942104
Short name T304
Test name
Test status
Simulation time 101115910 ps
CPU time 2.41 seconds
Started Jan 24 07:52:32 PM PST 24
Finished Jan 24 07:52:35 PM PST 24
Peak memory 216224 kb
Host smart-72f503a6-3658-4144-90bf-7caf073022dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60942104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.60942104
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1615945498
Short name T420
Test name
Test status
Simulation time 15520011 ps
CPU time 0.75 seconds
Started Jan 24 08:19:10 PM PST 24
Finished Jan 24 08:19:13 PM PST 24
Peak memory 204584 kb
Host smart-3c085819-98de-428f-92ec-054e2f050be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615945498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1615945498
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.4097651174
Short name T175
Test name
Test status
Simulation time 395971725692 ps
CPU time 444.46 seconds
Started Jan 24 07:52:27 PM PST 24
Finished Jan 24 07:59:53 PM PST 24
Peak memory 265176 kb
Host smart-88b439e8-67c4-4716-b6be-4fd5f93f4751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097651174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.4097651174
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2725273661
Short name T765
Test name
Test status
Simulation time 32403275824 ps
CPU time 141.7 seconds
Started Jan 24 07:52:23 PM PST 24
Finished Jan 24 07:54:46 PM PST 24
Peak memory 252492 kb
Host smart-9bc409f2-968a-46f9-a14a-b7ee56fa922b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725273661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2725273661
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3246772225
Short name T856
Test name
Test status
Simulation time 28604653845 ps
CPU time 195.66 seconds
Started Jan 24 07:52:26 PM PST 24
Finished Jan 24 07:55:42 PM PST 24
Peak memory 259924 kb
Host smart-b97c3bc3-0838-4cc7-ba0c-3b94a20d22fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246772225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3246772225
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.638049830
Short name T284
Test name
Test status
Simulation time 6048594834 ps
CPU time 24.04 seconds
Started Jan 24 07:52:32 PM PST 24
Finished Jan 24 07:52:57 PM PST 24
Peak memory 239700 kb
Host smart-fdb9ec37-13b2-4844-83f3-10bf72bc0b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638049830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.638049830
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3352184119
Short name T1039
Test name
Test status
Simulation time 343778925 ps
CPU time 4.79 seconds
Started Jan 24 07:52:23 PM PST 24
Finished Jan 24 07:52:29 PM PST 24
Peak memory 234128 kb
Host smart-eac7010f-b031-4fde-b309-03251bbb77e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352184119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3352184119
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1233525902
Short name T575
Test name
Test status
Simulation time 590511082 ps
CPU time 8.7 seconds
Started Jan 24 07:52:32 PM PST 24
Finished Jan 24 07:52:42 PM PST 24
Peak memory 234688 kb
Host smart-ad022956-3214-4aa3-861d-01425895385f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233525902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1233525902
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3831051370
Short name T976
Test name
Test status
Simulation time 39569616794 ps
CPU time 23.98 seconds
Started Jan 24 07:52:31 PM PST 24
Finished Jan 24 07:52:56 PM PST 24
Peak memory 228556 kb
Host smart-45b62b5e-921e-4c45-bcec-cf218e7a4c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831051370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3831051370
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.441070439
Short name T731
Test name
Test status
Simulation time 307921462 ps
CPU time 2.05 seconds
Started Jan 24 07:52:27 PM PST 24
Finished Jan 24 07:52:30 PM PST 24
Peak memory 215996 kb
Host smart-0427f84d-5d50-48af-8632-dcb3073d6be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441070439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.441070439
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3659112637
Short name T11
Test name
Test status
Simulation time 286548222 ps
CPU time 3.52 seconds
Started Jan 24 07:52:21 PM PST 24
Finished Jan 24 07:52:27 PM PST 24
Peak memory 216048 kb
Host smart-a0b03858-2285-4c67-9522-794410cc8982
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3659112637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3659112637
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.4121624876
Short name T582
Test name
Test status
Simulation time 32846840618 ps
CPU time 272.82 seconds
Started Jan 24 07:52:23 PM PST 24
Finished Jan 24 07:56:57 PM PST 24
Peak memory 257128 kb
Host smart-fbde3ab0-6c67-4c36-9308-ab09cbe2b82b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121624876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.4121624876
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.614784897
Short name T837
Test name
Test status
Simulation time 10113195167 ps
CPU time 51.48 seconds
Started Jan 24 07:52:16 PM PST 24
Finished Jan 24 07:53:08 PM PST 24
Peak memory 216016 kb
Host smart-1930faf8-ef17-4e51-8389-7ac51886db9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614784897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.614784897
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2300039847
Short name T796
Test name
Test status
Simulation time 1534618282 ps
CPU time 1.75 seconds
Started Jan 24 10:28:38 PM PST 24
Finished Jan 24 10:28:47 PM PST 24
Peak memory 205760 kb
Host smart-9aa9c3ec-e669-4438-ac1b-f7acbdcaa87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300039847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2300039847
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1091861792
Short name T1072
Test name
Test status
Simulation time 52417396 ps
CPU time 1.61 seconds
Started Jan 24 09:16:34 PM PST 24
Finished Jan 24 09:16:37 PM PST 24
Peak memory 207500 kb
Host smart-cec8d5f8-a76a-4e89-be45-8410cd318691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091861792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1091861792
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3459958934
Short name T480
Test name
Test status
Simulation time 27877628 ps
CPU time 0.74 seconds
Started Jan 24 07:52:23 PM PST 24
Finished Jan 24 07:52:25 PM PST 24
Peak memory 204560 kb
Host smart-639ef729-d275-4a8c-8b70-4601d42509dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459958934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3459958934
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1067148838
Short name T495
Test name
Test status
Simulation time 2255995597 ps
CPU time 9.36 seconds
Started Jan 24 07:52:23 PM PST 24
Finished Jan 24 07:52:33 PM PST 24
Peak memory 232632 kb
Host smart-16386c36-cc3d-4242-aff7-15b9493a5ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067148838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1067148838
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.191397132
Short name T524
Test name
Test status
Simulation time 17884163 ps
CPU time 0.7 seconds
Started Jan 24 08:36:11 PM PST 24
Finished Jan 24 08:36:12 PM PST 24
Peak memory 204432 kb
Host smart-7151bda3-b019-43b1-b2ab-8af9f250f464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191397132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.191397132
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2369328045
Short name T842
Test name
Test status
Simulation time 75042734 ps
CPU time 2.8 seconds
Started Jan 24 07:46:15 PM PST 24
Finished Jan 24 07:46:19 PM PST 24
Peak memory 232800 kb
Host smart-534fd0d7-09eb-4c47-bc6d-22763a023249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369328045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2369328045
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2498567381
Short name T10
Test name
Test status
Simulation time 15370868 ps
CPU time 0.75 seconds
Started Jan 24 07:46:04 PM PST 24
Finished Jan 24 07:46:06 PM PST 24
Peak memory 204232 kb
Host smart-3669d0b9-6152-4882-bb7d-76b681550a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498567381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2498567381
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.210447533
Short name T522
Test name
Test status
Simulation time 7746991143 ps
CPU time 66.05 seconds
Started Jan 24 07:46:12 PM PST 24
Finished Jan 24 07:47:20 PM PST 24
Peak memory 257024 kb
Host smart-91401022-f998-45fb-aae6-f2e1100028bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210447533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.210447533
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3958772340
Short name T244
Test name
Test status
Simulation time 27141584344 ps
CPU time 77.59 seconds
Started Jan 24 07:46:07 PM PST 24
Finished Jan 24 07:47:26 PM PST 24
Peak memory 264620 kb
Host smart-3eb480f5-5d81-4de4-a59d-84beb96b8d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958772340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3958772340
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2572830562
Short name T120
Test name
Test status
Simulation time 32552649707 ps
CPU time 106.28 seconds
Started Jan 24 07:46:17 PM PST 24
Finished Jan 24 07:48:04 PM PST 24
Peak memory 265204 kb
Host smart-c32a479b-9d95-4aed-b9c1-c90d9c74128a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572830562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2572830562
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.4032977857
Short name T681
Test name
Test status
Simulation time 837858943 ps
CPU time 7.4 seconds
Started Jan 24 07:46:17 PM PST 24
Finished Jan 24 07:46:25 PM PST 24
Peak memory 233824 kb
Host smart-fac9cbe7-481a-42df-b58a-5105e304f15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032977857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.4032977857
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.4162137538
Short name T800
Test name
Test status
Simulation time 11303482220 ps
CPU time 4.95 seconds
Started Jan 24 07:46:08 PM PST 24
Finished Jan 24 07:46:15 PM PST 24
Peak memory 232680 kb
Host smart-ce625212-a8a1-48ab-8f4e-140c2de3710f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162137538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.4162137538
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.344566778
Short name T893
Test name
Test status
Simulation time 6235330614 ps
CPU time 23.13 seconds
Started Jan 24 07:46:15 PM PST 24
Finished Jan 24 07:46:39 PM PST 24
Peak memory 225468 kb
Host smart-7c7a160d-b7f5-444d-98ea-48a59e29a68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344566778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.344566778
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2436539504
Short name T446
Test name
Test status
Simulation time 51229022 ps
CPU time 1.05 seconds
Started Jan 24 07:46:06 PM PST 24
Finished Jan 24 07:46:09 PM PST 24
Peak memory 215772 kb
Host smart-d8318b34-8897-40a1-9e0a-25ff014236f9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436539504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2436539504
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1302580421
Short name T234
Test name
Test status
Simulation time 7756954114 ps
CPU time 13.9 seconds
Started Jan 24 07:46:04 PM PST 24
Finished Jan 24 07:46:20 PM PST 24
Peak memory 232092 kb
Host smart-7a249b48-fee8-4478-8182-99968181429c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302580421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1302580421
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1352411517
Short name T588
Test name
Test status
Simulation time 310059407 ps
CPU time 5.66 seconds
Started Jan 24 07:46:12 PM PST 24
Finished Jan 24 07:46:20 PM PST 24
Peak memory 232708 kb
Host smart-8d3dc65f-78fb-4374-a9b6-3b8f7059647a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352411517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1352411517
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.1401543370
Short name T1007
Test name
Test status
Simulation time 15298778 ps
CPU time 0.72 seconds
Started Jan 24 07:46:04 PM PST 24
Finished Jan 24 07:46:06 PM PST 24
Peak memory 215876 kb
Host smart-fbde04f8-b719-4996-be43-e46d26e4f1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401543370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.1401543370
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1584395233
Short name T756
Test name
Test status
Simulation time 2560745980 ps
CPU time 4.16 seconds
Started Jan 24 07:46:09 PM PST 24
Finished Jan 24 07:46:15 PM PST 24
Peak memory 216164 kb
Host smart-d645a0b2-2496-45a2-9263-212be658de12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1584395233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1584395233
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1772920115
Short name T52
Test name
Test status
Simulation time 85706050 ps
CPU time 1.22 seconds
Started Jan 24 07:46:15 PM PST 24
Finished Jan 24 07:46:18 PM PST 24
Peak memory 234532 kb
Host smart-ea82906f-92f8-4276-b821-aa6b7155e241
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772920115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1772920115
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2217680577
Short name T628
Test name
Test status
Simulation time 35485230759 ps
CPU time 211.4 seconds
Started Jan 24 07:46:12 PM PST 24
Finished Jan 24 07:49:45 PM PST 24
Peak memory 248932 kb
Host smart-ea239c98-474f-453d-a380-2abfb53b9a35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217680577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2217680577
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2844927912
Short name T287
Test name
Test status
Simulation time 19601550051 ps
CPU time 106.21 seconds
Started Jan 24 07:46:15 PM PST 24
Finished Jan 24 07:48:03 PM PST 24
Peak memory 220284 kb
Host smart-2532be33-8595-4986-a329-27bb4a782ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844927912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2844927912
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2058418591
Short name T646
Test name
Test status
Simulation time 1697511964 ps
CPU time 9.85 seconds
Started Jan 24 07:46:08 PM PST 24
Finished Jan 24 07:46:20 PM PST 24
Peak memory 207260 kb
Host smart-6b519610-1e3d-4cce-bbf6-5984ae5e4d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058418591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2058418591
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3860569726
Short name T569
Test name
Test status
Simulation time 1824713225 ps
CPU time 6.12 seconds
Started Jan 24 08:17:14 PM PST 24
Finished Jan 24 08:17:21 PM PST 24
Peak memory 216252 kb
Host smart-cdc4e9ee-010a-4e26-9ab1-3dbe8d051dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860569726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3860569726
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1995432278
Short name T527
Test name
Test status
Simulation time 121443567 ps
CPU time 0.83 seconds
Started Jan 24 07:46:12 PM PST 24
Finished Jan 24 07:46:15 PM PST 24
Peak memory 204604 kb
Host smart-e4457f12-27d7-4ec4-9202-5fb9b2281c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995432278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1995432278
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2198747081
Short name T807
Test name
Test status
Simulation time 26778642878 ps
CPU time 10.93 seconds
Started Jan 24 07:46:12 PM PST 24
Finished Jan 24 07:46:25 PM PST 24
Peak memory 218308 kb
Host smart-20caab94-591a-4a1d-8843-5bcc51b8159b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198747081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2198747081
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.683168273
Short name T523
Test name
Test status
Simulation time 16856067 ps
CPU time 0.75 seconds
Started Jan 24 07:52:47 PM PST 24
Finished Jan 24 07:52:49 PM PST 24
Peak memory 203852 kb
Host smart-05961511-8ac2-41c6-8511-19f58c430290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683168273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.683168273
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1417547321
Short name T493
Test name
Test status
Simulation time 3896122419 ps
CPU time 12.26 seconds
Started Jan 24 07:52:33 PM PST 24
Finished Jan 24 07:52:46 PM PST 24
Peak memory 233384 kb
Host smart-86a83809-288a-4c6b-bfed-d6ebb699fbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417547321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1417547321
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1584983165
Short name T949
Test name
Test status
Simulation time 90091013 ps
CPU time 0.74 seconds
Started Jan 24 08:43:54 PM PST 24
Finished Jan 24 08:44:05 PM PST 24
Peak memory 204280 kb
Host smart-9051a698-a737-4605-b2b6-96aa6b2d5588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584983165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1584983165
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2718605998
Short name T259
Test name
Test status
Simulation time 71514917368 ps
CPU time 304.59 seconds
Started Jan 24 07:52:26 PM PST 24
Finished Jan 24 07:57:31 PM PST 24
Peak memory 261336 kb
Host smart-08e1dcf5-1b46-4e91-84ad-7afc650e140f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718605998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2718605998
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3912620277
Short name T275
Test name
Test status
Simulation time 211647545920 ps
CPU time 487.25 seconds
Started Jan 24 07:52:31 PM PST 24
Finished Jan 24 08:00:39 PM PST 24
Peak memory 256680 kb
Host smart-28b7502e-8ba6-41b9-bc6f-5cb90cead091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912620277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3912620277
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3240390849
Short name T847
Test name
Test status
Simulation time 23756640474 ps
CPU time 29.4 seconds
Started Jan 24 07:52:31 PM PST 24
Finished Jan 24 07:53:01 PM PST 24
Peak memory 231128 kb
Host smart-52f7f48d-2fdf-48d4-8be9-efc321ded0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240390849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3240390849
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1949496671
Short name T867
Test name
Test status
Simulation time 2384127423 ps
CPU time 6.63 seconds
Started Jan 24 07:52:32 PM PST 24
Finished Jan 24 07:52:40 PM PST 24
Peak memory 219764 kb
Host smart-40f3e8df-caa7-4fdd-a08d-da8703b0a425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949496671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1949496671
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.910600089
Short name T680
Test name
Test status
Simulation time 9873920833 ps
CPU time 32.16 seconds
Started Jan 24 07:52:35 PM PST 24
Finished Jan 24 07:53:08 PM PST 24
Peak memory 233544 kb
Host smart-dd340435-d3e7-4f2d-b4ca-0768539be18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910600089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.910600089
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2465774797
Short name T755
Test name
Test status
Simulation time 78110302 ps
CPU time 2.51 seconds
Started Jan 24 07:52:32 PM PST 24
Finished Jan 24 07:52:36 PM PST 24
Peak memory 216108 kb
Host smart-b196de43-bbc9-4e70-b275-f4e6689535d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465774797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2465774797
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.104015240
Short name T733
Test name
Test status
Simulation time 38790241927 ps
CPU time 24.97 seconds
Started Jan 24 07:52:22 PM PST 24
Finished Jan 24 07:52:49 PM PST 24
Peak memory 218468 kb
Host smart-424a1f71-d798-458b-8ddc-0f75e7f28966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104015240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.104015240
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2490065606
Short name T675
Test name
Test status
Simulation time 1380415839 ps
CPU time 4.53 seconds
Started Jan 24 07:52:32 PM PST 24
Finished Jan 24 07:52:38 PM PST 24
Peak memory 215908 kb
Host smart-8858d50a-b55c-40ed-82ed-299f5d07053d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2490065606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2490065606
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.666613032
Short name T172
Test name
Test status
Simulation time 122506783462 ps
CPU time 271.29 seconds
Started Jan 24 07:52:37 PM PST 24
Finished Jan 24 07:57:09 PM PST 24
Peak memory 262568 kb
Host smart-086bb59a-5f9c-496f-aa7a-d1e1aa2016c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666613032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.666613032
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2438517913
Short name T454
Test name
Test status
Simulation time 2161031898 ps
CPU time 5.44 seconds
Started Jan 24 07:52:32 PM PST 24
Finished Jan 24 07:52:38 PM PST 24
Peak memory 216064 kb
Host smart-42bda187-80c8-4a75-84b8-7b65632b2919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438517913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2438517913
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2989230637
Short name T689
Test name
Test status
Simulation time 2044610874 ps
CPU time 4.33 seconds
Started Jan 24 07:52:27 PM PST 24
Finished Jan 24 07:52:33 PM PST 24
Peak memory 207248 kb
Host smart-122cf34d-b382-4a13-afcc-f7ba62e84d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989230637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2989230637
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.287469407
Short name T60
Test name
Test status
Simulation time 179747730 ps
CPU time 2.46 seconds
Started Jan 24 07:52:25 PM PST 24
Finished Jan 24 07:52:28 PM PST 24
Peak memory 216236 kb
Host smart-2c86ebda-b075-4719-9409-419934fe5b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287469407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.287469407
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3373218136
Short name T787
Test name
Test status
Simulation time 113007764 ps
CPU time 1 seconds
Started Jan 24 07:52:32 PM PST 24
Finished Jan 24 07:52:34 PM PST 24
Peak memory 203628 kb
Host smart-ba77b4cd-626e-4f70-b2a4-b9c10e1c677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373218136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3373218136
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2747249079
Short name T217
Test name
Test status
Simulation time 8898554550 ps
CPU time 32.47 seconds
Started Jan 24 07:52:35 PM PST 24
Finished Jan 24 07:53:08 PM PST 24
Peak memory 237600 kb
Host smart-107422a4-b024-428b-bce1-3a10251b31b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747249079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2747249079
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1553885670
Short name T1000
Test name
Test status
Simulation time 10887516 ps
CPU time 0.68 seconds
Started Jan 24 07:52:59 PM PST 24
Finished Jan 24 07:53:01 PM PST 24
Peak memory 203556 kb
Host smart-333c6936-779b-47f2-984a-c0191d287ff3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553885670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1553885670
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2430338428
Short name T213
Test name
Test status
Simulation time 330228928 ps
CPU time 3.95 seconds
Started Jan 24 07:52:45 PM PST 24
Finished Jan 24 07:52:50 PM PST 24
Peak memory 235324 kb
Host smart-7a543819-d98a-497d-b446-3cc624b8307e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430338428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2430338428
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1528243712
Short name T585
Test name
Test status
Simulation time 16050013 ps
CPU time 0.75 seconds
Started Jan 24 07:52:47 PM PST 24
Finished Jan 24 07:52:49 PM PST 24
Peak memory 204276 kb
Host smart-fbac2464-765c-4d27-9e07-bc5a93830835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528243712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1528243712
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2091764950
Short name T983
Test name
Test status
Simulation time 96838829417 ps
CPU time 246.33 seconds
Started Jan 24 07:52:52 PM PST 24
Finished Jan 24 07:56:59 PM PST 24
Peak memory 265308 kb
Host smart-7a068bbe-24dc-46eb-ac32-5754c0e8ecc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091764950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2091764950
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.4195131123
Short name T595
Test name
Test status
Simulation time 38616323901 ps
CPU time 87.7 seconds
Started Jan 24 07:52:47 PM PST 24
Finished Jan 24 07:54:15 PM PST 24
Peak memory 232528 kb
Host smart-5899d7c9-95e1-4dd8-b930-d263a256c720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195131123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.4195131123
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3102842785
Short name T473
Test name
Test status
Simulation time 4560771826 ps
CPU time 13.81 seconds
Started Jan 24 07:52:54 PM PST 24
Finished Jan 24 07:53:09 PM PST 24
Peak memory 234004 kb
Host smart-b741e541-aba8-4ede-acad-8f08828feb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102842785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3102842785
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2446768894
Short name T182
Test name
Test status
Simulation time 4667562963 ps
CPU time 3.83 seconds
Started Jan 24 07:52:55 PM PST 24
Finished Jan 24 07:53:00 PM PST 24
Peak memory 217704 kb
Host smart-d9020324-b1ad-4114-ba94-4d51c4dbf8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446768894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2446768894
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1332075154
Short name T241
Test name
Test status
Simulation time 876681541 ps
CPU time 9.23 seconds
Started Jan 24 07:52:48 PM PST 24
Finished Jan 24 07:52:59 PM PST 24
Peak memory 242852 kb
Host smart-5ed075b7-df0e-49d5-9904-14fa8e6d73fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332075154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1332075154
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.4264484510
Short name T280
Test name
Test status
Simulation time 1556483218 ps
CPU time 10.37 seconds
Started Jan 24 07:52:47 PM PST 24
Finished Jan 24 07:52:58 PM PST 24
Peak memory 227792 kb
Host smart-ae2ef5da-04c1-497e-91b3-02403339e18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264484510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.4264484510
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.327588248
Short name T744
Test name
Test status
Simulation time 6100165534 ps
CPU time 11.88 seconds
Started Jan 24 07:52:43 PM PST 24
Finished Jan 24 07:52:55 PM PST 24
Peak memory 232936 kb
Host smart-a8570840-1f25-4c35-bd18-38c4b833dca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327588248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.327588248
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.440126322
Short name T127
Test name
Test status
Simulation time 468430566 ps
CPU time 4.24 seconds
Started Jan 24 07:52:47 PM PST 24
Finished Jan 24 07:52:52 PM PST 24
Peak memory 216124 kb
Host smart-4732fe57-5b08-4a6d-8447-c015f9916ff6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=440126322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.440126322
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3126299526
Short name T648
Test name
Test status
Simulation time 4349202134 ps
CPU time 20.5 seconds
Started Jan 24 07:52:43 PM PST 24
Finished Jan 24 07:53:04 PM PST 24
Peak memory 218336 kb
Host smart-27615494-4230-4e3e-976a-22bee794ccfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126299526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3126299526
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1479164532
Short name T457
Test name
Test status
Simulation time 64256530385 ps
CPU time 24.84 seconds
Started Jan 24 07:52:43 PM PST 24
Finished Jan 24 07:53:08 PM PST 24
Peak memory 216040 kb
Host smart-691eafd0-e878-4d06-85ec-f4c19d430145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479164532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1479164532
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3905407915
Short name T742
Test name
Test status
Simulation time 65515567 ps
CPU time 0.84 seconds
Started Jan 24 07:52:43 PM PST 24
Finished Jan 24 07:52:45 PM PST 24
Peak memory 205248 kb
Host smart-34ed9146-7547-492b-9051-9e8560dedfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905407915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3905407915
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3616234817
Short name T1017
Test name
Test status
Simulation time 124002559 ps
CPU time 0.83 seconds
Started Jan 24 07:52:38 PM PST 24
Finished Jan 24 07:52:40 PM PST 24
Peak memory 204596 kb
Host smart-f3665695-b3e7-446a-884c-6b9c49c38e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616234817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3616234817
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2652200586
Short name T144
Test name
Test status
Simulation time 176894629 ps
CPU time 2.26 seconds
Started Jan 24 07:52:49 PM PST 24
Finished Jan 24 07:52:52 PM PST 24
Peak memory 216028 kb
Host smart-583d3eeb-9647-438b-a673-dc4d72ec503b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652200586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2652200586
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1031981453
Short name T1009
Test name
Test status
Simulation time 42699376 ps
CPU time 0.71 seconds
Started Jan 24 09:20:35 PM PST 24
Finished Jan 24 09:20:36 PM PST 24
Peak memory 203520 kb
Host smart-1afdd469-973a-48b0-9299-aa38f4b31875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031981453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1031981453
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1818483589
Short name T726
Test name
Test status
Simulation time 43964628 ps
CPU time 2.48 seconds
Started Jan 24 09:47:01 PM PST 24
Finished Jan 24 09:47:05 PM PST 24
Peak memory 232424 kb
Host smart-84a98256-8c20-489f-a5d4-b85da8bd0ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818483589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1818483589
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3671238359
Short name T789
Test name
Test status
Simulation time 62095898 ps
CPU time 0.82 seconds
Started Jan 24 07:52:59 PM PST 24
Finished Jan 24 07:53:01 PM PST 24
Peak memory 205608 kb
Host smart-837dcea6-dbc9-4b3f-af55-4445176bb4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671238359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3671238359
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.4204824934
Short name T1071
Test name
Test status
Simulation time 97925025693 ps
CPU time 77.76 seconds
Started Jan 24 07:53:08 PM PST 24
Finished Jan 24 07:54:26 PM PST 24
Peak memory 249924 kb
Host smart-72104ad9-ea6c-4f17-91cd-1d3c97d7043a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204824934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.4204824934
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3183465447
Short name T142
Test name
Test status
Simulation time 13277291473 ps
CPU time 121.42 seconds
Started Jan 24 08:57:53 PM PST 24
Finished Jan 24 08:59:58 PM PST 24
Peak memory 263408 kb
Host smart-7854546e-a725-4c3f-b5c2-267b315e9f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183465447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3183465447
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3199674093
Short name T37
Test name
Test status
Simulation time 36071820994 ps
CPU time 283.75 seconds
Started Jan 24 08:27:19 PM PST 24
Finished Jan 24 08:32:03 PM PST 24
Peak memory 261740 kb
Host smart-7beafe17-a47a-49f7-bcb8-546f06568bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199674093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3199674093
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.4188563233
Short name T752
Test name
Test status
Simulation time 30373622003 ps
CPU time 34.32 seconds
Started Jan 24 08:52:25 PM PST 24
Finished Jan 24 08:53:00 PM PST 24
Peak memory 248544 kb
Host smart-20bf8b38-121b-4cd7-b955-7985ddc9dbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188563233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4188563233
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1114683332
Short name T962
Test name
Test status
Simulation time 221764489 ps
CPU time 3.48 seconds
Started Jan 24 07:52:58 PM PST 24
Finished Jan 24 07:53:02 PM PST 24
Peak memory 232796 kb
Host smart-ef764a62-e04a-4c82-b60a-a0e63be01763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114683332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1114683332
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3214926992
Short name T803
Test name
Test status
Simulation time 10876524019 ps
CPU time 17.7 seconds
Started Jan 24 07:53:04 PM PST 24
Finished Jan 24 07:53:24 PM PST 24
Peak memory 228376 kb
Host smart-d21805da-25d3-4874-8b9d-ac16d2cae94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214926992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3214926992
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1339205627
Short name T262
Test name
Test status
Simulation time 1588716625 ps
CPU time 10.26 seconds
Started Jan 24 08:20:06 PM PST 24
Finished Jan 24 08:20:17 PM PST 24
Peak memory 231860 kb
Host smart-4c036a98-2596-4e46-b6cb-d05f3ab22d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339205627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1339205627
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3450482386
Short name T489
Test name
Test status
Simulation time 635675843 ps
CPU time 8.79 seconds
Started Jan 24 07:52:53 PM PST 24
Finished Jan 24 07:53:02 PM PST 24
Peak memory 239876 kb
Host smart-b90cda08-d50b-4aa6-a727-4d1edde76ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450482386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3450482386
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.987344990
Short name T464
Test name
Test status
Simulation time 720343739 ps
CPU time 3.73 seconds
Started Jan 24 07:53:11 PM PST 24
Finished Jan 24 07:53:15 PM PST 24
Peak memory 221752 kb
Host smart-5c8c18cb-39f7-40de-bbb9-37eddae721d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=987344990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.987344990
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1322118804
Short name T654
Test name
Test status
Simulation time 80520212919 ps
CPU time 160.9 seconds
Started Jan 24 07:53:05 PM PST 24
Finished Jan 24 07:55:47 PM PST 24
Peak memory 240248 kb
Host smart-180fd684-c33a-4f4b-8f8b-c83951b8e163
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322118804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1322118804
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2797437643
Short name T447
Test name
Test status
Simulation time 2492862945 ps
CPU time 23.9 seconds
Started Jan 24 07:52:55 PM PST 24
Finished Jan 24 07:53:21 PM PST 24
Peak memory 216296 kb
Host smart-375b8dd6-c78c-40ae-8ef9-b782cb29d200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797437643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2797437643
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1496812476
Short name T1060
Test name
Test status
Simulation time 2718229522 ps
CPU time 7.97 seconds
Started Jan 24 07:52:53 PM PST 24
Finished Jan 24 07:53:01 PM PST 24
Peak memory 216000 kb
Host smart-c23600ec-9698-4f8d-b2e2-29622a00faea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496812476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1496812476
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.4031560091
Short name T2
Test name
Test status
Simulation time 142690005 ps
CPU time 1.7 seconds
Started Jan 24 07:52:54 PM PST 24
Finished Jan 24 07:52:56 PM PST 24
Peak memory 207268 kb
Host smart-ffba6d49-baf5-4723-a773-d9ae5e577a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031560091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.4031560091
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.382036135
Short name T22
Test name
Test status
Simulation time 13340149 ps
CPU time 0.74 seconds
Started Jan 24 07:52:59 PM PST 24
Finished Jan 24 07:53:01 PM PST 24
Peak memory 204604 kb
Host smart-970f980e-1b6b-4b26-bfcc-e075b58ccea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382036135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.382036135
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.536351576
Short name T42
Test name
Test status
Simulation time 4633021091 ps
CPU time 11.1 seconds
Started Jan 24 07:53:05 PM PST 24
Finished Jan 24 07:53:18 PM PST 24
Peak memory 233204 kb
Host smart-9a90b8e0-4f53-4330-aa52-f542a14ad9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536351576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.536351576
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4066180145
Short name T529
Test name
Test status
Simulation time 17547352 ps
CPU time 0.69 seconds
Started Jan 24 07:53:32 PM PST 24
Finished Jan 24 07:53:34 PM PST 24
Peak memory 204140 kb
Host smart-068d1372-9ee3-4629-bf13-b0cc933496b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066180145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4066180145
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2288501716
Short name T859
Test name
Test status
Simulation time 646763012 ps
CPU time 4.35 seconds
Started Jan 24 08:34:11 PM PST 24
Finished Jan 24 08:34:16 PM PST 24
Peak memory 233076 kb
Host smart-a5a2f0b1-ad2e-403c-a065-3b28ca7f9a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288501716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2288501716
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1194810579
Short name T301
Test name
Test status
Simulation time 46255636 ps
CPU time 0.76 seconds
Started Jan 24 07:53:15 PM PST 24
Finished Jan 24 07:53:16 PM PST 24
Peak memory 205288 kb
Host smart-ff589939-b824-426b-98fd-31deaf88785c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194810579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1194810579
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3626699204
Short name T705
Test name
Test status
Simulation time 477785533888 ps
CPU time 196.9 seconds
Started Jan 24 07:53:17 PM PST 24
Finished Jan 24 07:56:35 PM PST 24
Peak memory 255644 kb
Host smart-10bbc737-cbe2-48cb-b859-6bb4c1314812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626699204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3626699204
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2963474640
Short name T123
Test name
Test status
Simulation time 54100816880 ps
CPU time 413.69 seconds
Started Jan 24 09:18:54 PM PST 24
Finished Jan 24 09:25:49 PM PST 24
Peak memory 252272 kb
Host smart-f680c272-b9d3-4b18-9b20-befcfb5ea83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963474640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2963474640
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.519411301
Short name T545
Test name
Test status
Simulation time 1052709863 ps
CPU time 12.03 seconds
Started Jan 24 07:53:23 PM PST 24
Finished Jan 24 07:53:36 PM PST 24
Peak memory 232148 kb
Host smart-3118ecb2-c338-4a8b-8764-31103f231944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519411301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.519411301
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2899060761
Short name T708
Test name
Test status
Simulation time 3748265276 ps
CPU time 12.56 seconds
Started Jan 24 07:53:15 PM PST 24
Finished Jan 24 07:53:29 PM PST 24
Peak memory 234204 kb
Host smart-38a5f1fb-a19e-40bd-8ee2-c53261eeee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899060761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2899060761
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.519491913
Short name T240
Test name
Test status
Simulation time 727725675 ps
CPU time 11.35 seconds
Started Jan 24 07:53:15 PM PST 24
Finished Jan 24 07:53:28 PM PST 24
Peak memory 231968 kb
Host smart-e924ad1e-16da-46a2-80c5-6a52d15710e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519491913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.519491913
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.305135608
Short name T715
Test name
Test status
Simulation time 359017273 ps
CPU time 5.55 seconds
Started Jan 24 07:53:15 PM PST 24
Finished Jan 24 07:53:22 PM PST 24
Peak memory 238052 kb
Host smart-7e65a764-798f-42b3-95c9-abd43d264545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305135608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.305135608
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2464379928
Short name T221
Test name
Test status
Simulation time 1256475307 ps
CPU time 3.49 seconds
Started Jan 24 07:58:08 PM PST 24
Finished Jan 24 07:58:13 PM PST 24
Peak memory 217052 kb
Host smart-cbf60d41-0be5-45f3-b62f-9226f1119f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464379928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2464379928
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2041013540
Short name T879
Test name
Test status
Simulation time 1158598270 ps
CPU time 4.12 seconds
Started Jan 24 08:38:39 PM PST 24
Finished Jan 24 08:38:44 PM PST 24
Peak memory 221136 kb
Host smart-c92ded6b-081a-482f-a8df-8149d1dbf0d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2041013540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2041013540
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.389651587
Short name T849
Test name
Test status
Simulation time 105633144 ps
CPU time 0.92 seconds
Started Jan 25 01:09:21 AM PST 24
Finished Jan 25 01:09:23 AM PST 24
Peak memory 205640 kb
Host smart-dddf7592-201a-4233-b5ca-c3dd94317cd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389651587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.389651587
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1630041671
Short name T618
Test name
Test status
Simulation time 182896650886 ps
CPU time 222.06 seconds
Started Jan 24 07:53:11 PM PST 24
Finished Jan 24 07:56:54 PM PST 24
Peak memory 216168 kb
Host smart-d42b3b5d-2b1d-4231-8099-460ce214b43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630041671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1630041671
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.179343537
Short name T56
Test name
Test status
Simulation time 7865960762 ps
CPU time 21.14 seconds
Started Jan 24 07:53:15 PM PST 24
Finished Jan 24 07:53:38 PM PST 24
Peak memory 216000 kb
Host smart-155c54e1-36e6-4e72-9db0-79431f02713c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179343537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.179343537
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.867433253
Short name T598
Test name
Test status
Simulation time 122264143 ps
CPU time 3.57 seconds
Started Jan 24 07:53:14 PM PST 24
Finished Jan 24 07:53:19 PM PST 24
Peak memory 207148 kb
Host smart-455a989c-fd76-4e15-b97e-a777a3b5795c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867433253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.867433253
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2969522807
Short name T759
Test name
Test status
Simulation time 68468111 ps
CPU time 1 seconds
Started Jan 24 07:53:11 PM PST 24
Finished Jan 24 07:53:13 PM PST 24
Peak memory 205588 kb
Host smart-4cb47c86-10fd-4d67-96dc-d940cb94279c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969522807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2969522807
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3003553530
Short name T586
Test name
Test status
Simulation time 2177023802 ps
CPU time 16.92 seconds
Started Jan 24 07:53:12 PM PST 24
Finished Jan 24 07:53:30 PM PST 24
Peak memory 242772 kb
Host smart-3508c851-2219-4901-acfa-9c3223763e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003553530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3003553530
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.744946480
Short name T751
Test name
Test status
Simulation time 23732963 ps
CPU time 0.7 seconds
Started Jan 24 07:53:32 PM PST 24
Finished Jan 24 07:53:34 PM PST 24
Peak memory 204428 kb
Host smart-83684f49-b13f-4e64-a664-a3865ca3f70f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744946480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.744946480
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1763742044
Short name T436
Test name
Test status
Simulation time 326823715 ps
CPU time 2.45 seconds
Started Jan 24 07:53:41 PM PST 24
Finished Jan 24 07:53:44 PM PST 24
Peak memory 216192 kb
Host smart-2c07c64a-c345-4a7c-b79c-46591f2747d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763742044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1763742044
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1842632009
Short name T984
Test name
Test status
Simulation time 33291797 ps
CPU time 0.76 seconds
Started Jan 24 07:53:33 PM PST 24
Finished Jan 24 07:53:35 PM PST 24
Peak memory 204572 kb
Host smart-6b15002d-230b-4e0d-bdf6-e0029c8f8663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842632009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1842632009
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2330658131
Short name T486
Test name
Test status
Simulation time 18048658565 ps
CPU time 182.86 seconds
Started Jan 24 07:53:41 PM PST 24
Finished Jan 24 07:56:45 PM PST 24
Peak memory 262580 kb
Host smart-92093e60-7488-4cef-b072-43a0e94539b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330658131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2330658131
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.238092111
Short name T254
Test name
Test status
Simulation time 53239946552 ps
CPU time 232.32 seconds
Started Jan 24 07:53:33 PM PST 24
Finished Jan 24 07:57:27 PM PST 24
Peak memory 258600 kb
Host smart-aea006ca-4dba-4255-9ef1-227986980700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238092111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.238092111
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4269451706
Short name T988
Test name
Test status
Simulation time 2505011331 ps
CPU time 4.14 seconds
Started Jan 24 07:53:33 PM PST 24
Finished Jan 24 07:53:38 PM PST 24
Peak memory 232764 kb
Host smart-a0bef8ef-579d-45ac-967e-af9a6cf494f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269451706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4269451706
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.335489026
Short name T882
Test name
Test status
Simulation time 10142782277 ps
CPU time 10.3 seconds
Started Jan 24 07:53:33 PM PST 24
Finished Jan 24 07:53:45 PM PST 24
Peak memory 224124 kb
Host smart-390f512a-aa0d-4669-91f9-7eac460a6ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335489026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.335489026
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.41269371
Short name T906
Test name
Test status
Simulation time 7263690389 ps
CPU time 20.19 seconds
Started Jan 24 07:53:28 PM PST 24
Finished Jan 24 07:53:49 PM PST 24
Peak memory 233764 kb
Host smart-0eaff56a-5a21-487d-994c-5ca0020bd010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41269371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.41269371
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3568776022
Short name T1058
Test name
Test status
Simulation time 37707085388 ps
CPU time 25.73 seconds
Started Jan 24 07:53:25 PM PST 24
Finished Jan 24 07:53:51 PM PST 24
Peak memory 228720 kb
Host smart-017ce7ca-f67b-423d-a0e2-d9566c0a9014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568776022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3568776022
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.98688524
Short name T573
Test name
Test status
Simulation time 146427276 ps
CPU time 3.87 seconds
Started Jan 24 07:53:32 PM PST 24
Finished Jan 24 07:53:37 PM PST 24
Peak memory 221244 kb
Host smart-90cecbef-d11f-4811-a34a-8898789b642e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=98688524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direc
t.98688524
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2120517385
Short name T729
Test name
Test status
Simulation time 34875062626 ps
CPU time 48.14 seconds
Started Jan 24 07:53:33 PM PST 24
Finished Jan 24 07:54:22 PM PST 24
Peak memory 216376 kb
Host smart-8ac37971-03b0-448b-8140-b77af8c6d022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120517385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2120517385
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.108180180
Short name T306
Test name
Test status
Simulation time 4395717280 ps
CPU time 4.67 seconds
Started Jan 24 07:53:29 PM PST 24
Finished Jan 24 07:53:34 PM PST 24
Peak memory 215840 kb
Host smart-1d068c18-0ce9-45f1-989d-5de65cfce4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108180180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.108180180
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.257331249
Short name T707
Test name
Test status
Simulation time 216758636 ps
CPU time 2.15 seconds
Started Jan 24 07:53:27 PM PST 24
Finished Jan 24 07:53:30 PM PST 24
Peak memory 208080 kb
Host smart-c9d1700a-8a93-4a99-a364-d892947b6d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257331249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.257331249
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1107102315
Short name T943
Test name
Test status
Simulation time 71473274 ps
CPU time 0.89 seconds
Started Jan 24 07:53:29 PM PST 24
Finished Jan 24 07:53:31 PM PST 24
Peak memory 204572 kb
Host smart-7755c3e0-c0b5-47cc-973f-aa84b139b17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107102315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1107102315
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1410444328
Short name T12
Test name
Test status
Simulation time 20224224728 ps
CPU time 22.05 seconds
Started Jan 24 07:53:32 PM PST 24
Finished Jan 24 07:53:55 PM PST 24
Peak memory 233384 kb
Host smart-13116f9a-8a42-4140-9f8c-e4a72511da52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410444328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1410444328
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.68826864
Short name T482
Test name
Test status
Simulation time 51381941 ps
CPU time 0.7 seconds
Started Jan 24 08:20:50 PM PST 24
Finished Jan 24 08:20:53 PM PST 24
Peak memory 204112 kb
Host smart-9444e558-4667-4313-a070-7a5449798e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68826864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.68826864
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2949941662
Short name T876
Test name
Test status
Simulation time 76802563 ps
CPU time 2.96 seconds
Started Jan 24 07:53:47 PM PST 24
Finished Jan 24 07:53:50 PM PST 24
Peak memory 233928 kb
Host smart-006a90b7-b063-4664-b831-c7d6f50844bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949941662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2949941662
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2256438667
Short name T492
Test name
Test status
Simulation time 24174235 ps
CPU time 0.83 seconds
Started Jan 24 07:53:41 PM PST 24
Finished Jan 24 07:53:43 PM PST 24
Peak memory 205104 kb
Host smart-de206b18-e014-4b89-a9de-4c64e302bf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256438667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2256438667
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3189544508
Short name T979
Test name
Test status
Simulation time 28266424960 ps
CPU time 52.31 seconds
Started Jan 24 07:53:51 PM PST 24
Finished Jan 24 07:54:48 PM PST 24
Peak memory 248852 kb
Host smart-7543fe1f-c40e-4c4f-af72-4970a5368086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189544508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3189544508
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.4143896120
Short name T264
Test name
Test status
Simulation time 333398042302 ps
CPU time 594.82 seconds
Started Jan 24 07:53:48 PM PST 24
Finished Jan 24 08:03:44 PM PST 24
Peak memory 250544 kb
Host smart-2852c39d-fee0-4bfb-b1f2-6f588d91fed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143896120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.4143896120
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3838335415
Short name T497
Test name
Test status
Simulation time 13118165351 ps
CPU time 110.79 seconds
Started Jan 24 07:53:47 PM PST 24
Finished Jan 24 07:55:39 PM PST 24
Peak memory 234552 kb
Host smart-29c4392c-2fd1-4b56-94a0-69a37876d4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838335415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3838335415
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2031838715
Short name T738
Test name
Test status
Simulation time 651459393 ps
CPU time 11.29 seconds
Started Jan 24 07:53:44 PM PST 24
Finished Jan 24 07:53:55 PM PST 24
Peak memory 256896 kb
Host smart-d13408f9-a7b0-48bf-85f4-5e4987c65e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031838715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2031838715
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.116711053
Short name T822
Test name
Test status
Simulation time 1678113355 ps
CPU time 3.32 seconds
Started Jan 24 07:53:42 PM PST 24
Finished Jan 24 07:53:46 PM PST 24
Peak memory 216028 kb
Host smart-6c47a789-f069-460b-92df-ccf74f4b925e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116711053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.116711053
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3793054880
Short name T535
Test name
Test status
Simulation time 810874309 ps
CPU time 10.77 seconds
Started Jan 24 07:53:45 PM PST 24
Finished Jan 24 07:53:56 PM PST 24
Peak memory 239976 kb
Host smart-36289511-36e7-4dc9-ac14-1806fe9e01a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793054880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3793054880
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3659996408
Short name T1062
Test name
Test status
Simulation time 18626913043 ps
CPU time 55.58 seconds
Started Jan 24 07:53:39 PM PST 24
Finished Jan 24 07:54:35 PM PST 24
Peak memory 245556 kb
Host smart-bca0e01e-7298-420b-978a-eaaae8d56161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659996408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3659996408
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.4035877123
Short name T594
Test name
Test status
Simulation time 183927936931 ps
CPU time 26.41 seconds
Started Jan 24 07:53:38 PM PST 24
Finished Jan 24 07:54:04 PM PST 24
Peak memory 240136 kb
Host smart-835f4445-6760-4ab5-927b-6c4361608e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035877123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.4035877123
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1377159310
Short name T516
Test name
Test status
Simulation time 780546379 ps
CPU time 4.09 seconds
Started Jan 24 07:53:47 PM PST 24
Finished Jan 24 07:53:52 PM PST 24
Peak memory 221168 kb
Host smart-e869207a-c8d2-451f-94ee-8e5a45c33fb3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1377159310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1377159310
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2363650886
Short name T903
Test name
Test status
Simulation time 143314777868 ps
CPU time 258.2 seconds
Started Jan 24 07:53:47 PM PST 24
Finished Jan 24 07:58:05 PM PST 24
Peak memory 271068 kb
Host smart-1a4f278a-92e6-4f51-8d52-5c7b34cc3156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363650886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2363650886
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1047671484
Short name T1036
Test name
Test status
Simulation time 14676547013 ps
CPU time 68.23 seconds
Started Jan 24 07:53:38 PM PST 24
Finished Jan 24 07:54:47 PM PST 24
Peak memory 216060 kb
Host smart-661f8221-38c1-44af-949e-60483260ea39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047671484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1047671484
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2351743012
Short name T66
Test name
Test status
Simulation time 5946512877 ps
CPU time 18.23 seconds
Started Jan 24 07:53:34 PM PST 24
Finished Jan 24 07:53:53 PM PST 24
Peak memory 207864 kb
Host smart-181508a8-ee65-44fd-975e-1b04acef3ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351743012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2351743012
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1519899082
Short name T439
Test name
Test status
Simulation time 15551627 ps
CPU time 0.79 seconds
Started Jan 24 07:53:37 PM PST 24
Finished Jan 24 07:53:38 PM PST 24
Peak memory 204580 kb
Host smart-06d2bc79-a504-4ae4-a14d-e42adcdec3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519899082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1519899082
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.4199343578
Short name T470
Test name
Test status
Simulation time 128166413 ps
CPU time 0.94 seconds
Started Jan 24 07:53:45 PM PST 24
Finished Jan 24 07:53:46 PM PST 24
Peak memory 204608 kb
Host smart-5a3c692a-28bb-4cdc-8d11-c492fbb331b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199343578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4199343578
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1738761697
Short name T686
Test name
Test status
Simulation time 1722307510 ps
CPU time 8.81 seconds
Started Jan 24 07:53:46 PM PST 24
Finished Jan 24 07:53:56 PM PST 24
Peak memory 233056 kb
Host smart-4f466368-ff9a-4f02-a0a9-bd10be4376b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738761697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1738761697
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2315764604
Short name T771
Test name
Test status
Simulation time 33332210 ps
CPU time 0.7 seconds
Started Jan 24 07:54:01 PM PST 24
Finished Jan 24 07:54:05 PM PST 24
Peak memory 204508 kb
Host smart-e5d2e7a0-f224-4c86-9e31-592adb6beea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315764604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2315764604
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.206166986
Short name T721
Test name
Test status
Simulation time 530684247 ps
CPU time 4.99 seconds
Started Jan 24 07:53:57 PM PST 24
Finished Jan 24 07:54:05 PM PST 24
Peak memory 232756 kb
Host smart-d31d62f2-0b06-4ce1-9871-a7b2b86236d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206166986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.206166986
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3534655242
Short name T679
Test name
Test status
Simulation time 40294248 ps
CPU time 0.74 seconds
Started Jan 24 07:53:47 PM PST 24
Finished Jan 24 07:53:49 PM PST 24
Peak memory 204220 kb
Host smart-d034ab46-6548-4d0e-a32b-6ec72ad862d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534655242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3534655242
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.514143644
Short name T189
Test name
Test status
Simulation time 12951340494 ps
CPU time 131.89 seconds
Started Jan 24 08:07:43 PM PST 24
Finished Jan 24 08:09:56 PM PST 24
Peak memory 266544 kb
Host smart-4aa7ccd3-f390-4d38-b7d4-be14b5b7073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514143644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.514143644
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2813239668
Short name T980
Test name
Test status
Simulation time 107875027496 ps
CPU time 113.1 seconds
Started Jan 24 07:53:56 PM PST 24
Finished Jan 24 07:55:52 PM PST 24
Peak memory 256816 kb
Host smart-cf5d6aec-1f43-4956-9576-8b183ac44ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813239668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2813239668
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1234432080
Short name T180
Test name
Test status
Simulation time 2778391966 ps
CPU time 29.69 seconds
Started Jan 24 08:06:49 PM PST 24
Finished Jan 24 08:07:20 PM PST 24
Peak memory 232528 kb
Host smart-bf0bafcc-9875-4561-b8af-63a1462870aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234432080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1234432080
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.479510057
Short name T43
Test name
Test status
Simulation time 664028595 ps
CPU time 6.18 seconds
Started Jan 24 07:54:06 PM PST 24
Finished Jan 24 07:54:13 PM PST 24
Peak memory 228016 kb
Host smart-ae13e6d3-6de0-4375-9298-77aa8e5d6c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479510057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.479510057
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.4206724635
Short name T613
Test name
Test status
Simulation time 9226209051 ps
CPU time 7.98 seconds
Started Jan 24 07:53:53 PM PST 24
Finished Jan 24 07:54:07 PM PST 24
Peak memory 217148 kb
Host smart-1c03e673-4d22-4ba8-9679-0b60e8c2dc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206724635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.4206724635
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3563520968
Short name T825
Test name
Test status
Simulation time 3444902789 ps
CPU time 10.71 seconds
Started Jan 24 07:53:57 PM PST 24
Finished Jan 24 07:54:10 PM PST 24
Peak memory 223044 kb
Host smart-52d5ac8a-c0f8-4215-9e7b-7b2d3e1cdbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563520968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3563520968
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2991272512
Short name T7
Test name
Test status
Simulation time 561572442 ps
CPU time 9.63 seconds
Started Jan 24 08:25:19 PM PST 24
Finished Jan 24 08:25:30 PM PST 24
Peak memory 219320 kb
Host smart-cbc97aa4-1ede-4fb1-9c1d-8fde4669b11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991272512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2991272512
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2704831924
Short name T1043
Test name
Test status
Simulation time 6559917484 ps
CPU time 19.88 seconds
Started Jan 24 07:54:01 PM PST 24
Finished Jan 24 07:54:25 PM PST 24
Peak memory 232796 kb
Host smart-d3e113ff-2929-4786-baac-38e3b7ae5b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704831924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2704831924
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2578008010
Short name T673
Test name
Test status
Simulation time 2079041808 ps
CPU time 5.66 seconds
Started Jan 24 11:02:59 PM PST 24
Finished Jan 24 11:03:16 PM PST 24
Peak memory 216160 kb
Host smart-cd4e8b7d-d032-43e6-a312-150e3c628d02
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2578008010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2578008010
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.323808134
Short name T995
Test name
Test status
Simulation time 180413935 ps
CPU time 0.96 seconds
Started Jan 24 07:54:01 PM PST 24
Finished Jan 24 07:54:06 PM PST 24
Peak memory 204560 kb
Host smart-9c569169-2fe1-4759-915d-dcdb194245a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323808134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.323808134
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.955637554
Short name T671
Test name
Test status
Simulation time 10266492144 ps
CPU time 39.17 seconds
Started Jan 24 07:53:51 PM PST 24
Finished Jan 24 07:54:31 PM PST 24
Peak memory 215976 kb
Host smart-2e30d6f2-3889-4e52-b54f-5361bc1399ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955637554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.955637554
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2733609938
Short name T424
Test name
Test status
Simulation time 1997911072 ps
CPU time 2.02 seconds
Started Jan 24 07:53:46 PM PST 24
Finished Jan 24 07:53:49 PM PST 24
Peak memory 205680 kb
Host smart-5f062212-2d45-4f2c-bf1d-e46e55bd3ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733609938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2733609938
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2119429235
Short name T1011
Test name
Test status
Simulation time 183796206 ps
CPU time 1.44 seconds
Started Jan 24 07:53:51 PM PST 24
Finished Jan 24 07:53:57 PM PST 24
Peak memory 216000 kb
Host smart-a49ca749-b0b8-4ce6-bdc3-eaab80ce039d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119429235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2119429235
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1383504671
Short name T838
Test name
Test status
Simulation time 67071639 ps
CPU time 0.78 seconds
Started Jan 24 07:53:49 PM PST 24
Finished Jan 24 07:53:52 PM PST 24
Peak memory 204584 kb
Host smart-7fe5d8a9-ba48-4b84-904b-ddee9f89c040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383504671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1383504671
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1479161956
Short name T228
Test name
Test status
Simulation time 2396880623 ps
CPU time 6.92 seconds
Started Jan 24 08:45:06 PM PST 24
Finished Jan 24 08:45:15 PM PST 24
Peak memory 216164 kb
Host smart-0efc81a1-eb4f-4783-b450-74caf75c85e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479161956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1479161956
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.676727100
Short name T778
Test name
Test status
Simulation time 13504075 ps
CPU time 0.7 seconds
Started Jan 24 07:54:15 PM PST 24
Finished Jan 24 07:54:17 PM PST 24
Peak memory 204112 kb
Host smart-71a1f5a7-9b24-4d24-999f-ad5e6936efe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676727100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.676727100
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.604187278
Short name T790
Test name
Test status
Simulation time 2508052433 ps
CPU time 6.29 seconds
Started Jan 24 07:54:09 PM PST 24
Finished Jan 24 07:54:16 PM PST 24
Peak memory 219208 kb
Host smart-4bf63ec6-5ee0-4bbf-994a-260aacc22e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604187278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.604187278
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3270164130
Short name T440
Test name
Test status
Simulation time 28838046 ps
CPU time 0.8 seconds
Started Jan 24 07:54:00 PM PST 24
Finished Jan 24 07:54:05 PM PST 24
Peak memory 204256 kb
Host smart-dbdbf723-c373-4329-80f5-741c6f85681f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270164130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3270164130
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3189032197
Short name T232
Test name
Test status
Simulation time 50869396799 ps
CPU time 17.09 seconds
Started Jan 24 10:43:03 PM PST 24
Finished Jan 24 10:43:21 PM PST 24
Peak memory 235556 kb
Host smart-dafb9992-ca00-4c8e-9452-f95ae05de073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189032197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3189032197
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3378512734
Short name T896
Test name
Test status
Simulation time 30675167578 ps
CPU time 27.7 seconds
Started Jan 24 08:29:17 PM PST 24
Finished Jan 24 08:29:45 PM PST 24
Peak memory 245260 kb
Host smart-93488543-18ac-432a-b1bb-62f0bc622793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378512734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3378512734
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.156394876
Short name T892
Test name
Test status
Simulation time 1020180855 ps
CPU time 3.3 seconds
Started Jan 24 07:54:08 PM PST 24
Finished Jan 24 07:54:12 PM PST 24
Peak memory 232896 kb
Host smart-5cd48dba-cc7f-4d66-bc93-e791b4d3547e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156394876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.156394876
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.17117806
Short name T966
Test name
Test status
Simulation time 1255033572 ps
CPU time 9.64 seconds
Started Jan 24 07:54:05 PM PST 24
Finished Jan 24 07:54:16 PM PST 24
Peak memory 240160 kb
Host smart-ad24dada-67fc-42b4-97b3-e8b854ef5a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17117806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.17117806
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1688926963
Short name T181
Test name
Test status
Simulation time 11029254664 ps
CPU time 26.54 seconds
Started Jan 24 07:54:07 PM PST 24
Finished Jan 24 07:54:35 PM PST 24
Peak memory 228620 kb
Host smart-635720cb-017a-4512-a360-281ce8e044f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688926963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1688926963
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3921843232
Short name T499
Test name
Test status
Simulation time 315545138 ps
CPU time 3.46 seconds
Started Jan 24 07:53:58 PM PST 24
Finished Jan 24 07:54:05 PM PST 24
Peak memory 217164 kb
Host smart-2e88fc4d-b584-409d-8bd3-00b85f25cd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921843232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3921843232
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1749668726
Short name T596
Test name
Test status
Simulation time 1092950839 ps
CPU time 6.2 seconds
Started Jan 24 08:56:13 PM PST 24
Finished Jan 24 08:56:21 PM PST 24
Peak memory 221108 kb
Host smart-359178c8-71bc-4294-8163-f14b43d7e464
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1749668726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1749668726
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.567968142
Short name T901
Test name
Test status
Simulation time 22370840311 ps
CPU time 164.66 seconds
Started Jan 24 07:54:10 PM PST 24
Finished Jan 24 07:56:56 PM PST 24
Peak memory 248932 kb
Host smart-3cdc59a6-a939-4397-a006-117bd3109424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567968142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.567968142
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1451689170
Short name T650
Test name
Test status
Simulation time 7587859082 ps
CPU time 41.03 seconds
Started Jan 24 07:54:00 PM PST 24
Finished Jan 24 07:54:45 PM PST 24
Peak memory 209548 kb
Host smart-bcfd31a5-7b37-4360-9682-d783d53505c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451689170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1451689170
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.942139929
Short name T732
Test name
Test status
Simulation time 1258033015 ps
CPU time 8.52 seconds
Started Jan 24 07:54:01 PM PST 24
Finished Jan 24 07:54:14 PM PST 24
Peak memory 207736 kb
Host smart-df9882e3-f5b3-4a58-a414-71bfd1d9b004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942139929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.942139929
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3363721169
Short name T1003
Test name
Test status
Simulation time 185731258 ps
CPU time 1.5 seconds
Started Jan 24 07:54:01 PM PST 24
Finished Jan 24 07:54:06 PM PST 24
Peak memory 207888 kb
Host smart-b18d32ff-5a8d-424b-ba68-33c8b3a4970b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363721169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3363721169
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3576611166
Short name T694
Test name
Test status
Simulation time 29930550 ps
CPU time 0.87 seconds
Started Jan 24 07:54:00 PM PST 24
Finished Jan 24 07:54:05 PM PST 24
Peak memory 204600 kb
Host smart-38ecc62f-c306-4196-b450-d099481e644c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576611166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3576611166
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2053916586
Short name T526
Test name
Test status
Simulation time 720520256 ps
CPU time 5.59 seconds
Started Jan 24 07:54:07 PM PST 24
Finished Jan 24 07:54:13 PM PST 24
Peak memory 233136 kb
Host smart-1ad8c1cf-db57-4d42-82d9-efbef391f393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053916586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2053916586
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2890763910
Short name T727
Test name
Test status
Simulation time 28222748 ps
CPU time 0.7 seconds
Started Jan 24 07:54:30 PM PST 24
Finished Jan 24 07:54:33 PM PST 24
Peak memory 204396 kb
Host smart-e96f816d-9eef-4380-b673-5b63e26bd93e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890763910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2890763910
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2709030548
Short name T445
Test name
Test status
Simulation time 298512184 ps
CPU time 3.02 seconds
Started Jan 24 07:54:22 PM PST 24
Finished Jan 24 07:54:31 PM PST 24
Peak memory 218200 kb
Host smart-2277d800-d1f7-4c6c-8efd-fff86416ce6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709030548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2709030548
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2294672433
Short name T855
Test name
Test status
Simulation time 21886731 ps
CPU time 0.79 seconds
Started Jan 24 07:54:12 PM PST 24
Finished Jan 24 07:54:13 PM PST 24
Peak memory 205304 kb
Host smart-10b56db5-8670-4c32-b444-45b587ed6850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294672433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2294672433
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1338197529
Short name T272
Test name
Test status
Simulation time 78701152005 ps
CPU time 80 seconds
Started Jan 24 07:54:30 PM PST 24
Finished Jan 24 07:55:52 PM PST 24
Peak memory 234888 kb
Host smart-81e4354d-ccee-4bb7-936a-4405eb61209b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338197529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1338197529
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1836403813
Short name T941
Test name
Test status
Simulation time 41507367495 ps
CPU time 133.72 seconds
Started Jan 24 07:54:30 PM PST 24
Finished Jan 24 07:56:46 PM PST 24
Peak memory 262552 kb
Host smart-e482f83d-9bd5-4fc4-8ba8-5ef83e9a8e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836403813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1836403813
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3355894459
Short name T844
Test name
Test status
Simulation time 41458374122 ps
CPU time 142.34 seconds
Started Jan 24 09:42:58 PM PST 24
Finished Jan 24 09:45:21 PM PST 24
Peak memory 265288 kb
Host smart-5eb9d45c-e334-4fc4-bf92-ed55f64255ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355894459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3355894459
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2550566906
Short name T34
Test name
Test status
Simulation time 939005287 ps
CPU time 5.14 seconds
Started Jan 24 07:54:22 PM PST 24
Finished Jan 24 07:54:33 PM PST 24
Peak memory 218912 kb
Host smart-a5f4425c-02a9-4b4a-825d-bf8d0cd18b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550566906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2550566906
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4095414048
Short name T209
Test name
Test status
Simulation time 2640469256 ps
CPU time 10.8 seconds
Started Jan 24 07:54:22 PM PST 24
Finished Jan 24 07:54:39 PM PST 24
Peak memory 218220 kb
Host smart-139516b8-ade7-4e29-81bf-490c986d477d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095414048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4095414048
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2205639304
Short name T83
Test name
Test status
Simulation time 371055055 ps
CPU time 3.96 seconds
Started Jan 24 07:54:18 PM PST 24
Finished Jan 24 07:54:24 PM PST 24
Peak memory 217140 kb
Host smart-075b0faf-c034-47c0-83d8-8b6f08290ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205639304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2205639304
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1420887057
Short name T71
Test name
Test status
Simulation time 24350734257 ps
CPU time 17.02 seconds
Started Jan 24 07:54:23 PM PST 24
Finished Jan 24 07:54:45 PM PST 24
Peak memory 239072 kb
Host smart-a6017b8b-7ca4-4d3c-ab3b-259d3d3c20d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420887057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1420887057
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1860847460
Short name T1012
Test name
Test status
Simulation time 214976765 ps
CPU time 3.79 seconds
Started Jan 24 07:54:23 PM PST 24
Finished Jan 24 07:54:32 PM PST 24
Peak memory 221856 kb
Host smart-bac21442-cd50-4934-a0b7-c4acf0930081
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1860847460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1860847460
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2198793284
Short name T808
Test name
Test status
Simulation time 207023137 ps
CPU time 1.17 seconds
Started Jan 24 07:54:28 PM PST 24
Finished Jan 24 07:54:33 PM PST 24
Peak memory 206552 kb
Host smart-89c46b5f-8174-4538-87af-03ce6cab2314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198793284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2198793284
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2586875212
Short name T1002
Test name
Test status
Simulation time 5693905733 ps
CPU time 25.04 seconds
Started Jan 24 07:54:20 PM PST 24
Finished Jan 24 07:54:47 PM PST 24
Peak memory 218376 kb
Host smart-fc665969-d050-4a53-ae9c-cb58d52e9458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586875212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2586875212
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4225872731
Short name T804
Test name
Test status
Simulation time 45607776652 ps
CPU time 29.82 seconds
Started Jan 24 07:54:22 PM PST 24
Finished Jan 24 07:54:58 PM PST 24
Peak memory 216056 kb
Host smart-57b8b7d7-3f13-4e71-a8da-8289128f09f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225872731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4225872731
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1734585598
Short name T17
Test name
Test status
Simulation time 542289519 ps
CPU time 7.79 seconds
Started Jan 24 09:44:44 PM PST 24
Finished Jan 24 09:44:53 PM PST 24
Peak memory 216200 kb
Host smart-3a6442ca-879a-41ac-af6b-4c41f356d5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734585598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1734585598
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1873996414
Short name T644
Test name
Test status
Simulation time 478097065 ps
CPU time 1.07 seconds
Started Jan 24 07:54:22 PM PST 24
Finished Jan 24 07:54:28 PM PST 24
Peak memory 205620 kb
Host smart-02b39573-b9ab-4420-810c-d772ca80c79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873996414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1873996414
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1137674535
Short name T936
Test name
Test status
Simulation time 482467491 ps
CPU time 3.81 seconds
Started Jan 24 07:54:19 PM PST 24
Finished Jan 24 07:54:25 PM PST 24
Peak memory 217308 kb
Host smart-a6e01420-8498-40c3-aaf6-47dcd1f01f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137674535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1137674535
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3097068876
Short name T1086
Test name
Test status
Simulation time 13616148 ps
CPU time 0.74 seconds
Started Jan 24 07:54:47 PM PST 24
Finished Jan 24 07:54:54 PM PST 24
Peak memory 204104 kb
Host smart-98ad92dc-b33e-40d6-b20e-85eb6d081ae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097068876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3097068876
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3141567645
Short name T225
Test name
Test status
Simulation time 882588674 ps
CPU time 4.33 seconds
Started Jan 24 07:54:35 PM PST 24
Finished Jan 24 07:54:40 PM PST 24
Peak memory 233912 kb
Host smart-fbdc721b-12ac-47b2-9f01-b8aea4349ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141567645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3141567645
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1109104752
Short name T619
Test name
Test status
Simulation time 16237782 ps
CPU time 0.75 seconds
Started Jan 24 07:54:30 PM PST 24
Finished Jan 24 07:54:33 PM PST 24
Peak memory 204564 kb
Host smart-03c0029f-bdf3-4d90-a53f-ec8c26b218d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109104752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1109104752
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3135258242
Short name T164
Test name
Test status
Simulation time 51844126973 ps
CPU time 252.59 seconds
Started Jan 24 07:54:35 PM PST 24
Finished Jan 24 07:58:49 PM PST 24
Peak memory 256844 kb
Host smart-6e6b1f6f-04f5-4d5f-9ffd-a58e6c25dbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135258242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3135258242
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2872208957
Short name T448
Test name
Test status
Simulation time 75077750767 ps
CPU time 131.17 seconds
Started Jan 24 07:54:36 PM PST 24
Finished Jan 24 07:56:47 PM PST 24
Peak memory 238432 kb
Host smart-27e4e27f-f2e6-4630-897e-b4b48bae9a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872208957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2872208957
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2354122006
Short name T899
Test name
Test status
Simulation time 236187794986 ps
CPU time 274.43 seconds
Started Jan 24 07:54:37 PM PST 24
Finished Jan 24 07:59:12 PM PST 24
Peak memory 260456 kb
Host smart-c62e6691-b35b-415d-a6e7-3040f4a57d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354122006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2354122006
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3993595213
Short name T1063
Test name
Test status
Simulation time 3630811879 ps
CPU time 16.78 seconds
Started Jan 24 07:54:36 PM PST 24
Finished Jan 24 07:54:54 PM PST 24
Peak memory 238608 kb
Host smart-ece1b359-19ad-48e9-945c-b6c5a9198614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993595213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3993595213
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1465290815
Short name T230
Test name
Test status
Simulation time 380419521 ps
CPU time 3.92 seconds
Started Jan 24 07:54:39 PM PST 24
Finished Jan 24 07:54:44 PM PST 24
Peak memory 218392 kb
Host smart-9fadac56-6a55-497d-a210-747107345d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465290815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1465290815
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3072071981
Short name T777
Test name
Test status
Simulation time 31089940533 ps
CPU time 13.41 seconds
Started Jan 25 01:19:11 AM PST 24
Finished Jan 25 01:19:25 AM PST 24
Peak memory 222512 kb
Host smart-f75122c8-1452-4daa-83c7-f12877c3cc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072071981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3072071981
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2001733089
Short name T258
Test name
Test status
Simulation time 2004033625 ps
CPU time 6.8 seconds
Started Jan 24 07:54:33 PM PST 24
Finished Jan 24 07:54:41 PM PST 24
Peak memory 219792 kb
Host smart-5776d71a-eb44-4d47-86fd-8c3e0afcd527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001733089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2001733089
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3019915704
Short name T581
Test name
Test status
Simulation time 42074132423 ps
CPU time 13.41 seconds
Started Jan 24 08:35:43 PM PST 24
Finished Jan 24 08:35:57 PM PST 24
Peak memory 217460 kb
Host smart-e3b61182-f94a-4931-8800-080dda1c2142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019915704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3019915704
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.275806033
Short name T450
Test name
Test status
Simulation time 1929250810 ps
CPU time 7.75 seconds
Started Jan 24 07:54:32 PM PST 24
Finished Jan 24 07:54:41 PM PST 24
Peak memory 221088 kb
Host smart-78c8dc21-a27c-41ca-88b4-468deb3caa39
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=275806033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.275806033
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.925639038
Short name T665
Test name
Test status
Simulation time 13808385858 ps
CPU time 39.88 seconds
Started Jan 24 07:54:31 PM PST 24
Finished Jan 24 07:55:12 PM PST 24
Peak memory 215984 kb
Host smart-8554e5d1-06e1-4809-aa3c-3b9d2e05693a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925639038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.925639038
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.827197273
Short name T791
Test name
Test status
Simulation time 1267207436 ps
CPU time 5.92 seconds
Started Jan 24 07:54:26 PM PST 24
Finished Jan 24 07:54:35 PM PST 24
Peak memory 207712 kb
Host smart-7d09074b-1031-4547-a732-3ca2796f0975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827197273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.827197273
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3842123524
Short name T823
Test name
Test status
Simulation time 28288382 ps
CPU time 1.12 seconds
Started Jan 24 08:19:21 PM PST 24
Finished Jan 24 08:19:25 PM PST 24
Peak memory 206048 kb
Host smart-a05f242b-f971-461d-9033-549d854ff8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842123524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3842123524
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3438828525
Short name T456
Test name
Test status
Simulation time 166677220 ps
CPU time 0.94 seconds
Started Jan 24 07:54:28 PM PST 24
Finished Jan 24 07:54:33 PM PST 24
Peak memory 204588 kb
Host smart-ad81a3c4-cb76-4c65-97b1-27218f007ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438828525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3438828525
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.214814298
Short name T610
Test name
Test status
Simulation time 11552859758 ps
CPU time 32.98 seconds
Started Jan 24 08:50:14 PM PST 24
Finished Jan 24 08:50:48 PM PST 24
Peak memory 217968 kb
Host smart-3a7438f3-fedc-4cad-bd7a-ca022c34999b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214814298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.214814298
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2822276638
Short name T691
Test name
Test status
Simulation time 40200834 ps
CPU time 0.71 seconds
Started Jan 24 07:46:39 PM PST 24
Finished Jan 24 07:46:40 PM PST 24
Peak memory 204072 kb
Host smart-79314361-3792-4b07-9827-57195e4bfaea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822276638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
822276638
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.740857593
Short name T541
Test name
Test status
Simulation time 134840839 ps
CPU time 2.47 seconds
Started Jan 24 07:46:41 PM PST 24
Finished Jan 24 07:46:44 PM PST 24
Peak memory 232524 kb
Host smart-7a77d7c4-73db-4aae-a120-500200576fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740857593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.740857593
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.112328430
Short name T928
Test name
Test status
Simulation time 52732581 ps
CPU time 0.73 seconds
Started Jan 24 07:46:18 PM PST 24
Finished Jan 24 07:46:20 PM PST 24
Peak memory 204220 kb
Host smart-1b43f61f-5eac-4703-8900-eacdd0b30768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112328430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.112328430
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.4180076061
Short name T961
Test name
Test status
Simulation time 9528168875 ps
CPU time 55.64 seconds
Started Jan 24 07:46:34 PM PST 24
Finished Jan 24 07:47:31 PM PST 24
Peak memory 257032 kb
Host smart-e18ccb6d-5836-41df-ab9c-88a1fd79c742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180076061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.4180076061
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3189317976
Short name T176
Test name
Test status
Simulation time 115766156834 ps
CPU time 755.34 seconds
Started Jan 24 07:46:39 PM PST 24
Finished Jan 24 07:59:16 PM PST 24
Peak memory 271448 kb
Host smart-c2baf231-bed7-4d45-933e-d24ffa4f4f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189317976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3189317976
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2729320316
Short name T468
Test name
Test status
Simulation time 3564291280 ps
CPU time 63.65 seconds
Started Jan 24 07:46:37 PM PST 24
Finished Jan 24 07:47:41 PM PST 24
Peak memory 252000 kb
Host smart-30755f33-446c-4d62-b479-deba593fd05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729320316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2729320316
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3589825570
Short name T871
Test name
Test status
Simulation time 43956565942 ps
CPU time 57.37 seconds
Started Jan 24 07:46:40 PM PST 24
Finished Jan 24 07:47:39 PM PST 24
Peak memory 246872 kb
Host smart-030f99aa-0ff3-42f6-b5da-c76021f5f1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589825570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3589825570
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3202409789
Short name T1064
Test name
Test status
Simulation time 14067999003 ps
CPU time 11.12 seconds
Started Jan 24 07:46:28 PM PST 24
Finished Jan 24 07:46:40 PM PST 24
Peak memory 219956 kb
Host smart-e228a55a-e717-4426-a0f4-e8533b11d002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202409789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3202409789
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1799750929
Short name T620
Test name
Test status
Simulation time 30088547180 ps
CPU time 24.03 seconds
Started Jan 24 09:10:25 PM PST 24
Finished Jan 24 09:10:53 PM PST 24
Peak memory 235884 kb
Host smart-0c22ba61-2c1a-4c4e-bfd1-6da1a52a0922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799750929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1799750929
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1242485658
Short name T26
Test name
Test status
Simulation time 35562480 ps
CPU time 1.09 seconds
Started Jan 24 10:01:56 PM PST 24
Finished Jan 24 10:01:58 PM PST 24
Peak memory 215792 kb
Host smart-8204bdad-c060-4e50-8d9c-009fa500b36e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242485658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1242485658
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1603458041
Short name T921
Test name
Test status
Simulation time 10638411989 ps
CPU time 30.76 seconds
Started Jan 24 07:46:24 PM PST 24
Finished Jan 24 07:46:56 PM PST 24
Peak memory 232492 kb
Host smart-ba3f4baf-5331-47ee-9953-871a2ae861d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603458041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1603458041
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2756128995
Short name T878
Test name
Test status
Simulation time 3930094770 ps
CPU time 17.23 seconds
Started Jan 24 07:54:43 PM PST 24
Finished Jan 24 07:55:02 PM PST 24
Peak memory 236648 kb
Host smart-764b39c3-1f6e-4ff7-8e0d-d30ee09a3854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756128995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2756128995
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.3541108421
Short name T1005
Test name
Test status
Simulation time 40787627 ps
CPU time 0.72 seconds
Started Jan 24 08:36:26 PM PST 24
Finished Jan 24 08:36:27 PM PST 24
Peak memory 215892 kb
Host smart-1d122998-abdd-4bff-8eed-7a947dd42d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541108421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.3541108421
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3029520425
Short name T1024
Test name
Test status
Simulation time 535764665 ps
CPU time 3.65 seconds
Started Jan 24 07:46:34 PM PST 24
Finished Jan 24 07:46:39 PM PST 24
Peak memory 221696 kb
Host smart-3f4c08ec-7df9-4ff2-a9cc-d32fba78eb4e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3029520425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3029520425
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1702492506
Short name T146
Test name
Test status
Simulation time 99058139 ps
CPU time 1.08 seconds
Started Jan 24 07:46:37 PM PST 24
Finished Jan 24 07:46:39 PM PST 24
Peak memory 205884 kb
Host smart-515ebc7a-0357-4a23-a8ad-82076ec8b51e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702492506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1702492506
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2400615989
Short name T105
Test name
Test status
Simulation time 10238038739 ps
CPU time 84.9 seconds
Started Jan 24 07:46:22 PM PST 24
Finished Jan 24 07:47:48 PM PST 24
Peak memory 218124 kb
Host smart-13edc4f5-49d7-479b-9e57-8b2237fe5cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400615989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2400615989
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3439915584
Short name T601
Test name
Test status
Simulation time 28717690506 ps
CPU time 18.31 seconds
Started Jan 24 07:46:22 PM PST 24
Finished Jan 24 07:46:41 PM PST 24
Peak memory 215976 kb
Host smart-150bf05c-e390-46ea-8dbd-3af84ce892a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439915584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3439915584
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.789704094
Short name T1073
Test name
Test status
Simulation time 61713385 ps
CPU time 1.6 seconds
Started Jan 24 07:46:28 PM PST 24
Finished Jan 24 07:46:31 PM PST 24
Peak memory 207772 kb
Host smart-b3ccc1ba-af2c-4d73-9075-7f3de995430b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789704094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.789704094
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.722177052
Short name T670
Test name
Test status
Simulation time 227102280 ps
CPU time 1.01 seconds
Started Jan 24 09:37:41 PM PST 24
Finished Jan 24 09:37:43 PM PST 24
Peak memory 205644 kb
Host smart-e60df964-0f44-4c78-bc0f-4d4769d507ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722177052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.722177052
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1698496289
Short name T953
Test name
Test status
Simulation time 1634486458 ps
CPU time 7.37 seconds
Started Jan 24 07:46:24 PM PST 24
Finished Jan 24 07:46:32 PM PST 24
Peak memory 217664 kb
Host smart-8bc0538a-a00d-4796-b3b0-c23332962919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698496289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1698496289
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3421299949
Short name T793
Test name
Test status
Simulation time 45496643 ps
CPU time 0.76 seconds
Started Jan 24 07:54:57 PM PST 24
Finished Jan 24 07:55:03 PM PST 24
Peak memory 204464 kb
Host smart-b52bae17-320a-490d-9b58-7e1015aec124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421299949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3421299949
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1823668461
Short name T696
Test name
Test status
Simulation time 1746911148 ps
CPU time 2.95 seconds
Started Jan 24 07:54:48 PM PST 24
Finished Jan 24 07:54:57 PM PST 24
Peak memory 218252 kb
Host smart-3574ed71-d54e-41eb-bf29-9697e49b6da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823668461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1823668461
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3366268095
Short name T911
Test name
Test status
Simulation time 177306790 ps
CPU time 0.8 seconds
Started Jan 24 07:54:44 PM PST 24
Finished Jan 24 07:54:47 PM PST 24
Peak memory 204256 kb
Host smart-7d6a16de-56ce-49d0-8349-b32f2cd1ca2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366268095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3366268095
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1069131737
Short name T952
Test name
Test status
Simulation time 20712641215 ps
CPU time 32.41 seconds
Started Jan 24 07:54:54 PM PST 24
Finished Jan 24 07:55:34 PM PST 24
Peak memory 232536 kb
Host smart-1ecbbfef-90ee-4336-8e68-b6cb6f4c3205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069131737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1069131737
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2135203952
Short name T1052
Test name
Test status
Simulation time 6848121717 ps
CPU time 10.93 seconds
Started Jan 24 07:54:48 PM PST 24
Finished Jan 24 07:55:05 PM PST 24
Peak memory 222696 kb
Host smart-79c2d28b-0b18-44e2-8686-da2d88ac9254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135203952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2135203952
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1485097636
Short name T826
Test name
Test status
Simulation time 4030827928 ps
CPU time 7.46 seconds
Started Jan 24 07:54:43 PM PST 24
Finished Jan 24 07:54:51 PM PST 24
Peak memory 216108 kb
Host smart-fe4305e8-c4fc-4a4f-852a-e2187acb7836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485097636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1485097636
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1174334266
Short name T472
Test name
Test status
Simulation time 240859501 ps
CPU time 2.62 seconds
Started Jan 24 07:54:44 PM PST 24
Finished Jan 24 07:54:49 PM PST 24
Peak memory 216028 kb
Host smart-13c20658-bf07-4e4b-b38c-465f7379dc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174334266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1174334266
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1794855146
Short name T754
Test name
Test status
Simulation time 2879180945 ps
CPU time 3.13 seconds
Started Jan 24 07:54:45 PM PST 24
Finished Jan 24 07:54:50 PM PST 24
Peak memory 232440 kb
Host smart-99172038-bbdd-4c83-ac19-799362f2c54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794855146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1794855146
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1726708828
Short name T887
Test name
Test status
Simulation time 6894270904 ps
CPU time 8.19 seconds
Started Jan 24 07:54:42 PM PST 24
Finished Jan 24 07:54:51 PM PST 24
Peak memory 232492 kb
Host smart-227fd09f-67e9-49fd-8c1d-742189884570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726708828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1726708828
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1483635412
Short name T1074
Test name
Test status
Simulation time 203605538 ps
CPU time 3.06 seconds
Started Jan 24 07:54:50 PM PST 24
Finished Jan 24 07:55:01 PM PST 24
Peak memory 221700 kb
Host smart-3161cd9a-622d-4980-9188-ae01592c885a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1483635412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1483635412
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3702851827
Short name T1083
Test name
Test status
Simulation time 307516318349 ps
CPU time 523.93 seconds
Started Jan 24 07:54:57 PM PST 24
Finished Jan 24 08:03:46 PM PST 24
Peak memory 273176 kb
Host smart-663d27b8-d044-4527-951a-df66010dac00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702851827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3702851827
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1138077365
Short name T554
Test name
Test status
Simulation time 1108339959 ps
CPU time 4.62 seconds
Started Jan 24 08:19:16 PM PST 24
Finished Jan 24 08:19:22 PM PST 24
Peak memory 215944 kb
Host smart-83fc21a0-c5c0-4b1f-9e76-9355dbda560a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138077365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1138077365
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2414824094
Short name T858
Test name
Test status
Simulation time 2701037008 ps
CPU time 10.86 seconds
Started Jan 24 08:43:38 PM PST 24
Finished Jan 24 08:44:08 PM PST 24
Peak memory 207820 kb
Host smart-2386c45e-c975-4f81-b6c7-009e6954e8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414824094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2414824094
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.660958786
Short name T451
Test name
Test status
Simulation time 56015530 ps
CPU time 1.07 seconds
Started Jan 24 07:54:43 PM PST 24
Finished Jan 24 07:54:46 PM PST 24
Peak memory 205708 kb
Host smart-f7ca48cb-94be-4f63-acff-c25dd0375e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660958786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.660958786
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3673961133
Short name T736
Test name
Test status
Simulation time 1157982951 ps
CPU time 1.12 seconds
Started Jan 24 07:54:43 PM PST 24
Finished Jan 24 07:54:45 PM PST 24
Peak memory 205620 kb
Host smart-ab8ec658-177a-469b-bcd2-dc684f202291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673961133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3673961133
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1992357557
Short name T55
Test name
Test status
Simulation time 1341830068 ps
CPU time 6.11 seconds
Started Jan 24 07:54:50 PM PST 24
Finished Jan 24 07:55:04 PM PST 24
Peak memory 217432 kb
Host smart-9bf89400-416b-4f77-9e4a-2e1ba07428d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992357557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1992357557
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.4143973383
Short name T918
Test name
Test status
Simulation time 52276901 ps
CPU time 0.72 seconds
Started Jan 24 07:54:59 PM PST 24
Finished Jan 24 07:55:06 PM PST 24
Peak memory 203500 kb
Host smart-a268619c-9b87-445b-88df-eb3b9126ba28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143973383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4143973383
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1608229554
Short name T734
Test name
Test status
Simulation time 539665800 ps
CPU time 4.06 seconds
Started Jan 24 07:55:03 PM PST 24
Finished Jan 24 07:55:12 PM PST 24
Peak memory 232460 kb
Host smart-744b151b-775b-44db-8d33-e61498f7b417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608229554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1608229554
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3442217861
Short name T868
Test name
Test status
Simulation time 84804475 ps
CPU time 0.78 seconds
Started Jan 24 07:54:52 PM PST 24
Finished Jan 24 07:55:00 PM PST 24
Peak memory 205296 kb
Host smart-6e63f817-0172-44ba-81fc-9e3647620836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442217861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3442217861
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2850514101
Short name T797
Test name
Test status
Simulation time 412731690594 ps
CPU time 230.16 seconds
Started Jan 24 08:34:49 PM PST 24
Finished Jan 24 08:38:40 PM PST 24
Peak memory 240076 kb
Host smart-314b2c5a-4828-46d6-9878-026eba8a368a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850514101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2850514101
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3635531623
Short name T273
Test name
Test status
Simulation time 413027115869 ps
CPU time 711.48 seconds
Started Jan 24 07:54:59 PM PST 24
Finished Jan 24 08:06:57 PM PST 24
Peak memory 256952 kb
Host smart-f2355095-6ec7-4688-aa4a-07bceadb89e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635531623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3635531623
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1837359903
Short name T62
Test name
Test status
Simulation time 37516992336 ps
CPU time 154.29 seconds
Started Jan 24 07:55:00 PM PST 24
Finished Jan 24 07:57:41 PM PST 24
Peak memory 248944 kb
Host smart-7852ab62-a9fe-4495-9bda-1a53f727fc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837359903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1837359903
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.227656428
Short name T128
Test name
Test status
Simulation time 7489970442 ps
CPU time 42.99 seconds
Started Jan 24 07:55:10 PM PST 24
Finished Jan 24 07:55:54 PM PST 24
Peak memory 236548 kb
Host smart-971e029c-1edb-44da-8da0-e2a0bcc6c057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227656428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.227656428
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1379174213
Short name T505
Test name
Test status
Simulation time 3545990272 ps
CPU time 8.62 seconds
Started Jan 24 07:55:01 PM PST 24
Finished Jan 24 07:55:16 PM PST 24
Peak memory 217436 kb
Host smart-393e6ad4-00bc-4c9d-9876-9b8b7f7eeaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379174213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1379174213
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2464552006
Short name T455
Test name
Test status
Simulation time 18936463114 ps
CPU time 35.26 seconds
Started Jan 24 07:54:59 PM PST 24
Finished Jan 24 07:55:41 PM PST 24
Peak memory 247312 kb
Host smart-ec5d9c9b-61ae-4d84-afac-211b16516ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464552006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2464552006
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.4145613390
Short name T710
Test name
Test status
Simulation time 1129486475 ps
CPU time 3.68 seconds
Started Jan 24 07:54:57 PM PST 24
Finished Jan 24 07:55:06 PM PST 24
Peak memory 216112 kb
Host smart-8ffbe165-93b9-427c-a223-75df6e3ba00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145613390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.4145613390
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2142091240
Short name T599
Test name
Test status
Simulation time 33359608 ps
CPU time 2.21 seconds
Started Jan 24 07:54:54 PM PST 24
Finished Jan 24 07:55:03 PM PST 24
Peak memory 216216 kb
Host smart-a5016a91-a505-468b-81bc-e652024cc5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142091240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2142091240
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2713288399
Short name T15
Test name
Test status
Simulation time 161998679 ps
CPU time 3.67 seconds
Started Jan 24 07:55:00 PM PST 24
Finished Jan 24 07:55:10 PM PST 24
Peak memory 221032 kb
Host smart-79fa59aa-4622-4dc5-b5ca-b75a231be643
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2713288399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2713288399
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1748194594
Short name T1018
Test name
Test status
Simulation time 28773430032 ps
CPU time 50.08 seconds
Started Jan 24 07:55:03 PM PST 24
Finished Jan 24 07:55:58 PM PST 24
Peak memory 234724 kb
Host smart-bb306d18-435d-400b-97cc-26958119defe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748194594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1748194594
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3455713522
Short name T3
Test name
Test status
Simulation time 3802726817 ps
CPU time 29.53 seconds
Started Jan 24 09:10:22 PM PST 24
Finished Jan 24 09:10:55 PM PST 24
Peak memory 216004 kb
Host smart-721a12ca-7663-48d4-b975-3d0a33165096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455713522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3455713522
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2464847774
Short name T558
Test name
Test status
Simulation time 1159901968 ps
CPU time 7.94 seconds
Started Jan 24 07:54:54 PM PST 24
Finished Jan 24 07:55:10 PM PST 24
Peak memory 207644 kb
Host smart-e3fb8dfa-e315-4443-85d9-766b7692d075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464847774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2464847774
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.149642847
Short name T531
Test name
Test status
Simulation time 83092034 ps
CPU time 1.98 seconds
Started Jan 24 08:41:03 PM PST 24
Finished Jan 24 08:41:06 PM PST 24
Peak memory 207840 kb
Host smart-4b90a7bd-ea2e-49f6-a092-55a41d1b26b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149642847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.149642847
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.25506359
Short name T687
Test name
Test status
Simulation time 62786050 ps
CPU time 0.77 seconds
Started Jan 24 07:54:54 PM PST 24
Finished Jan 24 07:55:03 PM PST 24
Peak memory 204608 kb
Host smart-0ccb4323-9c87-481a-b913-638156282d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25506359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.25506359
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.593790711
Short name T806
Test name
Test status
Simulation time 2086024242 ps
CPU time 7.9 seconds
Started Jan 24 07:55:01 PM PST 24
Finished Jan 24 07:55:15 PM PST 24
Peak memory 218752 kb
Host smart-3d0507b3-9543-4150-9fb7-ec25555a045d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593790711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.593790711
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2336891560
Short name T978
Test name
Test status
Simulation time 31113290 ps
CPU time 0.77 seconds
Started Jan 24 09:07:45 PM PST 24
Finished Jan 24 09:07:46 PM PST 24
Peak memory 204424 kb
Host smart-4f4af5eb-ea12-4263-b631-cbefc9303c37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336891560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2336891560
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1838515109
Short name T843
Test name
Test status
Simulation time 2065419744 ps
CPU time 5.27 seconds
Started Jan 24 07:55:19 PM PST 24
Finished Jan 24 07:55:26 PM PST 24
Peak memory 218412 kb
Host smart-f9dd469d-bccd-4904-b313-6621b680c6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838515109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1838515109
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1354408407
Short name T836
Test name
Test status
Simulation time 17017069 ps
CPU time 0.81 seconds
Started Jan 24 07:55:07 PM PST 24
Finished Jan 24 07:55:10 PM PST 24
Peak memory 204236 kb
Host smart-49a01bad-59c1-4cec-8977-d32d4a747269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354408407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1354408407
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2631552166
Short name T269
Test name
Test status
Simulation time 66785472351 ps
CPU time 114.8 seconds
Started Jan 24 07:55:16 PM PST 24
Finished Jan 24 07:57:11 PM PST 24
Peak memory 263728 kb
Host smart-8ea28511-6a6f-44b6-94bb-a99c348bd9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631552166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2631552166
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3754148350
Short name T935
Test name
Test status
Simulation time 19349675910 ps
CPU time 98.34 seconds
Started Jan 24 07:55:21 PM PST 24
Finished Jan 24 07:57:01 PM PST 24
Peak memory 253676 kb
Host smart-b44d8fd0-5b1d-42e5-82a8-d9efab54f199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754148350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3754148350
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1258997757
Short name T986
Test name
Test status
Simulation time 20920701198 ps
CPU time 26.23 seconds
Started Jan 24 07:55:15 PM PST 24
Finished Jan 24 07:55:42 PM PST 24
Peak memory 231400 kb
Host smart-dca0d092-e4bf-45ad-aa71-b5dbf4dbf2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258997757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1258997757
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1717277241
Short name T939
Test name
Test status
Simulation time 70608040265 ps
CPU time 14.18 seconds
Started Jan 24 07:55:18 PM PST 24
Finished Jan 24 07:55:33 PM PST 24
Peak memory 218896 kb
Host smart-3a751d71-a0c3-4c03-a914-a31bc008cd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717277241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1717277241
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1619931371
Short name T602
Test name
Test status
Simulation time 10513285868 ps
CPU time 6.92 seconds
Started Jan 24 07:55:16 PM PST 24
Finished Jan 24 07:55:24 PM PST 24
Peak memory 223356 kb
Host smart-e1c906b0-8b87-4768-a83e-e81464362fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619931371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1619931371
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3816123077
Short name T758
Test name
Test status
Simulation time 2192229661 ps
CPU time 8.71 seconds
Started Jan 24 07:55:15 PM PST 24
Finished Jan 24 07:55:24 PM PST 24
Peak memory 229112 kb
Host smart-9156cde4-8512-4f4b-878a-eaacc6baed4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816123077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3816123077
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.4154206790
Short name T713
Test name
Test status
Simulation time 5257899144 ps
CPU time 19.31 seconds
Started Jan 24 07:55:17 PM PST 24
Finished Jan 24 07:55:37 PM PST 24
Peak memory 230704 kb
Host smart-3b469803-dad4-4ac8-8454-8f4795c19c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154206790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.4154206790
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.73479515
Short name T528
Test name
Test status
Simulation time 787619360 ps
CPU time 4.91 seconds
Started Jan 24 07:55:17 PM PST 24
Finished Jan 24 07:55:23 PM PST 24
Peak memory 216188 kb
Host smart-34921050-ebc2-4ce1-942c-d9058ebe9c30
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=73479515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direc
t.73479515
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.912587211
Short name T20
Test name
Test status
Simulation time 225556960 ps
CPU time 1.03 seconds
Started Jan 24 07:55:20 PM PST 24
Finished Jan 24 07:55:22 PM PST 24
Peak memory 205752 kb
Host smart-09fe70d5-35fa-4e2f-afc0-b22a313f24d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912587211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.912587211
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3149895730
Short name T288
Test name
Test status
Simulation time 8442593861 ps
CPU time 61.81 seconds
Started Jan 24 07:55:10 PM PST 24
Finished Jan 24 07:56:13 PM PST 24
Peak memory 215984 kb
Host smart-95317798-b5e2-4df4-a77f-2940836f0e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149895730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3149895730
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3538258843
Short name T781
Test name
Test status
Simulation time 845999365 ps
CPU time 5.39 seconds
Started Jan 24 07:55:05 PM PST 24
Finished Jan 24 07:55:14 PM PST 24
Peak memory 207716 kb
Host smart-f6d4af70-353d-4e19-bce8-bf662fd583ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538258843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3538258843
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2793093091
Short name T881
Test name
Test status
Simulation time 31212725 ps
CPU time 1.74 seconds
Started Jan 24 07:55:17 PM PST 24
Finished Jan 24 07:55:20 PM PST 24
Peak memory 207516 kb
Host smart-599953c8-b110-46be-ae03-9ac4e96b867e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793093091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2793093091
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.662288541
Short name T940
Test name
Test status
Simulation time 321514920 ps
CPU time 0.99 seconds
Started Jan 24 07:55:11 PM PST 24
Finished Jan 24 07:55:13 PM PST 24
Peak memory 204596 kb
Host smart-ca86b98f-170c-4738-96f6-e6be5b5515df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662288541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.662288541
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1550676434
Short name T214
Test name
Test status
Simulation time 186083604031 ps
CPU time 58.4 seconds
Started Jan 24 07:55:15 PM PST 24
Finished Jan 24 07:56:15 PM PST 24
Peak memory 244192 kb
Host smart-4b07da9b-66ec-44f1-bfb5-1cccea0ddb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550676434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1550676434
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1049372534
Short name T716
Test name
Test status
Simulation time 32790288 ps
CPU time 0.7 seconds
Started Jan 24 07:55:32 PM PST 24
Finished Jan 24 07:55:34 PM PST 24
Peak memory 204068 kb
Host smart-adf77f7c-0560-4afa-b2c9-7a0d9b019e17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049372534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1049372534
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3437087496
Short name T219
Test name
Test status
Simulation time 540910738 ps
CPU time 4 seconds
Started Jan 24 07:55:35 PM PST 24
Finished Jan 24 07:55:40 PM PST 24
Peak memory 216272 kb
Host smart-cfe202c6-a8aa-45e2-b41a-512d08f49304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437087496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3437087496
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.783267311
Short name T462
Test name
Test status
Simulation time 185466036 ps
CPU time 0.73 seconds
Started Jan 24 07:55:25 PM PST 24
Finished Jan 24 07:55:27 PM PST 24
Peak memory 204256 kb
Host smart-e4c555b6-3d3b-4fcd-a999-407d6fd1c9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783267311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.783267311
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2735705253
Short name T158
Test name
Test status
Simulation time 13294237473 ps
CPU time 39.54 seconds
Started Jan 24 07:55:36 PM PST 24
Finished Jan 24 07:56:16 PM PST 24
Peak memory 239092 kb
Host smart-1d58552e-7db3-4355-8591-71f0f47d56b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735705253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2735705253
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3438037377
Short name T1056
Test name
Test status
Simulation time 7040609928 ps
CPU time 29.45 seconds
Started Jan 24 07:55:30 PM PST 24
Finished Jan 24 07:56:01 PM PST 24
Peak memory 248968 kb
Host smart-db54c534-07d2-417d-98fe-55f425b61a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438037377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3438037377
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1448049180
Short name T944
Test name
Test status
Simulation time 19763876420 ps
CPU time 138.22 seconds
Started Jan 24 07:55:35 PM PST 24
Finished Jan 24 07:57:53 PM PST 24
Peak memory 232608 kb
Host smart-50ab3874-cf0a-4e43-bfb2-958ba02b3393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448049180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1448049180
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3452286184
Short name T578
Test name
Test status
Simulation time 894159840 ps
CPU time 8.05 seconds
Started Jan 24 07:55:33 PM PST 24
Finished Jan 24 07:55:43 PM PST 24
Peak memory 231544 kb
Host smart-0faed793-e62f-4a77-99dc-932299b657c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452286184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3452286184
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.211610447
Short name T203
Test name
Test status
Simulation time 516823169 ps
CPU time 4.18 seconds
Started Jan 24 07:55:24 PM PST 24
Finished Jan 24 07:55:30 PM PST 24
Peak memory 219712 kb
Host smart-c3bd6cc4-0298-4b86-9b00-1952cc5dc2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211610447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.211610447
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3097427530
Short name T553
Test name
Test status
Simulation time 15873601433 ps
CPU time 17.82 seconds
Started Jan 24 07:55:24 PM PST 24
Finished Jan 24 07:55:43 PM PST 24
Peak memory 237788 kb
Host smart-8c5f32b9-2855-4c8d-9272-f9a77c7f1c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097427530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3097427530
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2428232847
Short name T985
Test name
Test status
Simulation time 73035578995 ps
CPU time 45.83 seconds
Started Jan 24 07:55:22 PM PST 24
Finished Jan 24 07:56:09 PM PST 24
Peak memory 249280 kb
Host smart-9a2a59d6-3576-4f6a-a84d-d99645959f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428232847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2428232847
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2268029031
Short name T509
Test name
Test status
Simulation time 14468368016 ps
CPU time 10.34 seconds
Started Jan 24 07:55:23 PM PST 24
Finished Jan 24 07:55:34 PM PST 24
Peak memory 217552 kb
Host smart-5c102211-a7e7-464b-ab19-60ef65cd83fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268029031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2268029031
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2660273737
Short name T780
Test name
Test status
Simulation time 697054670 ps
CPU time 3.72 seconds
Started Jan 24 07:55:32 PM PST 24
Finished Jan 24 07:55:37 PM PST 24
Peak memory 221056 kb
Host smart-a8be2665-07ea-4c07-a1eb-f9c1bfbf840e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2660273737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2660273737
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.148573731
Short name T145
Test name
Test status
Simulation time 62192885 ps
CPU time 1.05 seconds
Started Jan 24 07:55:32 PM PST 24
Finished Jan 24 07:55:34 PM PST 24
Peak memory 205876 kb
Host smart-8de4a5f2-1783-4fc2-95dd-28d0fafcf59b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148573731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.148573731
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.4028137204
Short name T1093
Test name
Test status
Simulation time 7991646555 ps
CPU time 74.92 seconds
Started Jan 24 08:39:11 PM PST 24
Finished Jan 24 08:40:27 PM PST 24
Peak memory 218044 kb
Host smart-0fabc50f-a3dc-405f-8ba7-293361c60b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028137204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4028137204
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1564248697
Short name T920
Test name
Test status
Simulation time 364692656 ps
CPU time 1.98 seconds
Started Jan 24 08:32:45 PM PST 24
Finished Jan 24 08:32:47 PM PST 24
Peak memory 207584 kb
Host smart-d495688f-a619-4866-afe0-e50ca81989e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564248697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1564248697
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2507680806
Short name T905
Test name
Test status
Simulation time 3502582307 ps
CPU time 3.17 seconds
Started Jan 24 07:55:21 PM PST 24
Finished Jan 24 07:55:26 PM PST 24
Peak memory 207816 kb
Host smart-71ff5d9f-590c-4e6a-93a5-82450258b639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507680806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2507680806
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.246021389
Short name T636
Test name
Test status
Simulation time 37148976 ps
CPU time 0.85 seconds
Started Jan 24 07:55:24 PM PST 24
Finished Jan 24 07:55:27 PM PST 24
Peak memory 204584 kb
Host smart-532f103d-64fc-438c-883e-0efc79767a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246021389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.246021389
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3049155117
Short name T432
Test name
Test status
Simulation time 25868999491 ps
CPU time 19.36 seconds
Started Jan 24 07:55:33 PM PST 24
Finished Jan 24 07:55:54 PM PST 24
Peak memory 218872 kb
Host smart-84196c77-0b29-47f3-8978-8beaf0c83aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049155117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3049155117
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1957739530
Short name T627
Test name
Test status
Simulation time 11205378 ps
CPU time 0.7 seconds
Started Jan 24 07:55:46 PM PST 24
Finished Jan 24 07:55:47 PM PST 24
Peak memory 204124 kb
Host smart-45bca63d-7317-4658-90d7-3caf1e84194f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957739530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1957739530
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1895939722
Short name T612
Test name
Test status
Simulation time 734451981 ps
CPU time 2.89 seconds
Started Jan 24 07:55:40 PM PST 24
Finished Jan 24 07:55:44 PM PST 24
Peak memory 233112 kb
Host smart-0295bac7-bd2d-4317-b388-4810e9cfb5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895939722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1895939722
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1286978362
Short name T291
Test name
Test status
Simulation time 19039682 ps
CPU time 0.79 seconds
Started Jan 24 11:25:51 PM PST 24
Finished Jan 24 11:25:59 PM PST 24
Peak memory 204284 kb
Host smart-bd4d8443-ed2c-44a8-956c-7663d32b4e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286978362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1286978362
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2627575947
Short name T651
Test name
Test status
Simulation time 3278733918 ps
CPU time 22.38 seconds
Started Jan 24 07:55:35 PM PST 24
Finished Jan 24 07:55:58 PM PST 24
Peak memory 233980 kb
Host smart-610cf8c1-3b98-40db-b443-f521c6cc1d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627575947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2627575947
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.850220033
Short name T895
Test name
Test status
Simulation time 6374865450 ps
CPU time 118.79 seconds
Started Jan 24 08:48:31 PM PST 24
Finished Jan 24 08:50:31 PM PST 24
Peak memory 268064 kb
Host smart-8a19317e-2b22-4009-bdbf-cdfaafe1939d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850220033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.850220033
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.705438776
Short name T281
Test name
Test status
Simulation time 44770824820 ps
CPU time 18.63 seconds
Started Jan 24 09:26:00 PM PST 24
Finished Jan 24 09:26:20 PM PST 24
Peak memory 244724 kb
Host smart-db68bb1b-d726-47e2-a062-d024f5f3ce20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705438776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.705438776
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2570253447
Short name T200
Test name
Test status
Simulation time 16092707931 ps
CPU time 14.19 seconds
Started Jan 24 07:55:38 PM PST 24
Finished Jan 24 07:55:53 PM PST 24
Peak memory 220252 kb
Host smart-17429326-43ce-47e0-86af-ec70c1964657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570253447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2570253447
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2897098067
Short name T1090
Test name
Test status
Simulation time 8663031144 ps
CPU time 16.51 seconds
Started Jan 24 07:55:40 PM PST 24
Finished Jan 24 07:55:58 PM PST 24
Peak memory 229000 kb
Host smart-724ef83a-2a04-4a13-b882-c3eb1390960e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897098067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2897098067
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2216129371
Short name T245
Test name
Test status
Simulation time 980787078 ps
CPU time 10.56 seconds
Started Jan 24 07:55:38 PM PST 24
Finished Jan 24 07:55:50 PM PST 24
Peak memory 238220 kb
Host smart-c7c73886-8793-46db-afb7-908fe8e11f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216129371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2216129371
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1833484747
Short name T561
Test name
Test status
Simulation time 11565235124 ps
CPU time 6.11 seconds
Started Jan 24 07:55:46 PM PST 24
Finished Jan 24 07:55:52 PM PST 24
Peak memory 232676 kb
Host smart-573d5520-4b26-40d3-93c6-b11ad6b77394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833484747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1833484747
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3559881070
Short name T426
Test name
Test status
Simulation time 2711700741 ps
CPU time 7.16 seconds
Started Jan 24 07:55:40 PM PST 24
Finished Jan 24 07:55:49 PM PST 24
Peak memory 221772 kb
Host smart-7483815c-432c-4b66-a5b2-cc33b8b8d332
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3559881070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3559881070
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2162354574
Short name T469
Test name
Test status
Simulation time 4054881695 ps
CPU time 25.55 seconds
Started Jan 24 07:55:32 PM PST 24
Finished Jan 24 07:55:59 PM PST 24
Peak memory 216372 kb
Host smart-60b4475f-faff-4e3d-93cd-6f48434ec614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162354574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2162354574
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3162511801
Short name T579
Test name
Test status
Simulation time 1982875437 ps
CPU time 6.66 seconds
Started Jan 24 07:55:33 PM PST 24
Finished Jan 24 07:55:41 PM PST 24
Peak memory 207704 kb
Host smart-83a9bbef-3721-4093-b69d-7f1293fd7809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162511801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3162511801
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3316060290
Short name T1061
Test name
Test status
Simulation time 121457949 ps
CPU time 0.88 seconds
Started Jan 24 08:07:29 PM PST 24
Finished Jan 24 08:07:31 PM PST 24
Peak memory 205296 kb
Host smart-ac59575a-635f-4d7c-91ae-d231a20f2f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316060290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3316060290
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2896840520
Short name T864
Test name
Test status
Simulation time 188593967 ps
CPU time 1.02 seconds
Started Jan 24 08:30:14 PM PST 24
Finished Jan 24 08:30:15 PM PST 24
Peak memory 205628 kb
Host smart-a4f0124e-ec73-49a2-8dce-285721e84228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896840520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2896840520
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2259991618
Short name T248
Test name
Test status
Simulation time 4374379991 ps
CPU time 7.81 seconds
Started Jan 24 07:55:42 PM PST 24
Finished Jan 24 07:55:51 PM PST 24
Peak memory 236340 kb
Host smart-8e7fa031-34a0-46b4-a151-07261d39b07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259991618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2259991618
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1274266631
Short name T657
Test name
Test status
Simulation time 21330503 ps
CPU time 0.71 seconds
Started Jan 24 07:55:58 PM PST 24
Finished Jan 24 07:55:59 PM PST 24
Peak memory 203552 kb
Host smart-0125b919-d614-4dcc-98a2-7e50cfdd2fa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274266631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1274266631
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2842441558
Short name T626
Test name
Test status
Simulation time 408814983 ps
CPU time 3.78 seconds
Started Jan 24 07:55:52 PM PST 24
Finished Jan 24 07:55:58 PM PST 24
Peak memory 217072 kb
Host smart-aa9a07a8-6f9a-44b4-8c4d-680b658f8212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842441558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2842441558
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.230939680
Short name T688
Test name
Test status
Simulation time 13864126 ps
CPU time 0.73 seconds
Started Jan 24 07:55:48 PM PST 24
Finished Jan 24 07:55:50 PM PST 24
Peak memory 204256 kb
Host smart-bf0514aa-fe72-4e9e-802f-40d08715daee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230939680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.230939680
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3254198934
Short name T942
Test name
Test status
Simulation time 53092065803 ps
CPU time 254.59 seconds
Started Jan 24 11:05:49 PM PST 24
Finished Jan 24 11:10:07 PM PST 24
Peak memory 257088 kb
Host smart-b85b6fa1-cfb1-445d-92bf-e0002bf2b999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254198934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3254198934
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.4238726744
Short name T839
Test name
Test status
Simulation time 102547695296 ps
CPU time 220.8 seconds
Started Jan 24 10:32:22 PM PST 24
Finished Jan 24 10:36:03 PM PST 24
Peak memory 256984 kb
Host smart-a1f9897f-ce44-43d6-a3a0-fe2bc505bf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238726744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.4238726744
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1802605544
Short name T827
Test name
Test status
Simulation time 148308481725 ps
CPU time 266.57 seconds
Started Jan 24 07:55:57 PM PST 24
Finished Jan 24 08:00:25 PM PST 24
Peak memory 235272 kb
Host smart-9ffa61d9-2282-4112-b928-e6878332dde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802605544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1802605544
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1247048118
Short name T126
Test name
Test status
Simulation time 4440603876 ps
CPU time 13.47 seconds
Started Jan 24 09:41:21 PM PST 24
Finished Jan 24 09:41:39 PM PST 24
Peak memory 232464 kb
Host smart-f13c9bf7-007a-4526-8d8c-730117579020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247048118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1247048118
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1906261855
Short name T684
Test name
Test status
Simulation time 2734857445 ps
CPU time 5.7 seconds
Started Jan 24 07:55:58 PM PST 24
Finished Jan 24 07:56:05 PM PST 24
Peak memory 232452 kb
Host smart-5ff203b8-c7d5-4951-a5c8-e8b45ffcb23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906261855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1906261855
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1833852877
Short name T197
Test name
Test status
Simulation time 853858122 ps
CPU time 5.57 seconds
Started Jan 24 07:55:57 PM PST 24
Finished Jan 24 07:56:04 PM PST 24
Peak memory 232860 kb
Host smart-375fe021-be80-436b-a5f5-c23b3c2931ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833852877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1833852877
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2492372714
Short name T1053
Test name
Test status
Simulation time 798154808 ps
CPU time 4.86 seconds
Started Jan 24 07:55:56 PM PST 24
Finished Jan 24 07:56:02 PM PST 24
Peak memory 217860 kb
Host smart-53977fe8-41c9-481e-8dfa-e26d1e227f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492372714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2492372714
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1687196417
Short name T1021
Test name
Test status
Simulation time 33804012928 ps
CPU time 22.85 seconds
Started Jan 24 07:55:50 PM PST 24
Finished Jan 24 07:56:14 PM PST 24
Peak memory 232364 kb
Host smart-99b5abee-94c6-459b-acb9-0d9004ad73bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687196417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1687196417
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1258790078
Short name T1041
Test name
Test status
Simulation time 136201913 ps
CPU time 3.66 seconds
Started Jan 24 09:11:58 PM PST 24
Finished Jan 24 09:12:03 PM PST 24
Peak memory 221176 kb
Host smart-0c19bce6-4fab-4579-9247-d3c72c93548b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1258790078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1258790078
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1278901443
Short name T638
Test name
Test status
Simulation time 61088434 ps
CPU time 1.12 seconds
Started Jan 24 07:55:56 PM PST 24
Finished Jan 24 07:55:59 PM PST 24
Peak memory 205948 kb
Host smart-d7ab2351-685f-49c6-9e7c-dc3acc96515a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278901443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1278901443
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.816559181
Short name T661
Test name
Test status
Simulation time 1963183287 ps
CPU time 28.35 seconds
Started Jan 24 07:55:49 PM PST 24
Finished Jan 24 07:56:19 PM PST 24
Peak memory 216340 kb
Host smart-ff3f80fa-5bd3-4849-b41e-be6516afd7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816559181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.816559181
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.362666097
Short name T647
Test name
Test status
Simulation time 433114402 ps
CPU time 2.32 seconds
Started Jan 24 07:55:49 PM PST 24
Finished Jan 24 07:55:53 PM PST 24
Peak memory 207076 kb
Host smart-b07d55f1-225e-4c5e-87ba-a1a0c85d0414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362666097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.362666097
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.426582305
Short name T851
Test name
Test status
Simulation time 1849520111 ps
CPU time 7.46 seconds
Started Jan 24 07:55:47 PM PST 24
Finished Jan 24 07:55:55 PM PST 24
Peak memory 208148 kb
Host smart-d4efcd3e-c50f-4ddd-93d6-2fe002399b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426582305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.426582305
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2531099528
Short name T428
Test name
Test status
Simulation time 34130279 ps
CPU time 0.89 seconds
Started Jan 24 07:55:49 PM PST 24
Finished Jan 24 07:55:51 PM PST 24
Peak memory 205592 kb
Host smart-f5f783ca-243f-49d3-b21e-f1dc8964fcfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531099528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2531099528
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1391091102
Short name T487
Test name
Test status
Simulation time 188480536 ps
CPU time 2.32 seconds
Started Jan 24 08:18:23 PM PST 24
Finished Jan 24 08:18:27 PM PST 24
Peak memory 216012 kb
Host smart-676e14d6-5eb4-43d4-acca-8ce75cf30d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391091102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1391091102
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1522875427
Short name T884
Test name
Test status
Simulation time 16526378 ps
CPU time 0.76 seconds
Started Jan 24 07:56:10 PM PST 24
Finished Jan 24 07:56:12 PM PST 24
Peak memory 204096 kb
Host smart-7e809be5-2c83-49be-8fa8-6cec1df809a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522875427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1522875427
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.119755459
Short name T924
Test name
Test status
Simulation time 2118004462 ps
CPU time 6.97 seconds
Started Jan 24 07:56:04 PM PST 24
Finished Jan 24 07:56:12 PM PST 24
Peak memory 234400 kb
Host smart-ab99c45e-af73-41ab-826e-a9384451fc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119755459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.119755459
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1451510317
Short name T757
Test name
Test status
Simulation time 102182334 ps
CPU time 0.78 seconds
Started Jan 24 08:48:39 PM PST 24
Finished Jan 24 08:48:41 PM PST 24
Peak memory 205272 kb
Host smart-33aab353-1290-4c75-9644-104ef4a3cf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451510317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1451510317
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1546726616
Short name T890
Test name
Test status
Simulation time 22799500065 ps
CPU time 32.93 seconds
Started Jan 24 07:56:07 PM PST 24
Finished Jan 24 07:56:41 PM PST 24
Peak memory 251460 kb
Host smart-ff7cd214-d65a-4aff-9318-17281e4e9e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546726616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1546726616
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.214488436
Short name T711
Test name
Test status
Simulation time 27841637705 ps
CPU time 196.29 seconds
Started Jan 24 07:56:08 PM PST 24
Finished Jan 24 07:59:25 PM PST 24
Peak memory 250376 kb
Host smart-5615ff40-8e3b-445f-8387-c5792b5f8bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214488436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.214488436
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1790046257
Short name T589
Test name
Test status
Simulation time 1582083202 ps
CPU time 10.94 seconds
Started Jan 24 07:56:11 PM PST 24
Finished Jan 24 07:56:23 PM PST 24
Peak memory 237996 kb
Host smart-70298c14-36c6-4989-be63-bc34a7a9d900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790046257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1790046257
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.4161918497
Short name T1015
Test name
Test status
Simulation time 1866009327 ps
CPU time 5.92 seconds
Started Jan 24 07:56:06 PM PST 24
Finished Jan 24 07:56:13 PM PST 24
Peak memory 235888 kb
Host smart-3c7441fa-c751-4958-ae38-4856872a1591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161918497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.4161918497
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.4098219261
Short name T766
Test name
Test status
Simulation time 431878397 ps
CPU time 12.21 seconds
Started Jan 24 07:56:09 PM PST 24
Finished Jan 24 07:56:22 PM PST 24
Peak memory 233124 kb
Host smart-ff49fdaf-22f5-4512-8d33-a132149a2d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098219261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4098219261
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1489227653
Short name T607
Test name
Test status
Simulation time 33821327264 ps
CPU time 25.85 seconds
Started Jan 24 07:56:12 PM PST 24
Finished Jan 24 07:56:39 PM PST 24
Peak memory 222396 kb
Host smart-5e00d9d8-51b6-4905-92fb-9856dcf85bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489227653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1489227653
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1476470817
Short name T1068
Test name
Test status
Simulation time 675545793 ps
CPU time 4.99 seconds
Started Jan 24 07:56:07 PM PST 24
Finished Jan 24 07:56:12 PM PST 24
Peak memory 217792 kb
Host smart-02f827af-6bb8-4a56-9300-d7ae36f7986e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476470817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1476470817
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2755536865
Short name T885
Test name
Test status
Simulation time 1490100351 ps
CPU time 7.45 seconds
Started Jan 24 07:56:11 PM PST 24
Finished Jan 24 07:56:19 PM PST 24
Peak memory 221856 kb
Host smart-36d2d9aa-72f6-48ad-bf2f-c1c22ceecb38
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2755536865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2755536865
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.656329704
Short name T484
Test name
Test status
Simulation time 55972997965 ps
CPU time 67.64 seconds
Started Jan 24 07:55:54 PM PST 24
Finished Jan 24 07:57:03 PM PST 24
Peak memory 215992 kb
Host smart-ab7295c6-1bdc-4fec-926a-e1309c5397c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656329704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.656329704
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2307425639
Short name T1070
Test name
Test status
Simulation time 3083908331 ps
CPU time 6.96 seconds
Started Jan 24 07:55:57 PM PST 24
Finished Jan 24 07:56:06 PM PST 24
Peak memory 215992 kb
Host smart-a1b93f8d-60d6-407c-b3fc-dca263749596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307425639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2307425639
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1456739170
Short name T577
Test name
Test status
Simulation time 113648366 ps
CPU time 1.37 seconds
Started Jan 24 07:56:07 PM PST 24
Finished Jan 24 07:56:09 PM PST 24
Peak memory 207448 kb
Host smart-2cfd76da-3ced-490d-aef4-9b1205ee258f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456739170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1456739170
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1109079291
Short name T720
Test name
Test status
Simulation time 124494641 ps
CPU time 1.18 seconds
Started Jan 24 07:55:55 PM PST 24
Finished Jan 24 07:55:58 PM PST 24
Peak memory 205588 kb
Host smart-68b3aaf2-a0d5-4a68-b54c-58f185ff4275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109079291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1109079291
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1614600426
Short name T1092
Test name
Test status
Simulation time 1186643883 ps
CPU time 3.53 seconds
Started Jan 24 07:56:10 PM PST 24
Finished Jan 24 07:56:15 PM PST 24
Peak memory 216216 kb
Host smart-dac1ae1c-0ec7-4385-b078-cd4d819f449f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614600426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1614600426
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.4076707295
Short name T490
Test name
Test status
Simulation time 26823988 ps
CPU time 0.72 seconds
Started Jan 24 07:56:29 PM PST 24
Finished Jan 24 07:56:30 PM PST 24
Peak memory 204472 kb
Host smart-348a90b1-a48a-439a-b746-cd71c9d175a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076707295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
4076707295
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.587630668
Short name T453
Test name
Test status
Simulation time 102202565 ps
CPU time 2.97 seconds
Started Jan 24 07:56:20 PM PST 24
Finished Jan 24 07:56:24 PM PST 24
Peak memory 232664 kb
Host smart-73478afb-8ef1-4c1e-a4db-50431aca62b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587630668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.587630668
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.4187531453
Short name T900
Test name
Test status
Simulation time 36069149 ps
CPU time 0.77 seconds
Started Jan 24 08:28:42 PM PST 24
Finished Jan 24 08:28:47 PM PST 24
Peak memory 204252 kb
Host smart-49e60478-f734-4bd9-a50d-017c2eea8d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187531453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.4187531453
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2503775797
Short name T201
Test name
Test status
Simulation time 77871605971 ps
CPU time 348.7 seconds
Started Jan 24 07:56:33 PM PST 24
Finished Jan 24 08:02:22 PM PST 24
Peak memory 254964 kb
Host smart-6d806381-833e-44bf-a4ce-215a2c7ec6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503775797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2503775797
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2679844386
Short name T277
Test name
Test status
Simulation time 87238632159 ps
CPU time 152.09 seconds
Started Jan 24 07:56:33 PM PST 24
Finished Jan 24 07:59:06 PM PST 24
Peak memory 261028 kb
Host smart-7c2d3eeb-e87d-45a2-82d5-f5458912d731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679844386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2679844386
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.849269648
Short name T508
Test name
Test status
Simulation time 22166898357 ps
CPU time 25.1 seconds
Started Jan 24 07:56:32 PM PST 24
Finished Jan 24 07:56:58 PM PST 24
Peak memory 225804 kb
Host smart-2b96f418-67cf-4b8a-be82-a911ba60c049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849269648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.849269648
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3652225711
Short name T700
Test name
Test status
Simulation time 154452798 ps
CPU time 4.23 seconds
Started Jan 24 07:56:22 PM PST 24
Finished Jan 24 07:56:27 PM PST 24
Peak memory 218440 kb
Host smart-f471970a-d63d-4424-9a5c-21c5bf938080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652225711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3652225711
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.530786880
Short name T212
Test name
Test status
Simulation time 50830106827 ps
CPU time 35.54 seconds
Started Jan 24 07:56:23 PM PST 24
Finished Jan 24 07:56:59 PM PST 24
Peak memory 239572 kb
Host smart-03421eb9-0f17-483b-8544-e9c83297c786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530786880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.530786880
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3369701356
Short name T958
Test name
Test status
Simulation time 96777571 ps
CPU time 3.15 seconds
Started Jan 24 07:56:33 PM PST 24
Finished Jan 24 07:56:37 PM PST 24
Peak memory 232880 kb
Host smart-e29bb238-c724-48f7-826b-cb3a4ffe56e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369701356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3369701356
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2713689510
Short name T54
Test name
Test status
Simulation time 167846930 ps
CPU time 3.32 seconds
Started Jan 24 07:56:33 PM PST 24
Finished Jan 24 07:56:37 PM PST 24
Peak memory 232800 kb
Host smart-3546c7b2-ee79-41ec-a8d6-c50b4e11585d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713689510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2713689510
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2631067676
Short name T667
Test name
Test status
Simulation time 539273152 ps
CPU time 3.39 seconds
Started Jan 24 07:56:20 PM PST 24
Finished Jan 24 07:56:25 PM PST 24
Peak memory 221796 kb
Host smart-8b872a5c-9921-4524-bf38-7db904207c06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2631067676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2631067676
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2899729817
Short name T972
Test name
Test status
Simulation time 1855100995 ps
CPU time 20.86 seconds
Started Jan 24 07:56:15 PM PST 24
Finished Jan 24 07:56:36 PM PST 24
Peak memory 218396 kb
Host smart-95156527-5bd3-4993-abbe-45c7f4d21028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899729817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2899729817
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1067531453
Short name T973
Test name
Test status
Simulation time 2614117275 ps
CPU time 6.06 seconds
Started Jan 24 08:27:36 PM PST 24
Finished Jan 24 08:27:44 PM PST 24
Peak memory 215816 kb
Host smart-14f0f376-8537-4af9-b96c-a488c6d175b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067531453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1067531453
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2871454040
Short name T1040
Test name
Test status
Simulation time 1721580771 ps
CPU time 14.84 seconds
Started Jan 24 09:44:32 PM PST 24
Finished Jan 24 09:44:48 PM PST 24
Peak memory 207780 kb
Host smart-07e4ec15-f2a6-497f-9b0a-78429498915e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871454040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2871454040
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2776469473
Short name T532
Test name
Test status
Simulation time 202426722 ps
CPU time 0.84 seconds
Started Jan 24 07:56:17 PM PST 24
Finished Jan 24 07:56:18 PM PST 24
Peak memory 204592 kb
Host smart-99660f3e-7c77-4f7f-a55c-3ef525a584cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776469473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2776469473
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2731116825
Short name T714
Test name
Test status
Simulation time 8198096793 ps
CPU time 24.52 seconds
Started Jan 24 07:56:33 PM PST 24
Finished Jan 24 07:56:58 PM PST 24
Peak memory 227400 kb
Host smart-dd3f80c0-39a4-47a1-b8c1-4d341a4d8624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731116825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2731116825
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1086038722
Short name T603
Test name
Test status
Simulation time 184159744 ps
CPU time 0.72 seconds
Started Jan 24 08:39:22 PM PST 24
Finished Jan 24 08:39:24 PM PST 24
Peak memory 203564 kb
Host smart-bdf5eee4-4f7c-467c-94d2-e552542024e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086038722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1086038722
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.608635145
Short name T591
Test name
Test status
Simulation time 164695229 ps
CPU time 3.55 seconds
Started Jan 24 08:45:16 PM PST 24
Finished Jan 24 08:45:20 PM PST 24
Peak memory 217484 kb
Host smart-b5e393f4-40eb-4bc2-a4f1-4dd91f61a872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608635145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.608635145
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1163645638
Short name T58
Test name
Test status
Simulation time 20696817 ps
CPU time 0.78 seconds
Started Jan 24 07:56:30 PM PST 24
Finished Jan 24 07:56:32 PM PST 24
Peak memory 205608 kb
Host smart-34f2bf39-2286-4448-9ef9-042612d7de5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163645638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1163645638
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.212943142
Short name T159
Test name
Test status
Simulation time 196596765298 ps
CPU time 275.99 seconds
Started Jan 24 08:04:09 PM PST 24
Finished Jan 24 08:08:50 PM PST 24
Peak memory 254740 kb
Host smart-bb667b01-9c69-4189-9f46-69282195ff72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212943142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.212943142
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3022651317
Short name T1089
Test name
Test status
Simulation time 34182001863 ps
CPU time 239.62 seconds
Started Jan 24 07:56:38 PM PST 24
Finished Jan 24 08:00:38 PM PST 24
Peak memory 224344 kb
Host smart-c2fea5ae-d3e8-4268-8720-4823f105e57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022651317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3022651317
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.61166137
Short name T583
Test name
Test status
Simulation time 2995063260 ps
CPU time 20.04 seconds
Started Jan 24 07:56:35 PM PST 24
Finished Jan 24 07:56:56 PM PST 24
Peak memory 248792 kb
Host smart-d475fded-a1c9-4849-b095-3a72464566ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61166137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.61166137
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2520610344
Short name T642
Test name
Test status
Simulation time 930462698 ps
CPU time 3.93 seconds
Started Jan 24 07:56:27 PM PST 24
Finished Jan 24 07:56:32 PM PST 24
Peak memory 218700 kb
Host smart-cec9a06a-67af-4888-98af-917fcc1e2e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520610344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2520610344
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4202843249
Short name T811
Test name
Test status
Simulation time 268195822 ps
CPU time 4.08 seconds
Started Jan 24 07:56:29 PM PST 24
Finished Jan 24 07:56:34 PM PST 24
Peak memory 220168 kb
Host smart-5169f687-ab96-4b1d-b0f3-2020ae13761c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202843249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4202843249
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2616043539
Short name T748
Test name
Test status
Simulation time 919979679 ps
CPU time 3.93 seconds
Started Jan 24 07:56:29 PM PST 24
Finished Jan 24 07:56:34 PM PST 24
Peak memory 232936 kb
Host smart-07cb2c05-281c-4cb9-ba60-0e169773ba23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616043539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2616043539
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.716347293
Short name T216
Test name
Test status
Simulation time 1079167888 ps
CPU time 5.47 seconds
Started Jan 24 07:56:31 PM PST 24
Finished Jan 24 07:56:37 PM PST 24
Peak memory 216104 kb
Host smart-02168bac-0ff9-4a08-8779-bed2c85bf63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716347293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.716347293
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3905938008
Short name T682
Test name
Test status
Simulation time 214173291 ps
CPU time 3.59 seconds
Started Jan 24 08:18:39 PM PST 24
Finished Jan 24 08:18:45 PM PST 24
Peak memory 216252 kb
Host smart-a073b0fd-deb7-4439-905f-74963b47f3e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3905938008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3905938008
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1905574808
Short name T810
Test name
Test status
Simulation time 181262411746 ps
CPU time 387.59 seconds
Started Jan 24 07:56:36 PM PST 24
Finished Jan 24 08:03:04 PM PST 24
Peak memory 257124 kb
Host smart-f96e237e-bcd2-4c92-89cb-bbb2aeb86869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905574808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1905574808
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.335318525
Short name T743
Test name
Test status
Simulation time 482671369 ps
CPU time 3.47 seconds
Started Jan 24 07:56:28 PM PST 24
Finished Jan 24 07:56:32 PM PST 24
Peak memory 207700 kb
Host smart-79979ce9-c3d0-4ed1-a539-dda965ab08bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335318525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.335318525
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1114902396
Short name T964
Test name
Test status
Simulation time 31222924 ps
CPU time 0.79 seconds
Started Jan 24 07:56:26 PM PST 24
Finished Jan 24 07:56:27 PM PST 24
Peak memory 204560 kb
Host smart-089245fa-db3b-43a7-ad16-3c1848a8f59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114902396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1114902396
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3233884847
Short name T295
Test name
Test status
Simulation time 241351873 ps
CPU time 0.92 seconds
Started Jan 24 07:56:32 PM PST 24
Finished Jan 24 07:56:34 PM PST 24
Peak memory 204584 kb
Host smart-39660d85-59ef-4e83-b678-5fdd137b0c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233884847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3233884847
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1867568161
Short name T242
Test name
Test status
Simulation time 629575994 ps
CPU time 4.94 seconds
Started Jan 24 07:56:25 PM PST 24
Finished Jan 24 07:56:31 PM PST 24
Peak memory 233152 kb
Host smart-ecf637ba-1d72-4f5e-a6a1-bee13ab3055f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867568161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1867568161
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3607230061
Short name T298
Test name
Test status
Simulation time 45402466 ps
CPU time 0.71 seconds
Started Jan 24 07:56:55 PM PST 24
Finished Jan 24 07:56:57 PM PST 24
Peak memory 203560 kb
Host smart-cde2adda-ae30-4908-912a-483a40d826a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607230061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3607230061
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.4086934702
Short name T640
Test name
Test status
Simulation time 396835326 ps
CPU time 3.75 seconds
Started Jan 24 07:56:51 PM PST 24
Finished Jan 24 07:56:56 PM PST 24
Peak memory 233104 kb
Host smart-4f8e4c07-65d5-4971-b6b0-764c68c161b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086934702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.4086934702
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3033476173
Short name T542
Test name
Test status
Simulation time 177286599 ps
CPU time 0.75 seconds
Started Jan 24 07:56:34 PM PST 24
Finished Jan 24 07:56:35 PM PST 24
Peak memory 204232 kb
Host smart-225b1599-b938-423f-8e5b-69cdcd7bf3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033476173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3033476173
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1999905285
Short name T719
Test name
Test status
Simulation time 104229133788 ps
CPU time 167.57 seconds
Started Jan 24 07:56:51 PM PST 24
Finished Jan 24 07:59:40 PM PST 24
Peak memory 255944 kb
Host smart-321ad331-a6f7-499f-94ea-b6cf3f4142c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999905285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1999905285
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1257736217
Short name T869
Test name
Test status
Simulation time 13820980077 ps
CPU time 173.85 seconds
Started Jan 24 07:56:49 PM PST 24
Finished Jan 24 07:59:44 PM PST 24
Peak memory 269544 kb
Host smart-36fab148-dcf5-4a59-85ec-5a9f7bc623ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257736217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1257736217
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2451848511
Short name T179
Test name
Test status
Simulation time 171239281900 ps
CPU time 326.39 seconds
Started Jan 24 07:56:51 PM PST 24
Finished Jan 24 08:02:18 PM PST 24
Peak memory 270292 kb
Host smart-2eba599f-d056-497e-968b-74ad16007d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451848511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2451848511
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2652726084
Short name T693
Test name
Test status
Simulation time 4141464591 ps
CPU time 21.98 seconds
Started Jan 24 07:56:51 PM PST 24
Finished Jan 24 07:57:13 PM PST 24
Peak memory 230944 kb
Host smart-5345b892-57f4-4623-87d4-faf61eadf464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652726084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2652726084
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2824700437
Short name T975
Test name
Test status
Simulation time 118957593 ps
CPU time 2.44 seconds
Started Jan 24 08:49:35 PM PST 24
Finished Jan 24 08:49:38 PM PST 24
Peak memory 232864 kb
Host smart-044fabf1-1525-40a3-9482-d124dd4f111e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824700437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2824700437
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.254447832
Short name T238
Test name
Test status
Simulation time 782108678 ps
CPU time 8.91 seconds
Started Jan 24 07:56:50 PM PST 24
Finished Jan 24 07:57:00 PM PST 24
Peak memory 232836 kb
Host smart-e3d0c047-16d1-4fc9-ba99-e8d739310dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254447832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.254447832
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.118389332
Short name T931
Test name
Test status
Simulation time 69248830399 ps
CPU time 42.39 seconds
Started Jan 24 07:56:43 PM PST 24
Finished Jan 24 07:57:27 PM PST 24
Peak memory 232452 kb
Host smart-45ed7bb6-effe-40e5-a1fa-73b8f8b05895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118389332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.118389332
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1114492614
Short name T252
Test name
Test status
Simulation time 8173854009 ps
CPU time 8.81 seconds
Started Jan 24 07:56:49 PM PST 24
Finished Jan 24 07:56:59 PM PST 24
Peak memory 216136 kb
Host smart-25f78900-260d-485d-a38d-3fdeaba704fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114492614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1114492614
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1611343292
Short name T559
Test name
Test status
Simulation time 364097759 ps
CPU time 4.42 seconds
Started Jan 24 07:56:44 PM PST 24
Finished Jan 24 07:56:49 PM PST 24
Peak memory 216068 kb
Host smart-dfa20c4f-e416-45e1-8821-4b1e6f4a44cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1611343292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1611343292
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3215045411
Short name T271
Test name
Test status
Simulation time 6648545533 ps
CPU time 88.19 seconds
Started Jan 24 07:56:48 PM PST 24
Finished Jan 24 07:58:18 PM PST 24
Peak memory 258664 kb
Host smart-0f1a48b8-32b5-4094-839f-0d5ea00dc825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215045411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3215045411
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1212433277
Short name T877
Test name
Test status
Simulation time 12351882331 ps
CPU time 53.5 seconds
Started Jan 24 07:56:48 PM PST 24
Finished Jan 24 07:57:42 PM PST 24
Peak memory 218464 kb
Host smart-20e3f3c2-11d2-4794-8a9f-c80849e2fa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212433277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1212433277
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2184074039
Short name T835
Test name
Test status
Simulation time 46423051 ps
CPU time 0.88 seconds
Started Jan 24 07:56:49 PM PST 24
Finished Jan 24 07:56:50 PM PST 24
Peak memory 205116 kb
Host smart-b2ef47cb-2aa0-4d5d-b4cf-481c69a85ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184074039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2184074039
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2071242297
Short name T655
Test name
Test status
Simulation time 203737050 ps
CPU time 1.08 seconds
Started Jan 24 07:56:44 PM PST 24
Finished Jan 24 07:56:46 PM PST 24
Peak memory 205588 kb
Host smart-48b0a21b-8ce5-4720-afe7-e35016afdaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071242297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2071242297
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1872638344
Short name T502
Test name
Test status
Simulation time 457345285 ps
CPU time 2.99 seconds
Started Jan 24 07:56:46 PM PST 24
Finished Jan 24 07:56:50 PM PST 24
Peak memory 233176 kb
Host smart-f161df35-35dd-4014-8741-f0d3149b4018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872638344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1872638344
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.420643836
Short name T423
Test name
Test status
Simulation time 24399429 ps
CPU time 0.7 seconds
Started Jan 24 07:46:47 PM PST 24
Finished Jan 24 07:46:49 PM PST 24
Peak memory 204128 kb
Host smart-ab35a8d7-c322-406b-ba15-b864cef46745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420643836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.420643836
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3081009847
Short name T536
Test name
Test status
Simulation time 720808302 ps
CPU time 2.58 seconds
Started Jan 24 07:46:52 PM PST 24
Finished Jan 24 07:46:57 PM PST 24
Peak memory 217028 kb
Host smart-6759e352-b67e-47db-b4bf-0802755a002b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081009847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3081009847
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2741751537
Short name T1091
Test name
Test status
Simulation time 24188840 ps
CPU time 0.73 seconds
Started Jan 24 07:46:44 PM PST 24
Finished Jan 24 07:46:45 PM PST 24
Peak memory 204220 kb
Host smart-aab64aaa-1258-4fa7-90ee-928469e1ec2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741751537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2741751537
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2276518746
Short name T915
Test name
Test status
Simulation time 167117304430 ps
CPU time 195.23 seconds
Started Jan 24 08:57:54 PM PST 24
Finished Jan 24 09:01:12 PM PST 24
Peak memory 252084 kb
Host smart-f29518e1-c34f-492c-b681-7cbe98944a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276518746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2276518746
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.851803321
Short name T429
Test name
Test status
Simulation time 68072590861 ps
CPU time 114.1 seconds
Started Jan 24 07:46:50 PM PST 24
Finished Jan 24 07:48:45 PM PST 24
Peak memory 232416 kb
Host smart-2dfb47a5-0ef9-45b3-8888-d5caa00f03f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851803321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.851803321
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3159658781
Short name T289
Test name
Test status
Simulation time 11032138755 ps
CPU time 110.95 seconds
Started Jan 24 09:21:43 PM PST 24
Finished Jan 24 09:23:37 PM PST 24
Peak memory 255052 kb
Host smart-8e613706-a3d5-4cb9-b0af-e90ecc615fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159658781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3159658781
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1737896700
Short name T910
Test name
Test status
Simulation time 7150640726 ps
CPU time 11.46 seconds
Started Jan 24 07:55:50 PM PST 24
Finished Jan 24 07:56:04 PM PST 24
Peak memory 236548 kb
Host smart-1d810a8e-f49e-4218-bb52-0d160d020c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737896700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1737896700
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2003938294
Short name T251
Test name
Test status
Simulation time 583840195 ps
CPU time 7.27 seconds
Started Jan 24 07:46:50 PM PST 24
Finished Jan 24 07:46:58 PM PST 24
Peak memory 233260 kb
Host smart-d1086a41-6dbb-4882-8132-bba9a4593ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003938294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2003938294
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3748278875
Short name T204
Test name
Test status
Simulation time 404553961 ps
CPU time 4.09 seconds
Started Jan 24 07:46:49 PM PST 24
Finished Jan 24 07:46:54 PM PST 24
Peak memory 216348 kb
Host smart-97fbd4ee-a5c0-4b3b-a00f-ea6964416075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748278875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3748278875
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2850293015
Short name T565
Test name
Test status
Simulation time 82890186 ps
CPU time 1.03 seconds
Started Jan 24 07:46:36 PM PST 24
Finished Jan 24 07:46:38 PM PST 24
Peak memory 215788 kb
Host smart-c06e78c9-7b1e-44b0-bf9b-23916fd3dbd4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850293015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2850293015
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.675179094
Short name T801
Test name
Test status
Simulation time 1231671677 ps
CPU time 4.63 seconds
Started Jan 24 07:46:52 PM PST 24
Finished Jan 24 07:46:59 PM PST 24
Peak memory 218288 kb
Host smart-26c054ea-106d-48b1-877e-1d41161c6925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675179094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
675179094
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2726791518
Short name T476
Test name
Test status
Simulation time 5729594910 ps
CPU time 17.58 seconds
Started Jan 24 07:46:45 PM PST 24
Finished Jan 24 07:47:03 PM PST 24
Peak memory 237076 kb
Host smart-033c64e2-047f-431a-a723-f1a71df9bbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726791518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2726791518
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.3587294338
Short name T46
Test name
Test status
Simulation time 15142137 ps
CPU time 0.82 seconds
Started Jan 24 07:46:50 PM PST 24
Finished Jan 24 07:46:52 PM PST 24
Peak memory 215636 kb
Host smart-7e74e33a-b2d6-4af6-a7e6-ea833131a042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587294338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.3587294338
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2890332066
Short name T604
Test name
Test status
Simulation time 3006678479 ps
CPU time 6.64 seconds
Started Jan 24 07:46:46 PM PST 24
Finished Jan 24 07:46:53 PM PST 24
Peak memory 221176 kb
Host smart-a7a531de-fc86-4e93-9c76-5e469f1dc6f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2890332066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2890332066
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3790692552
Short name T162
Test name
Test status
Simulation time 4150960188 ps
CPU time 63.45 seconds
Started Jan 24 07:46:50 PM PST 24
Finished Jan 24 07:47:54 PM PST 24
Peak memory 232460 kb
Host smart-f939ad92-0f82-4f52-aa66-a3cc456d1edf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790692552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3790692552
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3669678345
Short name T880
Test name
Test status
Simulation time 3423286869 ps
CPU time 29.13 seconds
Started Jan 24 09:42:02 PM PST 24
Finished Jan 24 09:42:32 PM PST 24
Peak memory 216028 kb
Host smart-f1a3fbec-8e64-4386-9c6e-4aae3c76f194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669678345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3669678345
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3654748683
Short name T652
Test name
Test status
Simulation time 2621373741 ps
CPU time 9.29 seconds
Started Jan 24 07:46:52 PM PST 24
Finished Jan 24 07:47:03 PM PST 24
Peak memory 207672 kb
Host smart-e87aabc1-03c7-429f-a2f7-73d522d59787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654748683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3654748683
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.148626271
Short name T669
Test name
Test status
Simulation time 128794754 ps
CPU time 5.24 seconds
Started Jan 24 07:46:47 PM PST 24
Finished Jan 24 07:46:53 PM PST 24
Peak memory 216060 kb
Host smart-680405e8-c4b5-4150-bef7-02bc82b5271d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148626271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.148626271
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2112475864
Short name T1069
Test name
Test status
Simulation time 506125288 ps
CPU time 1.06 seconds
Started Jan 24 07:46:50 PM PST 24
Finished Jan 24 07:46:52 PM PST 24
Peak memory 205612 kb
Host smart-711d7630-6dfc-4a01-a284-3fa121b4ecbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112475864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2112475864
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3016273820
Short name T1019
Test name
Test status
Simulation time 47349210648 ps
CPU time 38.33 seconds
Started Jan 24 07:46:54 PM PST 24
Finished Jan 24 07:47:33 PM PST 24
Peak memory 218836 kb
Host smart-48b1c7fa-c846-4f33-a9fa-2bb44a499864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016273820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3016273820
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3881160665
Short name T965
Test name
Test status
Simulation time 40081114 ps
CPU time 0.73 seconds
Started Jan 24 07:47:05 PM PST 24
Finished Jan 24 07:47:07 PM PST 24
Peak memory 204080 kb
Host smart-9a30748c-73df-4ee3-907a-7f400cd94688
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881160665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
881160665
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2653729210
Short name T828
Test name
Test status
Simulation time 5688549455 ps
CPU time 7.7 seconds
Started Jan 24 07:46:53 PM PST 24
Finished Jan 24 07:47:02 PM PST 24
Peak memory 218896 kb
Host smart-1940aedf-7256-4fe1-9d6f-46e72a66a292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653729210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2653729210
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.4003835024
Short name T443
Test name
Test status
Simulation time 57749272 ps
CPU time 0.77 seconds
Started Jan 24 07:46:51 PM PST 24
Finished Jan 24 07:46:53 PM PST 24
Peak memory 205308 kb
Host smart-037ed783-8e80-4c80-8359-1411810d50f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003835024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.4003835024
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.451770695
Short name T190
Test name
Test status
Simulation time 151490436368 ps
CPU time 199.36 seconds
Started Jan 24 07:46:51 PM PST 24
Finished Jan 24 07:50:11 PM PST 24
Peak memory 249932 kb
Host smart-f95c12c2-868d-4595-bc9f-5fbdd1dab22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451770695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.451770695
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2198985623
Short name T663
Test name
Test status
Simulation time 25602419719 ps
CPU time 235.45 seconds
Started Jan 24 07:46:53 PM PST 24
Finished Jan 24 07:50:50 PM PST 24
Peak memory 262472 kb
Host smart-a4ec6e48-d2e6-4adc-b5a8-3f15d9731387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198985623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2198985623
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3176965716
Short name T853
Test name
Test status
Simulation time 39423246971 ps
CPU time 178.52 seconds
Started Jan 24 07:46:51 PM PST 24
Finished Jan 24 07:49:51 PM PST 24
Peak memory 253636 kb
Host smart-eb4f8e68-01ef-4bf9-afe3-f4e1d8e5f503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176965716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3176965716
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3354420861
Short name T925
Test name
Test status
Simulation time 13028914379 ps
CPU time 24.66 seconds
Started Jan 24 08:16:30 PM PST 24
Finished Jan 24 08:16:56 PM PST 24
Peak memory 232528 kb
Host smart-6ca7b182-7e42-4cbe-9b60-64d63bcf192c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354420861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3354420861
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.90790451
Short name T991
Test name
Test status
Simulation time 696457182 ps
CPU time 3.95 seconds
Started Jan 24 07:46:52 PM PST 24
Finished Jan 24 07:46:57 PM PST 24
Peak memory 217384 kb
Host smart-b3fc61f7-46c1-419e-9cde-4f0e9c0a14cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90790451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.90790451
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.4098828568
Short name T854
Test name
Test status
Simulation time 7056822535 ps
CPU time 8.17 seconds
Started Jan 24 09:12:55 PM PST 24
Finished Jan 24 09:13:07 PM PST 24
Peak memory 236432 kb
Host smart-bed81a25-7660-441c-a079-17c6fa3df2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098828568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.4098828568
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3774211590
Short name T25
Test name
Test status
Simulation time 102113965 ps
CPU time 1.06 seconds
Started Jan 24 07:46:54 PM PST 24
Finished Jan 24 07:46:56 PM PST 24
Peak memory 215752 kb
Host smart-bd028821-f215-4d84-bfad-99a071f295e2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774211590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3774211590
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1938846419
Short name T261
Test name
Test status
Simulation time 2343965861 ps
CPU time 5.39 seconds
Started Jan 24 07:46:53 PM PST 24
Finished Jan 24 07:47:00 PM PST 24
Peak memory 233664 kb
Host smart-02b6e3b4-0045-48b8-a57b-fc209c4fc433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938846419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1938846419
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3907699996
Short name T224
Test name
Test status
Simulation time 796814649 ps
CPU time 10.8 seconds
Started Jan 24 07:46:55 PM PST 24
Finished Jan 24 07:47:07 PM PST 24
Peak memory 239552 kb
Host smart-9fb61ca2-eb67-4d71-90f3-778e8372ca47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907699996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3907699996
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.3645059328
Short name T45
Test name
Test status
Simulation time 16513226 ps
CPU time 0.75 seconds
Started Jan 24 07:46:50 PM PST 24
Finished Jan 24 07:46:52 PM PST 24
Peak memory 215868 kb
Host smart-46da5441-4b81-434d-b9ed-f99c6e242ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645059328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.3645059328
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2652816711
Short name T649
Test name
Test status
Simulation time 153176835 ps
CPU time 3.81 seconds
Started Jan 24 07:46:54 PM PST 24
Finished Jan 24 07:46:59 PM PST 24
Peak memory 221580 kb
Host smart-298d9b76-1fdb-4a8c-aab0-84a2a343988c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2652816711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2652816711
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1437625151
Short name T501
Test name
Test status
Simulation time 42435346 ps
CPU time 0.97 seconds
Started Jan 24 07:47:00 PM PST 24
Finished Jan 24 07:47:03 PM PST 24
Peak memory 205680 kb
Host smart-c30c012a-ae7f-495a-b450-d8db1e62b2e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437625151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1437625151
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3603310351
Short name T737
Test name
Test status
Simulation time 21106094400 ps
CPU time 35.82 seconds
Started Jan 24 07:46:56 PM PST 24
Finished Jan 24 07:47:33 PM PST 24
Peak memory 219672 kb
Host smart-21996e2a-7bcb-492d-a27f-ec18dd615a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603310351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3603310351
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1748523425
Short name T461
Test name
Test status
Simulation time 5662747934 ps
CPU time 11.28 seconds
Started Jan 24 08:42:47 PM PST 24
Finished Jan 24 08:43:00 PM PST 24
Peak memory 216052 kb
Host smart-9642aa17-7c3b-411d-ab8c-b47f2b821dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748523425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1748523425
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2356530790
Short name T297
Test name
Test status
Simulation time 195146379 ps
CPU time 3.73 seconds
Started Jan 24 07:46:54 PM PST 24
Finished Jan 24 07:46:59 PM PST 24
Peak memory 207724 kb
Host smart-52eedaf1-1255-4b31-a6a6-3127eb19441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356530790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2356530790
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1624994760
Short name T434
Test name
Test status
Simulation time 400926767 ps
CPU time 0.93 seconds
Started Jan 24 09:31:20 PM PST 24
Finished Jan 24 09:31:22 PM PST 24
Peak memory 204604 kb
Host smart-3586e6e9-b6da-4af6-b0fe-4ad80ba2a5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624994760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1624994760
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1110952613
Short name T676
Test name
Test status
Simulation time 38034493937 ps
CPU time 33.35 seconds
Started Jan 24 07:46:56 PM PST 24
Finished Jan 24 07:47:31 PM PST 24
Peak memory 233312 kb
Host smart-724d1b3a-7af6-4460-ba37-1491c37b05c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110952613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1110952613
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.369714167
Short name T989
Test name
Test status
Simulation time 12268532 ps
CPU time 0.7 seconds
Started Jan 24 07:47:17 PM PST 24
Finished Jan 24 07:47:19 PM PST 24
Peak memory 204392 kb
Host smart-346d8f86-8ec2-4875-8136-07acf5619c93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369714167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.369714167
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3370118823
Short name T1033
Test name
Test status
Simulation time 233553885 ps
CPU time 3.33 seconds
Started Jan 24 07:47:09 PM PST 24
Finished Jan 24 07:47:13 PM PST 24
Peak memory 233436 kb
Host smart-40916c2b-c1f6-4ab7-8a20-696e1f6792dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370118823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3370118823
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2607666176
Short name T57
Test name
Test status
Simulation time 32470517 ps
CPU time 0.76 seconds
Started Jan 24 07:47:01 PM PST 24
Finished Jan 24 07:47:03 PM PST 24
Peak memory 205264 kb
Host smart-5a9bb0b8-71eb-4db1-8165-f20194d6f3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607666176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2607666176
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3700169311
Short name T192
Test name
Test status
Simulation time 18723708386 ps
CPU time 85.46 seconds
Started Jan 24 07:47:09 PM PST 24
Finished Jan 24 07:48:36 PM PST 24
Peak memory 263168 kb
Host smart-b816f336-aee3-4ce7-9b2d-e0f7bc06d39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700169311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3700169311
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3079447729
Short name T1059
Test name
Test status
Simulation time 169592910995 ps
CPU time 309.2 seconds
Started Jan 24 07:47:12 PM PST 24
Finished Jan 24 07:52:22 PM PST 24
Peak memory 256616 kb
Host smart-ccaf58c9-5b82-4149-b172-ee2bd815ab79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079447729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3079447729
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1215490564
Short name T515
Test name
Test status
Simulation time 12687175494 ps
CPU time 81.03 seconds
Started Jan 24 08:00:26 PM PST 24
Finished Jan 24 08:01:50 PM PST 24
Peak memory 248984 kb
Host smart-8254b8c3-3508-44be-8dad-81de681d22a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215490564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1215490564
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1527375071
Short name T124
Test name
Test status
Simulation time 4574137322 ps
CPU time 28.67 seconds
Started Jan 24 07:56:12 PM PST 24
Finished Jan 24 07:56:42 PM PST 24
Peak memory 235776 kb
Host smart-45043ce7-d1c3-40b6-90c8-02184d8b19a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527375071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1527375071
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2372249820
Short name T512
Test name
Test status
Simulation time 240662227 ps
CPU time 4.38 seconds
Started Jan 24 07:47:09 PM PST 24
Finished Jan 24 07:47:14 PM PST 24
Peak memory 233332 kb
Host smart-8f2b2734-193d-4510-8d23-7a141db18c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372249820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2372249820
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3337898168
Short name T697
Test name
Test status
Simulation time 72978172613 ps
CPU time 18.95 seconds
Started Jan 24 07:47:12 PM PST 24
Finished Jan 24 07:47:33 PM PST 24
Peak memory 235300 kb
Host smart-7155a3f7-7191-4d24-8231-d8b6d5af5e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337898168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3337898168
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1471203882
Short name T1084
Test name
Test status
Simulation time 26723730 ps
CPU time 1.04 seconds
Started Jan 24 07:46:59 PM PST 24
Finished Jan 24 07:47:02 PM PST 24
Peak memory 215752 kb
Host smart-da56d3b4-c97b-4e38-8c70-fb81d4b90520
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471203882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1471203882
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1863166753
Short name T1046
Test name
Test status
Simulation time 4710824450 ps
CPU time 10.45 seconds
Started Jan 24 09:04:23 PM PST 24
Finished Jan 24 09:04:37 PM PST 24
Peak memory 217160 kb
Host smart-f1bcfb98-1b83-436e-940a-d19bd2208301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863166753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1863166753
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3403873160
Short name T632
Test name
Test status
Simulation time 1205138377 ps
CPU time 2.65 seconds
Started Jan 24 08:04:02 PM PST 24
Finished Jan 24 08:04:07 PM PST 24
Peak memory 216224 kb
Host smart-f8e0ee35-a89b-49ad-bbef-907f150964f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403873160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3403873160
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.3549016611
Short name T933
Test name
Test status
Simulation time 17167097 ps
CPU time 0.75 seconds
Started Jan 24 07:47:07 PM PST 24
Finished Jan 24 07:47:09 PM PST 24
Peak memory 215852 kb
Host smart-b70420fd-5b17-4dc0-ba0f-991622d173ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549016611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.3549016611
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.409573260
Short name T125
Test name
Test status
Simulation time 271384067 ps
CPU time 4.24 seconds
Started Jan 25 01:00:08 AM PST 24
Finished Jan 25 01:00:14 AM PST 24
Peak memory 221740 kb
Host smart-f84ef6dd-af52-4a04-ad86-a62ccd3c124e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=409573260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.409573260
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2665434801
Short name T1035
Test name
Test status
Simulation time 376213968247 ps
CPU time 1317 seconds
Started Jan 24 07:47:12 PM PST 24
Finished Jan 24 08:09:10 PM PST 24
Peak memory 288028 kb
Host smart-385ac8c9-e713-4324-8af1-66468435fff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665434801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2665434801
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1650648762
Short name T286
Test name
Test status
Simulation time 5327317390 ps
CPU time 29.04 seconds
Started Jan 24 07:47:05 PM PST 24
Finished Jan 24 07:47:36 PM PST 24
Peak memory 215992 kb
Host smart-d7036d79-e76e-4123-835e-467b77b942b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650648762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1650648762
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2407884811
Short name T546
Test name
Test status
Simulation time 1807657154 ps
CPU time 7.51 seconds
Started Jan 24 07:47:01 PM PST 24
Finished Jan 24 07:47:11 PM PST 24
Peak memory 207740 kb
Host smart-8e1de53a-48c0-4263-ad08-6d8793fa0d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407884811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2407884811
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3329626589
Short name T934
Test name
Test status
Simulation time 181967701 ps
CPU time 1.85 seconds
Started Jan 24 07:47:04 PM PST 24
Finished Jan 24 07:47:08 PM PST 24
Peak memory 216288 kb
Host smart-dc299fac-9be3-4fdd-abef-edcfbad2d44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329626589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3329626589
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.254459496
Short name T1047
Test name
Test status
Simulation time 30055614 ps
CPU time 0.75 seconds
Started Jan 24 07:47:02 PM PST 24
Finished Jan 24 07:47:06 PM PST 24
Peak memory 204612 kb
Host smart-e5768802-e2b3-49c4-ac18-960a9e681a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254459496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.254459496
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3080068076
Short name T625
Test name
Test status
Simulation time 5055096026 ps
CPU time 7.33 seconds
Started Jan 24 07:47:12 PM PST 24
Finished Jan 24 07:47:20 PM PST 24
Peak memory 232772 kb
Host smart-3e0c6972-5b16-41be-8a4f-7e5673eb5384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080068076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3080068076
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3499198000
Short name T33
Test name
Test status
Simulation time 39704938 ps
CPU time 0.69 seconds
Started Jan 24 07:47:36 PM PST 24
Finished Jan 24 07:47:38 PM PST 24
Peak memory 204064 kb
Host smart-c6f6f77e-5f20-4eda-94fe-d98b37a82317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499198000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
499198000
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2710343890
Short name T774
Test name
Test status
Simulation time 1178982539 ps
CPU time 4.52 seconds
Started Jan 24 07:47:28 PM PST 24
Finished Jan 24 07:47:34 PM PST 24
Peak memory 217628 kb
Host smart-e58be7fd-1ab2-44c4-801d-3eeeb5fa9e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710343890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2710343890
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1388934436
Short name T292
Test name
Test status
Simulation time 36372000 ps
CPU time 0.75 seconds
Started Jan 24 07:47:22 PM PST 24
Finished Jan 24 07:47:23 PM PST 24
Peak memory 204240 kb
Host smart-a3bfe6fa-4e2e-4b2b-b3b9-16fe9749eafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388934436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1388934436
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.4130371970
Short name T257
Test name
Test status
Simulation time 19230472312 ps
CPU time 13.31 seconds
Started Jan 24 07:47:24 PM PST 24
Finished Jan 24 07:47:38 PM PST 24
Peak memory 234116 kb
Host smart-b193e683-c83e-49f9-bdf7-4f1dde80a618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130371970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.4130371970
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1570092410
Short name T28
Test name
Test status
Simulation time 16910395748 ps
CPU time 117.65 seconds
Started Jan 24 07:47:28 PM PST 24
Finished Jan 24 07:49:27 PM PST 24
Peak memory 265388 kb
Host smart-f2973ea9-f4a8-4b28-b27c-96aa63ed1c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570092410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1570092410
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2750567863
Short name T161
Test name
Test status
Simulation time 15856927637 ps
CPU time 77.31 seconds
Started Jan 24 07:47:28 PM PST 24
Finished Jan 24 07:48:46 PM PST 24
Peak memory 256376 kb
Host smart-21d986c2-51a3-450e-9998-5e7aa6598f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750567863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2750567863
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.4110565650
Short name T621
Test name
Test status
Simulation time 7602949509 ps
CPU time 38.06 seconds
Started Jan 24 07:47:28 PM PST 24
Finished Jan 24 07:48:07 PM PST 24
Peak memory 240148 kb
Host smart-73596e6b-1b99-4671-a050-f55f78333201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110565650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.4110565650
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2261311739
Short name T923
Test name
Test status
Simulation time 692930316 ps
CPU time 6.84 seconds
Started Jan 24 07:47:27 PM PST 24
Finished Jan 24 07:47:35 PM PST 24
Peak memory 232744 kb
Host smart-1bfd19c6-b874-4923-b319-63a27f9e1d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261311739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2261311739
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3013457848
Short name T668
Test name
Test status
Simulation time 175135394 ps
CPU time 2.33 seconds
Started Jan 24 07:47:24 PM PST 24
Finished Jan 24 07:47:27 PM PST 24
Peak memory 216048 kb
Host smart-c2526ffd-5efb-4a2c-a6c6-2f38c7ee4e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013457848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3013457848
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3551359496
Short name T857
Test name
Test status
Simulation time 14842927 ps
CPU time 1 seconds
Started Jan 24 07:47:21 PM PST 24
Finished Jan 24 07:47:23 PM PST 24
Peak memory 215780 kb
Host smart-51695ba3-b323-478d-ac23-6666aabe515a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551359496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3551359496
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4014686857
Short name T605
Test name
Test status
Simulation time 954656100 ps
CPU time 6.26 seconds
Started Jan 24 07:47:22 PM PST 24
Finished Jan 24 07:47:29 PM PST 24
Peak memory 236492 kb
Host smart-fd80a8c1-a275-4611-8842-db4740e80c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014686857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4014686857
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3628171912
Short name T196
Test name
Test status
Simulation time 1454662371 ps
CPU time 11.99 seconds
Started Jan 24 07:47:22 PM PST 24
Finished Jan 24 07:47:35 PM PST 24
Peak memory 239788 kb
Host smart-dac502ec-ed04-4b96-af67-9ee840d318af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628171912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3628171912
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.1413531829
Short name T951
Test name
Test status
Simulation time 20938094 ps
CPU time 0.73 seconds
Started Jan 24 07:47:22 PM PST 24
Finished Jan 24 07:47:24 PM PST 24
Peak memory 215848 kb
Host smart-fd52ae41-7547-4281-b063-d2a7f570f9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413531829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.1413531829
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1451481504
Short name T422
Test name
Test status
Simulation time 7637266248 ps
CPU time 7.96 seconds
Started Jan 24 07:47:23 PM PST 24
Finished Jan 24 07:47:32 PM PST 24
Peak memory 221236 kb
Host smart-936739a6-24aa-458b-b193-1f645aa2effc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1451481504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1451481504
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.484667560
Short name T550
Test name
Test status
Simulation time 17605151959 ps
CPU time 145.58 seconds
Started Jan 24 07:47:26 PM PST 24
Finished Jan 24 07:49:52 PM PST 24
Peak memory 240224 kb
Host smart-1e9ca68d-5c06-454c-aa07-03beffbca69f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484667560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.484667560
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.792686164
Short name T832
Test name
Test status
Simulation time 3227684023 ps
CPU time 9.78 seconds
Started Jan 24 07:47:26 PM PST 24
Finished Jan 24 07:47:36 PM PST 24
Peak memory 218208 kb
Host smart-06c359a4-0f0d-411b-a7f5-9946b31b3b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792686164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.792686164
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2249919066
Short name T786
Test name
Test status
Simulation time 4017041527 ps
CPU time 7.78 seconds
Started Jan 24 07:47:20 PM PST 24
Finished Jan 24 07:47:29 PM PST 24
Peak memory 215968 kb
Host smart-2655e37e-7aa5-494e-aa2c-b3fb4a9c3b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249919066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2249919066
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2301045905
Short name T435
Test name
Test status
Simulation time 413941358 ps
CPU time 2.22 seconds
Started Jan 24 07:47:22 PM PST 24
Finished Jan 24 07:47:25 PM PST 24
Peak memory 207800 kb
Host smart-18cc0492-21da-4df1-a3c7-df63707b879c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301045905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2301045905
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1833370135
Short name T1050
Test name
Test status
Simulation time 766450936 ps
CPU time 1.17 seconds
Started Jan 24 07:47:22 PM PST 24
Finished Jan 24 07:47:24 PM PST 24
Peak memory 205616 kb
Host smart-fcf7336c-aa87-45c2-8ca7-0a08e8322bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833370135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1833370135
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2468428076
Short name T821
Test name
Test status
Simulation time 377572063 ps
CPU time 3.64 seconds
Started Jan 24 07:47:23 PM PST 24
Finished Jan 24 07:47:28 PM PST 24
Peak memory 217616 kb
Host smart-6f4b39bc-e885-4e32-94ee-17c594cce53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468428076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2468428076
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1276755029
Short name T507
Test name
Test status
Simulation time 23003849 ps
CPU time 0.7 seconds
Started Jan 24 09:03:11 PM PST 24
Finished Jan 24 09:03:12 PM PST 24
Peak memory 203552 kb
Host smart-489cad92-2634-4db3-987d-abdcb382bc73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276755029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
276755029
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1339129902
Short name T1004
Test name
Test status
Simulation time 206712633 ps
CPU time 3.43 seconds
Started Jan 24 07:47:47 PM PST 24
Finished Jan 24 07:47:51 PM PST 24
Peak memory 233064 kb
Host smart-feec8cae-d400-4521-87a5-3f274738e82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339129902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1339129902
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1306285507
Short name T1087
Test name
Test status
Simulation time 82612245 ps
CPU time 0.78 seconds
Started Jan 24 07:47:33 PM PST 24
Finished Jan 24 07:47:34 PM PST 24
Peak memory 205272 kb
Host smart-b2196cdc-1237-4f8e-92fe-ad208343c526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306285507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1306285507
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1774121806
Short name T6
Test name
Test status
Simulation time 632343534 ps
CPU time 5.97 seconds
Started Jan 24 07:47:43 PM PST 24
Finished Jan 24 07:47:50 PM PST 24
Peak memory 224172 kb
Host smart-4d3e5b08-fbae-41e2-824d-3705861a17ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774121806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1774121806
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3481152181
Short name T199
Test name
Test status
Simulation time 38656486600 ps
CPU time 224.74 seconds
Started Jan 24 07:47:44 PM PST 24
Finished Jan 24 07:51:30 PM PST 24
Peak memory 249624 kb
Host smart-d1483a4b-7bb1-482c-af0a-88a3d1110f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481152181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3481152181
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3926359559
Short name T894
Test name
Test status
Simulation time 1353528163 ps
CPU time 20.42 seconds
Started Jan 24 07:47:42 PM PST 24
Finished Jan 24 07:48:03 PM PST 24
Peak memory 248792 kb
Host smart-3f91b4d4-95df-486d-8278-2c27867706b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926359559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3926359559
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2318374538
Short name T220
Test name
Test status
Simulation time 1016330566 ps
CPU time 3.34 seconds
Started Jan 24 07:47:46 PM PST 24
Finished Jan 24 07:47:50 PM PST 24
Peak memory 233300 kb
Host smart-cc761d9d-4bb3-4125-84af-9dbdf2402e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318374538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2318374538
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1650533186
Short name T231
Test name
Test status
Simulation time 713067634 ps
CPU time 5.09 seconds
Started Jan 24 07:47:41 PM PST 24
Finished Jan 24 07:47:47 PM PST 24
Peak memory 219324 kb
Host smart-24e0bf30-3335-4f62-af95-c5603238ed07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650533186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1650533186
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1186740370
Short name T960
Test name
Test status
Simulation time 49693313 ps
CPU time 1.02 seconds
Started Jan 24 07:47:33 PM PST 24
Finished Jan 24 07:47:35 PM PST 24
Peak memory 215804 kb
Host smart-4fdbaee3-d812-44d1-9613-9fe58c64394f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186740370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1186740370
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.4276344182
Short name T643
Test name
Test status
Simulation time 2760071154 ps
CPU time 9.36 seconds
Started Jan 24 07:47:41 PM PST 24
Finished Jan 24 07:47:52 PM PST 24
Peak memory 217080 kb
Host smart-6e66042d-a7a7-4d50-9d27-e855ece0ba36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276344182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.4276344182
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3115469231
Short name T511
Test name
Test status
Simulation time 905555882 ps
CPU time 2.88 seconds
Started Jan 24 07:47:43 PM PST 24
Finished Jan 24 07:47:47 PM PST 24
Peak memory 216332 kb
Host smart-69b82792-16a7-44b1-b3e1-0e30cacb94fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115469231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3115469231
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.1162579746
Short name T690
Test name
Test status
Simulation time 27170635 ps
CPU time 0.77 seconds
Started Jan 24 07:47:39 PM PST 24
Finished Jan 24 07:47:41 PM PST 24
Peak memory 215892 kb
Host smart-72228e17-97ce-43c7-83da-6554afcbf6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162579746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.1162579746
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3579141275
Short name T608
Test name
Test status
Simulation time 76373523 ps
CPU time 3.31 seconds
Started Jan 24 08:41:29 PM PST 24
Finished Jan 24 08:41:33 PM PST 24
Peak memory 221908 kb
Host smart-02a26694-9676-446f-8050-46e48860d098
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3579141275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3579141275
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.4117074855
Short name T506
Test name
Test status
Simulation time 59140298 ps
CPU time 1.06 seconds
Started Jan 24 07:47:42 PM PST 24
Finished Jan 24 07:47:44 PM PST 24
Peak memory 205824 kb
Host smart-7da99aa3-755e-4efc-ab4e-9f8056d5127c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117074855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.4117074855
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.152521408
Short name T831
Test name
Test status
Simulation time 6618543819 ps
CPU time 22.1 seconds
Started Jan 24 07:47:41 PM PST 24
Finished Jan 24 07:48:05 PM PST 24
Peak memory 216048 kb
Host smart-9ecd59c3-1e12-414e-89aa-89a34ffd7564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152521408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.152521408
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3257490677
Short name T593
Test name
Test status
Simulation time 4053555958 ps
CPU time 6.72 seconds
Started Jan 24 07:47:35 PM PST 24
Finished Jan 24 07:47:43 PM PST 24
Peak memory 215980 kb
Host smart-5eeb97c3-8fca-47c7-ab54-d9c0b926bb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257490677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3257490677
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3102294883
Short name T592
Test name
Test status
Simulation time 43465155 ps
CPU time 0.9 seconds
Started Jan 24 07:47:43 PM PST 24
Finished Jan 24 07:47:46 PM PST 24
Peak memory 205444 kb
Host smart-c4de14e4-2b21-48a2-9401-11759584f53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102294883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3102294883
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3866945699
Short name T431
Test name
Test status
Simulation time 76388984 ps
CPU time 1.03 seconds
Started Jan 24 07:47:43 PM PST 24
Finished Jan 24 07:47:45 PM PST 24
Peak memory 205592 kb
Host smart-7e4b2b4e-6959-4ed9-9943-2dd77f12b74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866945699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3866945699
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.71738286
Short name T467
Test name
Test status
Simulation time 2928813854 ps
CPU time 6.07 seconds
Started Jan 24 07:47:42 PM PST 24
Finished Jan 24 07:47:49 PM PST 24
Peak memory 216184 kb
Host smart-64692ea7-e895-4798-9b09-2093fa3ec66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71738286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.71738286
Directory /workspace/9.spi_device_upload/latest
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