Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8832925	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7375801

1

T1

8

T2

112

T3

3788

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	11424755	1			T1	1		T2	101		T3	3221
values[0x0]	2391344	1			T1	15		T2	53		T3	1145
values[0x1]	2392627	1			T1	9		T2	47		T3	1029

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6313607	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9895119

1

T1

9

T2

161

T3

4091

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	64730	1			T2	1		T3	18		T7	888
valid_sources[0x01]	59965	1			T3	31		T6	2		T7	847
valid_sources[0x02]	62837	1			T3	27		T7	808		T8	6
valid_sources[0x03]	65477	1			T3	26		T7	783		T8	3
valid_sources[0x04]	59735	1			T3	14		T7	830		T8	3
valid_sources[0x05]	61710	1			T3	10		T4	1		T6	1
valid_sources[0x06]	60243	1			T3	16		T7	857		T8	4
valid_sources[0x07]	66189	1			T2	1		T3	29		T7	810
valid_sources[0x08]	60893	1			T2	1		T3	19		T7	928
valid_sources[0x09]	62346	1			T3	17		T7	858		T8	7
valid_sources[0x0a]	64001	1			T3	16		T7	805		T8	2
valid_sources[0x0b]	63192	1			T3	25		T4	416		T7	857
valid_sources[0x0c]	59109	1			T2	2		T3	33		T7	833
valid_sources[0x0d]	60534	1			T2	1		T3	21		T7	824
valid_sources[0x0e]	60578	1			T3	20		T7	897		T8	3
valid_sources[0x0f]	65853	1			T3	18		T6	3		T7	768
valid_sources[0x10]	59681	1			T2	1		T3	20		T7	822
valid_sources[0x11]	63928	1			T2	1		T3	9		T7	823
valid_sources[0x12]	60353	1			T3	26		T7	929		T8	7
valid_sources[0x13]	63447	1			T2	1		T3	25		T7	825
valid_sources[0x14]	65227	1			T3	19		T7	855		T8	1
valid_sources[0x15]	63646	1			T3	21		T7	791		T8	3
valid_sources[0x16]	63216	1			T2	1		T3	24		T7	923
valid_sources[0x17]	62365	1			T3	23		T6	2		T7	806
valid_sources[0x18]	59186	1			T3	30		T7	803		T18	13
valid_sources[0x19]	62618	1			T3	25		T6	1		T7	791
valid_sources[0x1a]	64300	1			T2	5		T3	11		T7	844
valid_sources[0x1b]	63093	1			T2	2		T3	10		T7	858
valid_sources[0x1c]	62039	1			T3	7		T7	833		T8	6
valid_sources[0x1d]	64270	1			T3	22		T7	883		T8	4
valid_sources[0x1e]	59324	1			T2	1		T3	24		T7	877
valid_sources[0x1f]	58839	1			T2	1		T3	13		T6	1
valid_sources[0x20]	66108	1			T2	1		T3	22		T6	4
valid_sources[0x21]	64400	1			T2	1		T3	25		T7	841
valid_sources[0x22]	60549	1			T2	1		T3	19		T7	854
valid_sources[0x23]	65695	1			T2	3		T3	14		T7	804
valid_sources[0x24]	62622	1			T3	27		T7	946		T8	4
valid_sources[0x25]	60282	1			T3	31		T7	839		T8	5
valid_sources[0x26]	61538	1			T3	21		T6	1		T7	830
valid_sources[0x27]	61396	1			T3	33		T6	5		T7	772
valid_sources[0x28]	62249	1			T3	31		T7	823		T18	23
valid_sources[0x29]	66764	1			T2	1		T3	35		T7	878
valid_sources[0x2a]	63866	1			T2	3		T3	31		T7	884
valid_sources[0x2b]	63332	1			T3	29		T7	894		T8	6
valid_sources[0x2c]	68157	1			T3	23		T7	929		T8	1
valid_sources[0x2d]	66422	1			T2	1		T3	33		T6	3
valid_sources[0x2e]	70511	1			T3	17		T7	847		T9	3
valid_sources[0x2f]	57461	1			T3	33		T7	889		T8	5
valid_sources[0x30]	64471	1			T3	22		T7	816		T8	12
valid_sources[0x31]	61122	1			T2	2		T3	12		T6	1
valid_sources[0x32]	68149	1			T2	1		T3	28		T7	811
valid_sources[0x33]	70933	1			T2	3		T3	23		T6	1
valid_sources[0x34]	62497	1			T3	9		T7	914		T8	3
valid_sources[0x35]	64085	1			T2	1		T3	23		T7	893
valid_sources[0x36]	60904	1			T2	1		T3	16		T6	1
valid_sources[0x37]	62730	1			T2	1		T3	29		T7	880
valid_sources[0x38]	60888	1			T3	21		T6	1		T7	855
valid_sources[0x39]	59905	1			T2	3		T3	13		T7	795
valid_sources[0x3a]	63585	1			T3	23		T6	1		T7	878
valid_sources[0x3b]	63979	1			T3	28		T7	873		T8	1
valid_sources[0x3c]	65992	1			T3	13		T7	846		T8	3
valid_sources[0x3d]	61125	1			T3	27		T7	891		T8	2
valid_sources[0x3e]	66959	1			T2	1		T3	16		T4	274
valid_sources[0x3f]	60343	1			T2	1		T3	16		T6	1
valid_sources[0x40]	64143	1			T2	4		T3	19		T7	828
valid_sources[0x41]	61106	1			T2	1		T3	8		T7	810
valid_sources[0x42]	64142	1			T2	3		T3	17		T6	1
valid_sources[0x43]	60963	1			T3	16		T6	4		T7	862
valid_sources[0x44]	67783	1			T2	1		T3	26		T4	2077
valid_sources[0x45]	60698	1			T3	20		T7	877		T8	4
valid_sources[0x46]	63449	1			T2	2		T3	20		T4	1958
valid_sources[0x47]	62500	1			T2	1		T3	17		T7	845
valid_sources[0x48]	61091	1			T3	28		T7	876		T8	1
valid_sources[0x49]	68550	1			T3	19		T6	5		T7	873
valid_sources[0x4a]	65815	1			T3	14		T7	884		T10	1
valid_sources[0x4b]	64459	1			T2	2		T3	15		T6	1
valid_sources[0x4c]	59950	1			T2	2		T3	22		T4	1
valid_sources[0x4d]	59031	1			T2	1		T3	24		T6	1
valid_sources[0x4e]	62113	1			T3	23		T6	1		T7	759
valid_sources[0x4f]	62960	1			T3	17		T7	899		T8	4
valid_sources[0x50]	63901	1			T2	1		T3	18		T7	824
valid_sources[0x51]	66981	1			T2	2		T3	22		T6	1
valid_sources[0x52]	67767	1			T2	1		T3	13		T7	867
valid_sources[0x53]	66299	1			T2	1		T3	24		T7	812
valid_sources[0x54]	66666	1			T3	30		T7	868		T8	6
valid_sources[0x55]	60550	1			T3	16		T4	4		T7	862
valid_sources[0x56]	61124	1			T2	1		T3	24		T7	801
valid_sources[0x57]	62161	1			T2	2		T3	11		T7	864
valid_sources[0x58]	59848	1			T3	21		T7	801		T8	4
valid_sources[0x59]	66127	1			T2	1		T3	16		T7	772
valid_sources[0x5a]	61888	1			T3	17		T7	844		T8	2
valid_sources[0x5b]	59005	1			T3	12		T7	785		T8	2
valid_sources[0x5c]	60478	1			T2	1		T3	16		T7	840
valid_sources[0x5d]	64895	1			T3	26		T7	856		T8	1
valid_sources[0x5e]	59193	1			T3	29		T7	871		T8	3
valid_sources[0x5f]	65091	1			T2	1		T3	14		T6	1
valid_sources[0x60]	61954	1			T3	32		T7	853		T8	8
valid_sources[0x61]	70613	1			T3	22		T6	1		T7	866
valid_sources[0x62]	61770	1			T3	25		T7	805		T8	2
valid_sources[0x63]	64329	1			T2	1		T3	22		T7	793
valid_sources[0x64]	62847	1			T2	2		T3	20		T7	794
valid_sources[0x65]	60808	1			T3	25		T7	856		T8	1
valid_sources[0x66]	61946	1			T3	21		T7	885		T8	5
valid_sources[0x67]	63226	1			T3	28		T7	867		T8	6
valid_sources[0x68]	66172	1			T3	15		T6	1		T7	856
valid_sources[0x69]	59311	1			T3	17		T7	849		T8	2
valid_sources[0x6a]	68915	1			T3	14		T6	1		T7	787
valid_sources[0x6b]	63980	1			T3	37		T7	826		T8	3
valid_sources[0x6c]	73363	1			T3	22		T7	861		T8	2
valid_sources[0x6d]	64349	1			T2	2		T3	13		T7	835
valid_sources[0x6e]	59500	1			T2	1		T3	26		T7	807
valid_sources[0x6f]	61797	1			T3	7		T7	810		T8	4
valid_sources[0x70]	64797	1			T3	14		T6	1		T7	892
valid_sources[0x71]	64196	1			T2	1		T3	23		T7	806
valid_sources[0x72]	59846	1			T2	1		T3	24		T7	850
valid_sources[0x73]	59966	1			T3	12		T7	864		T8	3
valid_sources[0x74]	59564	1			T2	1		T3	20		T7	849
valid_sources[0x75]	62952	1			T3	15		T7	788		T8	1
valid_sources[0x76]	60312	1			T3	26		T6	2		T7	850
valid_sources[0x77]	64305	1			T2	1		T3	36		T4	1
valid_sources[0x78]	67511	1			T2	1		T3	24		T6	1
valid_sources[0x79]	64596	1			T2	2		T3	14		T7	844
valid_sources[0x7a]	63939	1			T2	1		T3	16		T6	1
valid_sources[0x7b]	63849	1			T2	1		T3	16		T7	832
valid_sources[0x7c]	58364	1			T3	17		T6	1		T7	886
valid_sources[0x7d]	57937	1			T3	23		T7	866		T8	7
valid_sources[0x7e]	63096	1			T3	38		T7	858		T8	3
valid_sources[0x7f]	63374	1			T2	2		T3	22		T7	843
valid_sources[0x80]	60240	1			T2	3		T3	19		T7	816

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3012809

1

T1

1

T2

12

T3

1624

values[0x0]

all_enables

biggest_size

2192337

1

T1

6

T2

53

T3

1141

values[0x1]

all_enables

biggest_size

2170655

1

T1

1

T2

47

T3

1023