Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

8855727

1

T1

17

T3

1607

T4

1953

full_word

7375022

1

T1

8

T3

3788

T4

3388

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	16230379	1			T1	25		T3	5395		T4	5341
auto[TlIntgErrCmd]	155	1			T73	5		T78	7		T79	9
auto[TlIntgErrData]	102	1			T78	5		T79	9		T95	6
auto[TlIntgErrBoth]	113	1			T73	5		T78	8		T79	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11427048

1

T1

1

T3

3221

T4

3939

auto[1]

4803701

1

T1

24

T3

2174

T4

1402

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8413940	1			T3	1597		T4	1943		T6	62
auto[TlIntgErrNone]	partial	auto[1]	441451	1			T1	17		T3	10		T4	10
auto[TlIntgErrNone]	full_word	auto[0]	3012941	1			T1	1		T3	1624		T4	1996
auto[TlIntgErrNone]	full_word	auto[1]	4362047	1			T1	7		T3	2164		T4	1392
auto[TlIntgErrCmd]	partial	auto[0]	64	1			T73	3		T78	2		T79	4
auto[TlIntgErrCmd]	partial	auto[1]	80	1			T73	2		T78	4		T79	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T79	1		T153	1		T154	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T78	1		T127	1		T155	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T78	2		T79	1		T95	2
auto[TlIntgErrData]	partial	auto[1]	48	1			T78	3		T79	7		T95	3
auto[TlIntgErrData]	full_word	auto[0]	10	1			T79	1		T151	2		T155	3
auto[TlIntgErrData]	full_word	auto[1]	4	1			T95	1		T128	1		T156	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T73	3		T78	2		T79	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T73	2		T78	6		T79	6
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T79	4		T155	1		T157	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T95	1		T151	1		T158	1